Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	10	22	68.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	10	22	68.75	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32679	1		T4	4		T8	4		T66	1
auto[1]	15	1		T60	1		T51	1		T225	1
auto[2]	17	1		T160	8		T332	4		T333	1
auto[3]	109	1		T60	4		T37	2		T110	2

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8202	1		T4	1		T8	1		T83	1
evic_idx[1]	8209	1		T4	1		T8	1		T66	1
evic_idx[2]	8208	1		T4	1		T8	1		T83	1
evic_idx[3]	8201	1		T4	1		T8	1		T83	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	32002	1		T8	4		T66	1		T86	400
evic_op[2]	338	1		T4	4		T83	4		T67	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	10	22	68.75	10

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[3]]	*	[auto[2]]	--	--	2

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[0]]	[evic_op[2]]	[auto[2]]	0	1	1
[evic_idx[1]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[2]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[2]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7988	1		T8	1		T86	100		T87	100
evic_idx[0]	evic_op[1]	auto[3]	13	1		T60	1		T290	1		T286	6
evic_idx[0]	evic_op[2]	auto[0]	66	1		T4	1		T83	1		T67	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T334	1		T335	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	13	1		T37	1		T110	1		T292	1
evic_idx[1]	evic_op[1]	auto[0]	7988	1		T8	1		T66	1		T86	100
evic_idx[1]	evic_op[1]	auto[3]	14	1		T60	1		T290	1		T286	6
evic_idx[1]	evic_op[2]	auto[0]	68	1		T4	1		T83	1		T67	1
evic_idx[1]	evic_op[2]	auto[1]	2	1		T335	1		T336	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	1	1		T333	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	16	1		T37	1		T110	1		T337	1
evic_idx[2]	evic_op[1]	auto[0]	7988	1		T8	1		T86	100		T87	100
evic_idx[2]	evic_op[1]	auto[3]	12	1		T60	1		T290	1		T286	5
evic_idx[2]	evic_op[2]	auto[0]	65	1		T4	1		T83	1		T67	1
evic_idx[2]	evic_op[2]	auto[1]	7	1		T51	1		T225	1		T338	1
evic_idx[2]	evic_op[2]	auto[3]	16	1		T292	1		T339	1		T340	1
evic_idx[3]	evic_op[1]	auto[0]	7987	1		T8	1		T86	100		T87	100
evic_idx[3]	evic_op[1]	auto[1]	1	1		T60	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	11	1		T60	1		T286	5		T341	3
evic_idx[3]	evic_op[2]	auto[0]	65	1		T4	1		T83	1		T67	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T342	1		T334	1		T343	1
evic_idx[3]	evic_op[2]	auto[3]	14	1		T292	1		T313	1		T339	1