Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	23779	1		T34	15878		T352	2730		T353	2862
rd_lvl[2]	56909	1		T34	11530		T352	2423		T354	12568
rd_lvl[3]	11499	1		T26	933		T355	1163		T352	1411
rd_lvl[4]	33792	1		T26	5062		T355	1235		T330	1909
rd_lvl[5]	20213	1		T26	1184		T355	105		T195	2356
rd_lvl[6]	24402	1		T195	2354		T352	24		T287	19
rd_lvl[7]	10564	1		T195	1		T352	1257		T287	1
rd_lvl[8]	8371	1		T352	1251		T190	23		T356	419
rd_lvl[9]	5637	1		T352	1501		T357	208		T358	209
rd_lvl[10]	7207	1		T328	1415		T352	995		T357	1466
rd_lvl[11]	4204	1		T195	1		T33	190		T328	318
rd_lvl[12]	5560	1		T33	93		T359	311		T196	969
rd_lvl[13]	2881	1		T359	216		T287	19		T360	159
rd_lvl[14]	6321	1		T32	56		T33	1		T361	417
rd_lvl[15]	2659	1		T31	185		T32	22		T359	2