Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	322298	1		T1	1		T2	1		T3	1
all_pins[1]	322298	1		T1	1		T2	1		T3	1
all_pins[2]	322298	1		T1	1		T2	1		T3	1
all_pins[3]	322298	1		T1	1		T2	1		T3	1
all_pins[4]	322298	1		T1	1		T2	1		T3	1
all_pins[5]	322298	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1598338	1		T1	6		T2	6		T3	6
values[0x1]	335450	1		T26	8704		T34	30160		T28	1606
transitions[0x0=>0x1]	298875	1		T26	7452		T34	27408		T28	1606
transitions[0x1=>0x0]	298862	1		T26	7452		T34	27408		T28	1606

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	322159	1		T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	139	1		T265	4		T266	6		T267	3
all_pins[0]	transitions[0x0=>0x1]	67	1		T266	4		T344	2		T346	2
all_pins[0]	transitions[0x1=>0x0]	95	1		T267	1		T345	1		T344	3
all_pins[1]	values[0x0]	322131	1		T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	167	1		T265	4		T266	2		T267	4
all_pins[1]	transitions[0x0=>0x1]	133	1		T265	3		T266	1		T267	2
all_pins[1]	transitions[0x1=>0x0]	2849	1		T31	185		T32	2		T192	46
all_pins[2]	values[0x0]	319415	1		T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	2883	1		T31	185		T32	2		T192	46
all_pins[2]	transitions[0x0=>0x1]	50	1		T265	1		T266	2		T267	3
all_pins[2]	transitions[0x1=>0x0]	224092	1		T26	7179		T34	27408		T31	185
all_pins[3]	values[0x0]	95373	1		T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	226925	1		T26	7179		T34	27408		T31	370
all_pins[3]	transitions[0x0=>0x1]	193346	1		T26	5927		T34	24656		T31	185
all_pins[3]	transitions[0x1=>0x0]	71690	1		T26	273		T28	1606		T31	309
all_pins[4]	values[0x0]	217029	1		T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	105269	1		T26	1525		T34	2752		T28	1606
all_pins[4]	transitions[0x0=>0x1]	105250	1		T26	1525		T34	2752		T28	1606
all_pins[4]	transitions[0x1=>0x0]	48	1		T266	1		T344	1		T348	2
all_pins[5]	values[0x0]	322231	1		T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	67	1		T265	2		T266	3		T344	2
all_pins[5]	transitions[0x0=>0x1]	29	1		T265	1		T266	1		T348	1
all_pins[5]	transitions[0x1=>0x0]	88	1		T265	2		T266	3		T267	2