Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T265	4		T266	7		T267	7
all_values[1]	278	1		T265	4		T266	7		T267	7
all_values[2]	278	1		T265	4		T266	7		T267	7
all_values[3]	278	1		T265	4		T266	7		T267	7
all_values[4]	278	1		T265	4		T266	7		T267	7
all_values[5]	278	1		T265	4		T266	7		T267	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	955	1		T265	14		T266	26		T267	28
auto[1]	713	1		T265	10		T266	16		T267	14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	513	1		T265	7		T266	8		T267	16
auto[1]	1155	1		T265	17		T266	34		T267	26

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	965	1		T265	16		T266	21		T267	27
auto[1]	703	1		T265	8		T266	21		T267	15

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	99	1		T265	2		T266	3		T267	3
all_values[0]	auto[0]	auto[1]	auto[1]	70	1		T265	1		T266	4		T267	2
all_values[0]	auto[1]	auto[0]	auto[1]	69	1		T265	1		T267	2		T344	1
all_values[0]	auto[1]	auto[1]	auto[1]	40	1		T345	1		T346	1		T347	2
all_values[1]	auto[0]	auto[0]	auto[1]	86	1		T265	2		T266	4		T267	1
all_values[1]	auto[0]	auto[1]	auto[1]	72	1		T265	1		T266	1		T267	2
all_values[1]	auto[1]	auto[0]	auto[1]	63	1		T265	1		T266	1		T267	3
all_values[1]	auto[1]	auto[1]	auto[1]	57	1		T266	1		T267	1		T344	1
all_values[2]	auto[0]	auto[0]	auto[0]	90	1		T266	2		T267	2		T345	1
all_values[2]	auto[0]	auto[1]	auto[0]	66	1		T265	2		T267	1		T345	1
all_values[2]	auto[1]	auto[0]	auto[1]	59	1		T265	1		T266	3		T267	1
all_values[2]	auto[1]	auto[1]	auto[1]	63	1		T265	1		T266	2		T267	3
all_values[3]	auto[0]	auto[0]	auto[0]	88	1		T265	2		T266	1		T267	3
all_values[3]	auto[0]	auto[1]	auto[0]	68	1		T265	1		T266	1		T267	1
all_values[3]	auto[1]	auto[0]	auto[1]	65	1		T265	1		T266	4		T267	3
all_values[3]	auto[1]	auto[1]	auto[1]	57	1		T266	1		T344	1		T348	1
all_values[4]	auto[0]	auto[0]	auto[0]	51	1		T266	2		T267	2		T345	4
all_values[4]	auto[0]	auto[0]	auto[1]	38	1		T267	2		T349	1		T350	1
all_values[4]	auto[0]	auto[1]	auto[0]	36	1		T266	1		T344	1		T351	2
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T265	2		T267	1		T344	1
all_values[4]	auto[1]	auto[0]	auto[1]	78	1		T265	1		T266	2		T267	2
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T265	1		T266	2		T344	2
all_values[5]	auto[0]	auto[0]	auto[0]	73	1		T265	2		T266	1		T267	4
all_values[5]	auto[0]	auto[0]	auto[1]	32	1		T266	1		T345	1		T344	2
all_values[5]	auto[0]	auto[1]	auto[0]	41	1		T267	3		T351	1		T346	1
all_values[5]	auto[0]	auto[1]	auto[1]	25	1		T265	1		T344	1		T348	1
all_values[5]	auto[1]	auto[0]	auto[1]	64	1		T265	1		T266	2		T345	1
all_values[5]	auto[1]	auto[1]	auto[1]	43	1		T266	3		T345	1		T344	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal