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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.41 95.84 94.13 98.85 91.84 98.27 98.01 97.90


Total test records in report: 1229
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T1071 /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1564689775 Jun 02 03:24:30 PM PDT 24 Jun 02 03:30:04 PM PDT 24 110314547900 ps
T1072 /workspace/coverage/default/40.flash_ctrl_connect.1408582397 Jun 02 03:25:06 PM PDT 24 Jun 02 03:25:19 PM PDT 24 15028200 ps
T1073 /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.3515470781 Jun 02 03:23:34 PM PDT 24 Jun 02 03:24:03 PM PDT 24 41406500 ps
T1074 /workspace/coverage/default/44.flash_ctrl_connect.2709583153 Jun 02 03:25:18 PM PDT 24 Jun 02 03:25:35 PM PDT 24 16203800 ps
T1075 /workspace/coverage/default/6.flash_ctrl_error_prog_win.995950259 Jun 02 03:20:17 PM PDT 24 Jun 02 03:38:44 PM PDT 24 832751900 ps
T1076 /workspace/coverage/default/15.flash_ctrl_alert_test.3925261009 Jun 02 03:22:32 PM PDT 24 Jun 02 03:22:46 PM PDT 24 19497600 ps
T1077 /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.2604047238 Jun 02 03:25:06 PM PDT 24 Jun 02 03:28:49 PM PDT 24 13862297800 ps
T1078 /workspace/coverage/default/1.flash_ctrl_invalid_op.1665940518 Jun 02 03:18:56 PM PDT 24 Jun 02 03:20:11 PM PDT 24 4310257100 ps
T1079 /workspace/coverage/default/20.flash_ctrl_otp_reset.1627137895 Jun 02 03:23:20 PM PDT 24 Jun 02 03:25:34 PM PDT 24 83891400 ps
T1080 /workspace/coverage/default/13.flash_ctrl_invalid_op.925315480 Jun 02 03:22:01 PM PDT 24 Jun 02 03:23:18 PM PDT 24 1633337900 ps
T1081 /workspace/coverage/default/1.flash_ctrl_ro.2869046884 Jun 02 03:18:56 PM PDT 24 Jun 02 03:20:51 PM PDT 24 471540400 ps
T1082 /workspace/coverage/default/50.flash_ctrl_otp_reset.674617027 Jun 02 03:25:32 PM PDT 24 Jun 02 03:27:23 PM PDT 24 41545000 ps
T1083 /workspace/coverage/default/52.flash_ctrl_connect.1334772950 Jun 02 03:25:34 PM PDT 24 Jun 02 03:25:50 PM PDT 24 27751300 ps
T1084 /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.219494359 Jun 02 03:23:15 PM PDT 24 Jun 02 03:23:46 PM PDT 24 27442200 ps
T68 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1787135437 Jun 02 03:06:40 PM PDT 24 Jun 02 03:06:58 PM PDT 24 100524900 ps
T69 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1651868002 Jun 02 03:06:42 PM PDT 24 Jun 02 03:07:47 PM PDT 24 1448315000 ps
T1085 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3201660128 Jun 02 03:06:54 PM PDT 24 Jun 02 03:07:10 PM PDT 24 18099700 ps
T70 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2460952636 Jun 02 03:07:00 PM PDT 24 Jun 02 03:07:15 PM PDT 24 35753100 ps
T1086 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3320188747 Jun 02 03:06:42 PM PDT 24 Jun 02 03:06:56 PM PDT 24 17409200 ps
T206 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.35661312 Jun 02 03:06:57 PM PDT 24 Jun 02 03:07:15 PM PDT 24 51070100 ps
T1087 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1224629355 Jun 02 03:07:03 PM PDT 24 Jun 02 03:07:19 PM PDT 24 29796200 ps
T1088 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.845076735 Jun 02 03:07:06 PM PDT 24 Jun 02 03:07:20 PM PDT 24 19945900 ps
T210 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1017208938 Jun 02 03:06:45 PM PDT 24 Jun 02 03:07:25 PM PDT 24 3033268600 ps
T251 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2949883365 Jun 02 03:06:46 PM PDT 24 Jun 02 03:07:44 PM PDT 24 941880100 ps
T207 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3425645094 Jun 02 03:07:13 PM PDT 24 Jun 02 03:13:42 PM PDT 24 715852900 ps
T208 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.519704905 Jun 02 03:07:03 PM PDT 24 Jun 02 03:19:38 PM PDT 24 1691826900 ps
T252 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.40617594 Jun 02 03:07:15 PM PDT 24 Jun 02 03:07:45 PM PDT 24 636914200 ps
T265 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3290740244 Jun 02 03:07:16 PM PDT 24 Jun 02 03:07:30 PM PDT 24 14174100 ps
T209 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.700916141 Jun 02 03:06:45 PM PDT 24 Jun 02 03:07:04 PM PDT 24 28042600 ps
T253 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.405398531 Jun 02 03:06:52 PM PDT 24 Jun 02 03:07:11 PM PDT 24 67284300 ps
T219 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1198542280 Jun 02 03:07:03 PM PDT 24 Jun 02 03:14:48 PM PDT 24 1801873700 ps
T266 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3052396404 Jun 02 03:07:12 PM PDT 24 Jun 02 03:07:26 PM PDT 24 53108600 ps
T232 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1870304657 Jun 02 03:06:54 PM PDT 24 Jun 02 03:21:53 PM PDT 24 862062600 ps
T1089 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3494066177 Jun 02 03:07:04 PM PDT 24 Jun 02 03:07:20 PM PDT 24 14252000 ps
T217 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1821041659 Jun 02 03:06:52 PM PDT 24 Jun 02 03:07:11 PM PDT 24 119594500 ps
T267 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2219938158 Jun 02 03:07:15 PM PDT 24 Jun 02 03:07:30 PM PDT 24 48309500 ps
T1090 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.235007367 Jun 02 03:06:49 PM PDT 24 Jun 02 03:07:03 PM PDT 24 177168200 ps
T218 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.534895550 Jun 02 03:07:01 PM PDT 24 Jun 02 03:07:18 PM PDT 24 155647600 ps
T227 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3904554726 Jun 02 03:07:12 PM PDT 24 Jun 02 03:07:31 PM PDT 24 189756400 ps
T261 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.215729737 Jun 02 03:06:42 PM PDT 24 Jun 02 03:14:24 PM PDT 24 346775400 ps
T1091 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.756369456 Jun 02 03:07:09 PM PDT 24 Jun 02 03:07:26 PM PDT 24 43129800 ps
T228 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.322355939 Jun 02 03:07:08 PM PDT 24 Jun 02 03:07:29 PM PDT 24 62347300 ps
T229 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2285130352 Jun 02 03:07:02 PM PDT 24 Jun 02 03:07:22 PM PDT 24 170833300 ps
T230 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.556433327 Jun 02 03:06:53 PM PDT 24 Jun 02 03:21:52 PM PDT 24 703226900 ps
T1092 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.673591401 Jun 02 03:06:46 PM PDT 24 Jun 02 03:07:00 PM PDT 24 24515600 ps
T345 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.372147007 Jun 02 03:07:12 PM PDT 24 Jun 02 03:07:26 PM PDT 24 30883300 ps
T1093 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2694848561 Jun 02 03:07:02 PM PDT 24 Jun 02 03:07:19 PM PDT 24 36776600 ps
T344 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2177071842 Jun 02 03:07:11 PM PDT 24 Jun 02 03:07:25 PM PDT 24 15230400 ps
T351 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1341091168 Jun 02 03:07:07 PM PDT 24 Jun 02 03:07:21 PM PDT 24 34190200 ps
T231 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.22566087 Jun 02 03:06:55 PM PDT 24 Jun 02 03:07:11 PM PDT 24 52358800 ps
T233 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.358249478 Jun 02 03:06:57 PM PDT 24 Jun 02 03:07:14 PM PDT 24 42721900 ps
T236 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.87635881 Jun 02 03:06:48 PM PDT 24 Jun 02 03:07:02 PM PDT 24 44672500 ps
T1094 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.248361026 Jun 02 03:06:48 PM PDT 24 Jun 02 03:07:01 PM PDT 24 18906900 ps
T346 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1326811125 Jun 02 03:07:16 PM PDT 24 Jun 02 03:07:30 PM PDT 24 17243200 ps
T1095 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.950469237 Jun 02 03:07:12 PM PDT 24 Jun 02 03:07:26 PM PDT 24 31208900 ps
T275 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.150215996 Jun 02 03:06:51 PM PDT 24 Jun 02 03:13:23 PM PDT 24 448601100 ps
T348 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2564537703 Jun 02 03:06:54 PM PDT 24 Jun 02 03:07:07 PM PDT 24 15445900 ps
T347 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3714556638 Jun 02 03:07:17 PM PDT 24 Jun 02 03:07:31 PM PDT 24 30629200 ps
T281 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2030384782 Jun 02 03:07:02 PM PDT 24 Jun 02 03:07:20 PM PDT 24 169700500 ps
T1096 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.158373452 Jun 02 03:06:47 PM PDT 24 Jun 02 03:07:00 PM PDT 24 55359100 ps
T264 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1303415067 Jun 02 03:07:03 PM PDT 24 Jun 02 03:07:19 PM PDT 24 36877300 ps
T1097 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.239166638 Jun 02 03:06:46 PM PDT 24 Jun 02 03:07:06 PM PDT 24 38609200 ps
T367 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1172839509 Jun 02 03:07:03 PM PDT 24 Jun 02 03:14:47 PM PDT 24 492688200 ps
T282 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1190453368 Jun 02 03:06:46 PM PDT 24 Jun 02 03:14:22 PM PDT 24 1565054100 ps
T269 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.341858303 Jun 02 03:07:06 PM PDT 24 Jun 02 03:14:50 PM PDT 24 228656900 ps
T274 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2833706843 Jun 02 03:06:48 PM PDT 24 Jun 02 03:21:57 PM PDT 24 674808700 ps
T237 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.125593665 Jun 02 03:06:41 PM PDT 24 Jun 02 03:06:56 PM PDT 24 18529700 ps
T349 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3759582454 Jun 02 03:07:05 PM PDT 24 Jun 02 03:07:18 PM PDT 24 76122900 ps
T262 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2059759344 Jun 02 03:07:01 PM PDT 24 Jun 02 03:07:18 PM PDT 24 81374800 ps
T1098 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2980822610 Jun 02 03:07:12 PM PDT 24 Jun 02 03:07:29 PM PDT 24 52815100 ps
T1099 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3065142313 Jun 02 03:06:45 PM PDT 24 Jun 02 03:06:59 PM PDT 24 64295700 ps
T1100 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3142268317 Jun 02 03:06:45 PM PDT 24 Jun 02 03:07:02 PM PDT 24 24377400 ps
T1101 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2485149215 Jun 02 03:07:09 PM PDT 24 Jun 02 03:07:25 PM PDT 24 83058400 ps
T302 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1687131333 Jun 02 03:06:45 PM PDT 24 Jun 02 03:07:44 PM PDT 24 23426380300 ps
T1102 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2975378273 Jun 02 03:07:05 PM PDT 24 Jun 02 03:07:22 PM PDT 24 34886100 ps
T277 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3355053701 Jun 02 03:07:09 PM PDT 24 Jun 02 03:07:29 PM PDT 24 88251600 ps
T1103 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.509844744 Jun 02 03:06:52 PM PDT 24 Jun 02 03:07:06 PM PDT 24 24167900 ps
T1104 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4165809807 Jun 02 03:07:01 PM PDT 24 Jun 02 03:07:15 PM PDT 24 24339500 ps
T350 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3956534799 Jun 02 03:06:56 PM PDT 24 Jun 02 03:07:10 PM PDT 24 99014200 ps
T1105 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2316760564 Jun 02 03:06:52 PM PDT 24 Jun 02 03:07:11 PM PDT 24 132264600 ps
T1106 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1561463294 Jun 02 03:07:11 PM PDT 24 Jun 02 03:07:25 PM PDT 24 17731300 ps
T1107 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1550338341 Jun 02 03:06:49 PM PDT 24 Jun 02 03:07:04 PM PDT 24 79393700 ps
T1108 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.481343412 Jun 02 03:06:43 PM PDT 24 Jun 02 03:07:25 PM PDT 24 658937100 ps
T366 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1678058995 Jun 02 03:07:15 PM PDT 24 Jun 02 03:19:51 PM PDT 24 2702951300 ps
T1109 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1847626152 Jun 02 03:07:12 PM PDT 24 Jun 02 03:07:27 PM PDT 24 26800100 ps
T263 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2760359299 Jun 02 03:06:48 PM PDT 24 Jun 02 03:07:09 PM PDT 24 83155400 ps
T1110 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.651560992 Jun 02 03:07:11 PM PDT 24 Jun 02 03:07:26 PM PDT 24 52112600 ps
T1111 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2617753238 Jun 02 03:07:12 PM PDT 24 Jun 02 03:07:29 PM PDT 24 11033500 ps
T1112 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.327083232 Jun 02 03:06:42 PM PDT 24 Jun 02 03:06:59 PM PDT 24 13912500 ps
T1113 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3720482174 Jun 02 03:07:18 PM PDT 24 Jun 02 03:07:32 PM PDT 24 33419800 ps
T280 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1023324144 Jun 02 03:06:44 PM PDT 24 Jun 02 03:14:22 PM PDT 24 360443600 ps
T1114 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1143947529 Jun 02 03:07:12 PM PDT 24 Jun 02 03:07:26 PM PDT 24 55745100 ps
T1115 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.4263938187 Jun 02 03:07:10 PM PDT 24 Jun 02 03:07:26 PM PDT 24 19066800 ps
T270 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2278830284 Jun 02 03:06:45 PM PDT 24 Jun 02 03:07:03 PM PDT 24 178722300 ps
T1116 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1048933406 Jun 02 03:06:41 PM PDT 24 Jun 02 03:06:58 PM PDT 24 38152300 ps
T303 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3016712629 Jun 02 03:07:13 PM PDT 24 Jun 02 03:07:31 PM PDT 24 457706100 ps
T278 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.405162158 Jun 02 03:06:57 PM PDT 24 Jun 02 03:14:37 PM PDT 24 529363400 ps
T1117 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.680791680 Jun 02 03:06:42 PM PDT 24 Jun 02 03:07:49 PM PDT 24 2600898100 ps
T1118 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.850626004 Jun 02 03:06:47 PM PDT 24 Jun 02 03:07:16 PM PDT 24 66526900 ps
T1119 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2562321064 Jun 02 03:06:57 PM PDT 24 Jun 02 03:07:13 PM PDT 24 21360100 ps
T279 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.816100336 Jun 02 03:06:56 PM PDT 24 Jun 02 03:07:16 PM PDT 24 526658600 ps
T238 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1963525843 Jun 02 03:06:44 PM PDT 24 Jun 02 03:06:58 PM PDT 24 54657900 ps
T1120 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2597323833 Jun 02 03:06:46 PM PDT 24 Jun 02 03:07:32 PM PDT 24 22712100 ps
T1121 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2874214630 Jun 02 03:07:09 PM PDT 24 Jun 02 03:07:27 PM PDT 24 182047300 ps
T1122 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1602592179 Jun 02 03:07:13 PM PDT 24 Jun 02 03:07:29 PM PDT 24 24926700 ps
T271 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.462002682 Jun 02 03:06:43 PM PDT 24 Jun 02 03:07:03 PM PDT 24 178567600 ps
T304 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.471443904 Jun 02 03:06:49 PM PDT 24 Jun 02 03:07:36 PM PDT 24 142530400 ps
T1123 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3207316509 Jun 02 03:06:45 PM PDT 24 Jun 02 03:07:00 PM PDT 24 35047700 ps
T1124 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.5448650 Jun 02 03:06:51 PM PDT 24 Jun 02 03:07:05 PM PDT 24 44309200 ps
T1125 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2934169367 Jun 02 03:07:15 PM PDT 24 Jun 02 03:07:29 PM PDT 24 23172200 ps
T1126 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2265614492 Jun 02 03:07:11 PM PDT 24 Jun 02 03:07:25 PM PDT 24 45501600 ps
T1127 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.584540582 Jun 02 03:07:17 PM PDT 24 Jun 02 03:07:31 PM PDT 24 24417200 ps
T1128 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1724626034 Jun 02 03:07:00 PM PDT 24 Jun 02 03:07:17 PM PDT 24 179319200 ps
T305 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2943888827 Jun 02 03:06:50 PM PDT 24 Jun 02 03:07:20 PM PDT 24 950262100 ps
T306 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.435816907 Jun 02 03:06:44 PM PDT 24 Jun 02 03:07:02 PM PDT 24 108797000 ps
T1129 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.531330607 Jun 02 03:06:42 PM PDT 24 Jun 02 03:06:59 PM PDT 24 25856600 ps
T1130 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.4280716896 Jun 02 03:06:52 PM PDT 24 Jun 02 03:07:06 PM PDT 24 15743100 ps
T307 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.929688627 Jun 02 03:07:13 PM PDT 24 Jun 02 03:07:33 PM PDT 24 660041600 ps
T283 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.329978823 Jun 02 03:07:17 PM PDT 24 Jun 02 03:07:35 PM PDT 24 111573300 ps
T1131 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.794469344 Jun 02 03:07:01 PM PDT 24 Jun 02 03:07:14 PM PDT 24 16526300 ps
T1132 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1197736030 Jun 02 03:06:43 PM PDT 24 Jun 02 03:06:58 PM PDT 24 16299000 ps
T1133 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3924061665 Jun 02 03:07:07 PM PDT 24 Jun 02 03:07:20 PM PDT 24 24079600 ps
T1134 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3584786466 Jun 02 03:06:55 PM PDT 24 Jun 02 03:07:11 PM PDT 24 15515300 ps
T1135 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1708325430 Jun 02 03:06:50 PM PDT 24 Jun 02 03:07:09 PM PDT 24 97486500 ps
T1136 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.888728086 Jun 02 03:06:47 PM PDT 24 Jun 02 03:07:01 PM PDT 24 17251700 ps
T1137 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.295387789 Jun 02 03:06:57 PM PDT 24 Jun 02 03:07:13 PM PDT 24 12463800 ps
T1138 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4131163948 Jun 02 03:06:46 PM PDT 24 Jun 02 03:07:03 PM PDT 24 42956200 ps
T372 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3108492046 Jun 02 03:07:08 PM PDT 24 Jun 02 03:14:45 PM PDT 24 1603483200 ps
T369 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2962924108 Jun 02 03:06:40 PM PDT 24 Jun 02 03:21:48 PM PDT 24 8671310200 ps
T1139 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2863948588 Jun 02 03:06:42 PM PDT 24 Jun 02 03:06:56 PM PDT 24 47356700 ps
T1140 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2022020413 Jun 02 03:07:04 PM PDT 24 Jun 02 03:07:33 PM PDT 24 112968800 ps
T308 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.744258234 Jun 02 03:07:02 PM PDT 24 Jun 02 03:07:18 PM PDT 24 208188700 ps
T1141 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3139134940 Jun 02 03:07:15 PM PDT 24 Jun 02 03:07:29 PM PDT 24 15915500 ps
T1142 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1439183332 Jun 02 03:07:18 PM PDT 24 Jun 02 03:07:31 PM PDT 24 17171600 ps
T1143 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3234408822 Jun 02 03:06:58 PM PDT 24 Jun 02 03:07:14 PM PDT 24 38773000 ps
T1144 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.911083936 Jun 02 03:07:17 PM PDT 24 Jun 02 03:07:31 PM PDT 24 48698400 ps
T272 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2545210896 Jun 02 03:06:43 PM PDT 24 Jun 02 03:07:00 PM PDT 24 103502400 ps
T273 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1017784526 Jun 02 03:06:58 PM PDT 24 Jun 02 03:07:15 PM PDT 24 68250000 ps
T1145 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3922904522 Jun 02 03:07:05 PM PDT 24 Jun 02 03:07:22 PM PDT 24 38095800 ps
T368 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.144067475 Jun 02 03:07:00 PM PDT 24 Jun 02 03:21:57 PM PDT 24 1540455200 ps
T1146 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3132654741 Jun 02 03:06:50 PM PDT 24 Jun 02 03:07:06 PM PDT 24 32721700 ps
T1147 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3500809983 Jun 02 03:06:52 PM PDT 24 Jun 02 03:07:09 PM PDT 24 57742200 ps
T1148 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.243359522 Jun 02 03:07:12 PM PDT 24 Jun 02 03:07:29 PM PDT 24 19714000 ps
T1149 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4271978613 Jun 02 03:06:42 PM PDT 24 Jun 02 03:06:57 PM PDT 24 21869700 ps
T1150 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.493416693 Jun 02 03:07:13 PM PDT 24 Jun 02 03:07:27 PM PDT 24 20472900 ps
T1151 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.4113314525 Jun 02 03:06:41 PM PDT 24 Jun 02 03:06:55 PM PDT 24 16530800 ps
T1152 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.829222360 Jun 02 03:07:10 PM PDT 24 Jun 02 03:07:45 PM PDT 24 163365600 ps
T1153 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2530511691 Jun 02 03:06:49 PM PDT 24 Jun 02 03:07:03 PM PDT 24 48507700 ps
T1154 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2708608730 Jun 02 03:07:17 PM PDT 24 Jun 02 03:07:31 PM PDT 24 17525000 ps
T268 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.649725569 Jun 02 03:06:57 PM PDT 24 Jun 02 03:07:15 PM PDT 24 42723400 ps
T1155 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3679603792 Jun 02 03:07:11 PM PDT 24 Jun 02 03:07:29 PM PDT 24 177188300 ps
T1156 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.768918681 Jun 02 03:07:18 PM PDT 24 Jun 02 03:07:32 PM PDT 24 18613200 ps
T1157 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1418019759 Jun 02 03:06:42 PM PDT 24 Jun 02 03:06:59 PM PDT 24 25649000 ps
T1158 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2008782105 Jun 02 03:07:15 PM PDT 24 Jun 02 03:07:29 PM PDT 24 120528400 ps
T1159 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2992074199 Jun 02 03:06:51 PM PDT 24 Jun 02 03:07:05 PM PDT 24 267497300 ps
T276 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1219849359 Jun 02 03:06:50 PM PDT 24 Jun 02 03:07:06 PM PDT 24 36688400 ps
T1160 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.412849449 Jun 02 03:06:58 PM PDT 24 Jun 02 03:07:13 PM PDT 24 31606700 ps
T1161 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.816018458 Jun 02 03:07:01 PM PDT 24 Jun 02 03:07:15 PM PDT 24 16824800 ps
T1162 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.478638719 Jun 02 03:07:21 PM PDT 24 Jun 02 03:07:35 PM PDT 24 189627500 ps
T1163 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.4170786929 Jun 02 03:07:07 PM PDT 24 Jun 02 03:07:24 PM PDT 24 106265000 ps
T1164 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2331101506 Jun 02 03:07:07 PM PDT 24 Jun 02 03:07:23 PM PDT 24 96734100 ps
T239 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3770755578 Jun 02 03:06:44 PM PDT 24 Jun 02 03:06:59 PM PDT 24 39598100 ps
T1165 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3808278219 Jun 02 03:06:51 PM PDT 24 Jun 02 03:07:08 PM PDT 24 59189800 ps
T1166 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.989177459 Jun 02 03:06:44 PM PDT 24 Jun 02 03:06:58 PM PDT 24 67907800 ps
T1167 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.849035776 Jun 02 03:07:20 PM PDT 24 Jun 02 03:07:34 PM PDT 24 254040500 ps
T370 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.511829452 Jun 02 03:07:06 PM PDT 24 Jun 02 03:14:45 PM PDT 24 1553872300 ps
T1168 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3432063244 Jun 02 03:06:49 PM PDT 24 Jun 02 03:07:05 PM PDT 24 24208000 ps
T1169 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2951121015 Jun 02 03:06:49 PM PDT 24 Jun 02 03:07:24 PM PDT 24 62014600 ps
T1170 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.293823933 Jun 02 03:07:02 PM PDT 24 Jun 02 03:07:21 PM PDT 24 452274700 ps
T1171 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2920986927 Jun 02 03:06:55 PM PDT 24 Jun 02 03:07:11 PM PDT 24 14618000 ps
T1172 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3870217295 Jun 02 03:07:13 PM PDT 24 Jun 02 03:07:30 PM PDT 24 67506100 ps
T1173 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1675139453 Jun 02 03:07:02 PM PDT 24 Jun 02 03:07:15 PM PDT 24 16252700 ps
T1174 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.505220872 Jun 02 03:06:52 PM PDT 24 Jun 02 03:07:07 PM PDT 24 17436200 ps
T1175 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3750983846 Jun 02 03:07:13 PM PDT 24 Jun 02 03:07:32 PM PDT 24 1146354000 ps
T1176 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1412645504 Jun 02 03:06:56 PM PDT 24 Jun 02 03:07:13 PM PDT 24 33281500 ps
T1177 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.4213189785 Jun 02 03:07:13 PM PDT 24 Jun 02 03:07:28 PM PDT 24 25806100 ps
T1178 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3177494101 Jun 02 03:07:13 PM PDT 24 Jun 02 03:07:27 PM PDT 24 54556100 ps
T1179 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.400253495 Jun 02 03:06:48 PM PDT 24 Jun 02 03:07:08 PM PDT 24 435317000 ps
T1180 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1357881948 Jun 02 03:06:52 PM PDT 24 Jun 02 03:07:14 PM PDT 24 68177400 ps
T1181 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2628524009 Jun 02 03:06:58 PM PDT 24 Jun 02 03:07:13 PM PDT 24 15898800 ps
T1182 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2921177272 Jun 02 03:07:11 PM PDT 24 Jun 02 03:07:26 PM PDT 24 47335200 ps
T1183 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1169190592 Jun 02 03:06:54 PM PDT 24 Jun 02 03:07:14 PM PDT 24 46775600 ps
T1184 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2257364699 Jun 02 03:07:21 PM PDT 24 Jun 02 03:07:35 PM PDT 24 16040300 ps
T1185 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1838801533 Jun 02 03:07:05 PM PDT 24 Jun 02 03:07:20 PM PDT 24 70143500 ps
T1186 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3245606890 Jun 02 03:06:51 PM PDT 24 Jun 02 03:07:06 PM PDT 24 61670200 ps
T1187 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3070255808 Jun 02 03:06:58 PM PDT 24 Jun 02 03:07:14 PM PDT 24 35168400 ps
T1188 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4256401087 Jun 02 03:06:42 PM PDT 24 Jun 02 03:07:25 PM PDT 24 633373800 ps
T1189 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.14587714 Jun 02 03:07:11 PM PDT 24 Jun 02 03:07:29 PM PDT 24 50901900 ps
T1190 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.4195518794 Jun 02 03:07:05 PM PDT 24 Jun 02 03:07:23 PM PDT 24 89282700 ps
T1191 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3622140843 Jun 02 03:07:12 PM PDT 24 Jun 02 03:07:30 PM PDT 24 1173844400 ps
T1192 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2408075591 Jun 02 03:07:00 PM PDT 24 Jun 02 03:14:42 PM PDT 24 424288400 ps
T1193 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2746018763 Jun 02 03:07:13 PM PDT 24 Jun 02 03:07:32 PM PDT 24 47231100 ps
T1194 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2741544786 Jun 02 03:07:06 PM PDT 24 Jun 02 03:07:22 PM PDT 24 16337200 ps
T1195 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.945197753 Jun 02 03:06:41 PM PDT 24 Jun 02 03:06:56 PM PDT 24 28603600 ps
T1196 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2237312332 Jun 02 03:06:40 PM PDT 24 Jun 02 03:07:26 PM PDT 24 57551000 ps
T1197 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3320841848 Jun 02 03:06:44 PM PDT 24 Jun 02 03:07:01 PM PDT 24 24055500 ps
T1198 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1201743928 Jun 02 03:07:15 PM PDT 24 Jun 02 03:07:34 PM PDT 24 39092500 ps
T1199 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.864556240 Jun 02 03:06:50 PM PDT 24 Jun 02 03:07:11 PM PDT 24 87634500 ps
T1200 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.4134797689 Jun 02 03:06:41 PM PDT 24 Jun 02 03:06:56 PM PDT 24 393484400 ps
T1201 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2142912873 Jun 02 03:07:00 PM PDT 24 Jun 02 03:07:19 PM PDT 24 83353500 ps
T1202 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2434762144 Jun 02 03:06:52 PM PDT 24 Jun 02 03:07:09 PM PDT 24 11992100 ps
T1203 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2864125587 Jun 02 03:07:15 PM PDT 24 Jun 02 03:07:29 PM PDT 24 53452200 ps
T1204 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.250843826 Jun 02 03:07:03 PM PDT 24 Jun 02 03:07:19 PM PDT 24 13824900 ps
T1205 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3931566302 Jun 02 03:07:16 PM PDT 24 Jun 02 03:07:30 PM PDT 24 74641500 ps
T1206 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1467198846 Jun 02 03:07:02 PM PDT 24 Jun 02 03:07:17 PM PDT 24 62568200 ps
T1207 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.600080288 Jun 02 03:07:03 PM PDT 24 Jun 02 03:07:17 PM PDT 24 32485600 ps
T1208 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.868334752 Jun 02 03:06:49 PM PDT 24 Jun 02 03:07:35 PM PDT 24 129878200 ps
T1209 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3536151351 Jun 02 03:06:40 PM PDT 24 Jun 02 03:06:58 PM PDT 24 41508200 ps
T1210 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.10125215 Jun 02 03:07:00 PM PDT 24 Jun 02 03:07:34 PM PDT 24 238071800 ps
T1211 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1748503417 Jun 02 03:07:02 PM PDT 24 Jun 02 03:07:18 PM PDT 24 42415900 ps
T371 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.628394749 Jun 02 03:06:45 PM PDT 24 Jun 02 03:21:35 PM PDT 24 2781803300 ps
T1212 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3796254069 Jun 02 03:06:52 PM PDT 24 Jun 02 03:07:08 PM PDT 24 61720800 ps
T1213 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.4220730044 Jun 02 03:06:56 PM PDT 24 Jun 02 03:07:16 PM PDT 24 113186100 ps
T1214 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2720230209 Jun 02 03:07:02 PM PDT 24 Jun 02 03:07:19 PM PDT 24 84463300 ps
T1215 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.169105030 Jun 02 03:07:15 PM PDT 24 Jun 02 03:07:29 PM PDT 24 36994200 ps
T1216 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2643019022 Jun 02 03:06:46 PM PDT 24 Jun 02 03:07:48 PM PDT 24 865110200 ps
T1217 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3490432121 Jun 02 03:06:40 PM PDT 24 Jun 02 03:07:26 PM PDT 24 85459200 ps
T1218 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1831404362 Jun 02 03:07:01 PM PDT 24 Jun 02 03:07:17 PM PDT 24 31853400 ps
T1219 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.4288780008 Jun 02 03:06:55 PM PDT 24 Jun 02 03:07:11 PM PDT 24 33384000 ps
T1220 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1762710783 Jun 02 03:06:52 PM PDT 24 Jun 02 03:07:10 PM PDT 24 74327700 ps
T1221 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1016449130 Jun 02 03:06:43 PM PDT 24 Jun 02 03:07:05 PM PDT 24 251389200 ps
T1222 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2286513734 Jun 02 03:06:53 PM PDT 24 Jun 02 03:07:07 PM PDT 24 58442500 ps
T1223 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3649231133 Jun 02 03:06:46 PM PDT 24 Jun 02 03:07:06 PM PDT 24 98948800 ps
T1224 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2142367542 Jun 02 03:07:12 PM PDT 24 Jun 02 03:07:28 PM PDT 24 11191200 ps
T1225 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1797146397 Jun 02 03:07:13 PM PDT 24 Jun 02 03:07:27 PM PDT 24 21485400 ps
T1226 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2716927261 Jun 02 03:06:50 PM PDT 24 Jun 02 03:07:36 PM PDT 24 1666409700 ps
T1227 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3851044480 Jun 02 03:06:40 PM PDT 24 Jun 02 03:07:33 PM PDT 24 533612800 ps
T1228 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.650894539 Jun 02 03:06:45 PM PDT 24 Jun 02 03:07:01 PM PDT 24 30656000 ps
T1229 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1763643329 Jun 02 03:07:14 PM PDT 24 Jun 02 03:07:28 PM PDT 24 34520800 ps

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.3344826933
Short name T9
Test name
Test status
Simulation time 1108570000 ps
CPU time 163.81 seconds
Started Jun 02 03:19:52 PM PDT 24
Finished Jun 02 03:22:36 PM PDT 24
Peak memory 281180 kb
Host smart-c19bd6e0-bfcd-429a-b3fd-87ed7fb6e88c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344826933 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.3344826933
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.3284103571
Short name T67
Test name
Test status
Simulation time 3015180900 ps
CPU time 140.91 seconds
Started Jun 02 03:22:41 PM PDT 24
Finished Jun 02 03:25:02 PM PDT 24
Peak memory 262536 kb
Host smart-7f69b013-7290-4cf3-90f7-e6b559bfdfc0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284103571 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.3284103571
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.519704905
Short name T208
Test name
Test status
Simulation time 1691826900 ps
CPU time 754.04 seconds
Started Jun 02 03:07:03 PM PDT 24
Finished Jun 02 03:19:38 PM PDT 24
Peak memory 264212 kb
Host smart-51225113-b9c9-4ba5-ad55-f98851bc82b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519704905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl
_tl_intg_err.519704905
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.364714388
Short name T3
Test name
Test status
Simulation time 64935000 ps
CPU time 132.55 seconds
Started Jun 02 03:23:31 PM PDT 24
Finished Jun 02 03:25:44 PM PDT 24
Peak memory 259500 kb
Host smart-2f0d42ab-b423-487c-a2bb-6611331966e9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364714388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ot
p_reset.364714388
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.1040988740
Short name T80
Test name
Test status
Simulation time 317104250500 ps
CPU time 1997.37 seconds
Started Jun 02 03:18:51 PM PDT 24
Finished Jun 02 03:52:09 PM PDT 24
Peak memory 263652 kb
Host smart-c8c9be93-cce7-49d9-8827-f04e89b58b7b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040988740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.1040988740
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.3723278177
Short name T24
Test name
Test status
Simulation time 30559800 ps
CPU time 31.27 seconds
Started Jun 02 03:24:55 PM PDT 24
Finished Jun 02 03:25:26 PM PDT 24
Peak memory 273108 kb
Host smart-eb0c32ae-7bf6-41b1-9b7a-92e3775bc583
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723278177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.3723278177
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.3151942205
Short name T15
Test name
Test status
Simulation time 1023706400 ps
CPU time 4841.41 seconds
Started Jun 02 03:19:58 PM PDT 24
Finished Jun 02 04:40:41 PM PDT 24
Peak memory 282832 kb
Host smart-da3468f2-dbfc-4c0f-9141-56ec8b767996
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151942205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3151942205
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.851295155
Short name T53
Test name
Test status
Simulation time 840078000 ps
CPU time 71.32 seconds
Started Jun 02 03:19:23 PM PDT 24
Finished Jun 02 03:20:34 PM PDT 24
Peak memory 260516 kb
Host smart-7a87ca3a-ffc0-47d1-b2ca-f620cde323fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851295155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.851295155
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.2708069469
Short name T21
Test name
Test status
Simulation time 5050770400 ps
CPU time 732.21 seconds
Started Jun 02 03:18:45 PM PDT 24
Finished Jun 02 03:30:58 PM PDT 24
Peak memory 335056 kb
Host smart-f349aab6-a423-4636-b1cb-1ecf598a18c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708069469 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.2708069469
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.2558398651
Short name T159
Test name
Test status
Simulation time 5573718100 ps
CPU time 361.12 seconds
Started Jun 02 03:19:06 PM PDT 24
Finished Jun 02 03:25:07 PM PDT 24
Peak memory 262780 kb
Host smart-43dc629f-f2e3-41b9-8a09-6153df5de68c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558398651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.2558398651
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.2856697149
Short name T11
Test name
Test status
Simulation time 24843900 ps
CPU time 13.86 seconds
Started Jun 02 03:19:58 PM PDT 24
Finished Jun 02 03:20:13 PM PDT 24
Peak memory 261784 kb
Host smart-c63de933-7ad6-4be8-9c21-c088eb5434c0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856697149 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.2856697149
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.322355939
Short name T228
Test name
Test status
Simulation time 62347300 ps
CPU time 20.32 seconds
Started Jun 02 03:07:08 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 264220 kb
Host smart-0a046eca-2e73-4cb4-815a-101dfb55c9ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322355939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.322355939
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.304280311
Short name T102
Test name
Test status
Simulation time 90143905100 ps
CPU time 824.27 seconds
Started Jun 02 03:22:55 PM PDT 24
Finished Jun 02 03:36:40 PM PDT 24
Peak memory 263784 kb
Host smart-547b47ca-69f8-40c1-af0b-46850e4d64e9
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304280311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.flash_ctrl_hw_rma_reset.304280311
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.118756882
Short name T13
Test name
Test status
Simulation time 145691300 ps
CPU time 111.8 seconds
Started Jun 02 03:24:07 PM PDT 24
Finished Jun 02 03:25:59 PM PDT 24
Peak memory 264112 kb
Host smart-158343c5-1d4d-4b33-95d2-74a12f3a418a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118756882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ot
p_reset.118756882
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.2619269523
Short name T8
Test name
Test status
Simulation time 3128235900 ps
CPU time 64.78 seconds
Started Jun 02 03:25:23 PM PDT 24
Finished Jun 02 03:26:29 PM PDT 24
Peak memory 263032 kb
Host smart-bbd7d06b-146a-4158-8f15-7b27ac607d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619269523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.2619269523
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3052396404
Short name T266
Test name
Test status
Simulation time 53108600 ps
CPU time 13.44 seconds
Started Jun 02 03:07:12 PM PDT 24
Finished Jun 02 03:07:26 PM PDT 24
Peak memory 262684 kb
Host smart-0686bd77-f416-458b-8c6a-93918c9e7d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052396404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
3052396404
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.1042358243
Short name T137
Test name
Test status
Simulation time 39080300 ps
CPU time 131.49 seconds
Started Jun 02 03:25:33 PM PDT 24
Finished Jun 02 03:27:46 PM PDT 24
Peak memory 260900 kb
Host smart-9f6a12bb-c762-4f84-b9f7-e243a19ea299
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042358243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.1042358243
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2990737320
Short name T135
Test name
Test status
Simulation time 10020201600 ps
CPU time 91.65 seconds
Started Jun 02 03:19:02 PM PDT 24
Finished Jun 02 03:20:34 PM PDT 24
Peak memory 331484 kb
Host smart-a7519beb-d096-487e-878e-91a2f1710e4e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990737320 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2990737320
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.590125318
Short name T311
Test name
Test status
Simulation time 2509420400 ps
CPU time 194.96 seconds
Started Jun 02 03:22:36 PM PDT 24
Finished Jun 02 03:25:51 PM PDT 24
Peak memory 262412 kb
Host smart-e1075b74-b75d-4828-ad5b-eed826d5e7e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590125318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_h
w_sec_otp.590125318
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1934511066
Short name T32
Test name
Test status
Simulation time 36256621200 ps
CPU time 133.45 seconds
Started Jun 02 03:25:05 PM PDT 24
Finished Jun 02 03:27:20 PM PDT 24
Peak memory 291804 kb
Host smart-4a0cb3c5-7901-4bbb-a99c-b78cecce2eef
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934511066 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.1934511066
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.1466601569
Short name T74
Test name
Test status
Simulation time 10851871300 ps
CPU time 321.91 seconds
Started Jun 02 03:21:26 PM PDT 24
Finished Jun 02 03:26:49 PM PDT 24
Peak memory 272604 kb
Host smart-c855c83e-c8e4-4bf9-85f9-93de0791f48c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466601569 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.1466601569
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.101730066
Short name T85
Test name
Test status
Simulation time 11335300 ps
CPU time 21.88 seconds
Started Jun 02 03:18:57 PM PDT 24
Finished Jun 02 03:19:20 PM PDT 24
Peak memory 264968 kb
Host smart-76141dea-e6f1-44a0-babb-6034af4f462b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101730066 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.101730066
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.1020955742
Short name T52
Test name
Test status
Simulation time 4861747500 ps
CPU time 30.78 seconds
Started Jun 02 03:20:05 PM PDT 24
Finished Jun 02 03:20:37 PM PDT 24
Peak memory 264888 kb
Host smart-d8e60e3c-c930-4c50-b33c-aeb1be9783e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020955742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.1020955742
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.1330993003
Short name T331
Test name
Test status
Simulation time 32575900 ps
CPU time 14.2 seconds
Started Jun 02 03:21:50 PM PDT 24
Finished Jun 02 03:22:05 PM PDT 24
Peak memory 257836 kb
Host smart-2b81a982-e63a-4670-a9ad-fd8217560614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330993003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
1330993003
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.2713120766
Short name T165
Test name
Test status
Simulation time 15826700 ps
CPU time 14 seconds
Started Jun 02 03:19:07 PM PDT 24
Finished Jun 02 03:19:22 PM PDT 24
Peak memory 261840 kb
Host smart-2b11649c-15ad-404a-9007-acadee377760
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713120766 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.2713120766
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.1159529872
Short name T144
Test name
Test status
Simulation time 42003552500 ps
CPU time 853.53 seconds
Started Jun 02 03:18:47 PM PDT 24
Finished Jun 02 03:33:01 PM PDT 24
Peak memory 259020 kb
Host smart-b5c94018-8c54-474d-90f8-8ba577b89984
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159529872 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.1159529872
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.1260449137
Short name T161
Test name
Test status
Simulation time 1016492400 ps
CPU time 72.08 seconds
Started Jun 02 03:19:10 PM PDT 24
Finished Jun 02 03:20:22 PM PDT 24
Peak memory 260576 kb
Host smart-00823de5-357e-4042-97f5-7a06ba1171a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260449137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.1260449137
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.15459151
Short name T157
Test name
Test status
Simulation time 11881068700 ps
CPU time 82.14 seconds
Started Jun 02 03:18:56 PM PDT 24
Finished Jun 02 03:20:18 PM PDT 24
Peak memory 259652 kb
Host smart-d2ab2145-f653-4ce1-a573-660b44b27d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15459151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.15459151
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1787135437
Short name T68
Test name
Test status
Simulation time 100524900 ps
CPU time 17.15 seconds
Started Jun 02 03:06:40 PM PDT 24
Finished Jun 02 03:06:58 PM PDT 24
Peak memory 260672 kb
Host smart-676c5087-417a-419c-952c-def0abef774b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787135437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.1787135437
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.338323745
Short name T60
Test name
Test status
Simulation time 117229200 ps
CPU time 31.76 seconds
Started Jun 02 03:21:44 PM PDT 24
Finished Jun 02 03:22:16 PM PDT 24
Peak memory 270296 kb
Host smart-fbd9e95f-99f1-4ab7-bae6-6c0f78df9e64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338323745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_re_evict.338323745
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.1999876153
Short name T352
Test name
Test status
Simulation time 1709415400 ps
CPU time 288.62 seconds
Started Jun 02 03:20:43 PM PDT 24
Finished Jun 02 03:25:32 PM PDT 24
Peak memory 283592 kb
Host smart-bc72ebdc-3784-4efd-9c24-f65149734b72
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999876153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.1999876153
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1949236796
Short name T627
Test name
Test status
Simulation time 153490400 ps
CPU time 13.39 seconds
Started Jun 02 03:21:23 PM PDT 24
Finished Jun 02 03:21:37 PM PDT 24
Peak memory 260108 kb
Host smart-cf7485a0-725f-43a3-a140-8bd115d3b889
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949236796 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1949236796
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.4140577441
Short name T176
Test name
Test status
Simulation time 11698252900 ps
CPU time 449.81 seconds
Started Jun 02 03:19:18 PM PDT 24
Finished Jun 02 03:26:48 PM PDT 24
Peak memory 309176 kb
Host smart-a7ebe5bd-6a2a-41a1-aeda-fdb0f82e57b8
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140577441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_rw.4140577441
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.1745710781
Short name T87
Test name
Test status
Simulation time 4395942700 ps
CPU time 74.36 seconds
Started Jun 02 03:20:05 PM PDT 24
Finished Jun 02 03:21:21 PM PDT 24
Peak memory 260560 kb
Host smart-16efba90-d626-4f7c-bd02-ac4c31ae6404
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745710781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1745710781
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.125593665
Short name T237
Test name
Test status
Simulation time 18529700 ps
CPU time 13.84 seconds
Started Jun 02 03:06:41 PM PDT 24
Finished Jun 02 03:06:56 PM PDT 24
Peak memory 263984 kb
Host smart-09de3087-c2d6-43f1-a5c3-fdc27d9da4f9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125593665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_mem_partial_access.125593665
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3904554726
Short name T227
Test name
Test status
Simulation time 189756400 ps
CPU time 19.18 seconds
Started Jun 02 03:07:12 PM PDT 24
Finished Jun 02 03:07:31 PM PDT 24
Peak memory 264148 kb
Host smart-1cd6af7c-b3fd-4325-9f9f-ab8019b8b276
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904554726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
3904554726
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.1972410129
Short name T203
Test name
Test status
Simulation time 15978793800 ps
CPU time 125.35 seconds
Started Jun 02 03:25:11 PM PDT 24
Finished Jun 02 03:27:17 PM PDT 24
Peak memory 262392 kb
Host smart-8b6bd53c-fde0-4e18-a455-443f773dcaa2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972410129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.1972410129
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.1730285986
Short name T10
Test name
Test status
Simulation time 52093800 ps
CPU time 15.24 seconds
Started Jun 02 03:19:03 PM PDT 24
Finished Jun 02 03:19:19 PM PDT 24
Peak memory 264708 kb
Host smart-d63b44a2-095d-4cbc-8473-c00751ef5abf
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730285986 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.1730285986
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3637700547
Short name T196
Test name
Test status
Simulation time 12405327200 ps
CPU time 273.14 seconds
Started Jun 02 03:22:34 PM PDT 24
Finished Jun 02 03:27:08 PM PDT 24
Peak memory 292852 kb
Host smart-0eb302a5-155f-4e34-a580-1f4919419eb9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637700547 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.3637700547
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.3280263631
Short name T55
Test name
Test status
Simulation time 15042400 ps
CPU time 13.56 seconds
Started Jun 02 03:19:58 PM PDT 24
Finished Jun 02 03:20:12 PM PDT 24
Peak memory 264880 kb
Host smart-93902c05-0d71-494d-8326-2d9ba4718b35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280263631 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.3280263631
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1023324144
Short name T280
Test name
Test status
Simulation time 360443600 ps
CPU time 457.14 seconds
Started Jun 02 03:06:44 PM PDT 24
Finished Jun 02 03:14:22 PM PDT 24
Peak memory 264156 kb
Host smart-51ea569f-0acf-449a-bef8-50ae7f8054a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023324144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.1023324144
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3759582454
Short name T349
Test name
Test status
Simulation time 76122900 ps
CPU time 13.22 seconds
Started Jun 02 03:07:05 PM PDT 24
Finished Jun 02 03:07:18 PM PDT 24
Peak memory 262504 kb
Host smart-b2ee30f8-0436-4d55-b8ec-c8a9b2cdebbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759582454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
3759582454
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.3937195629
Short name T91
Test name
Test status
Simulation time 11931971500 ps
CPU time 270.1 seconds
Started Jun 02 03:22:40 PM PDT 24
Finished Jun 02 03:27:11 PM PDT 24
Peak memory 273904 kb
Host smart-f496269b-66ce-4724-a6df-2ab0e3f8e04b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937195629 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.3937195629
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.2413132162
Short name T168
Test name
Test status
Simulation time 3134019300 ps
CPU time 4924.11 seconds
Started Jun 02 03:19:01 PM PDT 24
Finished Jun 02 04:41:06 PM PDT 24
Peak memory 289128 kb
Host smart-21fca86a-899d-49ba-acc2-9e54e868dc6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413132162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.2413132162
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.848736804
Short name T340
Test name
Test status
Simulation time 8152522800 ps
CPU time 553.78 seconds
Started Jun 02 03:20:55 PM PDT 24
Finished Jun 02 03:30:09 PM PDT 24
Peak memory 309452 kb
Host smart-a9bf8370-2b79-4f7d-a9ae-a7c089bd6b6f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848736804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.flash_ctrl_rw.848736804
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.130564309
Short name T769
Test name
Test status
Simulation time 931732200 ps
CPU time 2600.26 seconds
Started Jun 02 03:19:03 PM PDT 24
Finished Jun 02 04:02:24 PM PDT 24
Peak memory 264692 kb
Host smart-8c0905f8-2ee8-474b-9030-ae45ea761a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130564309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.130564309
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2030384782
Short name T281
Test name
Test status
Simulation time 169700500 ps
CPU time 18.19 seconds
Started Jun 02 03:07:02 PM PDT 24
Finished Jun 02 03:07:20 PM PDT 24
Peak memory 271528 kb
Host smart-2098a610-fb24-4d01-a4b6-8b99d151a543
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030384782 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.2030384782
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.1609861182
Short name T65
Test name
Test status
Simulation time 14900000 ps
CPU time 14.02 seconds
Started Jun 02 03:19:01 PM PDT 24
Finished Jun 02 03:19:16 PM PDT 24
Peak memory 276296 kb
Host smart-c578992d-1cd3-4abb-a5db-3db6f26323e2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1609861182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1609861182
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.785354423
Short name T78
Test name
Test status
Simulation time 636061200 ps
CPU time 24.79 seconds
Started Jun 02 03:19:06 PM PDT 24
Finished Jun 02 03:19:32 PM PDT 24
Peak memory 264552 kb
Host smart-e2175864-f788-436e-9fef-8f5721d53799
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785354423 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.785354423
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.4195518794
Short name T1190
Test name
Test status
Simulation time 89282700 ps
CPU time 17.48 seconds
Started Jun 02 03:07:05 PM PDT 24
Finished Jun 02 03:07:23 PM PDT 24
Peak memory 264088 kb
Host smart-e43738f0-2af9-495d-9a4e-95a7888ae740
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195518794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
4195518794
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.3108527540
Short name T457
Test name
Test status
Simulation time 38923500 ps
CPU time 130.22 seconds
Started Jun 02 03:23:58 PM PDT 24
Finished Jun 02 03:26:09 PM PDT 24
Peak memory 264732 kb
Host smart-c7455577-2fb6-4f51-99af-e60108130538
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108527540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.3108527540
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.3729646454
Short name T316
Test name
Test status
Simulation time 78387700 ps
CPU time 132.07 seconds
Started Jun 02 03:25:42 PM PDT 24
Finished Jun 02 03:27:54 PM PDT 24
Peak memory 264236 kb
Host smart-150f8509-c349-4557-b9e6-02be2acf11b4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729646454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.3729646454
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.144067475
Short name T368
Test name
Test status
Simulation time 1540455200 ps
CPU time 896.49 seconds
Started Jun 02 03:07:00 PM PDT 24
Finished Jun 02 03:21:57 PM PDT 24
Peak memory 264164 kb
Host smart-a8b39533-269d-403c-aedc-111dbb7aba57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144067475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_
tl_intg_err.144067475
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.734785797
Short name T400
Test name
Test status
Simulation time 1366767600 ps
CPU time 70.9 seconds
Started Jun 02 03:22:12 PM PDT 24
Finished Jun 02 03:23:23 PM PDT 24
Peak memory 263764 kb
Host smart-cce45458-e35a-47f5-941f-64af7a14358f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734785797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.734785797
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.2559932843
Short name T335
Test name
Test status
Simulation time 2508562700 ps
CPU time 37.35 seconds
Started Jun 02 03:19:15 PM PDT 24
Finished Jun 02 03:19:53 PM PDT 24
Peak memory 261308 kb
Host smart-64869d4e-e8b7-452f-8dfe-fa3d8ea32bec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559932843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.2559932843
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.440533731
Short name T205
Test name
Test status
Simulation time 57386300 ps
CPU time 15.76 seconds
Started Jun 02 03:25:11 PM PDT 24
Finished Jun 02 03:25:28 PM PDT 24
Peak memory 275356 kb
Host smart-432529f7-841b-4f34-b29b-fb0e595fe0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440533731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.440533731
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.2374634987
Short name T173
Test name
Test status
Simulation time 15724500 ps
CPU time 13.36 seconds
Started Jun 02 03:21:43 PM PDT 24
Finished Jun 02 03:21:57 PM PDT 24
Peak memory 258084 kb
Host smart-f5244dbb-8f2c-4352-91f2-27c5ac2453bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374634987 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.2374634987
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.3637865923
Short name T185
Test name
Test status
Simulation time 75579600 ps
CPU time 13.81 seconds
Started Jun 02 03:18:50 PM PDT 24
Finished Jun 02 03:19:04 PM PDT 24
Peak memory 261788 kb
Host smart-a82e2d31-89a8-4c90-bd45-a0e0575a953b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637865923 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.3637865923
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.1463886928
Short name T902
Test name
Test status
Simulation time 15835200 ps
CPU time 13.62 seconds
Started Jun 02 03:18:47 PM PDT 24
Finished Jun 02 03:19:01 PM PDT 24
Peak memory 264796 kb
Host smart-54355e96-0387-4f65-9d6c-f414ebf23dfd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463886928 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.1463886928
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.109714676
Short name T941
Test name
Test status
Simulation time 10040375000 ps
CPU time 97.27 seconds
Started Jun 02 03:21:38 PM PDT 24
Finished Jun 02 03:23:16 PM PDT 24
Peak memory 271396 kb
Host smart-259b584c-5750-40bb-94b4-7efc84a95a5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109714676 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.109714676
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.1938421680
Short name T323
Test name
Test status
Simulation time 10125593600 ps
CPU time 38.01 seconds
Started Jun 02 03:19:15 PM PDT 24
Finished Jun 02 03:19:53 PM PDT 24
Peak memory 262776 kb
Host smart-41cde648-7fa0-473f-958e-f28b346c7c79
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938421680 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.1938421680
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.215729737
Short name T261
Test name
Test status
Simulation time 346775400 ps
CPU time 460.64 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:14:24 PM PDT 24
Peak memory 264256 kb
Host smart-22148cf9-6396-4c92-8bb8-ee57a6790e6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215729737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_
tl_intg_err.215729737
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1341091168
Short name T351
Test name
Test status
Simulation time 34190200 ps
CPU time 13.24 seconds
Started Jun 02 03:07:07 PM PDT 24
Finished Jun 02 03:07:21 PM PDT 24
Peak memory 262880 kb
Host smart-13ac15ef-4882-428e-ac21-22689a765173
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341091168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
1341091168
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.2776075168
Short name T333
Test name
Test status
Simulation time 96039600 ps
CPU time 29.32 seconds
Started Jun 02 03:21:32 PM PDT 24
Finished Jun 02 03:22:01 PM PDT 24
Peak memory 273076 kb
Host smart-6578621c-0083-4c34-9f01-290408896fde
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776075168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_rw_evict.2776075168
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.1276727386
Short name T392
Test name
Test status
Simulation time 1512881400 ps
CPU time 68.2 seconds
Started Jun 02 03:23:15 PM PDT 24
Finished Jun 02 03:24:24 PM PDT 24
Peak memory 264368 kb
Host smart-5ffa9dd2-cf2c-422b-bb91-df74b6f541c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276727386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.1276727386
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.1434457213
Short name T911
Test name
Test status
Simulation time 3560975600 ps
CPU time 72.76 seconds
Started Jun 02 03:24:22 PM PDT 24
Finished Jun 02 03:25:35 PM PDT 24
Peak memory 262140 kb
Host smart-3dfd33d0-bd3f-4c9f-9d7e-0ff11aa7b74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434457213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.1434457213
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.2209797658
Short name T192
Test name
Test status
Simulation time 1788714600 ps
CPU time 120.1 seconds
Started Jun 02 03:23:01 PM PDT 24
Finished Jun 02 03:25:02 PM PDT 24
Peak memory 292764 kb
Host smart-617d6536-22fa-4477-a6bb-b83e1a41f5ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209797658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.2209797658
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.1240251885
Short name T22
Test name
Test status
Simulation time 13977900 ps
CPU time 13.6 seconds
Started Jun 02 03:18:47 PM PDT 24
Finished Jun 02 03:19:01 PM PDT 24
Peak memory 264736 kb
Host smart-7d656bcf-7a07-4df7-9f5c-838d3e250c80
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240251885 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.1240251885
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.1903622414
Short name T874
Test name
Test status
Simulation time 12075443900 ps
CPU time 218.86 seconds
Started Jun 02 03:24:03 PM PDT 24
Finished Jun 02 03:27:43 PM PDT 24
Peak memory 262164 kb
Host smart-e5ea31aa-4a42-498e-ae24-921bcb6e4e95
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903622414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.1903622414
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.317062563
Short name T35
Test name
Test status
Simulation time 624967700 ps
CPU time 41.72 seconds
Started Jun 02 03:19:01 PM PDT 24
Finished Jun 02 03:19:44 PM PDT 24
Peak memory 261916 kb
Host smart-1b6d05b4-9d19-41ad-b2fc-0d466ad84006
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317062563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_fs_sup.317062563
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.314294423
Short name T287
Test name
Test status
Simulation time 592280300 ps
CPU time 137.51 seconds
Started Jun 02 03:18:56 PM PDT 24
Finished Jun 02 03:21:14 PM PDT 24
Peak memory 293080 kb
Host smart-e6fcf901-0265-4f99-9925-e3bddc52a9d9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314294423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash
_ctrl_intr_rd.314294423
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.3891778185
Short name T76
Test name
Test status
Simulation time 814014800 ps
CPU time 17.26 seconds
Started Jun 02 03:19:15 PM PDT 24
Finished Jun 02 03:19:33 PM PDT 24
Peak memory 263192 kb
Host smart-cd2e97fc-9086-4640-9888-5049a3a289fc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891778185 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.3891778185
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.511829452
Short name T370
Test name
Test status
Simulation time 1553872300 ps
CPU time 457.91 seconds
Started Jun 02 03:07:06 PM PDT 24
Finished Jun 02 03:14:45 PM PDT 24
Peak memory 261668 kb
Host smart-f16c8744-f5bf-4ca8-82ea-92963a4a5d4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511829452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl
_tl_intg_err.511829452
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1678058995
Short name T366
Test name
Test status
Simulation time 2702951300 ps
CPU time 756.21 seconds
Started Jun 02 03:07:15 PM PDT 24
Finished Jun 02 03:19:51 PM PDT 24
Peak memory 264180 kb
Host smart-0dcf8d45-8536-4349-94bd-3b7fa7dcd477
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678058995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.1678058995
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2833706843
Short name T274
Test name
Test status
Simulation time 674808700 ps
CPU time 908.71 seconds
Started Jun 02 03:06:48 PM PDT 24
Finished Jun 02 03:21:57 PM PDT 24
Peak memory 260568 kb
Host smart-1e5dfb27-23f1-4cb2-8932-d051d45c5fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833706843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.2833706843
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.2188013593
Short name T309
Test name
Test status
Simulation time 2544403000 ps
CPU time 57.46 seconds
Started Jun 02 03:21:45 PM PDT 24
Finished Jun 02 03:22:43 PM PDT 24
Peak memory 263804 kb
Host smart-02c089ef-48d5-4701-83a6-6b9fca618b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188013593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.2188013593
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.1376713024
Short name T343
Test name
Test status
Simulation time 45266800 ps
CPU time 31.03 seconds
Started Jun 02 03:21:57 PM PDT 24
Finished Jun 02 03:22:29 PM PDT 24
Peak memory 268832 kb
Host smart-1ac72701-ba38-4289-aff2-37cb951a72a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376713024 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.1376713024
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.999302288
Short name T837
Test name
Test status
Simulation time 11945300 ps
CPU time 20.32 seconds
Started Jun 02 03:22:07 PM PDT 24
Finished Jun 02 03:22:28 PM PDT 24
Peak memory 264968 kb
Host smart-acb2ff53-472a-400a-a3b5-76e6a7c56fe2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999302288 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.999302288
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.3899443316
Short name T390
Test name
Test status
Simulation time 19935400 ps
CPU time 21.77 seconds
Started Jun 02 03:22:42 PM PDT 24
Finished Jun 02 03:23:05 PM PDT 24
Peak memory 273420 kb
Host smart-46b4f377-8992-4d42-93ed-b32b6f2506fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899443316 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.3899443316
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.3752097609
Short name T151
Test name
Test status
Simulation time 17322100 ps
CPU time 22 seconds
Started Jun 02 03:19:17 PM PDT 24
Finished Jun 02 03:19:40 PM PDT 24
Peak memory 273288 kb
Host smart-0e1292c4-566e-4e94-be5e-253885dd548f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752097609 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.3752097609
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.428533648
Short name T376
Test name
Test status
Simulation time 11982400 ps
CPU time 21.79 seconds
Started Jun 02 03:23:27 PM PDT 24
Finished Jun 02 03:23:50 PM PDT 24
Peak memory 273076 kb
Host smart-46fe8cb9-7aab-4876-8c27-af5341e847e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428533648 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.428533648
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.1044033275
Short name T406
Test name
Test status
Simulation time 1022359500 ps
CPU time 61.49 seconds
Started Jun 02 03:23:26 PM PDT 24
Finished Jun 02 03:24:28 PM PDT 24
Peak memory 262952 kb
Host smart-3b7528ba-f518-4983-8a39-390f35b952bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044033275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.1044033275
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.2030422243
Short name T841
Test name
Test status
Simulation time 15221300 ps
CPU time 21.39 seconds
Started Jun 02 03:23:35 PM PDT 24
Finished Jun 02 03:23:57 PM PDT 24
Peak memory 273184 kb
Host smart-c3e8f91b-057d-4620-aa5a-0b02bdd5be7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030422243 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.2030422243
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.2818298561
Short name T404
Test name
Test status
Simulation time 5646841400 ps
CPU time 62.35 seconds
Started Jun 02 03:24:02 PM PDT 24
Finished Jun 02 03:25:05 PM PDT 24
Peak memory 263028 kb
Host smart-61b4414a-28df-4481-9bce-f4a5f09046dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818298561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2818298561
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.2721598720
Short name T260
Test name
Test status
Simulation time 19150700 ps
CPU time 13.86 seconds
Started Jun 02 03:19:39 PM PDT 24
Finished Jun 02 03:19:54 PM PDT 24
Peak memory 264760 kb
Host smart-ce120eb1-f715-4439-ba46-978709e7a9fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721598720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.2721598720
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.180152417
Short name T394
Test name
Test status
Simulation time 2436384700 ps
CPU time 64.54 seconds
Started Jun 02 03:25:30 PM PDT 24
Finished Jun 02 03:26:35 PM PDT 24
Peak memory 262896 kb
Host smart-f9ea59ce-f0a4-4fe9-870d-efeffb85f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180152417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.180152417
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.3899474640
Short name T410
Test name
Test status
Simulation time 4679186200 ps
CPU time 67.06 seconds
Started Jun 02 03:20:16 PM PDT 24
Finished Jun 02 03:21:24 PM PDT 24
Peak memory 260436 kb
Host smart-ee0b84dc-b5e8-4168-a746-6cef6428dddb
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899474640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.3899474640
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2059759344
Short name T262
Test name
Test status
Simulation time 81374800 ps
CPU time 17.3 seconds
Started Jun 02 03:07:01 PM PDT 24
Finished Jun 02 03:07:18 PM PDT 24
Peak memory 264248 kb
Host smart-25cd74ad-0d3e-4d33-8970-4ad6df28658b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059759344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
2059759344
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.2928578109
Short name T30
Test name
Test status
Simulation time 5010012900 ps
CPU time 77.04 seconds
Started Jun 02 03:18:40 PM PDT 24
Finished Jun 02 03:19:58 PM PDT 24
Peak memory 260568 kb
Host smart-a2302316-17a9-40c5-a6f6-1909a5e2856b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928578109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.2928578109
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.1879180383
Short name T284
Test name
Test status
Simulation time 58246500 ps
CPU time 102.93 seconds
Started Jun 02 03:18:37 PM PDT 24
Finished Jun 02 03:20:20 PM PDT 24
Peak memory 264948 kb
Host smart-e7bd3de4-3248-4459-b5e7-e417f568d230
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1879180383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.1879180383
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.2708119005
Short name T125
Test name
Test status
Simulation time 180182319100 ps
CPU time 823.53 seconds
Started Jun 02 03:23:08 PM PDT 24
Finished Jun 02 03:36:53 PM PDT 24
Peak memory 263240 kb
Host smart-d41b06f7-bab4-478a-83e1-eecebc8c65b7
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708119005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.2708119005
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.3256934102
Short name T20
Test name
Test status
Simulation time 104750701500 ps
CPU time 2496.9 seconds
Started Jun 02 03:18:41 PM PDT 24
Finished Jun 02 04:00:20 PM PDT 24
Peak memory 262824 kb
Host smart-3b7b550d-e019-4005-99d3-230156cde1d7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256934102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.3256934102
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.4284866469
Short name T222
Test name
Test status
Simulation time 15304000 ps
CPU time 14.33 seconds
Started Jun 02 03:18:49 PM PDT 24
Finished Jun 02 03:19:04 PM PDT 24
Peak memory 260452 kb
Host smart-0336fdbf-bd0b-48c2-bf39-959839276e70
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4284866469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.4284866469
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.2192022156
Short name T756
Test name
Test status
Simulation time 2449763100 ps
CPU time 2337.72 seconds
Started Jun 02 03:18:39 PM PDT 24
Finished Jun 02 03:57:37 PM PDT 24
Peak memory 264872 kb
Host smart-09824df1-b18f-498b-ae0e-e596b988c5de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192022156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.2192022156
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.3920719401
Short name T981
Test name
Test status
Simulation time 1300199300 ps
CPU time 852.63 seconds
Started Jun 02 03:18:40 PM PDT 24
Finished Jun 02 03:32:54 PM PDT 24
Peak memory 264780 kb
Host smart-65f4df1c-af14-485d-8b86-1543c84ab236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920719401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3920719401
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.2914588167
Short name T184
Test name
Test status
Simulation time 351044636100 ps
CPU time 2219.64 seconds
Started Jun 02 03:18:34 PM PDT 24
Finished Jun 02 03:55:35 PM PDT 24
Peak memory 264532 kb
Host smart-54cbc2d3-6f12-4b32-91bc-840048faf1f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914588167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.2914588167
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.222120641
Short name T183
Test name
Test status
Simulation time 9059962100 ps
CPU time 477.69 seconds
Started Jun 02 03:19:01 PM PDT 24
Finished Jun 02 03:27:00 PM PDT 24
Peak memory 311904 kb
Host smart-4c1a4f9c-f183-4819-ad4e-787c9c1108b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222120641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_se
rr.222120641
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3851044480
Short name T1227
Test name
Test status
Simulation time 533612800 ps
CPU time 52.41 seconds
Started Jun 02 03:06:40 PM PDT 24
Finished Jun 02 03:07:33 PM PDT 24
Peak memory 260544 kb
Host smart-7d3c3115-8fd4-4844-bdd2-c9109b5e64ce
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851044480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.3851044480
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1651868002
Short name T69
Test name
Test status
Simulation time 1448315000 ps
CPU time 63.51 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:07:47 PM PDT 24
Peak memory 260508 kb
Host smart-410a100e-23d0-4f5c-9daa-052d8e6aca11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651868002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.1651868002
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.471443904
Short name T304
Test name
Test status
Simulation time 142530400 ps
CPU time 46.59 seconds
Started Jun 02 03:06:49 PM PDT 24
Finished Jun 02 03:07:36 PM PDT 24
Peak memory 260508 kb
Host smart-5afd49a6-d1fb-43ea-af6b-477f17d8f48a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471443904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_hw_reset.471443904
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3536151351
Short name T1209
Test name
Test status
Simulation time 41508200 ps
CPU time 17.1 seconds
Started Jun 02 03:06:40 PM PDT 24
Finished Jun 02 03:06:58 PM PDT 24
Peak memory 272304 kb
Host smart-ab660962-a647-4743-8994-3a9bb784a4b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536151351 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3536151351
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1197736030
Short name T1132
Test name
Test status
Simulation time 16299000 ps
CPU time 13.41 seconds
Started Jun 02 03:06:43 PM PDT 24
Finished Jun 02 03:06:58 PM PDT 24
Peak memory 262632 kb
Host smart-aead4a00-1c63-4520-a52d-21c71f4fc918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197736030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.1
197736030
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3065142313
Short name T1099
Test name
Test status
Simulation time 64295700 ps
CPU time 13.29 seconds
Started Jun 02 03:06:45 PM PDT 24
Finished Jun 02 03:06:59 PM PDT 24
Peak memory 262828 kb
Host smart-95bb70a0-8d73-4e1c-b6fb-31244b162e35
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065142313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.3065142313
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1048933406
Short name T1116
Test name
Test status
Simulation time 38152300 ps
CPU time 16.81 seconds
Started Jun 02 03:06:41 PM PDT 24
Finished Jun 02 03:06:58 PM PDT 24
Peak memory 260600 kb
Host smart-fba86aad-20cd-47f2-9e54-ff9819fe019f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048933406 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.1048933406
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.650894539
Short name T1228
Test name
Test status
Simulation time 30656000 ps
CPU time 15.88 seconds
Started Jun 02 03:06:45 PM PDT 24
Finished Jun 02 03:07:01 PM PDT 24
Peak memory 260540 kb
Host smart-24b81679-59ec-471b-ac3f-045b9bc985c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650894539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.650894539
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4271978613
Short name T1149
Test name
Test status
Simulation time 21869700 ps
CPU time 13.35 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:06:57 PM PDT 24
Peak memory 260496 kb
Host smart-f08b80b5-1bd3-4c31-b7f1-a723d3dd6e62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271978613 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.4271978613
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2545210896
Short name T272
Test name
Test status
Simulation time 103502400 ps
CPU time 15.59 seconds
Started Jun 02 03:06:43 PM PDT 24
Finished Jun 02 03:07:00 PM PDT 24
Peak memory 264128 kb
Host smart-ecae0f38-7f24-41a9-830f-4ebb3574e2c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545210896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.2
545210896
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4256401087
Short name T1188
Test name
Test status
Simulation time 633373800 ps
CPU time 40.93 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:07:25 PM PDT 24
Peak memory 260512 kb
Host smart-8a283b47-1a9f-4359-afae-001fa008be1d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256401087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.4256401087
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1687131333
Short name T302
Test name
Test status
Simulation time 23426380300 ps
CPU time 57.36 seconds
Started Jun 02 03:06:45 PM PDT 24
Finished Jun 02 03:07:44 PM PDT 24
Peak memory 260472 kb
Host smart-4a1e2ba5-1704-46cd-9d7a-b9a4b00d2549
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687131333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.1687131333
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3490432121
Short name T1217
Test name
Test status
Simulation time 85459200 ps
CPU time 45.43 seconds
Started Jun 02 03:06:40 PM PDT 24
Finished Jun 02 03:07:26 PM PDT 24
Peak memory 260472 kb
Host smart-94dd622b-47c7-4c09-bb60-ab634155c451
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490432121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.3490432121
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.435816907
Short name T306
Test name
Test status
Simulation time 108797000 ps
CPU time 17.58 seconds
Started Jun 02 03:06:44 PM PDT 24
Finished Jun 02 03:07:02 PM PDT 24
Peak memory 271296 kb
Host smart-e0370a69-3523-4b0a-becb-b7f00ae2a3d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435816907 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.435816907
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.4134797689
Short name T1200
Test name
Test status
Simulation time 393484400 ps
CPU time 14.34 seconds
Started Jun 02 03:06:41 PM PDT 24
Finished Jun 02 03:06:56 PM PDT 24
Peak memory 260528 kb
Host smart-28fd0e66-b8d7-459c-bef6-702c6bb037c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134797689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.4134797689
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.945197753
Short name T1195
Test name
Test status
Simulation time 28603600 ps
CPU time 13.56 seconds
Started Jun 02 03:06:41 PM PDT 24
Finished Jun 02 03:06:56 PM PDT 24
Peak memory 262884 kb
Host smart-a6b0deb9-9245-4194-89aa-556a087223b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945197753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.945197753
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3770755578
Short name T239
Test name
Test status
Simulation time 39598100 ps
CPU time 13.52 seconds
Started Jun 02 03:06:44 PM PDT 24
Finished Jun 02 03:06:59 PM PDT 24
Peak memory 264032 kb
Host smart-72e90590-1711-485c-be26-d3876096bd67
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770755578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.3770755578
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2863948588
Short name T1139
Test name
Test status
Simulation time 47356700 ps
CPU time 13.45 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:06:56 PM PDT 24
Peak memory 262820 kb
Host smart-59325346-6a6e-4052-890e-c45ed371573c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863948588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.2863948588
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3207316509
Short name T1123
Test name
Test status
Simulation time 35047700 ps
CPU time 14.75 seconds
Started Jun 02 03:06:45 PM PDT 24
Finished Jun 02 03:07:00 PM PDT 24
Peak memory 260652 kb
Host smart-d5dd0682-a716-47ea-9955-6428769016e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207316509 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.3207316509
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.327083232
Short name T1112
Test name
Test status
Simulation time 13912500 ps
CPU time 15.91 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:06:59 PM PDT 24
Peak memory 260484 kb
Host smart-1e12c960-5a64-4633-a4e8-4308c13e3abb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327083232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.327083232
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.989177459
Short name T1166
Test name
Test status
Simulation time 67907800 ps
CPU time 13.92 seconds
Started Jun 02 03:06:44 PM PDT 24
Finished Jun 02 03:06:58 PM PDT 24
Peak memory 260540 kb
Host smart-90878893-07e3-40a6-92da-54a9fd2cf7a9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989177459 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.989177459
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.462002682
Short name T271
Test name
Test status
Simulation time 178567600 ps
CPU time 19.03 seconds
Started Jun 02 03:06:43 PM PDT 24
Finished Jun 02 03:07:03 PM PDT 24
Peak memory 264148 kb
Host smart-578dba84-e721-4005-90c5-6bc07551e1d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462002682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.462002682
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.22566087
Short name T231
Test name
Test status
Simulation time 52358800 ps
CPU time 15.11 seconds
Started Jun 02 03:06:55 PM PDT 24
Finished Jun 02 03:07:11 PM PDT 24
Peak memory 272356 kb
Host smart-0a584cf5-9904-450e-a82d-28e09557122e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22566087 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.22566087
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2720230209
Short name T1214
Test name
Test status
Simulation time 84463300 ps
CPU time 16.63 seconds
Started Jun 02 03:07:02 PM PDT 24
Finished Jun 02 03:07:19 PM PDT 24
Peak memory 260644 kb
Host smart-5c13b633-4d71-4df2-8136-ae893e12492b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720230209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.2720230209
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.412849449
Short name T1160
Test name
Test status
Simulation time 31606700 ps
CPU time 14.06 seconds
Started Jun 02 03:06:58 PM PDT 24
Finished Jun 02 03:07:13 PM PDT 24
Peak memory 261740 kb
Host smart-b4e6e9aa-4066-4fee-a195-8e136dde152c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412849449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.412849449
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2460952636
Short name T70
Test name
Test status
Simulation time 35753100 ps
CPU time 14.86 seconds
Started Jun 02 03:07:00 PM PDT 24
Finished Jun 02 03:07:15 PM PDT 24
Peak memory 262880 kb
Host smart-7443cab6-a309-4b4c-9bcb-3085d5687058
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460952636 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.2460952636
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.4288780008
Short name T1219
Test name
Test status
Simulation time 33384000 ps
CPU time 15.26 seconds
Started Jun 02 03:06:55 PM PDT 24
Finished Jun 02 03:07:11 PM PDT 24
Peak memory 260588 kb
Host smart-0104843f-fbf5-43a7-b957-ac6522c92884
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288780008 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.4288780008
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3070255808
Short name T1187
Test name
Test status
Simulation time 35168400 ps
CPU time 15.36 seconds
Started Jun 02 03:06:58 PM PDT 24
Finished Jun 02 03:07:14 PM PDT 24
Peak memory 260564 kb
Host smart-ab3e70f9-2f15-463b-98ce-396bd2ba8436
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070255808 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.3070255808
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1017784526
Short name T273
Test name
Test status
Simulation time 68250000 ps
CPU time 16.09 seconds
Started Jun 02 03:06:58 PM PDT 24
Finished Jun 02 03:07:15 PM PDT 24
Peak memory 264160 kb
Host smart-c3253ab1-b83e-4a17-9a2d-cc338dc98367
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017784526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
1017784526
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2408075591
Short name T1192
Test name
Test status
Simulation time 424288400 ps
CPU time 462.17 seconds
Started Jun 02 03:07:00 PM PDT 24
Finished Jun 02 03:14:42 PM PDT 24
Peak memory 264164 kb
Host smart-fd56de17-3eb6-47f7-8e2e-796907fbe520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408075591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.2408075591
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2285130352
Short name T229
Test name
Test status
Simulation time 170833300 ps
CPU time 19.29 seconds
Started Jun 02 03:07:02 PM PDT 24
Finished Jun 02 03:07:22 PM PDT 24
Peak memory 271612 kb
Host smart-9eceb796-c4d6-4554-b75c-0ae7e55df223
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285130352 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.2285130352
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1724626034
Short name T1128
Test name
Test status
Simulation time 179319200 ps
CPU time 16.36 seconds
Started Jun 02 03:07:00 PM PDT 24
Finished Jun 02 03:07:17 PM PDT 24
Peak memory 260548 kb
Host smart-6963ca77-15c4-49b6-8605-318550d69ef1
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724626034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.1724626034
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.794469344
Short name T1131
Test name
Test status
Simulation time 16526300 ps
CPU time 13.43 seconds
Started Jun 02 03:07:01 PM PDT 24
Finished Jun 02 03:07:14 PM PDT 24
Peak memory 262848 kb
Host smart-99f101a5-3eba-4f18-a8d9-da57530747e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794469344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.794469344
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2022020413
Short name T1140
Test name
Test status
Simulation time 112968800 ps
CPU time 28.66 seconds
Started Jun 02 03:07:04 PM PDT 24
Finished Jun 02 03:07:33 PM PDT 24
Peak memory 262048 kb
Host smart-54f032a5-3560-46d2-bae6-a54b552434e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022020413 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.2022020413
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3234408822
Short name T1143
Test name
Test status
Simulation time 38773000 ps
CPU time 15.44 seconds
Started Jun 02 03:06:58 PM PDT 24
Finished Jun 02 03:07:14 PM PDT 24
Peak memory 260492 kb
Host smart-4c4ba228-90ec-4ba6-9d4e-06006b7e3d8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234408822 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.3234408822
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3584786466
Short name T1134
Test name
Test status
Simulation time 15515300 ps
CPU time 15.45 seconds
Started Jun 02 03:06:55 PM PDT 24
Finished Jun 02 03:07:11 PM PDT 24
Peak memory 260432 kb
Host smart-e14d14e5-abef-4bc5-85b5-1be6af729bb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584786466 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.3584786466
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.649725569
Short name T268
Test name
Test status
Simulation time 42723400 ps
CPU time 17.62 seconds
Started Jun 02 03:06:57 PM PDT 24
Finished Jun 02 03:07:15 PM PDT 24
Peak memory 264148 kb
Host smart-dc30dd2d-b36d-4abc-8acb-e4dd48ba8216
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649725569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.649725569
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.405162158
Short name T278
Test name
Test status
Simulation time 529363400 ps
CPU time 459.45 seconds
Started Jun 02 03:06:57 PM PDT 24
Finished Jun 02 03:14:37 PM PDT 24
Peak memory 264116 kb
Host smart-4c6417e6-6939-45dc-80e0-6ef594da60a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405162158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl
_tl_intg_err.405162158
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3679603792
Short name T1155
Test name
Test status
Simulation time 177188300 ps
CPU time 16.86 seconds
Started Jun 02 03:07:11 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 260528 kb
Host smart-eafb9b5e-6bfe-46a7-b705-e0c9d2424f5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679603792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.3679603792
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.816018458
Short name T1161
Test name
Test status
Simulation time 16824800 ps
CPU time 13.4 seconds
Started Jun 02 03:07:01 PM PDT 24
Finished Jun 02 03:07:15 PM PDT 24
Peak memory 262784 kb
Host smart-3747ecd7-030e-46f2-b6e8-db8055cb4a9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816018458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.816018458
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.744258234
Short name T308
Test name
Test status
Simulation time 208188700 ps
CPU time 15.76 seconds
Started Jun 02 03:07:02 PM PDT 24
Finished Jun 02 03:07:18 PM PDT 24
Peak memory 260668 kb
Host smart-1157a920-da4a-44f6-a2e3-0b84daabbb71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744258234 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.744258234
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1224629355
Short name T1087
Test name
Test status
Simulation time 29796200 ps
CPU time 15.81 seconds
Started Jun 02 03:07:03 PM PDT 24
Finished Jun 02 03:07:19 PM PDT 24
Peak memory 260524 kb
Host smart-6ee76e2d-85e5-4fd5-b701-ce7ddfcdebfc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224629355 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.1224629355
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1675139453
Short name T1173
Test name
Test status
Simulation time 16252700 ps
CPU time 13.01 seconds
Started Jun 02 03:07:02 PM PDT 24
Finished Jun 02 03:07:15 PM PDT 24
Peak memory 260468 kb
Host smart-3acc9826-362b-465d-81f8-216ef9a63536
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675139453 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.1675139453
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1831404362
Short name T1218
Test name
Test status
Simulation time 31853400 ps
CPU time 15.7 seconds
Started Jun 02 03:07:01 PM PDT 24
Finished Jun 02 03:07:17 PM PDT 24
Peak memory 264188 kb
Host smart-5a212f23-d7ca-4cf5-a5e3-1a881fee6d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831404362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
1831404362
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1172839509
Short name T367
Test name
Test status
Simulation time 492688200 ps
CPU time 463.66 seconds
Started Jun 02 03:07:03 PM PDT 24
Finished Jun 02 03:14:47 PM PDT 24
Peak memory 264172 kb
Host smart-5f4de402-ce68-46b4-9677-02a9bc608e80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172839509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.1172839509
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.534895550
Short name T218
Test name
Test status
Simulation time 155647600 ps
CPU time 16.6 seconds
Started Jun 02 03:07:01 PM PDT 24
Finished Jun 02 03:07:18 PM PDT 24
Peak memory 270520 kb
Host smart-29ba3283-ceb3-418d-b6ab-ff3ad91295ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534895550 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.534895550
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.14587714
Short name T1189
Test name
Test status
Simulation time 50901900 ps
CPU time 16.99 seconds
Started Jun 02 03:07:11 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 261324 kb
Host smart-1407d1bf-6e96-47b8-b055-31fd98b0c6d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14587714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 13.flash_ctrl_csr_rw.14587714
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1467198846
Short name T1206
Test name
Test status
Simulation time 62568200 ps
CPU time 13.81 seconds
Started Jun 02 03:07:02 PM PDT 24
Finished Jun 02 03:07:17 PM PDT 24
Peak memory 262584 kb
Host smart-a9593501-9ac6-4c02-b1ec-9a2e9631c066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467198846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
1467198846
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.293823933
Short name T1170
Test name
Test status
Simulation time 452274700 ps
CPU time 18.4 seconds
Started Jun 02 03:07:02 PM PDT 24
Finished Jun 02 03:07:21 PM PDT 24
Peak memory 260652 kb
Host smart-b4973746-8130-45dd-a229-4d39841d4a2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293823933 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.293823933
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.250843826
Short name T1204
Test name
Test status
Simulation time 13824900 ps
CPU time 15.82 seconds
Started Jun 02 03:07:03 PM PDT 24
Finished Jun 02 03:07:19 PM PDT 24
Peak memory 260588 kb
Host smart-39e9ecda-8376-488a-98a4-8cacfe4ada8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250843826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.250843826
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3494066177
Short name T1089
Test name
Test status
Simulation time 14252000 ps
CPU time 15.7 seconds
Started Jun 02 03:07:04 PM PDT 24
Finished Jun 02 03:07:20 PM PDT 24
Peak memory 260472 kb
Host smart-48a9e206-d9dd-4c5c-aedc-3f55f9a30270
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494066177 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.3494066177
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1198542280
Short name T219
Test name
Test status
Simulation time 1801873700 ps
CPU time 464.68 seconds
Started Jun 02 03:07:03 PM PDT 24
Finished Jun 02 03:14:48 PM PDT 24
Peak memory 262792 kb
Host smart-47ed1e1f-e33b-4eb4-b696-5478ff9947f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198542280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.1198542280
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3016712629
Short name T303
Test name
Test status
Simulation time 457706100 ps
CPU time 17.39 seconds
Started Jun 02 03:07:13 PM PDT 24
Finished Jun 02 03:07:31 PM PDT 24
Peak memory 273452 kb
Host smart-4b59e19c-984c-467c-8268-0c041893d005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016712629 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3016712629
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2694848561
Short name T1093
Test name
Test status
Simulation time 36776600 ps
CPU time 16.28 seconds
Started Jun 02 03:07:02 PM PDT 24
Finished Jun 02 03:07:19 PM PDT 24
Peak memory 260564 kb
Host smart-25397126-03f9-4170-b2c4-1d50c0e73ee8
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694848561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.2694848561
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.600080288
Short name T1207
Test name
Test status
Simulation time 32485600 ps
CPU time 13.63 seconds
Started Jun 02 03:07:03 PM PDT 24
Finished Jun 02 03:07:17 PM PDT 24
Peak memory 261800 kb
Host smart-4bd320e6-4f34-4daa-8c07-0464c6c0c88a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600080288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.600080288
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.829222360
Short name T1152
Test name
Test status
Simulation time 163365600 ps
CPU time 34.68 seconds
Started Jun 02 03:07:10 PM PDT 24
Finished Jun 02 03:07:45 PM PDT 24
Peak memory 260636 kb
Host smart-7066edbe-90a5-4b51-b6c3-1405fc01fecc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829222360 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.829222360
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4165809807
Short name T1104
Test name
Test status
Simulation time 24339500 ps
CPU time 13.04 seconds
Started Jun 02 03:07:01 PM PDT 24
Finished Jun 02 03:07:15 PM PDT 24
Peak memory 260588 kb
Host smart-d8ff78bd-0149-46ae-b8ae-e9d5ad2b13cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165809807 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.4165809807
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1748503417
Short name T1211
Test name
Test status
Simulation time 42415900 ps
CPU time 15.46 seconds
Started Jun 02 03:07:02 PM PDT 24
Finished Jun 02 03:07:18 PM PDT 24
Peak memory 260592 kb
Host smart-2b1f30be-3541-4ab1-ba2e-c006afcc64fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748503417 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.1748503417
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1303415067
Short name T264
Test name
Test status
Simulation time 36877300 ps
CPU time 16.03 seconds
Started Jun 02 03:07:03 PM PDT 24
Finished Jun 02 03:07:19 PM PDT 24
Peak memory 264300 kb
Host smart-58c20cde-cf9f-4db9-91b9-073ada2a921b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303415067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
1303415067
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2485149215
Short name T1101
Test name
Test status
Simulation time 83058400 ps
CPU time 14.77 seconds
Started Jun 02 03:07:09 PM PDT 24
Finished Jun 02 03:07:25 PM PDT 24
Peak memory 262480 kb
Host smart-d3ad4449-b532-4900-97e1-3eec3b7c22e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485149215 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.2485149215
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2975378273
Short name T1102
Test name
Test status
Simulation time 34886100 ps
CPU time 16.31 seconds
Started Jun 02 03:07:05 PM PDT 24
Finished Jun 02 03:07:22 PM PDT 24
Peak memory 260320 kb
Host smart-111b2d03-0692-41b7-ad2b-8da9130bd1e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975378273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.2975378273
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3924061665
Short name T1133
Test name
Test status
Simulation time 24079600 ps
CPU time 13.2 seconds
Started Jun 02 03:07:07 PM PDT 24
Finished Jun 02 03:07:20 PM PDT 24
Peak memory 262936 kb
Host smart-5973ec84-8e71-465a-9b86-f6b4be518c32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924061665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
3924061665
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3750983846
Short name T1175
Test name
Test status
Simulation time 1146354000 ps
CPU time 19.1 seconds
Started Jun 02 03:07:13 PM PDT 24
Finished Jun 02 03:07:32 PM PDT 24
Peak memory 260536 kb
Host smart-0765218c-1665-420c-86d9-7a0e2776f8f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750983846 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.3750983846
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2741544786
Short name T1194
Test name
Test status
Simulation time 16337200 ps
CPU time 15.58 seconds
Started Jun 02 03:07:06 PM PDT 24
Finished Jun 02 03:07:22 PM PDT 24
Peak memory 260572 kb
Host smart-a42a2ee4-50de-4141-b21c-9b0a0303b19e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741544786 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.2741544786
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.756369456
Short name T1091
Test name
Test status
Simulation time 43129800 ps
CPU time 15.85 seconds
Started Jun 02 03:07:09 PM PDT 24
Finished Jun 02 03:07:26 PM PDT 24
Peak memory 260496 kb
Host smart-4369e778-712c-494b-bab7-127cd6bf5355
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756369456 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.756369456
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.341858303
Short name T269
Test name
Test status
Simulation time 228656900 ps
CPU time 463.49 seconds
Started Jun 02 03:07:06 PM PDT 24
Finished Jun 02 03:14:50 PM PDT 24
Peak memory 262172 kb
Host smart-b1f96dbb-2f56-4819-8c95-9e054feaf916
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341858303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl
_tl_intg_err.341858303
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3355053701
Short name T277
Test name
Test status
Simulation time 88251600 ps
CPU time 19.03 seconds
Started Jun 02 03:07:09 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 272328 kb
Host smart-1ece435f-8e90-425d-8019-b7c37a20c052
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355053701 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.3355053701
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1838801533
Short name T1185
Test name
Test status
Simulation time 70143500 ps
CPU time 13.98 seconds
Started Jun 02 03:07:05 PM PDT 24
Finished Jun 02 03:07:20 PM PDT 24
Peak memory 260536 kb
Host smart-811f2e08-9bc5-4e7f-9201-55d166ceed24
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838801533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.1838801533
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.4170786929
Short name T1163
Test name
Test status
Simulation time 106265000 ps
CPU time 16.01 seconds
Started Jun 02 03:07:07 PM PDT 24
Finished Jun 02 03:07:24 PM PDT 24
Peak memory 260812 kb
Host smart-7faa1e6a-28ff-4c26-972a-0d277c428f75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170786929 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.4170786929
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.845076735
Short name T1088
Test name
Test status
Simulation time 19945900 ps
CPU time 13.01 seconds
Started Jun 02 03:07:06 PM PDT 24
Finished Jun 02 03:07:20 PM PDT 24
Peak memory 260624 kb
Host smart-e8bc641a-bb7b-4f2e-b843-4c18b57ab03d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845076735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.845076735
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.4263938187
Short name T1115
Test name
Test status
Simulation time 19066800 ps
CPU time 15.45 seconds
Started Jun 02 03:07:10 PM PDT 24
Finished Jun 02 03:07:26 PM PDT 24
Peak memory 260560 kb
Host smart-08ecfd86-3e5f-4ef6-86bb-6b2bf636d44b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263938187 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.4263938187
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3922904522
Short name T1145
Test name
Test status
Simulation time 38095800 ps
CPU time 16.79 seconds
Started Jun 02 03:07:05 PM PDT 24
Finished Jun 02 03:07:22 PM PDT 24
Peak memory 264204 kb
Host smart-2328c688-4548-4bba-aa22-9f218050f136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922904522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
3922904522
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1201743928
Short name T1198
Test name
Test status
Simulation time 39092500 ps
CPU time 18.72 seconds
Started Jun 02 03:07:15 PM PDT 24
Finished Jun 02 03:07:34 PM PDT 24
Peak memory 278872 kb
Host smart-966826ec-611a-404b-82e2-20121def9936
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201743928 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1201743928
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2874214630
Short name T1121
Test name
Test status
Simulation time 182047300 ps
CPU time 16.79 seconds
Started Jun 02 03:07:09 PM PDT 24
Finished Jun 02 03:07:27 PM PDT 24
Peak memory 260484 kb
Host smart-55eef02e-3588-47c8-a9b1-52b9ac187169
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874214630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.2874214630
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2746018763
Short name T1193
Test name
Test status
Simulation time 47231100 ps
CPU time 17.76 seconds
Started Jun 02 03:07:13 PM PDT 24
Finished Jun 02 03:07:32 PM PDT 24
Peak memory 260720 kb
Host smart-09695bd4-5ede-4724-b521-6eee5b36f88c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746018763 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.2746018763
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2617753238
Short name T1111
Test name
Test status
Simulation time 11033500 ps
CPU time 15.39 seconds
Started Jun 02 03:07:12 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 260440 kb
Host smart-d2cc95de-7682-4e60-9545-c035f28f10d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617753238 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.2617753238
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2331101506
Short name T1164
Test name
Test status
Simulation time 96734100 ps
CPU time 15.54 seconds
Started Jun 02 03:07:07 PM PDT 24
Finished Jun 02 03:07:23 PM PDT 24
Peak memory 260572 kb
Host smart-053bb63a-c1e0-423b-9104-6c03727bc69e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331101506 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.2331101506
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3108492046
Short name T372
Test name
Test status
Simulation time 1603483200 ps
CPU time 457.08 seconds
Started Jun 02 03:07:08 PM PDT 24
Finished Jun 02 03:14:45 PM PDT 24
Peak memory 261800 kb
Host smart-83044667-f7bc-41d2-85db-9b1c03b114b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108492046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.3108492046
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.329978823
Short name T283
Test name
Test status
Simulation time 111573300 ps
CPU time 17.3 seconds
Started Jun 02 03:07:17 PM PDT 24
Finished Jun 02 03:07:35 PM PDT 24
Peak memory 271364 kb
Host smart-9bf23e84-b1c5-40a6-8f10-82a5d55fdd1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329978823 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.329978823
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1602592179
Short name T1122
Test name
Test status
Simulation time 24926700 ps
CPU time 14.56 seconds
Started Jun 02 03:07:13 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 260464 kb
Host smart-4cc2e8a9-1f50-453c-91dd-2c124d79b8d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602592179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.1602592179
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2265614492
Short name T1126
Test name
Test status
Simulation time 45501600 ps
CPU time 13.67 seconds
Started Jun 02 03:07:11 PM PDT 24
Finished Jun 02 03:07:25 PM PDT 24
Peak memory 262808 kb
Host smart-71b21ff4-8733-44fa-8a40-5b11d015a0e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265614492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
2265614492
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.929688627
Short name T307
Test name
Test status
Simulation time 660041600 ps
CPU time 19.32 seconds
Started Jun 02 03:07:13 PM PDT 24
Finished Jun 02 03:07:33 PM PDT 24
Peak memory 260556 kb
Host smart-e90556c2-3ab5-4b3c-817c-bd3ecf9ff1cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929688627 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.929688627
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2142367542
Short name T1224
Test name
Test status
Simulation time 11191200 ps
CPU time 15.59 seconds
Started Jun 02 03:07:12 PM PDT 24
Finished Jun 02 03:07:28 PM PDT 24
Peak memory 260600 kb
Host smart-4ca39093-1ad5-4490-9f15-7df2631d1e05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142367542 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.2142367542
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.950469237
Short name T1095
Test name
Test status
Simulation time 31208900 ps
CPU time 13.23 seconds
Started Jun 02 03:07:12 PM PDT 24
Finished Jun 02 03:07:26 PM PDT 24
Peak memory 260572 kb
Host smart-f6e229f0-0fdd-4670-8a2d-f933efb7fae4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950469237 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.950469237
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3622140843
Short name T1191
Test name
Test status
Simulation time 1173844400 ps
CPU time 17.14 seconds
Started Jun 02 03:07:12 PM PDT 24
Finished Jun 02 03:07:30 PM PDT 24
Peak memory 270764 kb
Host smart-c289c083-2fa1-42f0-9309-b2b194f67b63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622140843 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.3622140843
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2980822610
Short name T1098
Test name
Test status
Simulation time 52815100 ps
CPU time 16.65 seconds
Started Jun 02 03:07:12 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 260540 kb
Host smart-9b95a1f3-b881-4b8e-a675-61f93b5a9168
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980822610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.2980822610
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.4213189785
Short name T1177
Test name
Test status
Simulation time 25806100 ps
CPU time 13.69 seconds
Started Jun 02 03:07:13 PM PDT 24
Finished Jun 02 03:07:28 PM PDT 24
Peak memory 262888 kb
Host smart-732c3f0a-21d3-4d64-a4d8-c0eaac4199f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213189785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
4213189785
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.40617594
Short name T252
Test name
Test status
Simulation time 636914200 ps
CPU time 29.56 seconds
Started Jun 02 03:07:15 PM PDT 24
Finished Jun 02 03:07:45 PM PDT 24
Peak memory 260580 kb
Host smart-bb13e3cf-0541-4e7c-9f82-f11d625c58ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40617594 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.40617594
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.493416693
Short name T1150
Test name
Test status
Simulation time 20472900 ps
CPU time 13.1 seconds
Started Jun 02 03:07:13 PM PDT 24
Finished Jun 02 03:07:27 PM PDT 24
Peak memory 260588 kb
Host smart-c2e4b991-49a9-4ab4-84bd-245d61335eda
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493416693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.493416693
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.243359522
Short name T1148
Test name
Test status
Simulation time 19714000 ps
CPU time 15.62 seconds
Started Jun 02 03:07:12 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 260480 kb
Host smart-1706a9cb-3099-4510-beb2-1be57c8d86e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243359522 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.243359522
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3870217295
Short name T1172
Test name
Test status
Simulation time 67506100 ps
CPU time 16.38 seconds
Started Jun 02 03:07:13 PM PDT 24
Finished Jun 02 03:07:30 PM PDT 24
Peak memory 264200 kb
Host smart-d1db7d1c-c821-4a05-b511-ac9996e49382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870217295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
3870217295
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3425645094
Short name T207
Test name
Test status
Simulation time 715852900 ps
CPU time 388.48 seconds
Started Jun 02 03:07:13 PM PDT 24
Finished Jun 02 03:13:42 PM PDT 24
Peak memory 264160 kb
Host smart-36179d78-0559-4e84-8f3b-4466ec2ab312
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425645094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.3425645094
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.680791680
Short name T1117
Test name
Test status
Simulation time 2600898100 ps
CPU time 66.18 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:07:49 PM PDT 24
Peak memory 260496 kb
Host smart-eb318654-7343-444a-b8c3-ef4ff7c2faf8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680791680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_aliasing.680791680
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.481343412
Short name T1108
Test name
Test status
Simulation time 658937100 ps
CPU time 41.24 seconds
Started Jun 02 03:06:43 PM PDT 24
Finished Jun 02 03:07:25 PM PDT 24
Peak memory 263028 kb
Host smart-a2b6358b-486a-47b6-b493-4f188667ccc4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481343412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_bit_bash.481343412
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2237312332
Short name T1196
Test name
Test status
Simulation time 57551000 ps
CPU time 45.83 seconds
Started Jun 02 03:06:40 PM PDT 24
Finished Jun 02 03:07:26 PM PDT 24
Peak memory 260524 kb
Host smart-7bad62d8-624f-4f54-981d-da0a000fcde2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237312332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.2237312332
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.400253495
Short name T1179
Test name
Test status
Simulation time 435317000 ps
CPU time 19.53 seconds
Started Jun 02 03:06:48 PM PDT 24
Finished Jun 02 03:07:08 PM PDT 24
Peak memory 272384 kb
Host smart-e1c6a606-ad39-47e6-8c7d-a1cedcd117f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400253495 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.400253495
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.531330607
Short name T1129
Test name
Test status
Simulation time 25856600 ps
CPU time 16.83 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:06:59 PM PDT 24
Peak memory 260608 kb
Host smart-837fd805-5902-4b92-96d1-369faa42d4c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531330607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_csr_rw.531330607
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.4113314525
Short name T1151
Test name
Test status
Simulation time 16530800 ps
CPU time 13.47 seconds
Started Jun 02 03:06:41 PM PDT 24
Finished Jun 02 03:06:55 PM PDT 24
Peak memory 262552 kb
Host smart-53375d33-9c9a-474d-9cb9-2a3a05c50c55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113314525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.4
113314525
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1963525843
Short name T238
Test name
Test status
Simulation time 54657900 ps
CPU time 13.42 seconds
Started Jun 02 03:06:44 PM PDT 24
Finished Jun 02 03:06:58 PM PDT 24
Peak memory 263912 kb
Host smart-82f33df2-cf68-428b-93a6-eaa99201abfc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963525843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.1963525843
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3320188747
Short name T1086
Test name
Test status
Simulation time 17409200 ps
CPU time 13.34 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:06:56 PM PDT 24
Peak memory 262816 kb
Host smart-6cb53c66-924f-46ea-bf4f-4d982003a98c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320188747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.3320188747
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.850626004
Short name T1118
Test name
Test status
Simulation time 66526900 ps
CPU time 28.93 seconds
Started Jun 02 03:06:47 PM PDT 24
Finished Jun 02 03:07:16 PM PDT 24
Peak memory 260496 kb
Host smart-2ecdffe3-8f12-464c-b449-caef0d357a1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850626004 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.850626004
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3432063244
Short name T1168
Test name
Test status
Simulation time 24208000 ps
CPU time 15.9 seconds
Started Jun 02 03:06:49 PM PDT 24
Finished Jun 02 03:07:05 PM PDT 24
Peak memory 260512 kb
Host smart-cbb7ecb5-1b8c-4d95-8436-9638d660c6e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432063244 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.3432063244
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.248361026
Short name T1094
Test name
Test status
Simulation time 18906900 ps
CPU time 13.05 seconds
Started Jun 02 03:06:48 PM PDT 24
Finished Jun 02 03:07:01 PM PDT 24
Peak memory 260544 kb
Host smart-a2dc0a56-3ad5-49bb-aee1-4b741906fa10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248361026 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.248361026
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1016449130
Short name T1221
Test name
Test status
Simulation time 251389200 ps
CPU time 21.21 seconds
Started Jun 02 03:06:43 PM PDT 24
Finished Jun 02 03:07:05 PM PDT 24
Peak memory 264180 kb
Host smart-7468cacf-09cd-430d-8bfa-cd43d8b2f97a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016449130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.1
016449130
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.628394749
Short name T371
Test name
Test status
Simulation time 2781803300 ps
CPU time 889.35 seconds
Started Jun 02 03:06:45 PM PDT 24
Finished Jun 02 03:21:35 PM PDT 24
Peak memory 260660 kb
Host smart-5de82923-5576-4e1a-89aa-f1d3ac819d09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628394749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_
tl_intg_err.628394749
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3177494101
Short name T1178
Test name
Test status
Simulation time 54556100 ps
CPU time 13.37 seconds
Started Jun 02 03:07:13 PM PDT 24
Finished Jun 02 03:07:27 PM PDT 24
Peak memory 262672 kb
Host smart-5c1312b3-2cbd-45a3-aef6-6c4ddcc665b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177494101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
3177494101
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.169105030
Short name T1215
Test name
Test status
Simulation time 36994200 ps
CPU time 13.33 seconds
Started Jun 02 03:07:15 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 262708 kb
Host smart-54f63d8d-8fab-4e31-ad21-3ed0c0dabe17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169105030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.169105030
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3290740244
Short name T265
Test name
Test status
Simulation time 14174100 ps
CPU time 13.9 seconds
Started Jun 02 03:07:16 PM PDT 24
Finished Jun 02 03:07:30 PM PDT 24
Peak memory 262952 kb
Host smart-c7735784-1654-46a6-ad2e-18589fa2d7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290740244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
3290740244
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.651560992
Short name T1110
Test name
Test status
Simulation time 52112600 ps
CPU time 14.15 seconds
Started Jun 02 03:07:11 PM PDT 24
Finished Jun 02 03:07:26 PM PDT 24
Peak memory 262480 kb
Host smart-0be616bb-fae2-4b80-89f7-ea8e246c0ad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651560992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.651560992
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2864125587
Short name T1203
Test name
Test status
Simulation time 53452200 ps
CPU time 13.49 seconds
Started Jun 02 03:07:15 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 262632 kb
Host smart-a49387fe-55ee-405a-818e-7bcb6f06811d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864125587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
2864125587
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3139134940
Short name T1141
Test name
Test status
Simulation time 15915500 ps
CPU time 13.76 seconds
Started Jun 02 03:07:15 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 262672 kb
Host smart-4a2c3531-c3af-4144-bcd8-0a705c2b7b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139134940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
3139134940
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2708608730
Short name T1154
Test name
Test status
Simulation time 17525000 ps
CPU time 13.33 seconds
Started Jun 02 03:07:17 PM PDT 24
Finished Jun 02 03:07:31 PM PDT 24
Peak memory 262732 kb
Host smart-dfb190ea-0c59-403d-b335-6370f88e59f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708608730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
2708608730
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.584540582
Short name T1127
Test name
Test status
Simulation time 24417200 ps
CPU time 13.29 seconds
Started Jun 02 03:07:17 PM PDT 24
Finished Jun 02 03:07:31 PM PDT 24
Peak memory 262840 kb
Host smart-4540ffa9-946c-48b2-9021-cb4ab5e26d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584540582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.584540582
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.768918681
Short name T1156
Test name
Test status
Simulation time 18613200 ps
CPU time 13.31 seconds
Started Jun 02 03:07:18 PM PDT 24
Finished Jun 02 03:07:32 PM PDT 24
Peak memory 262592 kb
Host smart-ccd7e5d2-f839-4321-a7d1-50a446117f8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768918681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.768918681
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2008782105
Short name T1158
Test name
Test status
Simulation time 120528400 ps
CPU time 14.07 seconds
Started Jun 02 03:07:15 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 262552 kb
Host smart-32a1c4dc-3ef3-41b6-b4d9-24e6f27faaa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008782105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
2008782105
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2949883365
Short name T251
Test name
Test status
Simulation time 941880100 ps
CPU time 58.12 seconds
Started Jun 02 03:06:46 PM PDT 24
Finished Jun 02 03:07:44 PM PDT 24
Peak memory 260520 kb
Host smart-51aff1e4-e9ae-4b66-b010-d248a1bf1164
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949883365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.2949883365
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2643019022
Short name T1216
Test name
Test status
Simulation time 865110200 ps
CPU time 60.98 seconds
Started Jun 02 03:06:46 PM PDT 24
Finished Jun 02 03:07:48 PM PDT 24
Peak memory 260584 kb
Host smart-81ef0049-ecec-4d30-a8ef-0887f6d9aa7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643019022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.2643019022
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2597323833
Short name T1120
Test name
Test status
Simulation time 22712100 ps
CPU time 45.42 seconds
Started Jun 02 03:06:46 PM PDT 24
Finished Jun 02 03:07:32 PM PDT 24
Peak memory 260528 kb
Host smart-f50f31c4-79dd-4087-9143-d0f8f5ecb9dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597323833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.2597323833
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.239166638
Short name T1097
Test name
Test status
Simulation time 38609200 ps
CPU time 19.32 seconds
Started Jun 02 03:06:46 PM PDT 24
Finished Jun 02 03:07:06 PM PDT 24
Peak memory 271692 kb
Host smart-60992452-f680-4c4a-a5c9-d216817eefdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239166638 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.239166638
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1550338341
Short name T1107
Test name
Test status
Simulation time 79393700 ps
CPU time 14.73 seconds
Started Jun 02 03:06:49 PM PDT 24
Finished Jun 02 03:07:04 PM PDT 24
Peak memory 260524 kb
Host smart-aadf7f9e-d28c-4b63-8308-58534e58750f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550338341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.1550338341
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.158373452
Short name T1096
Test name
Test status
Simulation time 55359100 ps
CPU time 13.32 seconds
Started Jun 02 03:06:47 PM PDT 24
Finished Jun 02 03:07:00 PM PDT 24
Peak memory 262940 kb
Host smart-1266e5ec-d3e3-4a39-939a-27e79f74087b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158373452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.158373452
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.87635881
Short name T236
Test name
Test status
Simulation time 44672500 ps
CPU time 14 seconds
Started Jun 02 03:06:48 PM PDT 24
Finished Jun 02 03:07:02 PM PDT 24
Peak memory 263684 kb
Host smart-b04982c0-d0c2-41ac-93e5-ffc5078120a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87635881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_mem_partial_access.87635881
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.509844744
Short name T1103
Test name
Test status
Simulation time 24167900 ps
CPU time 13.51 seconds
Started Jun 02 03:06:52 PM PDT 24
Finished Jun 02 03:07:06 PM PDT 24
Peak memory 262660 kb
Host smart-17c900ed-75ad-4df5-8cc3-ed3d5c6953c3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509844744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem
_walk.509844744
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2951121015
Short name T1169
Test name
Test status
Simulation time 62014600 ps
CPU time 34.59 seconds
Started Jun 02 03:06:49 PM PDT 24
Finished Jun 02 03:07:24 PM PDT 24
Peak memory 262016 kb
Host smart-2ddd5646-bfa1-4521-9ded-eefca466e98a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951121015 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.2951121015
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1418019759
Short name T1157
Test name
Test status
Simulation time 25649000 ps
CPU time 15.97 seconds
Started Jun 02 03:06:42 PM PDT 24
Finished Jun 02 03:06:59 PM PDT 24
Peak memory 260496 kb
Host smart-6f100c98-46c8-41a8-adbb-9661386c666f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418019759 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.1418019759
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2434762144
Short name T1202
Test name
Test status
Simulation time 11992100 ps
CPU time 16.52 seconds
Started Jun 02 03:06:52 PM PDT 24
Finished Jun 02 03:07:09 PM PDT 24
Peak memory 260444 kb
Host smart-f924d210-f35f-47d2-b7c9-06f4cf78a288
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434762144 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.2434762144
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1219849359
Short name T276
Test name
Test status
Simulation time 36688400 ps
CPU time 15.96 seconds
Started Jun 02 03:06:50 PM PDT 24
Finished Jun 02 03:07:06 PM PDT 24
Peak memory 264140 kb
Host smart-7522f23f-260e-4b4c-b6bd-4d63d413372c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219849359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1
219849359
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2962924108
Short name T369
Test name
Test status
Simulation time 8671310200 ps
CPU time 907.1 seconds
Started Jun 02 03:06:40 PM PDT 24
Finished Jun 02 03:21:48 PM PDT 24
Peak memory 263292 kb
Host smart-9c155c1f-9a98-4556-a141-d58889eef98d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962924108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.2962924108
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1797146397
Short name T1225
Test name
Test status
Simulation time 21485400 ps
CPU time 13.74 seconds
Started Jun 02 03:07:13 PM PDT 24
Finished Jun 02 03:07:27 PM PDT 24
Peak memory 262584 kb
Host smart-9c5d6edf-5c46-4e1a-aab9-1c416818d539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797146397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
1797146397
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1847626152
Short name T1109
Test name
Test status
Simulation time 26800100 ps
CPU time 13.96 seconds
Started Jun 02 03:07:12 PM PDT 24
Finished Jun 02 03:07:27 PM PDT 24
Peak memory 262628 kb
Host smart-a97d7354-a060-4839-8e5b-e34df4faa95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847626152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
1847626152
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.372147007
Short name T345
Test name
Test status
Simulation time 30883300 ps
CPU time 13.59 seconds
Started Jun 02 03:07:12 PM PDT 24
Finished Jun 02 03:07:26 PM PDT 24
Peak memory 262924 kb
Host smart-f1f727e7-993e-4d8c-9f92-e4cbb7858a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372147007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.372147007
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1763643329
Short name T1229
Test name
Test status
Simulation time 34520800 ps
CPU time 13.4 seconds
Started Jun 02 03:07:14 PM PDT 24
Finished Jun 02 03:07:28 PM PDT 24
Peak memory 262828 kb
Host smart-4c52b64d-b5ac-4a6a-8b39-4cdb85da8835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763643329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
1763643329
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2219938158
Short name T267
Test name
Test status
Simulation time 48309500 ps
CPU time 13.96 seconds
Started Jun 02 03:07:15 PM PDT 24
Finished Jun 02 03:07:30 PM PDT 24
Peak memory 262356 kb
Host smart-3b7f1dda-a28a-47d2-8bdc-0cac586c391f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219938158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
2219938158
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1561463294
Short name T1106
Test name
Test status
Simulation time 17731300 ps
CPU time 13.5 seconds
Started Jun 02 03:07:11 PM PDT 24
Finished Jun 02 03:07:25 PM PDT 24
Peak memory 262716 kb
Host smart-c4efa9ec-cc6d-403c-a016-cb98df9883d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561463294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
1561463294
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2934169367
Short name T1125
Test name
Test status
Simulation time 23172200 ps
CPU time 13.66 seconds
Started Jun 02 03:07:15 PM PDT 24
Finished Jun 02 03:07:29 PM PDT 24
Peak memory 262728 kb
Host smart-16221ed8-01a8-40d9-b0f5-4cdf72e0cf2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934169367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
2934169367
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2177071842
Short name T344
Test name
Test status
Simulation time 15230400 ps
CPU time 13.18 seconds
Started Jun 02 03:07:11 PM PDT 24
Finished Jun 02 03:07:25 PM PDT 24
Peak memory 262672 kb
Host smart-90afd0a3-fd5e-4948-9caf-df6e7a75d6af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177071842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
2177071842
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1143947529
Short name T1114
Test name
Test status
Simulation time 55745100 ps
CPU time 13.49 seconds
Started Jun 02 03:07:12 PM PDT 24
Finished Jun 02 03:07:26 PM PDT 24
Peak memory 262808 kb
Host smart-ee0750cc-0433-431a-9460-526d71b3c9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143947529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
1143947529
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1017208938
Short name T210
Test name
Test status
Simulation time 3033268600 ps
CPU time 38.61 seconds
Started Jun 02 03:06:45 PM PDT 24
Finished Jun 02 03:07:25 PM PDT 24
Peak memory 260560 kb
Host smart-5fee469b-573e-486a-b337-535e5b1306e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017208938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.1017208938
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2716927261
Short name T1226
Test name
Test status
Simulation time 1666409700 ps
CPU time 45.42 seconds
Started Jun 02 03:06:50 PM PDT 24
Finished Jun 02 03:07:36 PM PDT 24
Peak memory 260596 kb
Host smart-412888d8-09e7-4ee1-aa41-070fb677b957
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716927261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.2716927261
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.868334752
Short name T1208
Test name
Test status
Simulation time 129878200 ps
CPU time 45.81 seconds
Started Jun 02 03:06:49 PM PDT 24
Finished Jun 02 03:07:35 PM PDT 24
Peak memory 260552 kb
Host smart-c14b1b08-37ba-4bcb-94ac-7c4a9b8a7bfc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868334752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_hw_reset.868334752
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.700916141
Short name T209
Test name
Test status
Simulation time 28042600 ps
CPU time 17.99 seconds
Started Jun 02 03:06:45 PM PDT 24
Finished Jun 02 03:07:04 PM PDT 24
Peak memory 272368 kb
Host smart-61523514-ab07-466b-b3e1-f99b71846584
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700916141 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.700916141
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4131163948
Short name T1138
Test name
Test status
Simulation time 42956200 ps
CPU time 16.74 seconds
Started Jun 02 03:06:46 PM PDT 24
Finished Jun 02 03:07:03 PM PDT 24
Peak memory 260580 kb
Host smart-b9e43b2f-2226-4b01-be29-9da04d12ef27
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131163948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.4131163948
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.5448650
Short name T1124
Test name
Test status
Simulation time 44309200 ps
CPU time 13.76 seconds
Started Jun 02 03:06:51 PM PDT 24
Finished Jun 02 03:07:05 PM PDT 24
Peak memory 262548 kb
Host smart-58e101a7-2907-419b-b523-e6b7fc087a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5448650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.5448650
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.888728086
Short name T1136
Test name
Test status
Simulation time 17251700 ps
CPU time 13.26 seconds
Started Jun 02 03:06:47 PM PDT 24
Finished Jun 02 03:07:01 PM PDT 24
Peak memory 263656 kb
Host smart-1dc8aeac-ad34-4c65-86c3-29b3bd692c30
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888728086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_mem_partial_access.888728086
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.235007367
Short name T1090
Test name
Test status
Simulation time 177168200 ps
CPU time 13.39 seconds
Started Jun 02 03:06:49 PM PDT 24
Finished Jun 02 03:07:03 PM PDT 24
Peak memory 262672 kb
Host smart-92cf70cb-e939-43ae-a72f-5edc5bb62355
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235007367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem
_walk.235007367
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3649231133
Short name T1223
Test name
Test status
Simulation time 98948800 ps
CPU time 19.8 seconds
Started Jun 02 03:06:46 PM PDT 24
Finished Jun 02 03:07:06 PM PDT 24
Peak memory 262388 kb
Host smart-f345151a-25d4-433c-bdc4-aaadc625027b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649231133 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.3649231133
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.673591401
Short name T1092
Test name
Test status
Simulation time 24515600 ps
CPU time 13.29 seconds
Started Jun 02 03:06:46 PM PDT 24
Finished Jun 02 03:07:00 PM PDT 24
Peak memory 260484 kb
Host smart-324b7176-be9e-4825-8c7d-b6f464b3bc7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673591401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.673591401
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3320841848
Short name T1197
Test name
Test status
Simulation time 24055500 ps
CPU time 15.55 seconds
Started Jun 02 03:06:44 PM PDT 24
Finished Jun 02 03:07:01 PM PDT 24
Peak memory 260612 kb
Host smart-cd834b0b-6dbc-4e64-8adb-c7e76b88182c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320841848 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.3320841848
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2278830284
Short name T270
Test name
Test status
Simulation time 178722300 ps
CPU time 16.66 seconds
Started Jun 02 03:06:45 PM PDT 24
Finished Jun 02 03:07:03 PM PDT 24
Peak memory 264164 kb
Host smart-52c34d36-63e8-4090-8b90-6637b5df5f26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278830284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.2
278830284
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2921177272
Short name T1182
Test name
Test status
Simulation time 47335200 ps
CPU time 13.46 seconds
Started Jun 02 03:07:11 PM PDT 24
Finished Jun 02 03:07:26 PM PDT 24
Peak memory 262852 kb
Host smart-6320261c-60e1-45b8-b2a6-9f33d615f9b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921177272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
2921177272
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1439183332
Short name T1142
Test name
Test status
Simulation time 17171600 ps
CPU time 13.22 seconds
Started Jun 02 03:07:18 PM PDT 24
Finished Jun 02 03:07:31 PM PDT 24
Peak memory 262672 kb
Host smart-ca4a07e5-70ea-485b-a609-08ecc213112e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439183332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
1439183332
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.849035776
Short name T1167
Test name
Test status
Simulation time 254040500 ps
CPU time 13.29 seconds
Started Jun 02 03:07:20 PM PDT 24
Finished Jun 02 03:07:34 PM PDT 24
Peak memory 262496 kb
Host smart-0a1d57c2-071d-4e0c-a669-0473af708a0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849035776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.849035776
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1326811125
Short name T346
Test name
Test status
Simulation time 17243200 ps
CPU time 13.3 seconds
Started Jun 02 03:07:16 PM PDT 24
Finished Jun 02 03:07:30 PM PDT 24
Peak memory 262836 kb
Host smart-84f4a594-146e-440f-818f-731b576a314f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326811125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
1326811125
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.911083936
Short name T1144
Test name
Test status
Simulation time 48698400 ps
CPU time 13.48 seconds
Started Jun 02 03:07:17 PM PDT 24
Finished Jun 02 03:07:31 PM PDT 24
Peak memory 262900 kb
Host smart-476698fc-500c-44d0-8518-2de1bfbaf5f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911083936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.911083936
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3714556638
Short name T347
Test name
Test status
Simulation time 30629200 ps
CPU time 13.48 seconds
Started Jun 02 03:07:17 PM PDT 24
Finished Jun 02 03:07:31 PM PDT 24
Peak memory 262856 kb
Host smart-105c125b-e27b-41b8-b49c-0e6102153d89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714556638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
3714556638
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3720482174
Short name T1113
Test name
Test status
Simulation time 33419800 ps
CPU time 13.41 seconds
Started Jun 02 03:07:18 PM PDT 24
Finished Jun 02 03:07:32 PM PDT 24
Peak memory 262896 kb
Host smart-eed95ee6-5bfb-420c-bf0f-9c74f36064a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720482174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
3720482174
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.478638719
Short name T1162
Test name
Test status
Simulation time 189627500 ps
CPU time 13.22 seconds
Started Jun 02 03:07:21 PM PDT 24
Finished Jun 02 03:07:35 PM PDT 24
Peak memory 262648 kb
Host smart-def30120-c52a-49b5-842c-db13f9762009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478638719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.478638719
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2257364699
Short name T1184
Test name
Test status
Simulation time 16040300 ps
CPU time 13.39 seconds
Started Jun 02 03:07:21 PM PDT 24
Finished Jun 02 03:07:35 PM PDT 24
Peak memory 262584 kb
Host smart-427a3d93-7394-46b2-afef-3d828dbc95a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257364699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
2257364699
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3931566302
Short name T1205
Test name
Test status
Simulation time 74641500 ps
CPU time 13.3 seconds
Started Jun 02 03:07:16 PM PDT 24
Finished Jun 02 03:07:30 PM PDT 24
Peak memory 262664 kb
Host smart-09d48743-2de1-4338-a8e4-8fb12617a454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931566302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
3931566302
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3245606890
Short name T1186
Test name
Test status
Simulation time 61670200 ps
CPU time 14.87 seconds
Started Jun 02 03:06:51 PM PDT 24
Finished Jun 02 03:07:06 PM PDT 24
Peak memory 272344 kb
Host smart-6cc30744-6436-4466-97e3-6c40f97cf213
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245606890 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.3245606890
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.405398531
Short name T253
Test name
Test status
Simulation time 67284300 ps
CPU time 17.84 seconds
Started Jun 02 03:06:52 PM PDT 24
Finished Jun 02 03:07:11 PM PDT 24
Peak memory 260500 kb
Host smart-b08100c4-292d-4a0b-8724-875a3c339f22
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405398531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_csr_rw.405398531
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2564537703
Short name T348
Test name
Test status
Simulation time 15445900 ps
CPU time 13.19 seconds
Started Jun 02 03:06:54 PM PDT 24
Finished Jun 02 03:07:07 PM PDT 24
Peak memory 262888 kb
Host smart-4ee4a2ec-0c27-49fe-8fc8-11fa6fe83069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564537703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2
564537703
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1762710783
Short name T1220
Test name
Test status
Simulation time 74327700 ps
CPU time 17.85 seconds
Started Jun 02 03:06:52 PM PDT 24
Finished Jun 02 03:07:10 PM PDT 24
Peak memory 260572 kb
Host smart-57a1858e-7015-4186-9e86-804862cf82df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762710783 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.1762710783
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3142268317
Short name T1100
Test name
Test status
Simulation time 24377400 ps
CPU time 15.64 seconds
Started Jun 02 03:06:45 PM PDT 24
Finished Jun 02 03:07:02 PM PDT 24
Peak memory 260556 kb
Host smart-a9fe0016-bc1c-462d-8bb8-f75f5fde4a3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142268317 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.3142268317
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.505220872
Short name T1174
Test name
Test status
Simulation time 17436200 ps
CPU time 15.44 seconds
Started Jun 02 03:06:52 PM PDT 24
Finished Jun 02 03:07:07 PM PDT 24
Peak memory 260576 kb
Host smart-e68d5767-1545-44eb-8d46-975504a5c05a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505220872 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.505220872
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2760359299
Short name T263
Test name
Test status
Simulation time 83155400 ps
CPU time 20.26 seconds
Started Jun 02 03:06:48 PM PDT 24
Finished Jun 02 03:07:09 PM PDT 24
Peak memory 264176 kb
Host smart-6baba1b4-c554-4e83-ac76-3cac83b7071c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760359299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.2
760359299
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1190453368
Short name T282
Test name
Test status
Simulation time 1565054100 ps
CPU time 455.31 seconds
Started Jun 02 03:06:46 PM PDT 24
Finished Jun 02 03:14:22 PM PDT 24
Peak memory 264188 kb
Host smart-56ccf194-1aac-48d3-84b5-3f7a40b36a9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190453368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.1190453368
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1169190592
Short name T1183
Test name
Test status
Simulation time 46775600 ps
CPU time 19.89 seconds
Started Jun 02 03:06:54 PM PDT 24
Finished Jun 02 03:07:14 PM PDT 24
Peak memory 278436 kb
Host smart-3a73ed84-ecee-42c3-bfeb-033d3b1b76ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169190592 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.1169190592
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1708325430
Short name T1135
Test name
Test status
Simulation time 97486500 ps
CPU time 17.87 seconds
Started Jun 02 03:06:50 PM PDT 24
Finished Jun 02 03:07:09 PM PDT 24
Peak memory 260608 kb
Host smart-e91d6008-c4a2-41ba-a476-bc1f47157fcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708325430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.1708325430
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2992074199
Short name T1159
Test name
Test status
Simulation time 267497300 ps
CPU time 13.38 seconds
Started Jun 02 03:06:51 PM PDT 24
Finished Jun 02 03:07:05 PM PDT 24
Peak memory 262644 kb
Host smart-b9037a5d-da2c-4631-b97b-e4f8a497e70b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992074199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.2
992074199
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2316760564
Short name T1105
Test name
Test status
Simulation time 132264600 ps
CPU time 18.02 seconds
Started Jun 02 03:06:52 PM PDT 24
Finished Jun 02 03:07:11 PM PDT 24
Peak memory 262064 kb
Host smart-6712b71c-81da-457b-aa71-950d4e2ddef9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316760564 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.2316760564
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2920986927
Short name T1171
Test name
Test status
Simulation time 14618000 ps
CPU time 16.29 seconds
Started Jun 02 03:06:55 PM PDT 24
Finished Jun 02 03:07:11 PM PDT 24
Peak memory 260624 kb
Host smart-eab4b192-006c-460e-8aed-fe06a74d73e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920986927 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.2920986927
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3796254069
Short name T1212
Test name
Test status
Simulation time 61720800 ps
CPU time 15.57 seconds
Started Jun 02 03:06:52 PM PDT 24
Finished Jun 02 03:07:08 PM PDT 24
Peak memory 260604 kb
Host smart-9f4efa5d-9337-4fa5-b278-71b1cbc087dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796254069 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.3796254069
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3808278219
Short name T1165
Test name
Test status
Simulation time 59189800 ps
CPU time 16.65 seconds
Started Jun 02 03:06:51 PM PDT 24
Finished Jun 02 03:07:08 PM PDT 24
Peak memory 264180 kb
Host smart-4786bd30-2e03-4f97-a750-9480813c9465
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808278219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.3
808278219
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.150215996
Short name T275
Test name
Test status
Simulation time 448601100 ps
CPU time 390.91 seconds
Started Jun 02 03:06:51 PM PDT 24
Finished Jun 02 03:13:23 PM PDT 24
Peak memory 261852 kb
Host smart-e977bebb-8a6b-42d6-9447-c2aeb24782bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150215996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_
tl_intg_err.150215996
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1821041659
Short name T217
Test name
Test status
Simulation time 119594500 ps
CPU time 18.59 seconds
Started Jun 02 03:06:52 PM PDT 24
Finished Jun 02 03:07:11 PM PDT 24
Peak memory 272308 kb
Host smart-b361691e-eeb4-4624-bf29-0e549c24687d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821041659 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.1821041659
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3500809983
Short name T1147
Test name
Test status
Simulation time 57742200 ps
CPU time 16.51 seconds
Started Jun 02 03:06:52 PM PDT 24
Finished Jun 02 03:07:09 PM PDT 24
Peak memory 260900 kb
Host smart-f9cdfbe9-2470-44c9-9daa-826073a918d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500809983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.3500809983
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.4280716896
Short name T1130
Test name
Test status
Simulation time 15743100 ps
CPU time 13.32 seconds
Started Jun 02 03:06:52 PM PDT 24
Finished Jun 02 03:07:06 PM PDT 24
Peak memory 261840 kb
Host smart-4da15267-4507-4226-bec2-fff5faeeb393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280716896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.4
280716896
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2943888827
Short name T305
Test name
Test status
Simulation time 950262100 ps
CPU time 29.89 seconds
Started Jun 02 03:06:50 PM PDT 24
Finished Jun 02 03:07:20 PM PDT 24
Peak memory 263752 kb
Host smart-f4d7f84d-ef58-4bf8-88fc-874ca5ab2225
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943888827 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.2943888827
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2530511691
Short name T1153
Test name
Test status
Simulation time 48507700 ps
CPU time 13.04 seconds
Started Jun 02 03:06:49 PM PDT 24
Finished Jun 02 03:07:03 PM PDT 24
Peak memory 260564 kb
Host smart-c30060c6-f8c7-4ae4-a13d-4d88e62ac96c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530511691 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2530511691
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3132654741
Short name T1146
Test name
Test status
Simulation time 32721700 ps
CPU time 15.55 seconds
Started Jun 02 03:06:50 PM PDT 24
Finished Jun 02 03:07:06 PM PDT 24
Peak memory 260544 kb
Host smart-9c6238d5-efb0-4ed7-abf7-2664c5e521af
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132654741 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.3132654741
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.864556240
Short name T1199
Test name
Test status
Simulation time 87634500 ps
CPU time 20.51 seconds
Started Jun 02 03:06:50 PM PDT 24
Finished Jun 02 03:07:11 PM PDT 24
Peak memory 264128 kb
Host smart-26fe63ac-1860-415a-af2b-5f53a0c1f247
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864556240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.864556240
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.556433327
Short name T230
Test name
Test status
Simulation time 703226900 ps
CPU time 898.32 seconds
Started Jun 02 03:06:53 PM PDT 24
Finished Jun 02 03:21:52 PM PDT 24
Peak memory 264152 kb
Host smart-095387cc-d406-4af5-9ef6-cb11b4605452
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556433327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_
tl_intg_err.556433327
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2142912873
Short name T1201
Test name
Test status
Simulation time 83353500 ps
CPU time 18.28 seconds
Started Jun 02 03:07:00 PM PDT 24
Finished Jun 02 03:07:19 PM PDT 24
Peak memory 272288 kb
Host smart-f58c386b-4b49-472a-b83c-cbeecb1a0fc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142912873 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.2142912873
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1412645504
Short name T1176
Test name
Test status
Simulation time 33281500 ps
CPU time 16.14 seconds
Started Jun 02 03:06:56 PM PDT 24
Finished Jun 02 03:07:13 PM PDT 24
Peak memory 260608 kb
Host smart-6854e45a-9444-4fa1-a7ca-9acf3f3a546f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412645504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.1412645504
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3956534799
Short name T350
Test name
Test status
Simulation time 99014200 ps
CPU time 13.48 seconds
Started Jun 02 03:06:56 PM PDT 24
Finished Jun 02 03:07:10 PM PDT 24
Peak memory 262744 kb
Host smart-026c6e8e-403e-490d-9856-a0f24e8a5b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956534799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.3
956534799
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.10125215
Short name T1210
Test name
Test status
Simulation time 238071800 ps
CPU time 34.02 seconds
Started Jun 02 03:07:00 PM PDT 24
Finished Jun 02 03:07:34 PM PDT 24
Peak memory 263456 kb
Host smart-a004bcb8-a4b2-4a45-9efd-2e68cd424cd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10125215 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.10125215
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3201660128
Short name T1085
Test name
Test status
Simulation time 18099700 ps
CPU time 15.48 seconds
Started Jun 02 03:06:54 PM PDT 24
Finished Jun 02 03:07:10 PM PDT 24
Peak memory 260688 kb
Host smart-2f668999-94bb-4377-b7f8-3775977d8b64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201660128 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.3201660128
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2286513734
Short name T1222
Test name
Test status
Simulation time 58442500 ps
CPU time 13.12 seconds
Started Jun 02 03:06:53 PM PDT 24
Finished Jun 02 03:07:07 PM PDT 24
Peak memory 260564 kb
Host smart-f384797b-db8c-4eaa-8485-dfb927a7cd31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286513734 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.2286513734
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1357881948
Short name T1180
Test name
Test status
Simulation time 68177400 ps
CPU time 20.6 seconds
Started Jun 02 03:06:52 PM PDT 24
Finished Jun 02 03:07:14 PM PDT 24
Peak memory 264416 kb
Host smart-78afc674-72a7-4386-b174-477f25dfb99d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357881948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.1
357881948
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1870304657
Short name T232
Test name
Test status
Simulation time 862062600 ps
CPU time 898.23 seconds
Started Jun 02 03:06:54 PM PDT 24
Finished Jun 02 03:21:53 PM PDT 24
Peak memory 264152 kb
Host smart-7e8500cb-4afb-4d30-8c3f-57e16952a9b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870304657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.1870304657
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.816100336
Short name T279
Test name
Test status
Simulation time 526658600 ps
CPU time 19.68 seconds
Started Jun 02 03:06:56 PM PDT 24
Finished Jun 02 03:07:16 PM PDT 24
Peak memory 272320 kb
Host smart-883903dc-7af6-4385-864f-8aed15c5fee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816100336 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.816100336
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.35661312
Short name T206
Test name
Test status
Simulation time 51070100 ps
CPU time 17.23 seconds
Started Jun 02 03:06:57 PM PDT 24
Finished Jun 02 03:07:15 PM PDT 24
Peak memory 260596 kb
Host smart-1ed3ec47-ca92-4f1a-8f09-35e2e69c9965
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35661312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 9.flash_ctrl_csr_rw.35661312
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2628524009
Short name T1181
Test name
Test status
Simulation time 15898800 ps
CPU time 13.99 seconds
Started Jun 02 03:06:58 PM PDT 24
Finished Jun 02 03:07:13 PM PDT 24
Peak memory 262048 kb
Host smart-b7963af8-7685-4c29-a414-a22a7bbbcef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628524009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.2
628524009
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.4220730044
Short name T1213
Test name
Test status
Simulation time 113186100 ps
CPU time 19.26 seconds
Started Jun 02 03:06:56 PM PDT 24
Finished Jun 02 03:07:16 PM PDT 24
Peak memory 260584 kb
Host smart-592b219d-87ce-4edd-ab14-e921f5a13e66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220730044 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.4220730044
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.295387789
Short name T1137
Test name
Test status
Simulation time 12463800 ps
CPU time 15.46 seconds
Started Jun 02 03:06:57 PM PDT 24
Finished Jun 02 03:07:13 PM PDT 24
Peak memory 260596 kb
Host smart-b906a149-e481-4de6-a1ad-7b1bbf0f2f55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295387789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.295387789
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2562321064
Short name T1119
Test name
Test status
Simulation time 21360100 ps
CPU time 15.47 seconds
Started Jun 02 03:06:57 PM PDT 24
Finished Jun 02 03:07:13 PM PDT 24
Peak memory 260548 kb
Host smart-204fe53c-1920-4709-8ee2-7535bdf8462e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562321064 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.2562321064
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.358249478
Short name T233
Test name
Test status
Simulation time 42721900 ps
CPU time 16.2 seconds
Started Jun 02 03:06:57 PM PDT 24
Finished Jun 02 03:07:14 PM PDT 24
Peak memory 264192 kb
Host smart-54f593aa-22ac-490f-ae49-2b58d78eba0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358249478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.358249478
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.2585511870
Short name T662
Test name
Test status
Simulation time 161570400 ps
CPU time 13.63 seconds
Started Jun 02 03:18:47 PM PDT 24
Finished Jun 02 03:19:01 PM PDT 24
Peak memory 257808 kb
Host smart-f889d666-7c56-4d4a-8c2d-2ce8422ac86f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585511870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.2
585511870
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.425585506
Short name T536
Test name
Test status
Simulation time 34801600 ps
CPU time 16.1 seconds
Started Jun 02 03:18:48 PM PDT 24
Finished Jun 02 03:19:05 PM PDT 24
Peak memory 275452 kb
Host smart-3f507266-46c6-438e-9012-b8f5731e4f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425585506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.425585506
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.2347724218
Short name T1015
Test name
Test status
Simulation time 189511100 ps
CPU time 104.2 seconds
Started Jun 02 03:18:41 PM PDT 24
Finished Jun 02 03:20:26 PM PDT 24
Peak memory 273748 kb
Host smart-898c943b-cd1e-4f9e-9c74-367fb0bf6fef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347724218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.2347724218
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.4224072167
Short name T856
Test name
Test status
Simulation time 23276700 ps
CPU time 21.72 seconds
Started Jun 02 03:18:51 PM PDT 24
Finished Jun 02 03:19:13 PM PDT 24
Peak memory 273088 kb
Host smart-d20d5d55-f2b2-4c54-a4b8-5f721e68064d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224072167 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.4224072167
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.263381044
Short name T972
Test name
Test status
Simulation time 11219961100 ps
CPU time 446.41 seconds
Started Jun 02 03:18:39 PM PDT 24
Finished Jun 02 03:26:06 PM PDT 24
Peak memory 262876 kb
Host smart-6b3fbeed-5450-48ea-b7b5-07e05b9ad30b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=263381044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.263381044
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.2704949146
Short name T194
Test name
Test status
Simulation time 1054240300 ps
CPU time 2190.28 seconds
Started Jun 02 03:18:44 PM PDT 24
Finished Jun 02 03:55:15 PM PDT 24
Peak memory 264744 kb
Host smart-5179cb57-7334-4858-8c42-c6e4ecee92cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704949146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.2704949146
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.3546571352
Short name T886
Test name
Test status
Simulation time 168605900 ps
CPU time 25.8 seconds
Started Jun 02 03:18:42 PM PDT 24
Finished Jun 02 03:19:08 PM PDT 24
Peak memory 264856 kb
Host smart-5eec5f0a-5c53-4afd-8250-624dfb2c9262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546571352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.3546571352
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.3246680524
Short name T601
Test name
Test status
Simulation time 2739119900 ps
CPU time 41.62 seconds
Started Jun 02 03:18:46 PM PDT 24
Finished Jun 02 03:19:29 PM PDT 24
Peak memory 261868 kb
Host smart-8b4e6c73-a7c0-4a0a-b3c8-c3cd4933e8d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246680524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.3246680524
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.2087359085
Short name T433
Test name
Test status
Simulation time 255446500 ps
CPU time 26.67 seconds
Started Jun 02 03:18:34 PM PDT 24
Finished Jun 02 03:19:01 PM PDT 24
Peak memory 263904 kb
Host smart-4e83073e-ebb5-46e0-9d0a-49b71641ae3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2087359085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2087359085
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2094409274
Short name T514
Test name
Test status
Simulation time 10013085400 ps
CPU time 139.48 seconds
Started Jun 02 03:18:47 PM PDT 24
Finished Jun 02 03:21:07 PM PDT 24
Peak memory 385060 kb
Host smart-ee98f80f-2fb0-43e2-a233-2d5400096c31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094409274 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.2094409274
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.3587533455
Short name T613
Test name
Test status
Simulation time 81242500 ps
CPU time 13.44 seconds
Started Jun 02 03:18:50 PM PDT 24
Finished Jun 02 03:19:04 PM PDT 24
Peak memory 257932 kb
Host smart-4e68e2af-8dd5-4b3a-9e82-8ae44079799d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587533455 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.3587533455
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.1564746163
Short name T84
Test name
Test status
Simulation time 375990360500 ps
CPU time 2217.38 seconds
Started Jun 02 03:18:36 PM PDT 24
Finished Jun 02 03:55:34 PM PDT 24
Peak memory 263840 kb
Host smart-38a09a2d-03f5-4420-9b3b-09c033831c69
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564746163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.1564746163
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.1825777804
Short name T619
Test name
Test status
Simulation time 80136052100 ps
CPU time 930.09 seconds
Started Jun 02 03:18:36 PM PDT 24
Finished Jun 02 03:34:07 PM PDT 24
Peak memory 264192 kb
Host smart-c13fbcbd-86ed-47c0-948a-86fc8d208227
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825777804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.1825777804
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.3718360627
Short name T957
Test name
Test status
Simulation time 7880418300 ps
CPU time 70.96 seconds
Started Jun 02 03:18:34 PM PDT 24
Finished Jun 02 03:19:46 PM PDT 24
Peak memory 262328 kb
Host smart-eaa2db91-2204-43af-a662-34a642713716
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718360627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.3718360627
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.2713857209
Short name T240
Test name
Test status
Simulation time 5118412500 ps
CPU time 761.06 seconds
Started Jun 02 03:18:46 PM PDT 24
Finished Jun 02 03:31:27 PM PDT 24
Peak memory 318744 kb
Host smart-792f585d-69e7-4d92-99e8-da4bac1ad82b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713857209 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_integrity.2713857209
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.2284116750
Short name T741
Test name
Test status
Simulation time 2529325800 ps
CPU time 138.18 seconds
Started Jun 02 03:18:40 PM PDT 24
Finished Jun 02 03:20:59 PM PDT 24
Peak memory 292908 kb
Host smart-09b6497b-71a4-4939-919c-698b6feae38f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284116750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_intr_rd.2284116750
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2831482764
Short name T735
Test name
Test status
Simulation time 5593221100 ps
CPU time 135.31 seconds
Started Jun 02 03:18:46 PM PDT 24
Finished Jun 02 03:21:01 PM PDT 24
Peak memory 291228 kb
Host smart-8ecbc7fd-a3c5-4524-b2f8-cd232e1760de
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831482764 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.2831482764
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.1247331788
Short name T727
Test name
Test status
Simulation time 8128609500 ps
CPU time 91.57 seconds
Started Jun 02 03:18:40 PM PDT 24
Finished Jun 02 03:20:12 PM PDT 24
Peak memory 259756 kb
Host smart-80349fee-1899-44df-920b-5fca459929b2
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247331788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.1247331788
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.977925315
Short name T167
Test name
Test status
Simulation time 6378264500 ps
CPU time 70.37 seconds
Started Jun 02 03:18:46 PM PDT 24
Finished Jun 02 03:19:56 PM PDT 24
Peak memory 260500 kb
Host smart-3260cffd-2d93-4925-ba62-5804bce1e1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977925315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.977925315
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.2188370157
Short name T97
Test name
Test status
Simulation time 9721418200 ps
CPU time 289.44 seconds
Started Jun 02 03:18:40 PM PDT 24
Finished Jun 02 03:23:30 PM PDT 24
Peak memory 273720 kb
Host smart-bee03f0d-89cd-441b-af01-66bffd856b09
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188370157 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.2188370157
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.3218646526
Short name T527
Test name
Test status
Simulation time 510792300 ps
CPU time 129.83 seconds
Started Jun 02 03:18:35 PM PDT 24
Finished Jun 02 03:20:45 PM PDT 24
Peak memory 264128 kb
Host smart-daf22dec-04b0-4586-8786-2581cc0576d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218646526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.3218646526
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.3571225790
Short name T177
Test name
Test status
Simulation time 1567721400 ps
CPU time 158.54 seconds
Started Jun 02 03:18:44 PM PDT 24
Finished Jun 02 03:21:23 PM PDT 24
Peak memory 281260 kb
Host smart-bbafff16-d4a7-476b-a189-8a60dfe6be62
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571225790 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.3571225790
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.3896541132
Short name T720
Test name
Test status
Simulation time 67946000 ps
CPU time 288.52 seconds
Started Jun 02 03:18:39 PM PDT 24
Finished Jun 02 03:23:29 PM PDT 24
Peak memory 261516 kb
Host smart-194aa4df-b392-4d6e-bcd5-0d749c3e33e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3896541132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.3896541132
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.1627203028
Short name T77
Test name
Test status
Simulation time 826784900 ps
CPU time 17.41 seconds
Started Jun 02 03:18:49 PM PDT 24
Finished Jun 02 03:19:08 PM PDT 24
Peak memory 261992 kb
Host smart-86f2b3b8-0fa8-4984-b50d-3e6d1e97ed45
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627203028 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.1627203028
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.2239692925
Short name T895
Test name
Test status
Simulation time 1240754200 ps
CPU time 38.99 seconds
Started Jun 02 03:18:41 PM PDT 24
Finished Jun 02 03:19:21 PM PDT 24
Peak memory 258960 kb
Host smart-a2bf963c-e689-4cbb-b428-f07ea5d0e8ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239692925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.2239692925
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.2091171553
Short name T104
Test name
Test status
Simulation time 2884697700 ps
CPU time 1141.64 seconds
Started Jun 02 03:18:39 PM PDT 24
Finished Jun 02 03:37:42 PM PDT 24
Peak memory 287120 kb
Host smart-0c845b17-d985-40bc-84a9-77445089c8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091171553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.2091171553
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.188083429
Short name T363
Test name
Test status
Simulation time 185280800 ps
CPU time 29.71 seconds
Started Jun 02 03:18:49 PM PDT 24
Finished Jun 02 03:19:19 PM PDT 24
Peak memory 273216 kb
Host smart-c0407c27-3833-4f83-89c2-f51584b7e2d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188083429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_rd_intg.188083429
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.2237303723
Short name T702
Test name
Test status
Simulation time 72375000 ps
CPU time 45.38 seconds
Started Jun 02 03:18:47 PM PDT 24
Finished Jun 02 03:19:33 PM PDT 24
Peak memory 275140 kb
Host smart-889b4bc8-0258-4248-9a76-e746103d0514
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237303723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.2237303723
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.4168020317
Short name T1043
Test name
Test status
Simulation time 445829500 ps
CPU time 37.63 seconds
Started Jun 02 03:18:48 PM PDT 24
Finished Jun 02 03:19:26 PM PDT 24
Peak memory 273100 kb
Host smart-418ffdb3-c432-45dd-aca2-76063c48ecf7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168020317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.4168020317
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.2436089552
Short name T827
Test name
Test status
Simulation time 15660000 ps
CPU time 13.47 seconds
Started Jun 02 03:18:45 PM PDT 24
Finished Jun 02 03:18:59 PM PDT 24
Peak memory 257936 kb
Host smart-920e1fa9-422f-4e6f-9899-78ff5291908c
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2436089552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.2436089552
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.384497148
Short name T996
Test name
Test status
Simulation time 24733000 ps
CPU time 22.87 seconds
Started Jun 02 03:18:44 PM PDT 24
Finished Jun 02 03:19:07 PM PDT 24
Peak memory 264724 kb
Host smart-cf42e7b6-93e1-4ff8-be0d-3b8fb21d0296
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384497148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_read_word_sweep_serr.384497148
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.2871391546
Short name T441
Test name
Test status
Simulation time 470192000 ps
CPU time 106.5 seconds
Started Jun 02 03:18:44 PM PDT 24
Finished Jun 02 03:20:31 PM PDT 24
Peak memory 296668 kb
Host smart-964d7dbd-45d7-4704-b257-860359281454
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871391546 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.2871391546
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.1432868349
Short name T494
Test name
Test status
Simulation time 2670727500 ps
CPU time 138.52 seconds
Started Jun 02 03:18:41 PM PDT 24
Finished Jun 02 03:21:00 PM PDT 24
Peak memory 281608 kb
Host smart-86f07ed3-9c7a-47d2-b256-b846e1644487
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1432868349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.1432868349
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.539236702
Short name T201
Test name
Test status
Simulation time 696259500 ps
CPU time 142.43 seconds
Started Jun 02 03:18:41 PM PDT 24
Finished Jun 02 03:21:04 PM PDT 24
Peak memory 281216 kb
Host smart-a8c348d8-524b-412b-9882-e77ed18d2bc5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539236702 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.539236702
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.4011857311
Short name T945
Test name
Test status
Simulation time 16716998000 ps
CPU time 521.81 seconds
Started Jun 02 03:18:41 PM PDT 24
Finished Jun 02 03:27:24 PM PDT 24
Peak memory 309112 kb
Host smart-1463d46e-932d-42e5-8484-34c7fbdd6ea8
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011857311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.4011857311
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.4071374228
Short name T943
Test name
Test status
Simulation time 65182100 ps
CPU time 30.82 seconds
Started Jun 02 03:18:49 PM PDT 24
Finished Jun 02 03:19:21 PM PDT 24
Peak memory 274460 kb
Host smart-0ea37bd9-d40e-426f-9c42-04ea73320181
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071374228 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.4071374228
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.3296233088
Short name T38
Test name
Test status
Simulation time 3422732600 ps
CPU time 4891.64 seconds
Started Jun 02 03:18:47 PM PDT 24
Finished Jun 02 04:40:19 PM PDT 24
Peak memory 287500 kb
Host smart-6ce1052a-90db-41d4-ac6b-c1a80f75d133
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296233088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.3296233088
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.3148739245
Short name T4
Test name
Test status
Simulation time 592994100 ps
CPU time 62.38 seconds
Started Jun 02 03:18:49 PM PDT 24
Finished Jun 02 03:19:52 PM PDT 24
Peak memory 262148 kb
Host smart-f36e22f7-854d-4f05-bee9-69b47ab9be79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148739245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3148739245
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.2596897573
Short name T620
Test name
Test status
Simulation time 1545014600 ps
CPU time 76.11 seconds
Started Jun 02 03:18:41 PM PDT 24
Finished Jun 02 03:19:58 PM PDT 24
Peak memory 273040 kb
Host smart-70a77b30-4779-41f7-830d-87fd17061d9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596897573 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.2596897573
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.2577460718
Short name T550
Test name
Test status
Simulation time 3952806000 ps
CPU time 102.24 seconds
Started Jun 02 03:18:41 PM PDT 24
Finished Jun 02 03:20:25 PM PDT 24
Peak memory 273896 kb
Host smart-f56f6791-b612-499c-bc9f-6edc1526cdab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577460718 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.2577460718
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.4226955413
Short name T704
Test name
Test status
Simulation time 31347200 ps
CPU time 74.97 seconds
Started Jun 02 03:18:38 PM PDT 24
Finished Jun 02 03:19:53 PM PDT 24
Peak memory 274772 kb
Host smart-30753530-0ba7-4f52-b8f5-81a7dacb2951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226955413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.4226955413
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.4173133666
Short name T459
Test name
Test status
Simulation time 32400300 ps
CPU time 25.64 seconds
Started Jun 02 03:18:34 PM PDT 24
Finished Jun 02 03:19:00 PM PDT 24
Peak memory 258784 kb
Host smart-c5e88bea-2e65-4b32-9764-092a5b466973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173133666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.4173133666
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.3235530551
Short name T1041
Test name
Test status
Simulation time 3437646600 ps
CPU time 1690.81 seconds
Started Jun 02 03:18:50 PM PDT 24
Finished Jun 02 03:47:02 PM PDT 24
Peak memory 288788 kb
Host smart-39c5d92b-5424-4923-8b00-c45b2c1dd47a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235530551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.3235530551
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.2756508444
Short name T806
Test name
Test status
Simulation time 40807400 ps
CPU time 23.64 seconds
Started Jun 02 03:18:36 PM PDT 24
Finished Jun 02 03:19:00 PM PDT 24
Peak memory 261260 kb
Host smart-cd88287d-a337-4928-80a7-57786cf06731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756508444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.2756508444
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.2703607204
Short name T585
Test name
Test status
Simulation time 2521070000 ps
CPU time 211.37 seconds
Started Jun 02 03:18:40 PM PDT 24
Finished Jun 02 03:22:12 PM PDT 24
Peak memory 264792 kb
Host smart-32b0ba5d-bdc4-49ad-984f-c05ee198e926
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703607204 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_wo.2703607204
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.2119786218
Short name T12
Test name
Test status
Simulation time 46128500 ps
CPU time 15.28 seconds
Started Jun 02 03:18:49 PM PDT 24
Finished Jun 02 03:19:05 PM PDT 24
Peak memory 259688 kb
Host smart-c530804a-9ce6-49d6-91b8-055a59ff22a3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119786218 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.2119786218
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.1853190378
Short name T19
Test name
Test status
Simulation time 103760700 ps
CPU time 14.79 seconds
Started Jun 02 03:18:40 PM PDT 24
Finished Jun 02 03:18:56 PM PDT 24
Peak memory 258164 kb
Host smart-be27579b-ed05-4b86-bd8b-1dfbeb54b894
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1853190378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.1853190378
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.3417734862
Short name T43
Test name
Test status
Simulation time 24936800 ps
CPU time 13.73 seconds
Started Jun 02 03:19:03 PM PDT 24
Finished Jun 02 03:19:17 PM PDT 24
Peak memory 260968 kb
Host smart-3c4143df-b4f0-4496-b767-d88c5fed36c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417734862 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.3417734862
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.2073370174
Short name T853
Test name
Test status
Simulation time 33464900 ps
CPU time 13.78 seconds
Started Jun 02 03:19:02 PM PDT 24
Finished Jun 02 03:19:17 PM PDT 24
Peak memory 264200 kb
Host smart-4fe3c5ba-d3de-484b-a681-cd430bd0f0cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073370174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.2
073370174
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.3725562546
Short name T522
Test name
Test status
Simulation time 16330800 ps
CPU time 15.72 seconds
Started Jun 02 03:19:04 PM PDT 24
Finished Jun 02 03:19:20 PM PDT 24
Peak memory 275764 kb
Host smart-ed6ebb20-f8e5-4880-af33-2064fd67c3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725562546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.3725562546
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.4112360010
Short name T781
Test name
Test status
Simulation time 173135800 ps
CPU time 101.14 seconds
Started Jun 02 03:18:56 PM PDT 24
Finished Jun 02 03:20:37 PM PDT 24
Peak memory 272172 kb
Host smart-d14b25df-96bb-471c-89fa-24d941dcef27
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112360010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.4112360010
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.4205851897
Short name T160
Test name
Test status
Simulation time 3489281200 ps
CPU time 550.25 seconds
Started Jun 02 03:18:48 PM PDT 24
Finished Jun 02 03:27:59 PM PDT 24
Peak memory 260908 kb
Host smart-932ecf9f-b784-4ef8-b5cd-40c76a4c792e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4205851897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.4205851897
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.2905193491
Short name T455
Test name
Test status
Simulation time 2022913600 ps
CPU time 2292.56 seconds
Started Jun 02 03:18:57 PM PDT 24
Finished Jun 02 03:57:10 PM PDT 24
Peak memory 264888 kb
Host smart-7013cc79-32dd-4b1b-804d-75c1ace4faf2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905193491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.2905193491
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.4058352084
Short name T170
Test name
Test status
Simulation time 584615500 ps
CPU time 3161.34 seconds
Started Jun 02 03:19:03 PM PDT 24
Finished Jun 02 04:11:45 PM PDT 24
Peak memory 264316 kb
Host smart-1a996501-3be1-463d-981a-5a8b03f56992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058352084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.4058352084
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.3878319043
Short name T301
Test name
Test status
Simulation time 1698955500 ps
CPU time 845.96 seconds
Started Jun 02 03:18:57 PM PDT 24
Finished Jun 02 03:33:04 PM PDT 24
Peak memory 272976 kb
Host smart-1fa60e1a-4f02-4860-846c-58ab47f823cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878319043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.3878319043
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.2950222870
Short name T596
Test name
Test status
Simulation time 239029600 ps
CPU time 21.22 seconds
Started Jun 02 03:18:48 PM PDT 24
Finished Jun 02 03:19:10 PM PDT 24
Peak memory 264776 kb
Host smart-647bf40e-f8f3-47bc-a734-5f4d32e6127a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950222870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.2950222870
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.1726113977
Short name T796
Test name
Test status
Simulation time 97828102400 ps
CPU time 4517.87 seconds
Started Jun 02 03:18:48 PM PDT 24
Finished Jun 02 04:34:07 PM PDT 24
Peak memory 264900 kb
Host smart-63ed3c78-51f6-411f-98af-393eda6ae564
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726113977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.1726113977
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.4264957944
Short name T88
Test name
Test status
Simulation time 676674518100 ps
CPU time 2439.16 seconds
Started Jun 02 03:18:48 PM PDT 24
Finished Jun 02 03:59:28 PM PDT 24
Peak memory 264952 kb
Host smart-f950f33f-7969-4478-afd6-4e8eb9629f2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264957944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.4264957944
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.1022717195
Short name T838
Test name
Test status
Simulation time 251393700 ps
CPU time 114.86 seconds
Started Jun 02 03:18:50 PM PDT 24
Finished Jun 02 03:20:46 PM PDT 24
Peak memory 264820 kb
Host smart-4c9bd457-0db1-4ffb-ae7d-77d6302c3a41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1022717195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.1022717195
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2564820862
Short name T626
Test name
Test status
Simulation time 48707400 ps
CPU time 13.49 seconds
Started Jun 02 03:19:02 PM PDT 24
Finished Jun 02 03:19:16 PM PDT 24
Peak memory 258096 kb
Host smart-2aca5f44-d156-41aa-bfe9-ce2fc791083a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564820862 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.2564820862
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.4270909197
Short name T800
Test name
Test status
Simulation time 40127027500 ps
CPU time 828.76 seconds
Started Jun 02 03:18:48 PM PDT 24
Finished Jun 02 03:32:38 PM PDT 24
Peak memory 262992 kb
Host smart-80c5574b-7fc5-4956-9086-f24bb52cfeff
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270909197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.4270909197
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.1298817907
Short name T642
Test name
Test status
Simulation time 2892849000 ps
CPU time 107.85 seconds
Started Jun 02 03:18:51 PM PDT 24
Finished Jun 02 03:20:40 PM PDT 24
Peak memory 262276 kb
Host smart-4b8c7b67-9dcc-45e7-8bbd-29465398cba6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298817907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.1298817907
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.679272737
Short name T960
Test name
Test status
Simulation time 50314577600 ps
CPU time 353.13 seconds
Started Jun 02 03:18:57 PM PDT 24
Finished Jun 02 03:24:51 PM PDT 24
Peak memory 283968 kb
Host smart-3dde68f7-4505-4ea1-ad7f-edf70f366e36
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679272737 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.679272737
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.352745902
Short name T732
Test name
Test status
Simulation time 2808154400 ps
CPU time 73.71 seconds
Started Jun 02 03:18:56 PM PDT 24
Finished Jun 02 03:20:11 PM PDT 24
Peak memory 264644 kb
Host smart-33b69822-50d7-4309-81f1-1e48d22f6387
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352745902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_intr_wr.352745902
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.2488619110
Short name T503
Test name
Test status
Simulation time 82390117000 ps
CPU time 210.71 seconds
Started Jun 02 03:18:57 PM PDT 24
Finished Jun 02 03:22:29 PM PDT 24
Peak memory 264852 kb
Host smart-2fc391e8-6028-4192-b255-45261c86f5f7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248
8619110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.2488619110
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.1665940518
Short name T1078
Test name
Test status
Simulation time 4310257100 ps
CPU time 73.89 seconds
Started Jun 02 03:18:56 PM PDT 24
Finished Jun 02 03:20:11 PM PDT 24
Peak memory 259516 kb
Host smart-f9c5b7ec-7702-4659-ab7e-b5899fb67e1b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665940518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1665940518
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.3831244247
Short name T851
Test name
Test status
Simulation time 15566600 ps
CPU time 13.36 seconds
Started Jun 02 03:19:02 PM PDT 24
Finished Jun 02 03:19:16 PM PDT 24
Peak memory 259224 kb
Host smart-cc866f0d-a922-440b-82b6-eaaf0af6432b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831244247 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.3831244247
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.3831775596
Short name T114
Test name
Test status
Simulation time 7510932800 ps
CPU time 585.64 seconds
Started Jun 02 03:18:50 PM PDT 24
Finished Jun 02 03:28:36 PM PDT 24
Peak memory 274048 kb
Host smart-6445d98b-a665-4343-85ee-d1485be9d95d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831775596 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.3831775596
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.1472853546
Short name T638
Test name
Test status
Simulation time 46107700 ps
CPU time 130.69 seconds
Started Jun 02 03:18:48 PM PDT 24
Finished Jun 02 03:20:59 PM PDT 24
Peak memory 259964 kb
Host smart-021b4bcf-8edf-4954-a24e-9fa2b3ce3efc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472853546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.1472853546
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.1479396866
Short name T465
Test name
Test status
Simulation time 4544389900 ps
CPU time 167.33 seconds
Started Jun 02 03:19:03 PM PDT 24
Finished Jun 02 03:21:51 PM PDT 24
Peak memory 281212 kb
Host smart-cdb9e127-4174-405d-91b4-98c38b850346
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479396866 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.1479396866
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.2115154311
Short name T768
Test name
Test status
Simulation time 1357499700 ps
CPU time 217.75 seconds
Started Jun 02 03:18:49 PM PDT 24
Finished Jun 02 03:22:28 PM PDT 24
Peak memory 262088 kb
Host smart-cf176223-3e26-4d29-9e96-d69523f71e88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2115154311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2115154311
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.122640199
Short name T163
Test name
Test status
Simulation time 75107300 ps
CPU time 13.55 seconds
Started Jun 02 03:19:00 PM PDT 24
Finished Jun 02 03:19:14 PM PDT 24
Peak memory 258320 kb
Host smart-7425b32f-36ac-4dc1-ad1e-cec435fc1dd5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122640199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_rese
t.122640199
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.844880624
Short name T106
Test name
Test status
Simulation time 1619060000 ps
CPU time 1026.84 seconds
Started Jun 02 03:18:49 PM PDT 24
Finished Jun 02 03:35:57 PM PDT 24
Peak memory 285064 kb
Host smart-49ea1ef5-f09e-4e7f-a7a9-7ecdeb24ccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844880624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.844880624
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.3242561193
Short name T952
Test name
Test status
Simulation time 292425600 ps
CPU time 99.77 seconds
Started Jun 02 03:18:48 PM PDT 24
Finished Jun 02 03:20:28 PM PDT 24
Peak memory 265044 kb
Host smart-c2e5bc2b-41fe-4bcf-9aa7-2981b0d49c80
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3242561193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.3242561193
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.746002297
Short name T99
Test name
Test status
Simulation time 229206600 ps
CPU time 29.19 seconds
Started Jun 02 03:19:04 PM PDT 24
Finished Jun 02 03:19:34 PM PDT 24
Peak memory 274056 kb
Host smart-1aaed60a-88fb-4503-be40-453d200104fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746002297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_rd_intg.746002297
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.961099905
Short name T866
Test name
Test status
Simulation time 505106600 ps
CPU time 35.84 seconds
Started Jun 02 03:18:58 PM PDT 24
Finished Jun 02 03:19:35 PM PDT 24
Peak memory 273096 kb
Host smart-9b962661-8e10-4694-add6-c7bbd40fd1dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961099905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_re_evict.961099905
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.846686182
Short name T920
Test name
Test status
Simulation time 18043800 ps
CPU time 22.73 seconds
Started Jun 02 03:18:58 PM PDT 24
Finished Jun 02 03:19:21 PM PDT 24
Peak memory 264388 kb
Host smart-d6d82786-fa63-411e-b3e5-2bdffde5c5a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846686182 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.846686182
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.1498227576
Short name T917
Test name
Test status
Simulation time 44522900 ps
CPU time 21.4 seconds
Started Jun 02 03:19:00 PM PDT 24
Finished Jun 02 03:19:21 PM PDT 24
Peak memory 264872 kb
Host smart-39ad232d-2508-4106-901e-11df12a28d57
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498227576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.1498227576
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.3614632432
Short name T143
Test name
Test status
Simulation time 157492129800 ps
CPU time 1006.62 seconds
Started Jun 02 03:19:01 PM PDT 24
Finished Jun 02 03:35:48 PM PDT 24
Peak memory 259084 kb
Host smart-6d1d519d-2fa4-4603-89ee-bcca8df60f69
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614632432 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.3614632432
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.2869046884
Short name T1081
Test name
Test status
Simulation time 471540400 ps
CPU time 114.48 seconds
Started Jun 02 03:18:56 PM PDT 24
Finished Jun 02 03:20:51 PM PDT 24
Peak memory 297012 kb
Host smart-a4950a4a-2586-461f-99ce-728b0055bf23
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869046884 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_ro.2869046884
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.1314020188
Short name T502
Test name
Test status
Simulation time 1115461800 ps
CPU time 167.45 seconds
Started Jun 02 03:18:56 PM PDT 24
Finished Jun 02 03:21:44 PM PDT 24
Peak memory 281172 kb
Host smart-7a22a3de-af0b-45fe-8d13-7236860bca98
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1314020188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.1314020188
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.3445390673
Short name T1005
Test name
Test status
Simulation time 1452615700 ps
CPU time 134.83 seconds
Started Jun 02 03:18:57 PM PDT 24
Finished Jun 02 03:21:13 PM PDT 24
Peak memory 293632 kb
Host smart-16b9e019-fb84-4f41-b676-e95c29bdcbfd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445390673 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.3445390673
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.3085819814
Short name T1011
Test name
Test status
Simulation time 16360429900 ps
CPU time 607.65 seconds
Started Jun 02 03:18:57 PM PDT 24
Finished Jun 02 03:29:05 PM PDT 24
Peak memory 313496 kb
Host smart-b8f97079-8da9-4c2a-81e8-0e2b9b6b9d0b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085819814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.flash_ctrl_rw.3085819814
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.3796957928
Short name T51
Test name
Test status
Simulation time 28323900 ps
CPU time 28.86 seconds
Started Jun 02 03:18:57 PM PDT 24
Finished Jun 02 03:19:27 PM PDT 24
Peak memory 267764 kb
Host smart-1218cdc6-5b8f-405c-b71e-936cd971e8d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796957928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.3796957928
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.511287553
Short name T336
Test name
Test status
Simulation time 88712600 ps
CPU time 27.75 seconds
Started Jun 02 03:18:56 PM PDT 24
Finished Jun 02 03:19:24 PM PDT 24
Peak memory 274468 kb
Host smart-122e133e-dd42-45a1-a2f7-700c6d91c6d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511287553 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.511287553
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.1427164996
Short name T380
Test name
Test status
Simulation time 8961049100 ps
CPU time 73.91 seconds
Started Jun 02 03:19:03 PM PDT 24
Finished Jun 02 03:20:17 PM PDT 24
Peak memory 263788 kb
Host smart-9bd9f192-e32e-4371-ab71-a17ad23814fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427164996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.1427164996
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.400524674
Short name T700
Test name
Test status
Simulation time 387605200 ps
CPU time 50.77 seconds
Started Jun 02 03:18:55 PM PDT 24
Finished Jun 02 03:19:47 PM PDT 24
Peak memory 273100 kb
Host smart-ebc1a7be-be4a-464d-9f46-aad1c3b38a1a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400524674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_serr_address.400524674
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.1103207822
Short name T107
Test name
Test status
Simulation time 2792025600 ps
CPU time 67.81 seconds
Started Jun 02 03:18:56 PM PDT 24
Finished Jun 02 03:20:05 PM PDT 24
Peak memory 274456 kb
Host smart-f1fea86e-f77e-41a7-a708-87b12999a8eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103207822 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.1103207822
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.763749762
Short name T608
Test name
Test status
Simulation time 31940500 ps
CPU time 100.16 seconds
Started Jun 02 03:18:46 PM PDT 24
Finished Jun 02 03:20:27 PM PDT 24
Peak memory 276196 kb
Host smart-b8fd1bc8-7879-475c-8ad4-1d7b9e85d024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763749762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.763749762
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.679121227
Short name T839
Test name
Test status
Simulation time 16699900 ps
CPU time 24.06 seconds
Started Jun 02 03:18:48 PM PDT 24
Finished Jun 02 03:19:12 PM PDT 24
Peak memory 258900 kb
Host smart-36e97a6b-3845-49f7-8984-381c2fbb9e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679121227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.679121227
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.1058016317
Short name T912
Test name
Test status
Simulation time 970763300 ps
CPU time 2218.56 seconds
Started Jun 02 03:19:06 PM PDT 24
Finished Jun 02 03:56:05 PM PDT 24
Peak memory 297732 kb
Host smart-cafa2230-f83f-4d68-9197-b853fc1909fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058016317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.1058016317
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.2546352012
Short name T953
Test name
Test status
Simulation time 90125700 ps
CPU time 26.9 seconds
Started Jun 02 03:18:49 PM PDT 24
Finished Jun 02 03:19:16 PM PDT 24
Peak memory 261292 kb
Host smart-ace53673-790a-4c5e-8258-0a363e571cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546352012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2546352012
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.521186834
Short name T649
Test name
Test status
Simulation time 4238364600 ps
CPU time 175.15 seconds
Started Jun 02 03:18:55 PM PDT 24
Finished Jun 02 03:21:51 PM PDT 24
Peak memory 264800 kb
Host smart-aec5522b-7bcd-413e-9fcf-5f20d93c75f7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521186834 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_wo.521186834
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.2243936486
Short name T759
Test name
Test status
Simulation time 65857500 ps
CPU time 14.01 seconds
Started Jun 02 03:21:38 PM PDT 24
Finished Jun 02 03:21:53 PM PDT 24
Peak memory 264772 kb
Host smart-01aea1e1-136c-449e-b4ff-9fbd234ac29c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243936486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
2243936486
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.1393974620
Short name T982
Test name
Test status
Simulation time 25170000 ps
CPU time 13.38 seconds
Started Jun 02 03:21:39 PM PDT 24
Finished Jun 02 03:21:53 PM PDT 24
Peak memory 275788 kb
Host smart-1a66866b-3bc4-4730-b13b-b56c4d93ef93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393974620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1393974620
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.3709592422
Short name T388
Test name
Test status
Simulation time 27507000 ps
CPU time 22.07 seconds
Started Jun 02 03:21:38 PM PDT 24
Finished Jun 02 03:22:01 PM PDT 24
Peak memory 279964 kb
Host smart-ebb46511-6954-499e-afaa-12979f0e2ec0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709592422 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.3709592422
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.2942167528
Short name T850
Test name
Test status
Simulation time 27481600 ps
CPU time 13.41 seconds
Started Jun 02 03:21:37 PM PDT 24
Finished Jun 02 03:21:52 PM PDT 24
Peak memory 265000 kb
Host smart-da10d612-0750-4ed2-9176-5ea60dc70858
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942167528 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.2942167528
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.3096017482
Short name T864
Test name
Test status
Simulation time 40125032200 ps
CPU time 795.73 seconds
Started Jun 02 03:21:25 PM PDT 24
Finished Jun 02 03:34:42 PM PDT 24
Peak memory 259128 kb
Host smart-3c39b38c-fa44-41b9-b46b-4a681e9c4833
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096017482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.3096017482
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.2956931743
Short name T180
Test name
Test status
Simulation time 10330989700 ps
CPU time 212.98 seconds
Started Jun 02 03:21:25 PM PDT 24
Finished Jun 02 03:24:59 PM PDT 24
Peak memory 262308 kb
Host smart-cd1a59f3-3678-4f52-b275-87613a416f1d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956931743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.2956931743
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.1063541553
Short name T766
Test name
Test status
Simulation time 3018833600 ps
CPU time 197.17 seconds
Started Jun 02 03:21:31 PM PDT 24
Finished Jun 02 03:24:49 PM PDT 24
Peak memory 289432 kb
Host smart-23481b35-d8c5-4092-a460-01cf52e368d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063541553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.1063541553
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1186818145
Short name T330
Test name
Test status
Simulation time 14793164700 ps
CPU time 174.92 seconds
Started Jun 02 03:21:31 PM PDT 24
Finished Jun 02 03:24:27 PM PDT 24
Peak memory 291420 kb
Host smart-f11cedce-6d55-46c9-aecb-1b53d6b97129
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186818145 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.1186818145
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.525430364
Short name T568
Test name
Test status
Simulation time 3459241700 ps
CPU time 90.25 seconds
Started Jun 02 03:21:28 PM PDT 24
Finished Jun 02 03:22:59 PM PDT 24
Peak memory 260520 kb
Host smart-b6c1868f-fad8-4740-8442-182410a3b995
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525430364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.525430364
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.1963161911
Short name T921
Test name
Test status
Simulation time 47872600 ps
CPU time 13.39 seconds
Started Jun 02 03:21:38 PM PDT 24
Finished Jun 02 03:21:53 PM PDT 24
Peak memory 264724 kb
Host smart-a36548b3-70b5-4b20-affd-13bd165204e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963161911 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.1963161911
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.3804874852
Short name T487
Test name
Test status
Simulation time 489956800 ps
CPU time 112.76 seconds
Started Jun 02 03:21:25 PM PDT 24
Finished Jun 02 03:23:18 PM PDT 24
Peak memory 259668 kb
Host smart-9a94b2a7-8e9c-440e-b460-e17eded51337
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804874852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.3804874852
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.144363442
Short name T868
Test name
Test status
Simulation time 76355300 ps
CPU time 152.65 seconds
Started Jun 02 03:21:25 PM PDT 24
Finished Jun 02 03:23:59 PM PDT 24
Peak memory 264888 kb
Host smart-75dd2ab7-a2b1-43f4-a989-69e6fcdd29d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=144363442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.144363442
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.3891996635
Short name T706
Test name
Test status
Simulation time 2426915600 ps
CPU time 210.86 seconds
Started Jun 02 03:21:32 PM PDT 24
Finished Jun 02 03:25:03 PM PDT 24
Peak memory 264692 kb
Host smart-4a41ba96-a362-4199-9827-f39dcf824e64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891996635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.3891996635
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.2452166522
Short name T314
Test name
Test status
Simulation time 67324700 ps
CPU time 488.19 seconds
Started Jun 02 03:21:21 PM PDT 24
Finished Jun 02 03:29:30 PM PDT 24
Peak memory 281236 kb
Host smart-07085c94-7676-4783-8c1b-a0cc301d0e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452166522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2452166522
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.3903591147
Short name T1022
Test name
Test status
Simulation time 88119100 ps
CPU time 34.41 seconds
Started Jun 02 03:21:33 PM PDT 24
Finished Jun 02 03:22:08 PM PDT 24
Peak memory 273152 kb
Host smart-f6c12b2e-c226-44c3-8e58-1ccb4798f31f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903591147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.3903591147
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.2581458746
Short name T535
Test name
Test status
Simulation time 1670496400 ps
CPU time 132.01 seconds
Started Jun 02 03:21:25 PM PDT 24
Finished Jun 02 03:23:37 PM PDT 24
Peak memory 281300 kb
Host smart-f23b3fbf-e566-498b-bec5-db3e110e0cf5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581458746 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.flash_ctrl_ro.2581458746
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.836978254
Short name T105
Test name
Test status
Simulation time 7126135100 ps
CPU time 494.19 seconds
Started Jun 02 03:21:25 PM PDT 24
Finished Jun 02 03:29:40 PM PDT 24
Peak memory 309224 kb
Host smart-e2efcef2-f875-4f39-827e-ddecb4de8343
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836978254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.flash_ctrl_rw.836978254
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.3015580031
Short name T225
Test name
Test status
Simulation time 77414200 ps
CPU time 30.69 seconds
Started Jun 02 03:21:32 PM PDT 24
Finished Jun 02 03:22:03 PM PDT 24
Peak memory 275080 kb
Host smart-ace97269-2a41-4d9b-a631-30c876a6364e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015580031 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.3015580031
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.2019984039
Short name T83
Test name
Test status
Simulation time 486678000 ps
CPU time 59.44 seconds
Started Jun 02 03:21:40 PM PDT 24
Finished Jun 02 03:22:40 PM PDT 24
Peak memory 262384 kb
Host smart-08793360-79d9-405a-9710-55ede60d8078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019984039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.2019984039
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.527396250
Short name T463
Test name
Test status
Simulation time 33402300 ps
CPU time 122.55 seconds
Started Jun 02 03:21:18 PM PDT 24
Finished Jun 02 03:23:22 PM PDT 24
Peak memory 275376 kb
Host smart-6656d055-ea8a-4120-ada6-b17600fa5c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527396250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.527396250
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.611500859
Short name T1040
Test name
Test status
Simulation time 2435889100 ps
CPU time 203.45 seconds
Started Jun 02 03:21:26 PM PDT 24
Finished Jun 02 03:24:50 PM PDT 24
Peak memory 263892 kb
Host smart-91c89cae-6147-43a7-af7f-bd8a79b4b92b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611500859 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.flash_ctrl_wo.611500859
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.3041105523
Short name T1066
Test name
Test status
Simulation time 22095600 ps
CPU time 15.72 seconds
Started Jun 02 03:21:44 PM PDT 24
Finished Jun 02 03:22:00 PM PDT 24
Peak memory 274768 kb
Host smart-070bb84f-488f-4cfe-b4cd-9c1ca092cfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041105523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.3041105523
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.3306767906
Short name T698
Test name
Test status
Simulation time 15690800 ps
CPU time 21.23 seconds
Started Jun 02 03:21:45 PM PDT 24
Finished Jun 02 03:22:07 PM PDT 24
Peak memory 273112 kb
Host smart-d8029844-695d-4b9f-aac6-b04c67abfc2c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306767906 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.3306767906
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.112146896
Short name T717
Test name
Test status
Simulation time 10012254200 ps
CPU time 131.14 seconds
Started Jun 02 03:21:50 PM PDT 24
Finished Jun 02 03:24:02 PM PDT 24
Peak memory 372812 kb
Host smart-f61bb202-3dca-454a-86f6-de1624d96e5a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112146896 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.112146896
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.2658366601
Short name T172
Test name
Test status
Simulation time 200200870000 ps
CPU time 861.29 seconds
Started Jun 02 03:21:38 PM PDT 24
Finished Jun 02 03:36:00 PM PDT 24
Peak memory 263324 kb
Host smart-165909d2-0908-4887-bda0-f96e205f4839
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658366601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.2658366601
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.3364749033
Short name T310
Test name
Test status
Simulation time 2238912800 ps
CPU time 52.65 seconds
Started Jun 02 03:21:39 PM PDT 24
Finished Jun 02 03:22:32 PM PDT 24
Peak memory 261792 kb
Host smart-7eaf5057-587a-41f8-b756-57ad0b9516a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364749033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.3364749033
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.2813078143
Short name T493
Test name
Test status
Simulation time 1479009000 ps
CPU time 213.41 seconds
Started Jun 02 03:21:39 PM PDT 24
Finished Jun 02 03:25:13 PM PDT 24
Peak memory 290548 kb
Host smart-913693b6-c030-4dde-a5e3-d981ebc3abee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813078143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.2813078143
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.1274118195
Short name T823
Test name
Test status
Simulation time 5802451300 ps
CPU time 127.68 seconds
Started Jun 02 03:21:37 PM PDT 24
Finished Jun 02 03:23:46 PM PDT 24
Peak memory 291500 kb
Host smart-1490bcaf-3140-449b-8878-911b0d41f630
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274118195 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.1274118195
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.1046133487
Short name T833
Test name
Test status
Simulation time 9715415900 ps
CPU time 96.49 seconds
Started Jun 02 03:21:38 PM PDT 24
Finished Jun 02 03:23:16 PM PDT 24
Peak memory 263084 kb
Host smart-0979bd60-91d3-4bea-86b3-411e0a7df8e1
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046133487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.1
046133487
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.4235522152
Short name T857
Test name
Test status
Simulation time 26126900 ps
CPU time 13.69 seconds
Started Jun 02 03:21:44 PM PDT 24
Finished Jun 02 03:21:58 PM PDT 24
Peak memory 259176 kb
Host smart-b6d3146b-3b61-4f0d-a71d-c8a868f39bf0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235522152 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.4235522152
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.1946545967
Short name T116
Test name
Test status
Simulation time 11731402400 ps
CPU time 295.19 seconds
Started Jun 02 03:21:38 PM PDT 24
Finished Jun 02 03:26:34 PM PDT 24
Peak memory 273440 kb
Host smart-f0551dad-b2b4-4d61-92bf-513ba8e0d83a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946545967 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.1946545967
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.4090874029
Short name T520
Test name
Test status
Simulation time 34146900 ps
CPU time 131.17 seconds
Started Jun 02 03:21:38 PM PDT 24
Finished Jun 02 03:23:50 PM PDT 24
Peak memory 259764 kb
Host smart-77aea0e2-7cdc-499f-858e-55a75ecf7583
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090874029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.4090874029
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.1823682281
Short name T478
Test name
Test status
Simulation time 7531717800 ps
CPU time 138.54 seconds
Started Jun 02 03:21:38 PM PDT 24
Finished Jun 02 03:23:58 PM PDT 24
Peak memory 261512 kb
Host smart-c836e844-13b1-413a-b286-293fb07653e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823682281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.1823682281
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.315994273
Short name T986
Test name
Test status
Simulation time 20741500 ps
CPU time 13.5 seconds
Started Jun 02 03:21:39 PM PDT 24
Finished Jun 02 03:21:53 PM PDT 24
Peak memory 264744 kb
Host smart-4834435f-95b0-4ab9-bad8-48825e93399a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315994273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_res
et.315994273
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.1698047511
Short name T679
Test name
Test status
Simulation time 25711300 ps
CPU time 220.62 seconds
Started Jun 02 03:21:39 PM PDT 24
Finished Jun 02 03:25:20 PM PDT 24
Peak memory 272004 kb
Host smart-83b2ec74-037b-48e2-b60a-1e42b6461550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698047511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.1698047511
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.771049845
Short name T182
Test name
Test status
Simulation time 4040411200 ps
CPU time 113.16 seconds
Started Jun 02 03:21:39 PM PDT 24
Finished Jun 02 03:23:33 PM PDT 24
Peak memory 296996 kb
Host smart-0f7d2739-dc5f-4587-aad8-f1203b91005b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771049845 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.flash_ctrl_ro.771049845
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.3248296977
Short name T696
Test name
Test status
Simulation time 3785663000 ps
CPU time 519.8 seconds
Started Jun 02 03:21:37 PM PDT 24
Finished Jun 02 03:30:18 PM PDT 24
Peak memory 313400 kb
Host smart-52e9f570-b250-4189-81ba-64e0a5dc1f05
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248296977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_rw.3248296977
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.51459945
Short name T25
Test name
Test status
Simulation time 88327800 ps
CPU time 31.72 seconds
Started Jun 02 03:21:38 PM PDT 24
Finished Jun 02 03:22:11 PM PDT 24
Peak memory 273172 kb
Host smart-3e7096e2-f7ce-4d48-9a72-f20022f12c92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51459945 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.51459945
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.1681091949
Short name T242
Test name
Test status
Simulation time 57705500 ps
CPU time 170.93 seconds
Started Jun 02 03:21:39 PM PDT 24
Finished Jun 02 03:24:31 PM PDT 24
Peak memory 276604 kb
Host smart-6075e1e2-5e6b-473d-8548-a71797f50480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681091949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.1681091949
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.1681945141
Short name T427
Test name
Test status
Simulation time 5374871400 ps
CPU time 226.38 seconds
Started Jun 02 03:21:39 PM PDT 24
Finished Jun 02 03:25:26 PM PDT 24
Peak memory 264796 kb
Host smart-b1ded1c4-5635-4974-b01f-8f6eeaca444b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681945141 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.flash_ctrl_wo.1681945141
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.3977240123
Short name T889
Test name
Test status
Simulation time 24540400 ps
CPU time 13.64 seconds
Started Jun 02 03:21:57 PM PDT 24
Finished Jun 02 03:22:11 PM PDT 24
Peak memory 264852 kb
Host smart-5c4e6bca-aa28-48a4-aa3d-0002a7d75479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977240123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
3977240123
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.1737168654
Short name T867
Test name
Test status
Simulation time 16013000 ps
CPU time 13.39 seconds
Started Jun 02 03:21:57 PM PDT 24
Finished Jun 02 03:22:11 PM PDT 24
Peak memory 275532 kb
Host smart-6a58a134-b62b-4229-a2fe-941b468f9d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737168654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.1737168654
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.3013600366
Short name T546
Test name
Test status
Simulation time 17529800 ps
CPU time 21.61 seconds
Started Jun 02 03:21:55 PM PDT 24
Finished Jun 02 03:22:17 PM PDT 24
Peak memory 273224 kb
Host smart-53e086a2-5550-454b-87d6-cd4fcf9fe43a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013600366 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.3013600366
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2721095185
Short name T134
Test name
Test status
Simulation time 10039345100 ps
CPU time 59.75 seconds
Started Jun 02 03:21:58 PM PDT 24
Finished Jun 02 03:22:58 PM PDT 24
Peak memory 287008 kb
Host smart-4566a9b5-b2e0-44b1-bbf4-f1e8ef9c9391
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721095185 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2721095185
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.2276912029
Short name T825
Test name
Test status
Simulation time 148557700 ps
CPU time 13.83 seconds
Started Jun 02 03:21:57 PM PDT 24
Finished Jun 02 03:22:12 PM PDT 24
Peak memory 258776 kb
Host smart-9bb6136e-a19a-4516-b871-dea4bd5a85fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276912029 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.2276912029
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.3444924372
Short name T126
Test name
Test status
Simulation time 40125255400 ps
CPU time 836.9 seconds
Started Jun 02 03:21:49 PM PDT 24
Finished Jun 02 03:35:46 PM PDT 24
Peak memory 263048 kb
Host smart-84f1c174-c296-40e4-bfcf-4e4f34810560
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444924372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.3444924372
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.916725172
Short name T934
Test name
Test status
Simulation time 6822816700 ps
CPU time 124.83 seconds
Started Jun 02 03:21:50 PM PDT 24
Finished Jun 02 03:23:56 PM PDT 24
Peak memory 262476 kb
Host smart-c6cca91a-d8e9-4660-bc8b-e8b037471493
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916725172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_h
w_sec_otp.916725172
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.3166376193
Short name T710
Test name
Test status
Simulation time 6324354200 ps
CPU time 191.15 seconds
Started Jun 02 03:21:55 PM PDT 24
Finished Jun 02 03:25:07 PM PDT 24
Peak memory 290476 kb
Host smart-29fc8e55-3b5d-43a5-93f3-9d1018e894f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166376193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.3166376193
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.2058628453
Short name T612
Test name
Test status
Simulation time 49629047200 ps
CPU time 356.86 seconds
Started Jun 02 03:21:58 PM PDT 24
Finished Jun 02 03:27:55 PM PDT 24
Peak memory 292376 kb
Host smart-fae647bf-0399-4b1b-9b02-3d76226712a7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058628453 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.2058628453
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.4204540467
Short name T93
Test name
Test status
Simulation time 1002119700 ps
CPU time 88.01 seconds
Started Jun 02 03:21:50 PM PDT 24
Finished Jun 02 03:23:18 PM PDT 24
Peak memory 259508 kb
Host smart-35da4d73-5b44-49ef-8611-3edb1f4bddd5
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204540467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.4
204540467
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.3626333664
Short name T119
Test name
Test status
Simulation time 15976400 ps
CPU time 13.9 seconds
Started Jun 02 03:21:58 PM PDT 24
Finished Jun 02 03:22:12 PM PDT 24
Peak memory 260120 kb
Host smart-ef14ca8c-4897-495d-8a7e-c3e9c0e856c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626333664 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.3626333664
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.3051072156
Short name T113
Test name
Test status
Simulation time 8784586300 ps
CPU time 559.67 seconds
Started Jun 02 03:21:52 PM PDT 24
Finished Jun 02 03:31:12 PM PDT 24
Peak memory 273840 kb
Host smart-3ab7a546-d027-4825-8dfe-02c11264b6d3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051072156 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.3051072156
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.4152806417
Short name T451
Test name
Test status
Simulation time 144867500 ps
CPU time 129.58 seconds
Started Jun 02 03:21:51 PM PDT 24
Finished Jun 02 03:24:01 PM PDT 24
Peak memory 260932 kb
Host smart-ac12183b-b1cb-45a5-9707-96a9437492a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152806417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.4152806417
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.1124553251
Short name T562
Test name
Test status
Simulation time 262487100 ps
CPU time 373.28 seconds
Started Jun 02 03:21:50 PM PDT 24
Finished Jun 02 03:28:04 PM PDT 24
Peak memory 261468 kb
Host smart-74d9ca8b-e05b-442b-b5cd-20168eee7472
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1124553251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1124553251
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.3896794945
Short name T598
Test name
Test status
Simulation time 21890200 ps
CPU time 13.43 seconds
Started Jun 02 03:21:55 PM PDT 24
Finished Jun 02 03:22:09 PM PDT 24
Peak memory 258348 kb
Host smart-bcac5977-291c-4d43-b740-8da6f9342217
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896794945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.3896794945
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.2730185981
Short name T117
Test name
Test status
Simulation time 826850900 ps
CPU time 1338.68 seconds
Started Jun 02 03:21:50 PM PDT 24
Finished Jun 02 03:44:09 PM PDT 24
Peak memory 283988 kb
Host smart-106035f6-148e-43ff-95fe-3a5a5f4b1ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730185981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.2730185981
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.2979939774
Short name T456
Test name
Test status
Simulation time 107280400 ps
CPU time 37 seconds
Started Jun 02 03:21:58 PM PDT 24
Finished Jun 02 03:22:36 PM PDT 24
Peak memory 273040 kb
Host smart-b7167001-78b9-4698-9aeb-55c48b3aa59b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979939774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.2979939774
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.1741915181
Short name T181
Test name
Test status
Simulation time 2238873600 ps
CPU time 127.71 seconds
Started Jun 02 03:21:50 PM PDT 24
Finished Jun 02 03:23:58 PM PDT 24
Peak memory 281344 kb
Host smart-3784269f-52bf-4237-a718-1ec6089fc6f9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741915181 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_ro.1741915181
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.2888859794
Short name T670
Test name
Test status
Simulation time 7530268300 ps
CPU time 633.66 seconds
Started Jun 02 03:21:49 PM PDT 24
Finished Jun 02 03:32:24 PM PDT 24
Peak memory 313224 kb
Host smart-cab166d5-72d7-4c9d-ba9f-25ff8e662034
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888859794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.2888859794
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.1593356011
Short name T922
Test name
Test status
Simulation time 556293400 ps
CPU time 63.65 seconds
Started Jun 02 03:21:54 PM PDT 24
Finished Jun 02 03:22:58 PM PDT 24
Peak memory 263700 kb
Host smart-15635563-0f48-47a3-8340-2f6959ebe04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593356011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.1593356011
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.719684813
Short name T548
Test name
Test status
Simulation time 110798100 ps
CPU time 99.03 seconds
Started Jun 02 03:21:50 PM PDT 24
Finished Jun 02 03:23:29 PM PDT 24
Peak memory 275296 kb
Host smart-56e978cf-d968-46cd-8baf-1878c487ee61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719684813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.719684813
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.712617366
Short name T435
Test name
Test status
Simulation time 3956587100 ps
CPU time 190.3 seconds
Started Jun 02 03:21:50 PM PDT 24
Finished Jun 02 03:25:01 PM PDT 24
Peak memory 264764 kb
Host smart-33e0dd84-2881-4f75-963f-4839bd8f0678
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712617366 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.flash_ctrl_wo.712617366
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.4110197851
Short name T783
Test name
Test status
Simulation time 124640000 ps
CPU time 14.44 seconds
Started Jun 02 03:22:15 PM PDT 24
Finished Jun 02 03:22:30 PM PDT 24
Peak memory 263772 kb
Host smart-6b023db7-0814-414b-b157-f84224424e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110197851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
4110197851
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.2449118115
Short name T450
Test name
Test status
Simulation time 14589700 ps
CPU time 15.98 seconds
Started Jun 02 03:22:11 PM PDT 24
Finished Jun 02 03:22:28 PM PDT 24
Peak memory 274780 kb
Host smart-b8173073-7e70-4e3b-8d1b-4b3073573509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449118115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.2449118115
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2335764016
Short name T130
Test name
Test status
Simulation time 10018177100 ps
CPU time 189.92 seconds
Started Jun 02 03:22:14 PM PDT 24
Finished Jun 02 03:25:25 PM PDT 24
Peak memory 297320 kb
Host smart-bee0d956-eea5-40d2-a8a5-d96bd1322929
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335764016 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.2335764016
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.3889424384
Short name T572
Test name
Test status
Simulation time 129239400 ps
CPU time 14.06 seconds
Started Jun 02 03:22:14 PM PDT 24
Finished Jun 02 03:22:28 PM PDT 24
Peak memory 258084 kb
Host smart-5df34ba8-7896-4487-9029-bb6126ad94ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889424384 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3889424384
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.2857095338
Short name T665
Test name
Test status
Simulation time 180215433700 ps
CPU time 871.89 seconds
Started Jun 02 03:21:56 PM PDT 24
Finished Jun 02 03:36:28 PM PDT 24
Peak memory 263896 kb
Host smart-2183ed4f-7a9a-47c3-9f12-08de2f983a1e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857095338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.2857095338
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.2892836304
Short name T509
Test name
Test status
Simulation time 11910756100 ps
CPU time 231.18 seconds
Started Jun 02 03:21:56 PM PDT 24
Finished Jun 02 03:25:48 PM PDT 24
Peak memory 261960 kb
Host smart-6e3d1c20-4fe7-42a0-898a-ec95fde30b2a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892836304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.2892836304
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.648786692
Short name T34
Test name
Test status
Simulation time 64506344100 ps
CPU time 567.95 seconds
Started Jun 02 03:22:01 PM PDT 24
Finished Jun 02 03:31:30 PM PDT 24
Peak memory 292928 kb
Host smart-0b7e44fb-70e2-46bf-bc06-91ffcc87767a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648786692 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.648786692
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.925315480
Short name T1080
Test name
Test status
Simulation time 1633337900 ps
CPU time 75.78 seconds
Started Jun 02 03:22:01 PM PDT 24
Finished Jun 02 03:23:18 PM PDT 24
Peak memory 259568 kb
Host smart-d36b344a-6436-42ff-8132-f2d67ead9ae8
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925315480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.925315480
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2038131042
Short name T635
Test name
Test status
Simulation time 47174000 ps
CPU time 13.73 seconds
Started Jun 02 03:22:08 PM PDT 24
Finished Jun 02 03:22:22 PM PDT 24
Peak memory 264788 kb
Host smart-8dd729b5-4cc6-4edf-a4ba-c4d8ff97b66e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038131042 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2038131042
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.433551128
Short name T95
Test name
Test status
Simulation time 29203138300 ps
CPU time 369.98 seconds
Started Jun 02 03:22:02 PM PDT 24
Finished Jun 02 03:28:13 PM PDT 24
Peak memory 273880 kb
Host smart-2440f132-594c-4976-94a6-548a27040cdb
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433551128 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_mp_regions.433551128
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.586642779
Short name T474
Test name
Test status
Simulation time 78171800 ps
CPU time 129.4 seconds
Started Jun 02 03:22:02 PM PDT 24
Finished Jun 02 03:24:12 PM PDT 24
Peak memory 259920 kb
Host smart-b89fc548-bba9-4728-8696-adac42ca27a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586642779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ot
p_reset.586642779
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.3438367511
Short name T746
Test name
Test status
Simulation time 1519002400 ps
CPU time 494.02 seconds
Started Jun 02 03:22:00 PM PDT 24
Finished Jun 02 03:30:15 PM PDT 24
Peak memory 262268 kb
Host smart-c1f0c5c9-958d-4853-9f0d-cb0a38a5b3a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3438367511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.3438367511
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.1089548551
Short name T448
Test name
Test status
Simulation time 18722000 ps
CPU time 13.45 seconds
Started Jun 02 03:22:02 PM PDT 24
Finished Jun 02 03:22:16 PM PDT 24
Peak memory 264740 kb
Host smart-06141aed-82eb-485b-a0c8-2da0a6a74432
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089548551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.1089548551
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.941744129
Short name T109
Test name
Test status
Simulation time 231052800 ps
CPU time 316.53 seconds
Started Jun 02 03:21:55 PM PDT 24
Finished Jun 02 03:27:12 PM PDT 24
Peak memory 272260 kb
Host smart-bc2e8313-cded-4fe2-9fe6-371393acd2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941744129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.941744129
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.888406256
Short name T637
Test name
Test status
Simulation time 139980000 ps
CPU time 38.95 seconds
Started Jun 02 03:22:09 PM PDT 24
Finished Jun 02 03:22:48 PM PDT 24
Peak memory 273128 kb
Host smart-98294c3b-60de-4c31-92a7-13ac99e3f481
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888406256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_re_evict.888406256
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.1283281212
Short name T999
Test name
Test status
Simulation time 944156500 ps
CPU time 139.96 seconds
Started Jun 02 03:22:03 PM PDT 24
Finished Jun 02 03:24:23 PM PDT 24
Peak memory 297108 kb
Host smart-616fb884-48f6-47b7-a7fa-9cbb264e6a85
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283281212 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.flash_ctrl_ro.1283281212
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.2619496441
Short name T699
Test name
Test status
Simulation time 7963338400 ps
CPU time 583.43 seconds
Started Jun 02 03:22:02 PM PDT 24
Finished Jun 02 03:31:46 PM PDT 24
Peak memory 313368 kb
Host smart-375b7a79-e726-4212-b4fa-e0196fc18852
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619496441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.flash_ctrl_rw.2619496441
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.901834212
Short name T628
Test name
Test status
Simulation time 29996300 ps
CPU time 28.47 seconds
Started Jun 02 03:22:01 PM PDT 24
Finished Jun 02 03:22:30 PM PDT 24
Peak memory 274380 kb
Host smart-8fd7204b-3896-4931-905d-14e435195b91
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901834212 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.901834212
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.2562070047
Short name T669
Test name
Test status
Simulation time 38406700 ps
CPU time 96.14 seconds
Started Jun 02 03:21:57 PM PDT 24
Finished Jun 02 03:23:34 PM PDT 24
Peak memory 276248 kb
Host smart-ccd90834-48d8-4732-bf16-ea49e5691a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562070047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2562070047
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.589117762
Short name T865
Test name
Test status
Simulation time 8316371600 ps
CPU time 182.59 seconds
Started Jun 02 03:22:03 PM PDT 24
Finished Jun 02 03:25:06 PM PDT 24
Peak memory 263900 kb
Host smart-3505dba6-ef42-45a2-ae7c-b0dfeef9e0fe
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589117762 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.flash_ctrl_wo.589117762
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.1775094328
Short name T916
Test name
Test status
Simulation time 53783300 ps
CPU time 13.64 seconds
Started Jun 02 03:22:40 PM PDT 24
Finished Jun 02 03:22:54 PM PDT 24
Peak memory 264792 kb
Host smart-168561ae-d38f-47fe-bf3c-a90763156775
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775094328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
1775094328
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.2955153265
Short name T736
Test name
Test status
Simulation time 39709800 ps
CPU time 15.77 seconds
Started Jun 02 03:22:20 PM PDT 24
Finished Jun 02 03:22:36 PM PDT 24
Peak memory 275456 kb
Host smart-dd136da5-65cc-44d1-b6c5-827a6da2fda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955153265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.2955153265
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.3589978846
Short name T1034
Test name
Test status
Simulation time 11192700 ps
CPU time 21.43 seconds
Started Jun 02 03:22:28 PM PDT 24
Finished Jun 02 03:22:50 PM PDT 24
Peak memory 273188 kb
Host smart-6194a0b0-ccbe-455e-8eab-d03541a65ddb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589978846 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.3589978846
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1330471948
Short name T708
Test name
Test status
Simulation time 10038768100 ps
CPU time 47.69 seconds
Started Jun 02 03:22:40 PM PDT 24
Finished Jun 02 03:23:28 PM PDT 24
Peak memory 277892 kb
Host smart-f119408f-9464-4e8a-a947-377a8075a279
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330471948 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1330471948
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.211045971
Short name T365
Test name
Test status
Simulation time 27077700 ps
CPU time 13.4 seconds
Started Jun 02 03:22:26 PM PDT 24
Finished Jun 02 03:22:40 PM PDT 24
Peak memory 258872 kb
Host smart-04d77a28-b294-4789-9866-96e01adc4aff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211045971 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.211045971
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.4262787654
Short name T154
Test name
Test status
Simulation time 40124680300 ps
CPU time 862.1 seconds
Started Jun 02 03:22:14 PM PDT 24
Finished Jun 02 03:36:36 PM PDT 24
Peak memory 262992 kb
Host smart-db3b58a6-dfd5-4ccc-b5d4-d4d1126383a6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262787654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.4262787654
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.2522217077
Short name T931
Test name
Test status
Simulation time 3639555800 ps
CPU time 113.91 seconds
Started Jun 02 03:22:15 PM PDT 24
Finished Jun 02 03:24:09 PM PDT 24
Peak memory 262456 kb
Host smart-5de992a5-1f84-4896-9124-dec7e2d0022a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522217077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.2522217077
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.2727700811
Short name T758
Test name
Test status
Simulation time 1693384900 ps
CPU time 220.26 seconds
Started Jun 02 03:22:20 PM PDT 24
Finished Jun 02 03:26:01 PM PDT 24
Peak memory 291212 kb
Host smart-b401564f-cf2c-4dcb-b23c-3cd8f836d5b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727700811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.2727700811
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.1657180868
Short name T925
Test name
Test status
Simulation time 25493740200 ps
CPU time 293.7 seconds
Started Jun 02 03:22:20 PM PDT 24
Finished Jun 02 03:27:15 PM PDT 24
Peak memory 283780 kb
Host smart-f9fc95bf-c871-4564-8352-f892a68f2ccf
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657180868 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.1657180868
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.3161582413
Short name T631
Test name
Test status
Simulation time 3906671300 ps
CPU time 94.31 seconds
Started Jun 02 03:22:16 PM PDT 24
Finished Jun 02 03:23:50 PM PDT 24
Peak memory 259696 kb
Host smart-7d55b5e9-abb4-4519-b909-b3bce76e65b1
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161582413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.3
161582413
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.309800747
Short name T701
Test name
Test status
Simulation time 15328600 ps
CPU time 13.7 seconds
Started Jun 02 03:22:26 PM PDT 24
Finished Jun 02 03:22:40 PM PDT 24
Peak memory 264740 kb
Host smart-75460e53-fba2-466b-87ac-85450828c143
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309800747 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.309800747
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.2190443187
Short name T919
Test name
Test status
Simulation time 42208025200 ps
CPU time 275.66 seconds
Started Jun 02 03:22:16 PM PDT 24
Finished Jun 02 03:26:52 PM PDT 24
Peak memory 273892 kb
Host smart-713a692c-c28b-48b0-8813-84a9845e44ad
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190443187 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.2190443187
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.1270017179
Short name T765
Test name
Test status
Simulation time 43599800 ps
CPU time 131.2 seconds
Started Jun 02 03:22:15 PM PDT 24
Finished Jun 02 03:24:26 PM PDT 24
Peak memory 259592 kb
Host smart-a3d74096-9126-439e-912f-5b59e005c4fe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270017179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.1270017179
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.1925383384
Short name T71
Test name
Test status
Simulation time 2794147800 ps
CPU time 455.26 seconds
Started Jun 02 03:22:14 PM PDT 24
Finished Jun 02 03:29:50 PM PDT 24
Peak memory 262196 kb
Host smart-0437f394-4a70-4099-b360-a1aed9aeb973
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1925383384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.1925383384
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.4073941035
Short name T437
Test name
Test status
Simulation time 82532100 ps
CPU time 14.01 seconds
Started Jun 02 03:22:20 PM PDT 24
Finished Jun 02 03:22:35 PM PDT 24
Peak memory 258312 kb
Host smart-33b0be82-fa36-4da7-b327-e24b7ae3d8aa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073941035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.4073941035
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.3660336806
Short name T913
Test name
Test status
Simulation time 89627900 ps
CPU time 130.07 seconds
Started Jun 02 03:22:14 PM PDT 24
Finished Jun 02 03:24:25 PM PDT 24
Peak memory 269940 kb
Host smart-c31408c2-3d04-46d9-993d-67d4d178d75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660336806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3660336806
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3157607977
Short name T341
Test name
Test status
Simulation time 73142000 ps
CPU time 33.81 seconds
Started Jun 02 03:22:21 PM PDT 24
Finished Jun 02 03:22:55 PM PDT 24
Peak memory 273088 kb
Host smart-59ff84f9-1e86-471c-ad8d-fb89b4228e0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157607977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3157607977
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.2133616048
Short name T586
Test name
Test status
Simulation time 491845800 ps
CPU time 103.6 seconds
Started Jun 02 03:22:21 PM PDT 24
Finished Jun 02 03:24:05 PM PDT 24
Peak memory 288800 kb
Host smart-1c387716-ac0a-471e-9e6f-00d71103367a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133616048 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.flash_ctrl_ro.2133616048
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.1155874965
Short name T985
Test name
Test status
Simulation time 4162365900 ps
CPU time 632.36 seconds
Started Jun 02 03:22:20 PM PDT 24
Finished Jun 02 03:32:53 PM PDT 24
Peak memory 314200 kb
Host smart-4b1093ef-daee-4f65-b0a7-e5f0c77cb2d3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155874965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.1155874965
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.4276718159
Short name T110
Test name
Test status
Simulation time 32816600 ps
CPU time 30.75 seconds
Started Jun 02 03:22:21 PM PDT 24
Finished Jun 02 03:22:52 PM PDT 24
Peak memory 273052 kb
Host smart-2885cca9-eef7-4cf2-a70d-f74f5d259325
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276718159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.4276718159
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.3214445807
Short name T855
Test name
Test status
Simulation time 68433800 ps
CPU time 30.86 seconds
Started Jun 02 03:22:21 PM PDT 24
Finished Jun 02 03:22:52 PM PDT 24
Peak memory 274476 kb
Host smart-85c690e0-2d6a-4714-b022-f144aef12f7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214445807 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.3214445807
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.1945986848
Short name T401
Test name
Test status
Simulation time 8965384100 ps
CPU time 92.08 seconds
Started Jun 02 03:22:21 PM PDT 24
Finished Jun 02 03:23:53 PM PDT 24
Peak memory 262656 kb
Host smart-b9991537-5133-4cd2-87d0-48e27feb20fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945986848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.1945986848
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.438138935
Short name T567
Test name
Test status
Simulation time 26716300 ps
CPU time 102.12 seconds
Started Jun 02 03:22:14 PM PDT 24
Finished Jun 02 03:23:57 PM PDT 24
Peak memory 275104 kb
Host smart-37207a1f-7583-40a2-9f56-70726e1958ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438138935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.438138935
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.1370584262
Short name T500
Test name
Test status
Simulation time 3404696600 ps
CPU time 174.52 seconds
Started Jun 02 03:22:16 PM PDT 24
Finished Jun 02 03:25:12 PM PDT 24
Peak memory 259156 kb
Host smart-98d38bad-2d64-4920-bc7a-cdb2675975a9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370584262 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.1370584262
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.3925261009
Short name T1076
Test name
Test status
Simulation time 19497600 ps
CPU time 13.45 seconds
Started Jun 02 03:22:32 PM PDT 24
Finished Jun 02 03:22:46 PM PDT 24
Peak memory 264796 kb
Host smart-3b2d36ae-a9b4-4954-a030-2aec0c218a0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925261009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
3925261009
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.1639679204
Short name T464
Test name
Test status
Simulation time 69557400 ps
CPU time 15.56 seconds
Started Jun 02 03:22:33 PM PDT 24
Finished Jun 02 03:22:49 PM PDT 24
Peak memory 275560 kb
Host smart-567c4f60-9d3a-43f0-b063-9e8485f68b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639679204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1639679204
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.34349622
Short name T724
Test name
Test status
Simulation time 17282200 ps
CPU time 20.57 seconds
Started Jun 02 03:22:33 PM PDT 24
Finished Jun 02 03:22:55 PM PDT 24
Peak memory 273216 kb
Host smart-fe3a40a5-2911-4622-b32a-ed7b9585e02e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34349622 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.flash_ctrl_disable.34349622
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.973380058
Short name T505
Test name
Test status
Simulation time 10033867600 ps
CPU time 51.89 seconds
Started Jun 02 03:22:34 PM PDT 24
Finished Jun 02 03:23:27 PM PDT 24
Peak memory 281452 kb
Host smart-de2d20bc-834b-4fa2-a88e-60165bd614ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973380058 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.973380058
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.1381406664
Short name T558
Test name
Test status
Simulation time 27037900 ps
CPU time 13.44 seconds
Started Jun 02 03:22:32 PM PDT 24
Finished Jun 02 03:22:46 PM PDT 24
Peak memory 264928 kb
Host smart-4ed21e9f-cac2-47e6-a05a-69a371697496
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381406664 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.1381406664
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.4104373042
Short name T1069
Test name
Test status
Simulation time 60138169300 ps
CPU time 870.69 seconds
Started Jun 02 03:22:39 PM PDT 24
Finished Jun 02 03:37:11 PM PDT 24
Peak memory 263040 kb
Host smart-42a33cdb-5cc6-471b-b4ba-c5c1f04bd2e9
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104373042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.4104373042
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.3606914368
Short name T1060
Test name
Test status
Simulation time 812745400 ps
CPU time 45.4 seconds
Started Jun 02 03:22:40 PM PDT 24
Finished Jun 02 03:23:26 PM PDT 24
Peak memory 261776 kb
Host smart-d128276d-326c-43aa-94bb-76186dc7e370
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606914368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.3606914368
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.1378741086
Short name T298
Test name
Test status
Simulation time 11672264000 ps
CPU time 62.92 seconds
Started Jun 02 03:22:40 PM PDT 24
Finished Jun 02 03:23:43 PM PDT 24
Peak memory 260372 kb
Host smart-a338267b-714b-4a16-8690-29ae0c933b62
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378741086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1
378741086
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.1835090373
Short name T773
Test name
Test status
Simulation time 27183000 ps
CPU time 13.54 seconds
Started Jun 02 03:22:33 PM PDT 24
Finished Jun 02 03:22:48 PM PDT 24
Peak memory 264760 kb
Host smart-f02d5672-9b78-49ed-9f05-8ba96f66ee78
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835090373 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.1835090373
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.2335018886
Short name T75
Test name
Test status
Simulation time 50725900 ps
CPU time 129.95 seconds
Started Jun 02 03:22:26 PM PDT 24
Finished Jun 02 03:24:37 PM PDT 24
Peak memory 259540 kb
Host smart-e5e2e409-ff64-4b7a-a7ce-0042bd494600
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335018886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.2335018886
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.2391494729
Short name T1050
Test name
Test status
Simulation time 4129060400 ps
CPU time 484.57 seconds
Started Jun 02 03:22:25 PM PDT 24
Finished Jun 02 03:30:30 PM PDT 24
Peak memory 264856 kb
Host smart-69390eef-756d-48c0-8fb5-407a4df8faae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391494729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2391494729
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.2199402037
Short name T614
Test name
Test status
Simulation time 28201146700 ps
CPU time 199.84 seconds
Started Jun 02 03:22:32 PM PDT 24
Finished Jun 02 03:25:52 PM PDT 24
Peak memory 264808 kb
Host smart-16675a7d-d742-4505-92e5-66af5f5ed65f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199402037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_re
set.2199402037
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.2730929806
Short name T115
Test name
Test status
Simulation time 2122155500 ps
CPU time 1052.93 seconds
Started Jun 02 03:22:40 PM PDT 24
Finished Jun 02 03:40:14 PM PDT 24
Peak memory 286056 kb
Host smart-6ff037e7-7657-4ccc-95f3-64daa28ed202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730929806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.2730929806
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.1356528247
Short name T1008
Test name
Test status
Simulation time 75587300 ps
CPU time 31.51 seconds
Started Jun 02 03:22:35 PM PDT 24
Finished Jun 02 03:23:07 PM PDT 24
Peak memory 273116 kb
Host smart-c01c3c7e-8baf-4655-91d9-2ac093224d90
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356528247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.1356528247
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.3636413499
Short name T1032
Test name
Test status
Simulation time 1335111700 ps
CPU time 105.19 seconds
Started Jun 02 03:22:40 PM PDT 24
Finished Jun 02 03:24:26 PM PDT 24
Peak memory 281292 kb
Host smart-876d3017-0af1-48a5-ad2e-2a614219a50b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636413499 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_ro.3636413499
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.33338315
Short name T495
Test name
Test status
Simulation time 18781224900 ps
CPU time 581.52 seconds
Started Jun 02 03:22:27 PM PDT 24
Finished Jun 02 03:32:09 PM PDT 24
Peak memory 309120 kb
Host smart-89683d6e-35aa-4e7e-af56-b90517216e48
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33338315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.flash_ctrl_rw.33338315
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.3484191394
Short name T318
Test name
Test status
Simulation time 48041500 ps
CPU time 30.89 seconds
Started Jun 02 03:22:33 PM PDT 24
Finished Jun 02 03:23:05 PM PDT 24
Peak memory 274476 kb
Host smart-adeb3ee6-8131-495c-a586-8d635aa9d54d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484191394 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.3484191394
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.430779230
Short name T423
Test name
Test status
Simulation time 1761987400 ps
CPU time 64.59 seconds
Started Jun 02 03:22:35 PM PDT 24
Finished Jun 02 03:23:40 PM PDT 24
Peak memory 262040 kb
Host smart-96dcf0ba-b8ed-43bb-81b7-8c267c198836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430779230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.430779230
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.1539452335
Short name T483
Test name
Test status
Simulation time 56956800 ps
CPU time 72.23 seconds
Started Jun 02 03:22:26 PM PDT 24
Finished Jun 02 03:23:39 PM PDT 24
Peak memory 274784 kb
Host smart-ef0a1565-5559-4351-8009-d35517020403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539452335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.1539452335
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.2293992483
Short name T958
Test name
Test status
Simulation time 1803815800 ps
CPU time 134.66 seconds
Started Jun 02 03:22:27 PM PDT 24
Finished Jun 02 03:24:43 PM PDT 24
Peak memory 258484 kb
Host smart-01c6dbf7-f406-424c-84e6-f52cdad3f98c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293992483 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.flash_ctrl_wo.2293992483
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.2936234476
Short name T460
Test name
Test status
Simulation time 92601600 ps
CPU time 14.27 seconds
Started Jun 02 03:22:43 PM PDT 24
Finished Jun 02 03:22:58 PM PDT 24
Peak memory 264200 kb
Host smart-734859ec-6836-4afe-a52e-ccc3e747b8ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936234476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
2936234476
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.273680433
Short name T680
Test name
Test status
Simulation time 43726200 ps
CPU time 15.6 seconds
Started Jun 02 03:22:43 PM PDT 24
Finished Jun 02 03:22:59 PM PDT 24
Peak memory 275528 kb
Host smart-8413c1be-acb0-452b-89a5-43e51fa4d9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273680433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.273680433
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.1449303487
Short name T129
Test name
Test status
Simulation time 10019365700 ps
CPU time 173.68 seconds
Started Jun 02 03:22:44 PM PDT 24
Finished Jun 02 03:25:38 PM PDT 24
Peak memory 295204 kb
Host smart-02b0684a-0deb-40d1-81a1-4932a645fcd2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449303487 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.1449303487
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.2430434347
Short name T164
Test name
Test status
Simulation time 50390100 ps
CPU time 13.64 seconds
Started Jun 02 03:22:46 PM PDT 24
Finished Jun 02 03:23:01 PM PDT 24
Peak memory 257924 kb
Host smart-68ef63dc-473e-40fd-b7cd-2600981be760
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430434347 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.2430434347
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.104522549
Short name T98
Test name
Test status
Simulation time 40123607600 ps
CPU time 786.72 seconds
Started Jun 02 03:22:38 PM PDT 24
Finished Jun 02 03:35:46 PM PDT 24
Peak memory 264164 kb
Host smart-90b125b0-72b1-4533-ae65-8d9f9bdb5797
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104522549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 16.flash_ctrl_hw_rma_reset.104522549
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.550862419
Short name T942
Test name
Test status
Simulation time 1648491900 ps
CPU time 135.07 seconds
Started Jun 02 03:22:38 PM PDT 24
Finished Jun 02 03:24:54 PM PDT 24
Peak memory 289484 kb
Host smart-b43d67ad-a632-4944-ba2f-570c8ed02f5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550862419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flas
h_ctrl_intr_rd.550862419
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2021222141
Short name T1029
Test name
Test status
Simulation time 150313381000 ps
CPU time 333.69 seconds
Started Jun 02 03:22:39 PM PDT 24
Finished Jun 02 03:28:13 PM PDT 24
Peak memory 292884 kb
Host smart-382aa867-d4c7-47d0-ac82-ea1645f748ba
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021222141 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.2021222141
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.3366331072
Short name T86
Test name
Test status
Simulation time 3886471300 ps
CPU time 72.17 seconds
Started Jun 02 03:22:38 PM PDT 24
Finished Jun 02 03:23:51 PM PDT 24
Peak memory 259548 kb
Host smart-7fb84e15-9f2b-4406-929d-dc20fef4ed1b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366331072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3
366331072
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2358524615
Short name T673
Test name
Test status
Simulation time 45156100 ps
CPU time 13.75 seconds
Started Jun 02 03:22:46 PM PDT 24
Finished Jun 02 03:23:01 PM PDT 24
Peak memory 260060 kb
Host smart-26374224-0fa9-4204-acbd-fc3302e6a81a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358524615 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.2358524615
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.1569295633
Short name T470
Test name
Test status
Simulation time 150502100 ps
CPU time 128.82 seconds
Started Jun 02 03:22:37 PM PDT 24
Finished Jun 02 03:24:47 PM PDT 24
Peak memory 260836 kb
Host smart-bb9fc62c-a8cc-4455-a9a3-c80ce5b0fa3b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569295633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.1569295633
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.2672679603
Short name T434
Test name
Test status
Simulation time 65826500 ps
CPU time 69.77 seconds
Started Jun 02 03:22:34 PM PDT 24
Finished Jun 02 03:23:44 PM PDT 24
Peak memory 261396 kb
Host smart-620cd77d-e8eb-48e5-aef6-8b8c47d8c7e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2672679603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.2672679603
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.2701906203
Short name T636
Test name
Test status
Simulation time 21359100 ps
CPU time 13.31 seconds
Started Jun 02 03:22:41 PM PDT 24
Finished Jun 02 03:22:55 PM PDT 24
Peak memory 264832 kb
Host smart-385856cc-38b5-4a0e-a611-762b767962ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701906203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.2701906203
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.2527602518
Short name T591
Test name
Test status
Simulation time 743205200 ps
CPU time 636.04 seconds
Started Jun 02 03:22:33 PM PDT 24
Finished Jun 02 03:33:10 PM PDT 24
Peak memory 281212 kb
Host smart-53b2ed67-983d-443b-ac2b-5b0fd6c360a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527602518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2527602518
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.2848800986
Short name T1018
Test name
Test status
Simulation time 117015400 ps
CPU time 33.92 seconds
Started Jun 02 03:22:38 PM PDT 24
Finished Jun 02 03:23:13 PM PDT 24
Peak memory 273196 kb
Host smart-b34fe6d1-bd32-4867-a195-fcf408424e7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848800986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.2848800986
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.2504902501
Short name T189
Test name
Test status
Simulation time 454568900 ps
CPU time 106.83 seconds
Started Jun 02 03:22:38 PM PDT 24
Finished Jun 02 03:24:26 PM PDT 24
Peak memory 281172 kb
Host smart-6f05af05-13d4-4a76-8bc1-0e0496d69df0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504902501 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.2504902501
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.3644671543
Short name T533
Test name
Test status
Simulation time 3732313900 ps
CPU time 584.45 seconds
Started Jun 02 03:22:37 PM PDT 24
Finished Jun 02 03:32:22 PM PDT 24
Peak memory 312912 kb
Host smart-20cebe1a-3082-4b5d-86fe-057ef6cb8253
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644671543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_rw.3644671543
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.3220257534
Short name T770
Test name
Test status
Simulation time 31967700 ps
CPU time 31.27 seconds
Started Jun 02 03:22:38 PM PDT 24
Finished Jun 02 03:23:10 PM PDT 24
Peak memory 273120 kb
Host smart-1caa96a7-5863-49d2-b62f-737715fd0c9c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220257534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.3220257534
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.3349637759
Short name T646
Test name
Test status
Simulation time 26606900 ps
CPU time 27.73 seconds
Started Jun 02 03:22:38 PM PDT 24
Finished Jun 02 03:23:06 PM PDT 24
Peak memory 275716 kb
Host smart-c4c84554-da70-4652-9289-eb3f5f95fffa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349637759 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.3349637759
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.3481403979
Short name T808
Test name
Test status
Simulation time 6480697000 ps
CPU time 83.01 seconds
Started Jun 02 03:22:46 PM PDT 24
Finished Jun 02 03:24:09 PM PDT 24
Peak memory 262756 kb
Host smart-5b8bc473-1bd4-4370-bf05-e93e6e9903af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481403979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3481403979
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.1087978205
Short name T604
Test name
Test status
Simulation time 27794700 ps
CPU time 195.74 seconds
Started Jun 02 03:22:34 PM PDT 24
Finished Jun 02 03:25:50 PM PDT 24
Peak memory 279736 kb
Host smart-a69a489b-2e0c-40d1-8aca-a78b29a64b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087978205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.1087978205
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.2906801415
Short name T475
Test name
Test status
Simulation time 4309733000 ps
CPU time 191.79 seconds
Started Jun 02 03:22:38 PM PDT 24
Finished Jun 02 03:25:51 PM PDT 24
Peak memory 264724 kb
Host smart-56140425-d405-4289-9d9b-2488b27ac7a0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906801415 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.flash_ctrl_wo.2906801415
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.377690988
Short name T822
Test name
Test status
Simulation time 93188700 ps
CPU time 13.87 seconds
Started Jun 02 03:22:57 PM PDT 24
Finished Jun 02 03:23:11 PM PDT 24
Peak memory 258776 kb
Host smart-6f895ffe-54f1-4dd6-a6e8-cc35df81f12c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377690988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.377690988
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.2962848562
Short name T1025
Test name
Test status
Simulation time 14273100 ps
CPU time 15.62 seconds
Started Jun 02 03:22:49 PM PDT 24
Finished Jun 02 03:23:06 PM PDT 24
Peak memory 275796 kb
Host smart-e60569e4-cc82-4879-8f3d-44c68fc1e519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962848562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2962848562
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.3744544794
Short name T792
Test name
Test status
Simulation time 28725900 ps
CPU time 22.13 seconds
Started Jun 02 03:22:50 PM PDT 24
Finished Jun 02 03:23:13 PM PDT 24
Peak memory 273252 kb
Host smart-56c3946b-58c4-46ec-8765-5856dcf19139
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744544794 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.3744544794
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.1800064888
Short name T843
Test name
Test status
Simulation time 10041289600 ps
CPU time 50.54 seconds
Started Jun 02 03:22:55 PM PDT 24
Finished Jun 02 03:23:46 PM PDT 24
Peak memory 281444 kb
Host smart-528692f7-73d3-4298-8553-ce19a89ee59e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800064888 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.1800064888
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.3769874399
Short name T749
Test name
Test status
Simulation time 15842100 ps
CPU time 13.31 seconds
Started Jun 02 03:22:50 PM PDT 24
Finished Jun 02 03:23:05 PM PDT 24
Peak memory 257832 kb
Host smart-f43f4267-d83b-4bc0-98e0-e74571b214ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769874399 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.3769874399
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.2958148596
Short name T927
Test name
Test status
Simulation time 230207395900 ps
CPU time 889.88 seconds
Started Jun 02 03:22:44 PM PDT 24
Finished Jun 02 03:37:36 PM PDT 24
Peak memory 263016 kb
Host smart-13b964cc-8b1b-42ab-95ce-fdf5a8e9873e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958148596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.2958148596
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.982288337
Short name T414
Test name
Test status
Simulation time 32138785200 ps
CPU time 238.2 seconds
Started Jun 02 03:22:43 PM PDT 24
Finished Jun 02 03:26:41 PM PDT 24
Peak memory 262272 kb
Host smart-f272cb0b-76bc-4acf-be13-bcc23728e26b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982288337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_h
w_sec_otp.982288337
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.3397015050
Short name T353
Test name
Test status
Simulation time 3533341800 ps
CPU time 242.49 seconds
Started Jun 02 03:22:50 PM PDT 24
Finished Jun 02 03:26:53 PM PDT 24
Peak memory 283548 kb
Host smart-fbdc0fc4-36e7-4795-976e-3e58a6128b7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397015050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.3397015050
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.1352306024
Short name T328
Test name
Test status
Simulation time 177355991100 ps
CPU time 322.66 seconds
Started Jun 02 03:22:50 PM PDT 24
Finished Jun 02 03:28:14 PM PDT 24
Peak memory 292380 kb
Host smart-4ed7975c-5803-405b-b319-a2f8142823a8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352306024 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.1352306024
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.1355000456
Short name T676
Test name
Test status
Simulation time 11886190800 ps
CPU time 67.23 seconds
Started Jun 02 03:22:50 PM PDT 24
Finished Jun 02 03:23:58 PM PDT 24
Peak memory 260372 kb
Host smart-22e253ba-1f20-4095-bb2b-539f1f7ea73d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355000456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.1
355000456
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.690927739
Short name T757
Test name
Test status
Simulation time 15363000 ps
CPU time 13.1 seconds
Started Jun 02 03:22:50 PM PDT 24
Finished Jun 02 03:23:04 PM PDT 24
Peak memory 259272 kb
Host smart-0b987c74-a368-472e-8174-df962a1138b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690927739 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.690927739
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.2150854874
Short name T873
Test name
Test status
Simulation time 4644888000 ps
CPU time 132.45 seconds
Started Jun 02 03:22:45 PM PDT 24
Finished Jun 02 03:24:58 PM PDT 24
Peak memory 262780 kb
Host smart-5f9e1b86-7314-40b9-b8bc-011a8166e49e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150854874 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.2150854874
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.98411523
Short name T947
Test name
Test status
Simulation time 34597000 ps
CPU time 108.35 seconds
Started Jun 02 03:22:44 PM PDT 24
Finished Jun 02 03:24:33 PM PDT 24
Peak memory 263980 kb
Host smart-355ba76a-e744-4b08-a8d2-fc5dc0397a81
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98411523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp
_reset.98411523
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.2100209505
Short name T443
Test name
Test status
Simulation time 127235100 ps
CPU time 277.08 seconds
Started Jun 02 03:22:46 PM PDT 24
Finished Jun 02 03:27:24 PM PDT 24
Peak memory 262212 kb
Host smart-f929e54c-068e-4345-b45f-bfcb0ed7f920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100209505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.2100209505
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.1245200912
Short name T1056
Test name
Test status
Simulation time 2609812800 ps
CPU time 218.31 seconds
Started Jun 02 03:22:50 PM PDT 24
Finished Jun 02 03:26:29 PM PDT 24
Peak memory 264776 kb
Host smart-6aff35e5-398e-4dd1-89a8-f83c9abd5397
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245200912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.1245200912
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.16561705
Short name T907
Test name
Test status
Simulation time 1601386800 ps
CPU time 949.65 seconds
Started Jun 02 03:22:43 PM PDT 24
Finished Jun 02 03:38:33 PM PDT 24
Peak memory 286512 kb
Host smart-c19723e1-20c3-44a2-843a-c701eacfe9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16561705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.16561705
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.1218526374
Short name T512
Test name
Test status
Simulation time 92143100 ps
CPU time 34.5 seconds
Started Jun 02 03:22:51 PM PDT 24
Finished Jun 02 03:23:26 PM PDT 24
Peak memory 270312 kb
Host smart-5839b75a-cf49-44d9-b272-a139ed488eb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218526374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.1218526374
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.1489432973
Short name T824
Test name
Test status
Simulation time 1390616200 ps
CPU time 138.11 seconds
Started Jun 02 03:22:51 PM PDT 24
Finished Jun 02 03:25:10 PM PDT 24
Peak memory 280756 kb
Host smart-f3b5c5fa-4de3-49c5-ab54-f60327e1e408
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489432973 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.flash_ctrl_ro.1489432973
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.3732431701
Short name T6
Test name
Test status
Simulation time 8509159400 ps
CPU time 579.14 seconds
Started Jun 02 03:22:49 PM PDT 24
Finished Jun 02 03:32:29 PM PDT 24
Peak memory 313320 kb
Host smart-5ae5d356-b1fe-47ea-9059-7448b271dda1
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732431701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.flash_ctrl_rw.3732431701
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.2278540138
Short name T292
Test name
Test status
Simulation time 31144000 ps
CPU time 28.74 seconds
Started Jun 02 03:22:49 PM PDT 24
Finished Jun 02 03:23:19 PM PDT 24
Peak memory 266964 kb
Host smart-d32b2d55-cb78-4ab5-9649-67ff0020b729
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278540138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_rw_evict.2278540138
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.2215316046
Short name T37
Test name
Test status
Simulation time 60340000 ps
CPU time 31.46 seconds
Started Jun 02 03:22:49 PM PDT 24
Finished Jun 02 03:23:22 PM PDT 24
Peak memory 274456 kb
Host smart-64e9da1e-44e7-45dc-9142-b99d5ded5f19
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215316046 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.2215316046
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.4038926500
Short name T976
Test name
Test status
Simulation time 1616046100 ps
CPU time 66.55 seconds
Started Jun 02 03:22:50 PM PDT 24
Finished Jun 02 03:23:57 PM PDT 24
Peak memory 262256 kb
Host smart-9ff8bb1e-e46b-4d8c-ad5d-a60e25ab7e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038926500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.4038926500
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.1391440171
Short name T878
Test name
Test status
Simulation time 56452700 ps
CPU time 76.04 seconds
Started Jun 02 03:22:43 PM PDT 24
Finished Jun 02 03:23:59 PM PDT 24
Peak memory 274984 kb
Host smart-7a7943b5-4750-4f17-ba08-559632a78acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391440171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.1391440171
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.288981140
Short name T61
Test name
Test status
Simulation time 22809439700 ps
CPU time 208.87 seconds
Started Jun 02 03:22:52 PM PDT 24
Finished Jun 02 03:26:21 PM PDT 24
Peak memory 258344 kb
Host smart-1a137a6f-5069-46ef-a061-1e0307077741
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288981140 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.flash_ctrl_wo.288981140
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.3047932751
Short name T764
Test name
Test status
Simulation time 71766200 ps
CPU time 13.58 seconds
Started Jun 02 03:23:07 PM PDT 24
Finished Jun 02 03:23:21 PM PDT 24
Peak memory 264136 kb
Host smart-74bc69a9-76e9-43c7-9662-c66d7e530bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047932751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
3047932751
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.4274041276
Short name T951
Test name
Test status
Simulation time 14775000 ps
CPU time 13.43 seconds
Started Jun 02 03:23:05 PM PDT 24
Finished Jun 02 03:23:20 PM PDT 24
Peak memory 275512 kb
Host smart-9e9817a3-b999-4052-8683-df149c06b10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274041276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.4274041276
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.1169121521
Short name T860
Test name
Test status
Simulation time 14860900 ps
CPU time 22.2 seconds
Started Jun 02 03:23:06 PM PDT 24
Finished Jun 02 03:23:29 PM PDT 24
Peak memory 264904 kb
Host smart-cd68d1ae-df82-4a82-9500-055a83cda9dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169121521 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.1169121521
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.3077932730
Short name T128
Test name
Test status
Simulation time 10013907400 ps
CPU time 281.66 seconds
Started Jun 02 03:23:09 PM PDT 24
Finished Jun 02 03:27:52 PM PDT 24
Peak memory 322144 kb
Host smart-95463833-f6ba-44c7-a53d-404744f84e7a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077932730 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.3077932730
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.1470195719
Short name T1
Test name
Test status
Simulation time 79360100 ps
CPU time 13.4 seconds
Started Jun 02 03:23:05 PM PDT 24
Finished Jun 02 03:23:19 PM PDT 24
Peak memory 258064 kb
Host smart-4eabecbd-111f-4bb3-bc24-5d40dc59c832
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470195719 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.1470195719
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.3759411724
Short name T928
Test name
Test status
Simulation time 4187150000 ps
CPU time 86.71 seconds
Started Jun 02 03:22:57 PM PDT 24
Finished Jun 02 03:24:24 PM PDT 24
Peak memory 262272 kb
Host smart-162615aa-f36b-4361-9785-c154d68dcaa9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759411724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.3759411724
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3660411953
Short name T542
Test name
Test status
Simulation time 33397867100 ps
CPU time 169.53 seconds
Started Jun 02 03:23:02 PM PDT 24
Finished Jun 02 03:25:52 PM PDT 24
Peak memory 291648 kb
Host smart-4ae286d2-9088-4591-b57d-bc8b00a6a848
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660411953 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.3660411953
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.3878683068
Short name T651
Test name
Test status
Simulation time 2142699300 ps
CPU time 67.19 seconds
Started Jun 02 03:23:03 PM PDT 24
Finished Jun 02 03:24:10 PM PDT 24
Peak memory 260460 kb
Host smart-8ddf986f-6219-4cef-b140-89b582da3e3b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878683068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.3
878683068
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.3466133156
Short name T565
Test name
Test status
Simulation time 25678000 ps
CPU time 13.55 seconds
Started Jun 02 03:23:03 PM PDT 24
Finished Jun 02 03:23:17 PM PDT 24
Peak memory 259576 kb
Host smart-ab7d4bef-88bd-4802-afd4-e961340f0c0b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466133156 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.3466133156
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.268540649
Short name T96
Test name
Test status
Simulation time 20805854100 ps
CPU time 765.54 seconds
Started Jun 02 03:23:02 PM PDT 24
Finished Jun 02 03:35:48 PM PDT 24
Peak memory 273768 kb
Host smart-f082176b-b856-4c13-a3c3-51df46010294
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268540649 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_mp_regions.268540649
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.1904959465
Short name T1058
Test name
Test status
Simulation time 388003600 ps
CPU time 130.67 seconds
Started Jun 02 03:23:02 PM PDT 24
Finished Jun 02 03:25:14 PM PDT 24
Peak memory 259880 kb
Host smart-ef4c1d6a-50a9-4310-bae8-00f693469f18
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904959465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.1904959465
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.2384770547
Short name T526
Test name
Test status
Simulation time 56331400 ps
CPU time 111.13 seconds
Started Jun 02 03:22:58 PM PDT 24
Finished Jun 02 03:24:49 PM PDT 24
Peak memory 262196 kb
Host smart-39717552-85fd-4eb1-869f-d0dc0cc1593b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384770547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.2384770547
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.1521636015
Short name T633
Test name
Test status
Simulation time 30436294400 ps
CPU time 255.21 seconds
Started Jun 02 03:23:01 PM PDT 24
Finished Jun 02 03:27:17 PM PDT 24
Peak memory 264756 kb
Host smart-8c64b910-5a86-465c-a02a-61c0e9e2ddfc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521636015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.1521636015
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.1910913301
Short name T914
Test name
Test status
Simulation time 298156300 ps
CPU time 793.2 seconds
Started Jun 02 03:22:54 PM PDT 24
Finished Jun 02 03:36:09 PM PDT 24
Peak memory 282276 kb
Host smart-73e42c84-1f10-44cd-be73-c3aa121d6490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910913301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1910913301
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.1042327744
Short name T1000
Test name
Test status
Simulation time 419616700 ps
CPU time 34.83 seconds
Started Jun 02 03:23:04 PM PDT 24
Finished Jun 02 03:23:40 PM PDT 24
Peak memory 273164 kb
Host smart-41e4defc-2a0f-4310-ba9a-8343c0a97c4e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042327744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.1042327744
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.2005967057
Short name T716
Test name
Test status
Simulation time 7094575400 ps
CPU time 107.85 seconds
Started Jun 02 03:23:04 PM PDT 24
Finished Jun 02 03:24:53 PM PDT 24
Peak memory 296676 kb
Host smart-f643f4e8-c675-47b9-bd55-e09ea6b11c19
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005967057 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.2005967057
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.337941535
Short name T899
Test name
Test status
Simulation time 3295634600 ps
CPU time 584.63 seconds
Started Jun 02 03:23:03 PM PDT 24
Finished Jun 02 03:32:48 PM PDT 24
Peak memory 309116 kb
Host smart-7ebd5621-2e58-46a5-b968-f4594be12f39
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337941535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.flash_ctrl_rw.337941535
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.3830341510
Short name T929
Test name
Test status
Simulation time 49550000 ps
CPU time 31.21 seconds
Started Jun 02 03:23:02 PM PDT 24
Finished Jun 02 03:23:34 PM PDT 24
Peak memory 274488 kb
Host smart-8cf6a4ff-f6a6-498f-8dcd-0750e6e540ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830341510 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.3830341510
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.745570789
Short name T402
Test name
Test status
Simulation time 4389676900 ps
CPU time 70.56 seconds
Started Jun 02 03:23:02 PM PDT 24
Finished Jun 02 03:24:13 PM PDT 24
Peak memory 264204 kb
Host smart-53e0e0fd-9b0a-4800-a367-e944ea7ea922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745570789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.745570789
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.2130349555
Short name T652
Test name
Test status
Simulation time 22446900 ps
CPU time 77.19 seconds
Started Jun 02 03:22:55 PM PDT 24
Finished Jun 02 03:24:13 PM PDT 24
Peak memory 276260 kb
Host smart-e0139193-54f1-4cc9-a3f2-ef65869dad24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130349555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2130349555
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.1167663327
Short name T761
Test name
Test status
Simulation time 1950135200 ps
CPU time 159.71 seconds
Started Jun 02 03:23:05 PM PDT 24
Finished Jun 02 03:25:45 PM PDT 24
Peak memory 258572 kb
Host smart-23ac23ab-0f01-4b85-a68d-3f2935102c67
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167663327 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.1167663327
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.3231319757
Short name T731
Test name
Test status
Simulation time 49027700 ps
CPU time 13.82 seconds
Started Jun 02 03:23:23 PM PDT 24
Finished Jun 02 03:23:37 PM PDT 24
Peak memory 264768 kb
Host smart-2a9447d0-dbb2-4d9c-b19e-413c35cd096d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231319757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
3231319757
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.3591232210
Short name T471
Test name
Test status
Simulation time 22914300 ps
CPU time 16.01 seconds
Started Jun 02 03:23:16 PM PDT 24
Finished Jun 02 03:23:33 PM PDT 24
Peak memory 275460 kb
Host smart-54492721-9302-4996-97c3-9e5080841e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591232210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.3591232210
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.3394117264
Short name T630
Test name
Test status
Simulation time 12628400 ps
CPU time 22.78 seconds
Started Jun 02 03:23:14 PM PDT 24
Finished Jun 02 03:23:37 PM PDT 24
Peak memory 273084 kb
Host smart-c92b3e88-cec3-4ff3-a005-04d7a8a9b509
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394117264 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.3394117264
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.714852611
Short name T615
Test name
Test status
Simulation time 10041817600 ps
CPU time 50.12 seconds
Started Jun 02 03:23:21 PM PDT 24
Finished Jun 02 03:24:12 PM PDT 24
Peak memory 281584 kb
Host smart-076cd7cd-a274-4368-9b31-e610828300d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714852611 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.714852611
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.1188764616
Short name T506
Test name
Test status
Simulation time 47496700 ps
CPU time 13.47 seconds
Started Jun 02 03:23:15 PM PDT 24
Finished Jun 02 03:23:29 PM PDT 24
Peak memory 265056 kb
Host smart-e195929f-9f49-4ab4-97a3-b53bef407761
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188764616 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.1188764616
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.717507904
Short name T616
Test name
Test status
Simulation time 3078512500 ps
CPU time 113.31 seconds
Started Jun 02 03:23:11 PM PDT 24
Finished Jun 02 03:25:05 PM PDT 24
Peak memory 261696 kb
Host smart-e3ff4acf-de4a-4fc7-a603-74da7bc37562
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717507904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_h
w_sec_otp.717507904
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.324152661
Short name T1002
Test name
Test status
Simulation time 3031735900 ps
CPU time 132.89 seconds
Started Jun 02 03:23:15 PM PDT 24
Finished Jun 02 03:25:28 PM PDT 24
Peak memory 289428 kb
Host smart-4a9bec8a-a1df-46b4-9e4b-44db37d5e7ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324152661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flas
h_ctrl_intr_rd.324152661
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.3304258069
Short name T361
Test name
Test status
Simulation time 8657570900 ps
CPU time 202.76 seconds
Started Jun 02 03:23:14 PM PDT 24
Finished Jun 02 03:26:37 PM PDT 24
Peak memory 293008 kb
Host smart-3332f43b-9cde-4464-86ea-054434878595
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304258069 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.3304258069
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.1708398294
Short name T428
Test name
Test status
Simulation time 5320640000 ps
CPU time 71.16 seconds
Started Jun 02 03:23:09 PM PDT 24
Finished Jun 02 03:24:21 PM PDT 24
Peak memory 260360 kb
Host smart-1ab3ec63-5ad7-4bf6-953f-40d0a500e322
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708398294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.1
708398294
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.4160054409
Short name T1054
Test name
Test status
Simulation time 89841700 ps
CPU time 13.62 seconds
Started Jun 02 03:23:15 PM PDT 24
Finished Jun 02 03:23:30 PM PDT 24
Peak memory 259320 kb
Host smart-fd9e8722-02b1-417b-b127-51c288efda7a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160054409 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.4160054409
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.3939007308
Short name T72
Test name
Test status
Simulation time 34970301000 ps
CPU time 712.87 seconds
Started Jun 02 03:23:07 PM PDT 24
Finished Jun 02 03:35:01 PM PDT 24
Peak memory 274312 kb
Host smart-1053c42d-795c-4459-9b63-f67ac285a558
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939007308 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.3939007308
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.3117860592
Short name T504
Test name
Test status
Simulation time 152703800 ps
CPU time 129.93 seconds
Started Jun 02 03:23:10 PM PDT 24
Finished Jun 02 03:25:21 PM PDT 24
Peak memory 259616 kb
Host smart-ce3e0a3f-d6c3-4bbe-ae7b-f7d591c3a31e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117860592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.3117860592
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.470996490
Short name T890
Test name
Test status
Simulation time 1498772800 ps
CPU time 421.35 seconds
Started Jun 02 03:23:08 PM PDT 24
Finished Jun 02 03:30:10 PM PDT 24
Peak memory 264888 kb
Host smart-6a391a95-a6bc-4694-8854-1fbb1cd3f125
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=470996490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.470996490
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.2147957785
Short name T425
Test name
Test status
Simulation time 75973100 ps
CPU time 13.67 seconds
Started Jun 02 03:23:17 PM PDT 24
Finished Jun 02 03:23:31 PM PDT 24
Peak memory 258284 kb
Host smart-e75ee5ef-e159-41eb-a588-4c8f334276de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147957785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.2147957785
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.1244631830
Short name T705
Test name
Test status
Simulation time 599023700 ps
CPU time 801.57 seconds
Started Jun 02 03:23:07 PM PDT 24
Finished Jun 02 03:36:30 PM PDT 24
Peak memory 282068 kb
Host smart-fa855737-fa8c-426b-8b83-553f32484c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244631830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1244631830
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.573501199
Short name T290
Test name
Test status
Simulation time 174804000 ps
CPU time 36.41 seconds
Started Jun 02 03:23:16 PM PDT 24
Finished Jun 02 03:23:53 PM PDT 24
Peak memory 269332 kb
Host smart-0c6acb82-d1a7-42ad-ad04-c3b6f88ff88b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573501199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_re_evict.573501199
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.747117998
Short name T5
Test name
Test status
Simulation time 562169800 ps
CPU time 119.08 seconds
Started Jun 02 03:23:15 PM PDT 24
Finished Jun 02 03:25:15 PM PDT 24
Peak memory 296676 kb
Host smart-ac04390b-0756-4e35-8d8b-9ded23974212
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747117998 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.flash_ctrl_ro.747117998
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.1186543680
Short name T477
Test name
Test status
Simulation time 4333537800 ps
CPU time 614.84 seconds
Started Jun 02 03:23:15 PM PDT 24
Finished Jun 02 03:33:31 PM PDT 24
Peak memory 313656 kb
Host smart-cc9288b6-c481-4377-900f-564e7a4298ef
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186543680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.1186543680
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.1699334914
Short name T313
Test name
Test status
Simulation time 46583400 ps
CPU time 30.77 seconds
Started Jun 02 03:23:15 PM PDT 24
Finished Jun 02 03:23:46 PM PDT 24
Peak memory 273112 kb
Host smart-f14d2e11-44f3-435a-b9ad-2ff36339bc53
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699334914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.1699334914
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.219494359
Short name T1084
Test name
Test status
Simulation time 27442200 ps
CPU time 30.86 seconds
Started Jun 02 03:23:15 PM PDT 24
Finished Jun 02 03:23:46 PM PDT 24
Peak memory 274292 kb
Host smart-96f6d709-275c-41b1-901c-71abb0d93a08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219494359 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.219494359
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.1524043376
Short name T840
Test name
Test status
Simulation time 41374200 ps
CPU time 73.89 seconds
Started Jun 02 03:23:07 PM PDT 24
Finished Jun 02 03:24:22 PM PDT 24
Peak memory 274796 kb
Host smart-64892c4e-99ea-4006-a9d6-1780d64b407f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524043376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1524043376
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.3089719224
Short name T751
Test name
Test status
Simulation time 4179990900 ps
CPU time 170.83 seconds
Started Jun 02 03:23:07 PM PDT 24
Finished Jun 02 03:26:00 PM PDT 24
Peak memory 264788 kb
Host smart-aec69722-45c4-4b6c-abf8-2b0a73d9dfdd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089719224 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.flash_ctrl_wo.3089719224
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.1885290785
Short name T23
Test name
Test status
Simulation time 34890000 ps
CPU time 13.93 seconds
Started Jun 02 03:19:14 PM PDT 24
Finished Jun 02 03:19:28 PM PDT 24
Peak memory 260984 kb
Host smart-7bb6271d-4989-467b-ba44-699760bfeaa2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885290785 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.1885290785
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.635303269
Short name T507
Test name
Test status
Simulation time 70127100 ps
CPU time 13.62 seconds
Started Jun 02 03:19:13 PM PDT 24
Finished Jun 02 03:19:27 PM PDT 24
Peak memory 264820 kb
Host smart-9ee2052a-eaff-4729-83cf-b21fac80b51e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635303269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.635303269
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.1980801789
Short name T881
Test name
Test status
Simulation time 48041800 ps
CPU time 15.37 seconds
Started Jun 02 03:19:15 PM PDT 24
Finished Jun 02 03:19:31 PM PDT 24
Peak memory 275876 kb
Host smart-5c725ef9-085a-4b1a-b776-d2fea525e9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980801789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.1980801789
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.649328768
Short name T254
Test name
Test status
Simulation time 321922100 ps
CPU time 105.6 seconds
Started Jun 02 03:19:17 PM PDT 24
Finished Jun 02 03:21:03 PM PDT 24
Peak memory 280372 kb
Host smart-9ee44640-f55b-4f56-9bfd-4dbf331b113b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649328768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_derr_detect.649328768
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.1373042219
Short name T92
Test name
Test status
Simulation time 2744755000 ps
CPU time 2363.77 seconds
Started Jun 02 03:19:06 PM PDT 24
Finished Jun 02 03:58:30 PM PDT 24
Peak memory 263864 kb
Host smart-b14f4392-88af-4767-8a8a-e08fbc48c1e2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373042219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.1373042219
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.582195765
Short name T299
Test name
Test status
Simulation time 387226600 ps
CPU time 955.72 seconds
Started Jun 02 03:19:06 PM PDT 24
Finished Jun 02 03:35:02 PM PDT 24
Peak memory 272968 kb
Host smart-09579d26-6690-4ace-82cf-0970f9493c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582195765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.582195765
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.2721225695
Short name T1044
Test name
Test status
Simulation time 178342300 ps
CPU time 18.8 seconds
Started Jun 02 03:19:03 PM PDT 24
Finished Jun 02 03:19:23 PM PDT 24
Peak memory 261800 kb
Host smart-97ff9764-07ba-418d-932f-cc35e1f72e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721225695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.2721225695
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.1882502685
Short name T63
Test name
Test status
Simulation time 179877595000 ps
CPU time 2617.68 seconds
Started Jun 02 03:19:03 PM PDT 24
Finished Jun 02 04:02:43 PM PDT 24
Peak memory 262836 kb
Host smart-bfd3b907-5973-4f71-90e4-688fe1030930
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882502685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.1882502685
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3311931790
Short name T988
Test name
Test status
Simulation time 1175729541000 ps
CPU time 2611.9 seconds
Started Jun 02 03:19:06 PM PDT 24
Finished Jun 02 04:02:39 PM PDT 24
Peak memory 264928 kb
Host smart-71c7f9b7-37f8-484e-9dd7-32892af586e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311931790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.3311931790
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.4141792851
Short name T288
Test name
Test status
Simulation time 35698600 ps
CPU time 60.11 seconds
Started Jun 02 03:19:02 PM PDT 24
Finished Jun 02 03:20:03 PM PDT 24
Peak memory 262108 kb
Host smart-3b787cbd-1242-4ec5-af35-95a568b3f04e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4141792851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.4141792851
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.2944465559
Short name T846
Test name
Test status
Simulation time 26786300 ps
CPU time 13.71 seconds
Started Jun 02 03:19:20 PM PDT 24
Finished Jun 02 03:19:35 PM PDT 24
Peak memory 257816 kb
Host smart-ce8f7a56-6860-4d4b-a851-087d0db34d63
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944465559 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.2944465559
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.4086239733
Short name T834
Test name
Test status
Simulation time 169525016900 ps
CPU time 2117.37 seconds
Started Jun 02 03:19:03 PM PDT 24
Finished Jun 02 03:54:21 PM PDT 24
Peak memory 262496 kb
Host smart-be620030-be99-4661-8a17-926725e866d8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086239733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.4086239733
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.603649416
Short name T603
Test name
Test status
Simulation time 80138843700 ps
CPU time 859.81 seconds
Started Jun 02 03:19:01 PM PDT 24
Finished Jun 02 03:33:22 PM PDT 24
Peak memory 264324 kb
Host smart-83e7e69c-2d08-4720-bab7-f204afaa4f2c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603649416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_hw_rma_reset.603649416
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.3568165651
Short name T815
Test name
Test status
Simulation time 19447885400 ps
CPU time 150.17 seconds
Started Jun 02 03:19:02 PM PDT 24
Finished Jun 02 03:21:33 PM PDT 24
Peak memory 261784 kb
Host smart-e4f5a525-49cb-4160-a7c2-d9278b9af79d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568165651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.3568165651
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.12675797
Short name T559
Test name
Test status
Simulation time 112969076700 ps
CPU time 212.84 seconds
Started Jun 02 03:19:16 PM PDT 24
Finished Jun 02 03:22:50 PM PDT 24
Peak memory 291636 kb
Host smart-18d1f01e-51ff-4a51-98e9-b235fea98c38
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12675797 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.12675797
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.1071356231
Short name T882
Test name
Test status
Simulation time 2577883500 ps
CPU time 79.54 seconds
Started Jun 02 03:19:08 PM PDT 24
Finished Jun 02 03:20:28 PM PDT 24
Peak memory 264860 kb
Host smart-3b572adf-ba12-4f62-a939-26d3ba2fcca8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071356231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.1071356231
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.2837340824
Short name T975
Test name
Test status
Simulation time 26260634300 ps
CPU time 183.39 seconds
Started Jun 02 03:19:08 PM PDT 24
Finished Jun 02 03:22:12 PM PDT 24
Peak memory 264780 kb
Host smart-f8e8d943-3fd7-45b8-af09-f70a06cc55a0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283
7340824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.2837340824
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.3998370689
Short name T817
Test name
Test status
Simulation time 2118548600 ps
CPU time 80.75 seconds
Started Jun 02 03:19:02 PM PDT 24
Finished Jun 02 03:20:24 PM PDT 24
Peak memory 260368 kb
Host smart-33101734-e74c-4840-93ba-ffe271908600
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998370689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3998370689
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.2889530679
Short name T296
Test name
Test status
Simulation time 17241400 ps
CPU time 13.25 seconds
Started Jun 02 03:19:17 PM PDT 24
Finished Jun 02 03:19:31 PM PDT 24
Peak memory 259284 kb
Host smart-6c57c4dd-d070-4377-8b5a-10db6e09267e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889530679 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.2889530679
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.708964356
Short name T90
Test name
Test status
Simulation time 65352737300 ps
CPU time 366.56 seconds
Started Jun 02 03:19:03 PM PDT 24
Finished Jun 02 03:25:10 PM PDT 24
Peak memory 274312 kb
Host smart-12816476-8a25-4a41-978d-1f8b6212cdef
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708964356 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_mp_regions.708964356
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.2573535631
Short name T557
Test name
Test status
Simulation time 157826900 ps
CPU time 132.21 seconds
Started Jun 02 03:19:02 PM PDT 24
Finished Jun 02 03:21:15 PM PDT 24
Peak memory 259660 kb
Host smart-2030f088-fa95-4bae-8103-9e148b3ad9b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573535631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.2573535631
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.677699953
Short name T39
Test name
Test status
Simulation time 1025600400 ps
CPU time 164.63 seconds
Started Jun 02 03:19:10 PM PDT 24
Finished Jun 02 03:21:55 PM PDT 24
Peak memory 281324 kb
Host smart-e8ebd6ee-9c69-4a18-aba8-111e01c7ac59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677699953 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.677699953
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.1254299632
Short name T221
Test name
Test status
Simulation time 1324683200 ps
CPU time 23.65 seconds
Started Jun 02 03:19:15 PM PDT 24
Finished Jun 02 03:19:39 PM PDT 24
Peak memory 261188 kb
Host smart-1c808d7a-15ef-4fc9-8ac0-2ab2b88e9d85
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1254299632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.1254299632
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.1177902211
Short name T73
Test name
Test status
Simulation time 767796500 ps
CPU time 296.13 seconds
Started Jun 02 03:19:06 PM PDT 24
Finished Jun 02 03:24:02 PM PDT 24
Peak memory 262120 kb
Host smart-c45f929a-79d2-4293-9a34-b329ea4b255e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1177902211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.1177902211
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.3035898015
Short name T186
Test name
Test status
Simulation time 57787900 ps
CPU time 14.39 seconds
Started Jun 02 03:19:21 PM PDT 24
Finished Jun 02 03:19:36 PM PDT 24
Peak memory 261688 kb
Host smart-c821e0e5-ea18-4fb6-8361-b2393a6bc787
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035898015 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.3035898015
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.3846286097
Short name T545
Test name
Test status
Simulation time 2488639300 ps
CPU time 217.56 seconds
Started Jun 02 03:19:09 PM PDT 24
Finished Jun 02 03:22:47 PM PDT 24
Peak memory 259360 kb
Host smart-937c7132-1497-403b-b1a3-45027759d481
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846286097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.3846286097
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.3329472275
Short name T835
Test name
Test status
Simulation time 132615300 ps
CPU time 757.83 seconds
Started Jun 02 03:19:07 PM PDT 24
Finished Jun 02 03:31:46 PM PDT 24
Peak memory 285300 kb
Host smart-1f752e74-c6a8-484a-b7d3-0131913383a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329472275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.3329472275
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.159141540
Short name T707
Test name
Test status
Simulation time 1388034700 ps
CPU time 199.31 seconds
Started Jun 02 03:19:05 PM PDT 24
Finished Jun 02 03:22:25 PM PDT 24
Peak memory 264944 kb
Host smart-03fc2b19-ee29-4425-ad80-70c8c0a82e06
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=159141540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.159141540
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.240933770
Short name T803
Test name
Test status
Simulation time 65059600 ps
CPU time 31.97 seconds
Started Jun 02 03:19:21 PM PDT 24
Finished Jun 02 03:19:54 PM PDT 24
Peak memory 273272 kb
Host smart-65ee4781-87f9-419d-9b72-c4c61cf98c8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240933770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rd_intg.240933770
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.3141965026
Short name T903
Test name
Test status
Simulation time 215551200 ps
CPU time 36.42 seconds
Started Jun 02 03:19:09 PM PDT 24
Finished Jun 02 03:19:46 PM PDT 24
Peak memory 269676 kb
Host smart-ff75e50b-acad-4ced-ad1b-f25658a9b131
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141965026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.3141965026
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.3932366707
Short name T108
Test name
Test status
Simulation time 101037100 ps
CPU time 20.84 seconds
Started Jun 02 03:19:17 PM PDT 24
Finished Jun 02 03:19:38 PM PDT 24
Peak memory 264660 kb
Host smart-4d7e6ad8-6570-412d-b5e2-1daa9edda909
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932366707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.3932366707
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.2881175900
Short name T131
Test name
Test status
Simulation time 56815349100 ps
CPU time 983.96 seconds
Started Jun 02 03:19:14 PM PDT 24
Finished Jun 02 03:35:38 PM PDT 24
Peak memory 295464 kb
Host smart-03a6a3b4-7440-45ec-ab16-dbe127d7a330
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881175900 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.2881175900
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.1656820621
Short name T319
Test name
Test status
Simulation time 720015300 ps
CPU time 103.79 seconds
Started Jun 02 03:19:08 PM PDT 24
Finished Jun 02 03:20:53 PM PDT 24
Peak memory 288896 kb
Host smart-44067269-46b1-4187-8ce7-b88330fb0392
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656820621 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_ro.1656820621
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.1340862091
Short name T188
Test name
Test status
Simulation time 1281278100 ps
CPU time 130.45 seconds
Started Jun 02 03:19:08 PM PDT 24
Finished Jun 02 03:21:19 PM PDT 24
Peak memory 281184 kb
Host smart-0463dde5-6296-4cad-a766-2ad65cc25519
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1340862091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.1340862091
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.1557265538
Short name T836
Test name
Test status
Simulation time 1286452200 ps
CPU time 126.08 seconds
Started Jun 02 03:19:12 PM PDT 24
Finished Jun 02 03:21:19 PM PDT 24
Peak memory 281272 kb
Host smart-efb97b59-1223-44bf-9323-e58a7d964615
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557265538 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.1557265538
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.2052334444
Short name T179
Test name
Test status
Simulation time 3730381100 ps
CPU time 663.96 seconds
Started Jun 02 03:19:09 PM PDT 24
Finished Jun 02 03:30:14 PM PDT 24
Peak memory 314080 kb
Host smart-069dc9c6-a94d-4415-ae4a-7dbdb14ccf7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052334444 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_rw_derr.2052334444
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.365712501
Short name T556
Test name
Test status
Simulation time 110352400 ps
CPU time 30.92 seconds
Started Jun 02 03:19:08 PM PDT 24
Finished Jun 02 03:19:40 PM PDT 24
Peak memory 274404 kb
Host smart-736b2c84-a8bb-4aec-a153-09a4e4631f06
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365712501 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.365712501
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.2646969698
Short name T547
Test name
Test status
Simulation time 17211198700 ps
CPU time 603.62 seconds
Started Jun 02 03:19:08 PM PDT 24
Finished Jun 02 03:29:12 PM PDT 24
Peak memory 311652 kb
Host smart-0ca0d531-1ede-4e7f-bb85-a44e1783f324
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646969698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s
err.2646969698
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.2877534312
Short name T16
Test name
Test status
Simulation time 1319096500 ps
CPU time 4903.31 seconds
Started Jun 02 03:19:19 PM PDT 24
Finished Jun 02 04:41:03 PM PDT 24
Peak memory 294552 kb
Host smart-3dffb6e5-2c9e-4b17-b349-d95834d358c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877534312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.2877534312
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.1811670154
Short name T1017
Test name
Test status
Simulation time 1961700500 ps
CPU time 60.98 seconds
Started Jun 02 03:19:22 PM PDT 24
Finished Jun 02 03:20:23 PM PDT 24
Peak memory 264276 kb
Host smart-a4694f99-8899-458a-9c73-5b85c517ba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811670154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.1811670154
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.591066251
Short name T516
Test name
Test status
Simulation time 1610469300 ps
CPU time 89.88 seconds
Started Jun 02 03:19:08 PM PDT 24
Finished Jun 02 03:20:38 PM PDT 24
Peak memory 264876 kb
Host smart-e202e81b-c472-4c24-8a4c-2666701c4916
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591066251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_serr_address.591066251
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.4223036067
Short name T429
Test name
Test status
Simulation time 823466900 ps
CPU time 87.63 seconds
Started Jun 02 03:19:09 PM PDT 24
Finished Jun 02 03:20:37 PM PDT 24
Peak memory 273264 kb
Host smart-2e634644-6672-4e04-8020-f2983837d595
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223036067 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.4223036067
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.4070835381
Short name T234
Test name
Test status
Simulation time 368168900 ps
CPU time 97.14 seconds
Started Jun 02 03:19:03 PM PDT 24
Finished Jun 02 03:20:41 PM PDT 24
Peak memory 275276 kb
Host smart-30946f2b-bd69-4e28-8f3c-1526dc406dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070835381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.4070835381
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.331766932
Short name T54
Test name
Test status
Simulation time 15593000 ps
CPU time 24.01 seconds
Started Jun 02 03:19:03 PM PDT 24
Finished Jun 02 03:19:28 PM PDT 24
Peak memory 258812 kb
Host smart-22e83a18-fab7-48b5-8127-6ef1be0c50b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331766932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.331766932
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.2998268584
Short name T755
Test name
Test status
Simulation time 1610106800 ps
CPU time 1500.16 seconds
Started Jun 02 03:19:14 PM PDT 24
Finished Jun 02 03:44:15 PM PDT 24
Peak memory 296712 kb
Host smart-d1e47ada-088c-433a-abd0-93f13543b9df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998268584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.2998268584
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.1697726042
Short name T315
Test name
Test status
Simulation time 41436700 ps
CPU time 24.57 seconds
Started Jun 02 03:19:02 PM PDT 24
Finished Jun 02 03:19:28 PM PDT 24
Peak memory 261224 kb
Host smart-e523dcab-c898-4f82-8ba0-8debb4325a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697726042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.1697726042
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.1338103422
Short name T660
Test name
Test status
Simulation time 2479686700 ps
CPU time 178.55 seconds
Started Jun 02 03:19:09 PM PDT 24
Finished Jun 02 03:22:08 PM PDT 24
Peak memory 258956 kb
Host smart-749cbf68-f223-4626-926b-722d8d340c55
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338103422 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_wo.1338103422
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.1929086260
Short name T259
Test name
Test status
Simulation time 74047300 ps
CPU time 15.13 seconds
Started Jun 02 03:19:14 PM PDT 24
Finished Jun 02 03:19:30 PM PDT 24
Peak memory 259644 kb
Host smart-ba22bf21-3b2b-4f81-8431-ef4dfd22162b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929086260 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.1929086260
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.3304694642
Short name T436
Test name
Test status
Simulation time 53765700 ps
CPU time 13.7 seconds
Started Jun 02 03:23:26 PM PDT 24
Finished Jun 02 03:23:41 PM PDT 24
Peak memory 264792 kb
Host smart-15672180-f511-4856-bfa8-2f630fdcccba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304694642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
3304694642
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.3792953788
Short name T618
Test name
Test status
Simulation time 17192000 ps
CPU time 16.19 seconds
Started Jun 02 03:23:26 PM PDT 24
Finished Jun 02 03:23:43 PM PDT 24
Peak memory 275464 kb
Host smart-15ee8485-da8a-416d-b939-882f246f2ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792953788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.3792953788
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2580048695
Short name T1064
Test name
Test status
Simulation time 1749886700 ps
CPU time 150 seconds
Started Jun 02 03:23:22 PM PDT 24
Finished Jun 02 03:25:52 PM PDT 24
Peak memory 262320 kb
Host smart-86f3062b-b4ec-4785-ad63-7c989586c8d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580048695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.2580048695
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.3729011665
Short name T289
Test name
Test status
Simulation time 5045085200 ps
CPU time 195.05 seconds
Started Jun 02 03:23:21 PM PDT 24
Finished Jun 02 03:26:37 PM PDT 24
Peak memory 283544 kb
Host smart-dc4c2fae-28d6-4f93-924c-f307084cbd54
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729011665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.3729011665
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.4224465028
Short name T580
Test name
Test status
Simulation time 54430324000 ps
CPU time 327.88 seconds
Started Jun 02 03:23:21 PM PDT 24
Finished Jun 02 03:28:50 PM PDT 24
Peak memory 292840 kb
Host smart-b51e5a96-e328-401a-91eb-5350bb5eb912
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224465028 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.4224465028
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.1627137895
Short name T1079
Test name
Test status
Simulation time 83891400 ps
CPU time 133.28 seconds
Started Jun 02 03:23:20 PM PDT 24
Finished Jun 02 03:25:34 PM PDT 24
Peak memory 259552 kb
Host smart-0104b6c7-d357-4039-a5e6-14fbc4ffa5e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627137895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.1627137895
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.2180649802
Short name T690
Test name
Test status
Simulation time 2097684100 ps
CPU time 170.55 seconds
Started Jun 02 03:23:20 PM PDT 24
Finished Jun 02 03:26:11 PM PDT 24
Peak memory 264732 kb
Host smart-32b3d726-edbe-4a21-967c-3c6aa5a3c115
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180649802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.2180649802
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.1188668893
Short name T418
Test name
Test status
Simulation time 74034800 ps
CPU time 76.82 seconds
Started Jun 02 03:23:23 PM PDT 24
Finished Jun 02 03:24:40 PM PDT 24
Peak memory 274676 kb
Host smart-60c77e9e-dd85-45b9-a84a-500f384d5c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188668893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.1188668893
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.2408120070
Short name T932
Test name
Test status
Simulation time 97724800 ps
CPU time 13.92 seconds
Started Jun 02 03:23:30 PM PDT 24
Finished Jun 02 03:23:44 PM PDT 24
Peak memory 264756 kb
Host smart-0f585247-27dd-416b-9f6b-43be3b57026f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408120070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
2408120070
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.2506408777
Short name T739
Test name
Test status
Simulation time 17046000 ps
CPU time 15.6 seconds
Started Jun 02 03:23:33 PM PDT 24
Finished Jun 02 03:23:49 PM PDT 24
Peak memory 275792 kb
Host smart-f6b33e3e-a8f7-4e62-89bf-e68e51789428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506408777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.2506408777
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.1400968522
Short name T320
Test name
Test status
Simulation time 4254401900 ps
CPU time 70.38 seconds
Started Jun 02 03:23:27 PM PDT 24
Finished Jun 02 03:24:38 PM PDT 24
Peak memory 262308 kb
Host smart-8bbac6f3-f1d0-4dec-9dc1-f847558075d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400968522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.1400968522
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.688837393
Short name T777
Test name
Test status
Simulation time 2916609400 ps
CPU time 148.8 seconds
Started Jun 02 03:23:28 PM PDT 24
Finished Jun 02 03:25:58 PM PDT 24
Peak memory 297608 kb
Host smart-52c7e09f-353e-4f3f-8b56-fdec06624b5f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688837393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flas
h_ctrl_intr_rd.688837393
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.1821917691
Short name T197
Test name
Test status
Simulation time 11881415900 ps
CPU time 261.6 seconds
Started Jun 02 03:23:27 PM PDT 24
Finished Jun 02 03:27:50 PM PDT 24
Peak memory 292996 kb
Host smart-3bd00ca4-7069-4726-8a5e-7e1b9ff97b04
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821917691 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.1821917691
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.2370824148
Short name T872
Test name
Test status
Simulation time 144136200 ps
CPU time 131.91 seconds
Started Jun 02 03:23:30 PM PDT 24
Finished Jun 02 03:25:42 PM PDT 24
Peak memory 264132 kb
Host smart-f8dd0467-5ea5-4728-86e6-ede231dcb3b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370824148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.2370824148
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.743244620
Short name T1061
Test name
Test status
Simulation time 26230500 ps
CPU time 13.59 seconds
Started Jun 02 03:23:26 PM PDT 24
Finished Jun 02 03:23:40 PM PDT 24
Peak memory 258352 kb
Host smart-439169bd-b1b6-4036-95e9-69f418348268
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743244620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_res
et.743244620
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.3515470781
Short name T1073
Test name
Test status
Simulation time 41406500 ps
CPU time 28.45 seconds
Started Jun 02 03:23:34 PM PDT 24
Finished Jun 02 03:24:03 PM PDT 24
Peak memory 275140 kb
Host smart-53ce1167-c673-4b0b-85ba-3266b182d523
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515470781 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.3515470781
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.2104795109
Short name T156
Test name
Test status
Simulation time 27320395900 ps
CPU time 73.79 seconds
Started Jun 02 03:23:32 PM PDT 24
Finished Jun 02 03:24:46 PM PDT 24
Peak memory 262828 kb
Host smart-fc92d636-79cc-40dc-8a7a-c9980604215c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104795109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.2104795109
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.887149328
Short name T672
Test name
Test status
Simulation time 41169700 ps
CPU time 147.26 seconds
Started Jun 02 03:23:28 PM PDT 24
Finished Jun 02 03:25:56 PM PDT 24
Peak memory 275772 kb
Host smart-bcb56f9e-6c32-4a4c-aa53-61201eaeada9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887149328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.887149328
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.3562956388
Short name T528
Test name
Test status
Simulation time 65497200 ps
CPU time 13.4 seconds
Started Jun 02 03:23:39 PM PDT 24
Finished Jun 02 03:23:52 PM PDT 24
Peak memory 257812 kb
Host smart-c9d29560-74b5-4dd9-b40b-6e69200d51c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562956388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
3562956388
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.826517766
Short name T1048
Test name
Test status
Simulation time 29185600 ps
CPU time 15.66 seconds
Started Jun 02 03:23:38 PM PDT 24
Finished Jun 02 03:23:54 PM PDT 24
Peak memory 275956 kb
Host smart-57f42d37-392c-4a0c-8da0-01d3427886cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826517766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.826517766
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.3568386059
Short name T378
Test name
Test status
Simulation time 10487200 ps
CPU time 21.01 seconds
Started Jun 02 03:23:38 PM PDT 24
Finished Jun 02 03:23:59 PM PDT 24
Peak memory 273216 kb
Host smart-4e467ba8-408d-4ed6-822e-0e13a2623ec9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568386059 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.3568386059
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.295995553
Short name T496
Test name
Test status
Simulation time 2441757200 ps
CPU time 200.62 seconds
Started Jun 02 03:23:32 PM PDT 24
Finished Jun 02 03:26:53 PM PDT 24
Peak memory 262300 kb
Host smart-589fea89-d4e9-4ada-abcf-98e6cfa84c20
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295995553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_h
w_sec_otp.295995553
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.2814743637
Short name T971
Test name
Test status
Simulation time 797304700 ps
CPU time 151.98 seconds
Started Jun 02 03:23:34 PM PDT 24
Finished Jun 02 03:26:07 PM PDT 24
Peak memory 289452 kb
Host smart-da8f9cb8-41e7-4a87-b9c1-e8cb325d5a33
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814743637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.2814743637
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1310564798
Short name T849
Test name
Test status
Simulation time 11133329100 ps
CPU time 157.74 seconds
Started Jun 02 03:23:32 PM PDT 24
Finished Jun 02 03:26:10 PM PDT 24
Peak memory 292824 kb
Host smart-fd228c9a-fbc5-43e6-adaa-f7e218362d52
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310564798 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.1310564798
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.1102528166
Short name T1033
Test name
Test status
Simulation time 19021000 ps
CPU time 13.33 seconds
Started Jun 02 03:23:34 PM PDT 24
Finished Jun 02 03:23:48 PM PDT 24
Peak memory 264712 kb
Host smart-1930d5b0-cd6d-4586-875b-0319a81d1e59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102528166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.1102528166
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.1502838700
Short name T338
Test name
Test status
Simulation time 29039000 ps
CPU time 28.98 seconds
Started Jun 02 03:23:32 PM PDT 24
Finished Jun 02 03:24:01 PM PDT 24
Peak memory 274076 kb
Host smart-317119ac-7198-4b04-bbd9-bfcae4c9e2f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502838700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl
ash_ctrl_rw_evict.1502838700
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.878215624
Short name T458
Test name
Test status
Simulation time 157378800 ps
CPU time 30.91 seconds
Started Jun 02 03:23:38 PM PDT 24
Finished Jun 02 03:24:10 PM PDT 24
Peak memory 275084 kb
Host smart-6c168375-6f94-490c-9da5-51f850e4a361
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878215624 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.878215624
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.1624605446
Short name T977
Test name
Test status
Simulation time 5321171700 ps
CPU time 72.27 seconds
Started Jun 02 03:23:40 PM PDT 24
Finished Jun 02 03:24:52 PM PDT 24
Peak memory 264136 kb
Host smart-9c97ef92-a8c6-484d-9869-660e9a6a2b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624605446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.1624605446
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.713639920
Short name T774
Test name
Test status
Simulation time 153784600 ps
CPU time 122.78 seconds
Started Jun 02 03:23:35 PM PDT 24
Finished Jun 02 03:25:38 PM PDT 24
Peak memory 275944 kb
Host smart-714b29aa-c906-4172-b45d-eaff0f624c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713639920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.713639920
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.12345155
Short name T1026
Test name
Test status
Simulation time 32177100 ps
CPU time 13.78 seconds
Started Jun 02 03:23:49 PM PDT 24
Finished Jun 02 03:24:03 PM PDT 24
Peak memory 264824 kb
Host smart-b491cfff-ccf7-4601-bf34-bf7b72ac607d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12345155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.12345155
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.353309144
Short name T683
Test name
Test status
Simulation time 38895600 ps
CPU time 13.44 seconds
Started Jun 02 03:23:52 PM PDT 24
Finished Jun 02 03:24:06 PM PDT 24
Peak memory 275532 kb
Host smart-4a468f53-d0de-46ee-90bf-f0c20a360846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353309144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.353309144
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.2569662122
Short name T1057
Test name
Test status
Simulation time 20929400 ps
CPU time 21.91 seconds
Started Jun 02 03:23:51 PM PDT 24
Finished Jun 02 03:24:13 PM PDT 24
Peak memory 264964 kb
Host smart-190c7cd8-7c6d-4c9e-b7d6-2153b0a4cb91
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569662122 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.2569662122
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.2884654054
Short name T430
Test name
Test status
Simulation time 20235801700 ps
CPU time 156.03 seconds
Started Jun 02 03:23:39 PM PDT 24
Finished Jun 02 03:26:15 PM PDT 24
Peak memory 262384 kb
Host smart-0de295bb-11d6-419a-9fb2-14de62e8990f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884654054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.2884654054
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.2984120747
Short name T944
Test name
Test status
Simulation time 9580245200 ps
CPU time 202.74 seconds
Started Jun 02 03:23:37 PM PDT 24
Finished Jun 02 03:27:00 PM PDT 24
Peak memory 290404 kb
Host smart-37b40ab2-bc50-4ebe-a25e-a6e71d88738a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984120747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.2984120747
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.1557957255
Short name T490
Test name
Test status
Simulation time 50531325800 ps
CPU time 279.56 seconds
Started Jun 02 03:23:37 PM PDT 24
Finished Jun 02 03:28:17 PM PDT 24
Peak memory 293036 kb
Host smart-0e03d3b4-e53b-4b81-8f1f-cee11e9c5429
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557957255 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.1557957255
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.3721642686
Short name T790
Test name
Test status
Simulation time 47336500 ps
CPU time 131.17 seconds
Started Jun 02 03:23:38 PM PDT 24
Finished Jun 02 03:25:50 PM PDT 24
Peak memory 260760 kb
Host smart-66100e91-b4e5-4aba-8a61-0a4b2726068e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721642686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.3721642686
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.3554726770
Short name T100
Test name
Test status
Simulation time 48715100 ps
CPU time 14.13 seconds
Started Jun 02 03:23:53 PM PDT 24
Finished Jun 02 03:24:07 PM PDT 24
Peak memory 265008 kb
Host smart-63021498-0be4-4e30-8ad6-cf8f44138240
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554726770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.3554726770
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.1664155832
Short name T734
Test name
Test status
Simulation time 50175500 ps
CPU time 30.94 seconds
Started Jun 02 03:23:53 PM PDT 24
Finished Jun 02 03:24:24 PM PDT 24
Peak memory 274464 kb
Host smart-46b6b098-99cc-47b7-a060-6a547e25e70b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664155832 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.1664155832
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.2146714857
Short name T485
Test name
Test status
Simulation time 1394147600 ps
CPU time 67.16 seconds
Started Jun 02 03:23:51 PM PDT 24
Finished Jun 02 03:24:59 PM PDT 24
Peak memory 262716 kb
Host smart-1cb34351-ce1c-4ec2-bced-e112e6072166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146714857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.2146714857
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.3874427431
Short name T44
Test name
Test status
Simulation time 19036600 ps
CPU time 76.6 seconds
Started Jun 02 03:23:37 PM PDT 24
Finished Jun 02 03:24:54 PM PDT 24
Peak memory 275796 kb
Host smart-2b119bd8-295f-4794-ae33-8b94ea3c0e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874427431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.3874427431
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.2169413557
Short name T498
Test name
Test status
Simulation time 228456400 ps
CPU time 13.95 seconds
Started Jun 02 03:23:51 PM PDT 24
Finished Jun 02 03:24:06 PM PDT 24
Peak memory 257816 kb
Host smart-a3d98f44-060b-4262-90ad-cfb450e490e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169413557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
2169413557
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.3888114431
Short name T215
Test name
Test status
Simulation time 40543500 ps
CPU time 15.79 seconds
Started Jun 02 03:23:51 PM PDT 24
Finished Jun 02 03:24:07 PM PDT 24
Peak memory 275848 kb
Host smart-83f96c2d-cfc0-46c7-b80e-8b4ca6aeb83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888114431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3888114431
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.2506889911
Short name T386
Test name
Test status
Simulation time 11545400 ps
CPU time 21.72 seconds
Started Jun 02 03:23:49 PM PDT 24
Finished Jun 02 03:24:12 PM PDT 24
Peak memory 273160 kb
Host smart-5d600287-1b16-49b6-ac37-536e95649bcf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506889911 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.2506889911
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.575187101
Short name T1024
Test name
Test status
Simulation time 5632591900 ps
CPU time 84.68 seconds
Started Jun 02 03:23:50 PM PDT 24
Finished Jun 02 03:25:16 PM PDT 24
Peak memory 262400 kb
Host smart-a7ff4d91-3263-48c8-82f9-6d59613958f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575187101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_h
w_sec_otp.575187101
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.3742444095
Short name T355
Test name
Test status
Simulation time 4056828100 ps
CPU time 148.67 seconds
Started Jun 02 03:23:52 PM PDT 24
Finished Jun 02 03:26:21 PM PDT 24
Peak memory 283696 kb
Host smart-546f877b-bbeb-4da5-a96b-06abfb457529
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742444095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.3742444095
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.4123544802
Short name T195
Test name
Test status
Simulation time 46445944900 ps
CPU time 337.5 seconds
Started Jun 02 03:23:50 PM PDT 24
Finished Jun 02 03:29:28 PM PDT 24
Peak memory 294104 kb
Host smart-d45f4f93-4d71-43d6-bd1b-e715c94abb8d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123544802 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.4123544802
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.725333777
Short name T552
Test name
Test status
Simulation time 71603900 ps
CPU time 134.17 seconds
Started Jun 02 03:23:51 PM PDT 24
Finished Jun 02 03:26:06 PM PDT 24
Peak memory 259964 kb
Host smart-6b18001b-df54-41e0-9e25-3fab84b1642e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725333777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ot
p_reset.725333777
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.350830796
Short name T1070
Test name
Test status
Simulation time 121283100 ps
CPU time 13.5 seconds
Started Jun 02 03:23:50 PM PDT 24
Finished Jun 02 03:24:04 PM PDT 24
Peak memory 258464 kb
Host smart-1261240f-1502-4cf4-b18f-d05f1fef09e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350830796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_res
et.350830796
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.1686717381
Short name T245
Test name
Test status
Simulation time 29332500 ps
CPU time 31.25 seconds
Started Jun 02 03:23:52 PM PDT 24
Finished Jun 02 03:24:24 PM PDT 24
Peak memory 274468 kb
Host smart-eee1073a-bae6-47a7-b789-a3832b84d020
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686717381 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.1686717381
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.875716330
Short name T1047
Test name
Test status
Simulation time 9588027000 ps
CPU time 82.35 seconds
Started Jun 02 03:23:53 PM PDT 24
Finished Jun 02 03:25:16 PM PDT 24
Peak memory 263592 kb
Host smart-e0a861b4-16bf-4bb6-afa3-89860b2ab28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875716330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.875716330
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.209360927
Short name T454
Test name
Test status
Simulation time 20016700 ps
CPU time 98.86 seconds
Started Jun 02 03:23:51 PM PDT 24
Finished Jun 02 03:25:30 PM PDT 24
Peak memory 276556 kb
Host smart-6b2c682a-a412-48ab-b56c-cc6882265776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209360927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.209360927
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.4275678726
Short name T198
Test name
Test status
Simulation time 79520500 ps
CPU time 13.65 seconds
Started Jun 02 03:23:56 PM PDT 24
Finished Jun 02 03:24:10 PM PDT 24
Peak memory 264808 kb
Host smart-6af64e99-6aac-44d6-8e6b-db8b98f5b145
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275678726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
4275678726
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.871774583
Short name T930
Test name
Test status
Simulation time 19141300 ps
CPU time 15.49 seconds
Started Jun 02 03:23:55 PM PDT 24
Finished Jun 02 03:24:12 PM PDT 24
Peak memory 275560 kb
Host smart-b72d5a78-3b24-4469-8224-097f8d5c8344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871774583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.871774583
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.2548044182
Short name T1038
Test name
Test status
Simulation time 30316800 ps
CPU time 22.04 seconds
Started Jun 02 03:23:55 PM PDT 24
Finished Jun 02 03:24:17 PM PDT 24
Peak memory 273372 kb
Host smart-96ff5e1a-b84e-4dd7-bf99-26436d21468a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548044182 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.2548044182
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.3769438349
Short name T663
Test name
Test status
Simulation time 2758876200 ps
CPU time 104.53 seconds
Started Jun 02 03:23:55 PM PDT 24
Finished Jun 02 03:25:40 PM PDT 24
Peak memory 262280 kb
Host smart-3daf11a5-919f-447d-8d1b-48c55666943b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769438349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.3769438349
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.861178660
Short name T979
Test name
Test status
Simulation time 709484700 ps
CPU time 170.42 seconds
Started Jun 02 03:23:58 PM PDT 24
Finished Jun 02 03:26:49 PM PDT 24
Peak memory 294080 kb
Host smart-8318c957-7ccd-4e59-b3bc-371bb320e18c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861178660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flas
h_ctrl_intr_rd.861178660
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.110161486
Short name T602
Test name
Test status
Simulation time 5984667800 ps
CPU time 122.08 seconds
Started Jun 02 03:23:56 PM PDT 24
Finished Jun 02 03:25:59 PM PDT 24
Peak memory 293024 kb
Host smart-77ce0ace-d3ba-4fbf-88ba-b88a65211dc0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110161486 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.110161486
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.4269699143
Short name T802
Test name
Test status
Simulation time 175631300 ps
CPU time 112.26 seconds
Started Jun 02 03:23:54 PM PDT 24
Finished Jun 02 03:25:47 PM PDT 24
Peak memory 259552 kb
Host smart-9a98654b-832a-48b1-8bac-0317f39e2720
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269699143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.4269699143
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.2843148831
Short name T524
Test name
Test status
Simulation time 39733900 ps
CPU time 31.38 seconds
Started Jun 02 03:23:54 PM PDT 24
Finished Jun 02 03:24:26 PM PDT 24
Peak memory 273120 kb
Host smart-c8366a8c-f5a3-4a10-b9b2-e5557c3f6880
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843148831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.2843148831
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.3757895142
Short name T18
Test name
Test status
Simulation time 1285315100 ps
CPU time 52.59 seconds
Started Jun 02 03:23:56 PM PDT 24
Finished Jun 02 03:24:49 PM PDT 24
Peak memory 262900 kb
Host smart-1285de40-43b6-45bc-93f4-cd9c4b35f32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757895142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.3757895142
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.1142516852
Short name T688
Test name
Test status
Simulation time 35647300 ps
CPU time 77.72 seconds
Started Jun 02 03:23:52 PM PDT 24
Finished Jun 02 03:25:10 PM PDT 24
Peak memory 275656 kb
Host smart-6617b9b5-11ce-45e3-8d4c-771111147393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142516852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.1142516852
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.898923082
Short name T997
Test name
Test status
Simulation time 65949100 ps
CPU time 13.98 seconds
Started Jun 02 03:24:01 PM PDT 24
Finished Jun 02 03:24:16 PM PDT 24
Peak memory 257900 kb
Host smart-63b5adb6-b637-408d-969e-977fedc7cecb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898923082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.898923082
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.586865781
Short name T862
Test name
Test status
Simulation time 15143800 ps
CPU time 15.71 seconds
Started Jun 02 03:24:05 PM PDT 24
Finished Jun 02 03:24:21 PM PDT 24
Peak memory 275880 kb
Host smart-aa272ec5-7b67-4eac-aad9-61dc5a060dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586865781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.586865781
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.472987721
Short name T148
Test name
Test status
Simulation time 11565700 ps
CPU time 21.58 seconds
Started Jun 02 03:24:00 PM PDT 24
Finished Jun 02 03:24:22 PM PDT 24
Peak memory 264960 kb
Host smart-2d363e6b-ac3a-4d4f-9b34-988d46a0d1f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472987721 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.472987721
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.3148444777
Short name T327
Test name
Test status
Simulation time 2417607900 ps
CPU time 54.02 seconds
Started Jun 02 03:23:55 PM PDT 24
Finished Jun 02 03:24:49 PM PDT 24
Peak memory 262304 kb
Host smart-d6cde56e-e92b-4cf6-a55b-47e9ffe310b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148444777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.3148444777
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.3126533179
Short name T795
Test name
Test status
Simulation time 1473403500 ps
CPU time 153.6 seconds
Started Jun 02 03:23:55 PM PDT 24
Finished Jun 02 03:26:30 PM PDT 24
Peak memory 292720 kb
Host smart-011b48a7-2085-4681-918f-d94909933415
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126533179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.3126533179
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.2228998916
Short name T645
Test name
Test status
Simulation time 5874224400 ps
CPU time 123.75 seconds
Started Jun 02 03:24:06 PM PDT 24
Finished Jun 02 03:26:10 PM PDT 24
Peak memory 291636 kb
Host smart-00aa9fd5-15fb-44ad-bd58-3caef19fce86
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228998916 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.2228998916
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.2826387466
Short name T111
Test name
Test status
Simulation time 9285085000 ps
CPU time 185.4 seconds
Started Jun 02 03:24:01 PM PDT 24
Finished Jun 02 03:27:07 PM PDT 24
Peak memory 264820 kb
Host smart-ad105d12-6cc2-486a-b91b-bea9a45788ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826387466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.2826387466
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.1410052927
Short name T719
Test name
Test status
Simulation time 231698800 ps
CPU time 30.98 seconds
Started Jun 02 03:24:02 PM PDT 24
Finished Jun 02 03:24:33 PM PDT 24
Peak memory 273064 kb
Host smart-71faa541-d78f-49b6-b552-e55ca77816fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410052927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.1410052927
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.1611290324
Short name T926
Test name
Test status
Simulation time 31245300 ps
CPU time 31.28 seconds
Started Jun 02 03:24:03 PM PDT 24
Finished Jun 02 03:24:35 PM PDT 24
Peak memory 272120 kb
Host smart-84fbaca2-f44f-44c0-a2d5-7cc754fafb69
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611290324 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.1611290324
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.3812094531
Short name T995
Test name
Test status
Simulation time 21948200 ps
CPU time 124.66 seconds
Started Jun 02 03:23:56 PM PDT 24
Finished Jun 02 03:26:01 PM PDT 24
Peak memory 275464 kb
Host smart-b0db896a-d4ba-401e-9d97-5b932f323904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812094531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.3812094531
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.3594227058
Short name T467
Test name
Test status
Simulation time 77032300 ps
CPU time 13.83 seconds
Started Jun 02 03:24:06 PM PDT 24
Finished Jun 02 03:24:21 PM PDT 24
Peak memory 263984 kb
Host smart-b196d702-2bab-418b-98a4-90010c52321b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594227058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
3594227058
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.152174782
Short name T553
Test name
Test status
Simulation time 13640400 ps
CPU time 13.24 seconds
Started Jun 02 03:24:02 PM PDT 24
Finished Jun 02 03:24:16 PM PDT 24
Peak memory 275828 kb
Host smart-97ff2234-43c6-41f6-973e-1c83d2fba70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152174782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.152174782
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.3792512709
Short name T377
Test name
Test status
Simulation time 22545100 ps
CPU time 21.75 seconds
Started Jun 02 03:24:03 PM PDT 24
Finished Jun 02 03:24:25 PM PDT 24
Peak memory 273296 kb
Host smart-cadb4e7c-3a14-40f0-b4b6-dcaa5f1801cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792512709 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.3792512709
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.2246253992
Short name T753
Test name
Test status
Simulation time 469959700 ps
CPU time 113.12 seconds
Started Jun 02 03:24:01 PM PDT 24
Finished Jun 02 03:25:55 PM PDT 24
Peak memory 289432 kb
Host smart-163d96d8-17e5-4361-8c7a-29576616f6b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246253992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.2246253992
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1650060722
Short name T1021
Test name
Test status
Simulation time 13927571400 ps
CPU time 244.9 seconds
Started Jun 02 03:24:04 PM PDT 24
Finished Jun 02 03:28:09 PM PDT 24
Peak memory 292380 kb
Host smart-26f43233-498b-4065-a7f0-27cd6d039d19
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650060722 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1650060722
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.4077138577
Short name T904
Test name
Test status
Simulation time 132459600 ps
CPU time 13.62 seconds
Started Jun 02 03:24:03 PM PDT 24
Finished Jun 02 03:24:18 PM PDT 24
Peak memory 258348 kb
Host smart-9af2b10f-2012-4164-b7fa-14c8ee70f06e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077138577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_re
set.4077138577
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.1663120517
Short name T581
Test name
Test status
Simulation time 32164700 ps
CPU time 30.77 seconds
Started Jun 02 03:24:06 PM PDT 24
Finished Jun 02 03:24:37 PM PDT 24
Peak memory 273088 kb
Host smart-f7c8c4bf-d845-4e94-8f04-92e5fbea27e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663120517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl
ash_ctrl_rw_evict.1663120517
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.1051402045
Short name T648
Test name
Test status
Simulation time 69631100 ps
CPU time 29.02 seconds
Started Jun 02 03:24:01 PM PDT 24
Finished Jun 02 03:24:30 PM PDT 24
Peak memory 274408 kb
Host smart-8613b1bf-e35b-47d4-9d65-46edb2419a8a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051402045 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.1051402045
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.1061460377
Short name T786
Test name
Test status
Simulation time 439951300 ps
CPU time 58.45 seconds
Started Jun 02 03:24:02 PM PDT 24
Finished Jun 02 03:25:01 PM PDT 24
Peak memory 262988 kb
Host smart-8067a0a5-d3e0-4fc6-a24a-0b88fd097eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061460377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.1061460377
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.1294036549
Short name T990
Test name
Test status
Simulation time 31625000 ps
CPU time 121.94 seconds
Started Jun 02 03:24:05 PM PDT 24
Finished Jun 02 03:26:08 PM PDT 24
Peak memory 278628 kb
Host smart-99df95f7-20b0-4bde-b83b-6bb1c235341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294036549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.1294036549
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.703895188
Short name T592
Test name
Test status
Simulation time 27687000 ps
CPU time 13.38 seconds
Started Jun 02 03:24:13 PM PDT 24
Finished Jun 02 03:24:27 PM PDT 24
Peak memory 264196 kb
Host smart-78c1cb78-a466-47d2-8ebd-0fc5711886a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703895188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.703895188
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.657478576
Short name T325
Test name
Test status
Simulation time 86758900 ps
CPU time 15.72 seconds
Started Jun 02 03:24:13 PM PDT 24
Finished Jun 02 03:24:29 PM PDT 24
Peak memory 275528 kb
Host smart-cc976f9b-2340-4b10-bdcc-a46349614ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657478576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.657478576
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.545031623
Short name T1039
Test name
Test status
Simulation time 10317700 ps
CPU time 22.7 seconds
Started Jun 02 03:24:07 PM PDT 24
Finished Jun 02 03:24:30 PM PDT 24
Peak memory 279920 kb
Host smart-7041281c-1f5d-4f05-ac7c-e44a03b09d51
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545031623 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.545031623
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.2695950420
Short name T1010
Test name
Test status
Simulation time 940904400 ps
CPU time 47.94 seconds
Started Jun 02 03:24:07 PM PDT 24
Finished Jun 02 03:24:56 PM PDT 24
Peak memory 262536 kb
Host smart-6e5de11e-de41-4900-80b4-100d6ed65d4b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695950420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.2695950420
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.1304485024
Short name T31
Test name
Test status
Simulation time 2444305300 ps
CPU time 136.92 seconds
Started Jun 02 03:24:09 PM PDT 24
Finished Jun 02 03:26:26 PM PDT 24
Peak memory 293664 kb
Host smart-3459667d-c646-4ba9-b630-d90b820fc876
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304485024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_intr_rd.1304485024
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3708266091
Short name T421
Test name
Test status
Simulation time 16039343000 ps
CPU time 135.85 seconds
Started Jun 02 03:24:08 PM PDT 24
Finished Jun 02 03:26:25 PM PDT 24
Peak memory 291636 kb
Host smart-f82e3807-f117-45d6-bca5-98c36cf23dda
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708266091 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.3708266091
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.2086081762
Short name T136
Test name
Test status
Simulation time 39773900 ps
CPU time 129.55 seconds
Started Jun 02 03:24:07 PM PDT 24
Finished Jun 02 03:26:17 PM PDT 24
Peak memory 259776 kb
Host smart-db2a63c7-0a1c-437e-a496-90fb50f0c786
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086081762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.2086081762
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.374180572
Short name T439
Test name
Test status
Simulation time 62430100 ps
CPU time 13.54 seconds
Started Jun 02 03:24:07 PM PDT 24
Finished Jun 02 03:24:21 PM PDT 24
Peak memory 258444 kb
Host smart-a6558155-ab03-4b78-aac2-85d85f76f3eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374180572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_res
et.374180572
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.3829098478
Short name T600
Test name
Test status
Simulation time 54545200 ps
CPU time 28.87 seconds
Started Jun 02 03:24:07 PM PDT 24
Finished Jun 02 03:24:37 PM PDT 24
Peak memory 274444 kb
Host smart-b4982302-8188-4e88-b03a-f8d9a1e7d2d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829098478 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.3829098478
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.3203172315
Short name T714
Test name
Test status
Simulation time 3365957500 ps
CPU time 60.87 seconds
Started Jun 02 03:24:15 PM PDT 24
Finished Jun 02 03:25:17 PM PDT 24
Peak memory 263324 kb
Host smart-22024c73-f5c2-4969-a721-2d5aa7c855c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203172315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.3203172315
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.4002565245
Short name T1016
Test name
Test status
Simulation time 67932800 ps
CPU time 147.27 seconds
Started Jun 02 03:24:08 PM PDT 24
Finished Jun 02 03:26:35 PM PDT 24
Peak memory 276140 kb
Host smart-7b8f60ec-1505-4ad8-b1b8-364da4e2c5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002565245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.4002565245
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.296403279
Short name T571
Test name
Test status
Simulation time 149815100 ps
CPU time 13.54 seconds
Started Jun 02 03:24:20 PM PDT 24
Finished Jun 02 03:24:34 PM PDT 24
Peak memory 264776 kb
Host smart-bb69f0c7-999a-4551-9666-623bbc786f8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296403279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.296403279
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.2546113456
Short name T772
Test name
Test status
Simulation time 52315000 ps
CPU time 15.45 seconds
Started Jun 02 03:24:19 PM PDT 24
Finished Jun 02 03:24:35 PM PDT 24
Peak memory 275876 kb
Host smart-004b2263-0654-4dfd-aaf6-c6a77a8e0194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546113456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.2546113456
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.2590947298
Short name T963
Test name
Test status
Simulation time 69141900 ps
CPU time 21.69 seconds
Started Jun 02 03:24:13 PM PDT 24
Finished Jun 02 03:24:36 PM PDT 24
Peak memory 273068 kb
Host smart-9f1ca901-8dc2-40fa-835d-258be9624af9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590947298 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.2590947298
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.3641080183
Short name T905
Test name
Test status
Simulation time 2407656500 ps
CPU time 193.38 seconds
Started Jun 02 03:24:13 PM PDT 24
Finished Jun 02 03:27:27 PM PDT 24
Peak memory 262148 kb
Host smart-18279ffd-6485-4971-aa2b-a602cc4257ff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641080183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.3641080183
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.1158269648
Short name T190
Test name
Test status
Simulation time 642531600 ps
CPU time 145.82 seconds
Started Jun 02 03:24:15 PM PDT 24
Finished Jun 02 03:26:41 PM PDT 24
Peak memory 292812 kb
Host smart-e361f1b0-06e6-4273-8ea4-7d41c888b038
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158269648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.1158269648
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.2337398182
Short name T858
Test name
Test status
Simulation time 5973129200 ps
CPU time 164.9 seconds
Started Jun 02 03:24:14 PM PDT 24
Finished Jun 02 03:27:00 PM PDT 24
Peak memory 291832 kb
Host smart-262fca29-1ca7-4949-b46e-042521deec80
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337398182 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.2337398182
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.3730526152
Short name T140
Test name
Test status
Simulation time 43267700 ps
CPU time 131.45 seconds
Started Jun 02 03:24:13 PM PDT 24
Finished Jun 02 03:26:25 PM PDT 24
Peak memory 260740 kb
Host smart-2d095d35-06d6-429f-bd3c-88fc6f193e49
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730526152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.3730526152
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.457381654
Short name T910
Test name
Test status
Simulation time 19470700 ps
CPU time 13.47 seconds
Started Jun 02 03:24:15 PM PDT 24
Finished Jun 02 03:24:29 PM PDT 24
Peak memory 258364 kb
Host smart-cc055817-20d3-432c-95c4-4efcaf899bdc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457381654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_res
et.457381654
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.373886842
Short name T532
Test name
Test status
Simulation time 127634300 ps
CPU time 30.47 seconds
Started Jun 02 03:24:18 PM PDT 24
Finished Jun 02 03:24:48 PM PDT 24
Peak memory 273180 kb
Host smart-f9a3d127-6fa1-4dee-b16a-9ce0a0f28d0f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373886842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_rw_evict.373886842
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.3575170265
Short name T653
Test name
Test status
Simulation time 52168700 ps
CPU time 31.9 seconds
Started Jun 02 03:24:14 PM PDT 24
Finished Jun 02 03:24:46 PM PDT 24
Peak memory 274352 kb
Host smart-05e38d24-b058-4e8f-876e-0fe8be0494f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575170265 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.3575170265
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.1704044729
Short name T403
Test name
Test status
Simulation time 16725447600 ps
CPU time 86.16 seconds
Started Jun 02 03:24:23 PM PDT 24
Finished Jun 02 03:25:50 PM PDT 24
Peak memory 262160 kb
Host smart-42942161-82d0-4a18-9547-217b4f10c5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704044729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.1704044729
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.289732356
Short name T784
Test name
Test status
Simulation time 59348800 ps
CPU time 98.87 seconds
Started Jun 02 03:24:14 PM PDT 24
Finished Jun 02 03:25:54 PM PDT 24
Peak memory 275232 kb
Host smart-407374c8-5529-457a-a15f-2d0fa89d6058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289732356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.289732356
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.83941234
Short name T691
Test name
Test status
Simulation time 245030300 ps
CPU time 13.54 seconds
Started Jun 02 03:19:40 PM PDT 24
Finished Jun 02 03:19:54 PM PDT 24
Peak memory 257872 kb
Host smart-0ab90767-72cf-4329-b889-7af2b5b22918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83941234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.83941234
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.1221239676
Short name T748
Test name
Test status
Simulation time 13910900 ps
CPU time 15.62 seconds
Started Jun 02 03:19:32 PM PDT 24
Finished Jun 02 03:19:48 PM PDT 24
Peak memory 275504 kb
Host smart-8bc27847-b765-4b88-8c8a-b71e1d027d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221239676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.1221239676
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.1508387569
Short name T216
Test name
Test status
Simulation time 471971000 ps
CPU time 103.86 seconds
Started Jun 02 03:19:29 PM PDT 24
Finished Jun 02 03:21:13 PM PDT 24
Peak memory 273224 kb
Host smart-42e819ae-3c14-4000-b8a6-d909097a92c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508387569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_derr_detect.1508387569
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.2395797957
Short name T82
Test name
Test status
Simulation time 14635300 ps
CPU time 21.63 seconds
Started Jun 02 03:19:34 PM PDT 24
Finished Jun 02 03:19:56 PM PDT 24
Peak memory 274464 kb
Host smart-118b5d45-a1ba-4d6f-9618-fd6c44547661
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395797957 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.2395797957
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.1074143233
Short name T166
Test name
Test status
Simulation time 1395394300 ps
CPU time 354.99 seconds
Started Jun 02 03:19:17 PM PDT 24
Finished Jun 02 03:25:13 PM PDT 24
Peak memory 262804 kb
Host smart-ac5f703f-a806-4868-a3ca-944cdd301d78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1074143233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.1074143233
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.899347086
Short name T1006
Test name
Test status
Simulation time 32316430500 ps
CPU time 2413.92 seconds
Started Jun 02 03:19:21 PM PDT 24
Finished Jun 02 03:59:36 PM PDT 24
Peak memory 264880 kb
Host smart-d195c4e1-6480-4ba7-af3a-7a50ebadda4d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899347086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erro
r_mp.899347086
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.2586883677
Short name T809
Test name
Test status
Simulation time 2140124800 ps
CPU time 2197.96 seconds
Started Jun 02 03:19:21 PM PDT 24
Finished Jun 02 03:56:00 PM PDT 24
Peak memory 264824 kb
Host smart-7775b625-a740-48c0-960e-4b55f3b62deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586883677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.2586883677
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.2427878081
Short name T775
Test name
Test status
Simulation time 870251600 ps
CPU time 843.89 seconds
Started Jun 02 03:19:23 PM PDT 24
Finished Jun 02 03:33:27 PM PDT 24
Peak memory 273024 kb
Host smart-d4244c20-69c8-43f6-9475-0ba7da630782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427878081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.2427878081
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.3815936842
Short name T885
Test name
Test status
Simulation time 120906200 ps
CPU time 22.03 seconds
Started Jun 02 03:19:21 PM PDT 24
Finished Jun 02 03:19:43 PM PDT 24
Peak memory 264780 kb
Host smart-604ae9e1-6da3-4ab5-997a-eb094843e5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815936842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.3815936842
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.3874117651
Short name T658
Test name
Test status
Simulation time 1864241800 ps
CPU time 35.72 seconds
Started Jun 02 03:19:36 PM PDT 24
Finished Jun 02 03:20:12 PM PDT 24
Peak memory 261896 kb
Host smart-f6a69e2f-e1d5-48d2-bae0-d6cfb2566d1e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874117651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.3874117651
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.545828504
Short name T1014
Test name
Test status
Simulation time 445098944500 ps
CPU time 4141.99 seconds
Started Jun 02 03:19:20 PM PDT 24
Finished Jun 02 04:28:23 PM PDT 24
Peak memory 273120 kb
Host smart-acf6e9d6-4854-43cb-a21e-deea46887607
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545828504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_full_mem_access.545828504
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.2838871073
Short name T511
Test name
Test status
Simulation time 285403568800 ps
CPU time 2958.46 seconds
Started Jun 02 03:19:20 PM PDT 24
Finished Jun 02 04:08:39 PM PDT 24
Peak memory 264940 kb
Host smart-54a0d7da-c12d-4fb2-8a2e-71e8e50a605d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838871073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.2838871073
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.646716507
Short name T438
Test name
Test status
Simulation time 120544200 ps
CPU time 109.6 seconds
Started Jun 02 03:19:17 PM PDT 24
Finished Jun 02 03:21:07 PM PDT 24
Peak memory 262332 kb
Host smart-d64e1511-828f-4f9d-a710-102f732378aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=646716507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.646716507
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2216411965
Short name T294
Test name
Test status
Simulation time 10012837700 ps
CPU time 90.08 seconds
Started Jun 02 03:19:40 PM PDT 24
Finished Jun 02 03:21:11 PM PDT 24
Peak memory 265092 kb
Host smart-fe563a1a-a098-47ad-94db-cabec7a1c2a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216411965 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2216411965
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.3317971241
Short name T718
Test name
Test status
Simulation time 48098800 ps
CPU time 13.32 seconds
Started Jun 02 03:19:41 PM PDT 24
Finished Jun 02 03:19:55 PM PDT 24
Peak memory 258092 kb
Host smart-c4629d0f-9bd2-4732-b4ce-8af6612498ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317971241 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.3317971241
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.2125518508
Short name T508
Test name
Test status
Simulation time 160179954400 ps
CPU time 813.04 seconds
Started Jun 02 03:19:15 PM PDT 24
Finished Jun 02 03:32:49 PM PDT 24
Peak memory 263900 kb
Host smart-8e66d846-a874-4c04-b519-a35c457b78bb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125518508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_hw_rma_reset.2125518508
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.2310247387
Short name T312
Test name
Test status
Simulation time 75362705500 ps
CPU time 140.03 seconds
Started Jun 02 03:19:22 PM PDT 24
Finished Jun 02 03:21:42 PM PDT 24
Peak memory 262324 kb
Host smart-dae8ae41-e9e4-491c-8a7b-382b769bf887
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310247387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.2310247387
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.1076408192
Short name T248
Test name
Test status
Simulation time 22079353100 ps
CPU time 649.13 seconds
Started Jun 02 03:19:27 PM PDT 24
Finished Jun 02 03:30:16 PM PDT 24
Peak memory 332968 kb
Host smart-32661da1-3b1e-4ab3-aef2-89d199def68a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076408192 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_integrity.1076408192
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.541207073
Short name T788
Test name
Test status
Simulation time 1369995600 ps
CPU time 182.54 seconds
Started Jun 02 03:19:31 PM PDT 24
Finished Jun 02 03:22:34 PM PDT 24
Peak memory 283860 kb
Host smart-7e0db379-f186-42b9-b49b-abeefff6cc8d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541207073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_intr_rd.541207073
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.4177319989
Short name T876
Test name
Test status
Simulation time 88800092000 ps
CPU time 323.99 seconds
Started Jun 02 03:19:28 PM PDT 24
Finished Jun 02 03:24:53 PM PDT 24
Peak memory 291348 kb
Host smart-090ebba4-e473-49b1-8d42-abb2bfd962bf
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177319989 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.4177319989
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.3184664635
Short name T431
Test name
Test status
Simulation time 8504714800 ps
CPU time 67.42 seconds
Started Jun 02 03:19:28 PM PDT 24
Finished Jun 02 03:20:36 PM PDT 24
Peak memory 259480 kb
Host smart-0091a423-84b7-406e-9352-73af9dfd64d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184664635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.3184664635
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.956372245
Short name T446
Test name
Test status
Simulation time 3299463300 ps
CPU time 69.25 seconds
Started Jun 02 03:19:23 PM PDT 24
Finished Jun 02 03:20:33 PM PDT 24
Peak memory 259712 kb
Host smart-c3ef2281-2bbf-473e-9aeb-cacd1808042e
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956372245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.956372245
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.280607929
Short name T1013
Test name
Test status
Simulation time 17127100 ps
CPU time 13.64 seconds
Started Jun 02 03:19:40 PM PDT 24
Finished Jun 02 03:19:54 PM PDT 24
Peak memory 264780 kb
Host smart-7abcc687-399b-4c2d-8c2d-9289f645e6e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280607929 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.280607929
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.702896957
Short name T226
Test name
Test status
Simulation time 16824124800 ps
CPU time 548.75 seconds
Started Jun 02 03:19:23 PM PDT 24
Finished Jun 02 03:28:32 PM PDT 24
Peak memory 274156 kb
Host smart-95dabb30-a4cc-46f6-bedc-abd9257082b9
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702896957 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_mp_regions.702896957
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.2253234604
Short name T387
Test name
Test status
Simulation time 42492400 ps
CPU time 109.88 seconds
Started Jun 02 03:19:21 PM PDT 24
Finished Jun 02 03:21:11 PM PDT 24
Peak memory 259924 kb
Host smart-6855f629-212b-47b2-a20d-cbf376645590
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253234604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.2253234604
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.820320543
Short name T750
Test name
Test status
Simulation time 2037593500 ps
CPU time 169.14 seconds
Started Jun 02 03:19:31 PM PDT 24
Finished Jun 02 03:22:20 PM PDT 24
Peak memory 293864 kb
Host smart-dbc6eae0-8e48-4d1a-bfdd-6cd82c6a261e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820320543 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.820320543
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.2234082209
Short name T57
Test name
Test status
Simulation time 16355700 ps
CPU time 14.01 seconds
Started Jun 02 03:19:32 PM PDT 24
Finished Jun 02 03:19:47 PM PDT 24
Peak memory 276432 kb
Host smart-bd1b7afc-9668-4a9b-b93b-5e042f4e1be8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2234082209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.2234082209
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.3124616824
Short name T577
Test name
Test status
Simulation time 55810400 ps
CPU time 243.58 seconds
Started Jun 02 03:19:17 PM PDT 24
Finished Jun 02 03:23:21 PM PDT 24
Peak memory 262128 kb
Host smart-a3730f1a-2aac-4d7c-8d0f-6e8de149bdec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3124616824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.3124616824
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.3850933923
Short name T810
Test name
Test status
Simulation time 14793000 ps
CPU time 14.04 seconds
Started Jun 02 03:19:36 PM PDT 24
Finished Jun 02 03:19:50 PM PDT 24
Peak memory 264528 kb
Host smart-0acb6a00-26bc-48a8-a7cd-2b21218c95bd
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850933923 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3850933923
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.1062927468
Short name T162
Test name
Test status
Simulation time 55389100 ps
CPU time 13.41 seconds
Started Jun 02 03:19:29 PM PDT 24
Finished Jun 02 03:19:43 PM PDT 24
Peak memory 258284 kb
Host smart-dce34642-459b-4cbc-8a3b-61c1dddcca65
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062927468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.1062927468
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.1755501399
Short name T1019
Test name
Test status
Simulation time 77578600 ps
CPU time 127.2 seconds
Started Jun 02 03:19:16 PM PDT 24
Finished Jun 02 03:21:24 PM PDT 24
Peak memory 270588 kb
Host smart-750692a2-f5c5-47a5-b4d1-4642dc690345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755501399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.1755501399
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.3138600020
Short name T569
Test name
Test status
Simulation time 91368900 ps
CPU time 98.38 seconds
Started Jun 02 03:19:14 PM PDT 24
Finished Jun 02 03:20:53 PM PDT 24
Peak memory 264892 kb
Host smart-151c45c4-030a-427a-bce9-28aeb4c79df1
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3138600020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.3138600020
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.1823558685
Short name T1031
Test name
Test status
Simulation time 233064300 ps
CPU time 34.26 seconds
Started Jun 02 03:19:34 PM PDT 24
Finished Jun 02 03:20:09 PM PDT 24
Peak memory 269616 kb
Host smart-bcef3625-a6bc-4a3e-a822-ea297e7c30a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823558685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.1823558685
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.385340945
Short name T671
Test name
Test status
Simulation time 17936500 ps
CPU time 22.6 seconds
Started Jun 02 03:19:29 PM PDT 24
Finished Jun 02 03:19:52 PM PDT 24
Peak memory 264700 kb
Host smart-bdaab64d-7d7d-48f7-85c0-750ace6e1e4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385340945 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.385340945
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.3405726442
Short name T820
Test name
Test status
Simulation time 1163808900 ps
CPU time 140.95 seconds
Started Jun 02 03:19:22 PM PDT 24
Finished Jun 02 03:21:43 PM PDT 24
Peak memory 296736 kb
Host smart-d75d6720-d584-469e-8ddf-1245a29d4800
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405726442 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.3405726442
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.582050342
Short name T564
Test name
Test status
Simulation time 2350912900 ps
CPU time 137.84 seconds
Started Jun 02 03:19:27 PM PDT 24
Finished Jun 02 03:21:46 PM PDT 24
Peak memory 281240 kb
Host smart-11292cd5-a5a9-4d0c-bb9f-9d3193c2357b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
582050342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.582050342
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.324220191
Short name T607
Test name
Test status
Simulation time 657561100 ps
CPU time 123.73 seconds
Started Jun 02 03:19:29 PM PDT 24
Finished Jun 02 03:21:33 PM PDT 24
Peak memory 281172 kb
Host smart-5a953250-a4ca-486e-ad0b-d849234df53e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324220191 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.324220191
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.2806261939
Short name T515
Test name
Test status
Simulation time 16940932100 ps
CPU time 630.29 seconds
Started Jun 02 03:19:21 PM PDT 24
Finished Jun 02 03:29:52 PM PDT 24
Peak memory 313268 kb
Host smart-95f1a0a2-5b0b-4238-99a3-9bda7b7785e4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806261939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_rw.2806261939
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.1833548267
Short name T250
Test name
Test status
Simulation time 51148362700 ps
CPU time 502.42 seconds
Started Jun 02 03:19:28 PM PDT 24
Finished Jun 02 03:27:51 PM PDT 24
Peak memory 330356 kb
Host smart-49a6988b-2192-4872-88a3-f2a485fe677f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833548267 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_rw_derr.1833548267
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.1214671755
Short name T339
Test name
Test status
Simulation time 31027200 ps
CPU time 31.24 seconds
Started Jun 02 03:19:33 PM PDT 24
Finished Jun 02 03:20:05 PM PDT 24
Peak memory 273036 kb
Host smart-9f6e1f46-10af-491d-a637-c24772c4bf7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214671755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.1214671755
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.304036295
Short name T900
Test name
Test status
Simulation time 33410200 ps
CPU time 31.26 seconds
Started Jun 02 03:19:32 PM PDT 24
Finished Jun 02 03:20:04 PM PDT 24
Peak memory 274412 kb
Host smart-0cd9b4df-c012-4d8f-b076-5c9ea3c7a320
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304036295 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.304036295
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.1843993026
Short name T1007
Test name
Test status
Simulation time 4052582500 ps
CPU time 615.84 seconds
Started Jun 02 03:19:29 PM PDT 24
Finished Jun 02 03:29:45 PM PDT 24
Peak memory 319848 kb
Host smart-1e8621a4-60e1-4ee3-a8f0-ae3c855e069f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843993026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s
err.1843993026
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.944046926
Short name T169
Test name
Test status
Simulation time 25711486400 ps
CPU time 4953.8 seconds
Started Jun 02 03:19:36 PM PDT 24
Finished Jun 02 04:42:10 PM PDT 24
Peak memory 289232 kb
Host smart-11155114-1e34-4d55-935f-9adfd52c843e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944046926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.944046926
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.4143018747
Short name T409
Test name
Test status
Simulation time 4516633500 ps
CPU time 80.63 seconds
Started Jun 02 03:19:34 PM PDT 24
Finished Jun 02 03:20:55 PM PDT 24
Peak memory 262764 kb
Host smart-f473622d-4c3e-4944-8982-d2624aa3a941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143018747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.4143018747
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.2791527568
Short name T684
Test name
Test status
Simulation time 4147690800 ps
CPU time 93.68 seconds
Started Jun 02 03:19:27 PM PDT 24
Finished Jun 02 03:21:02 PM PDT 24
Peak memory 264868 kb
Host smart-acc26883-4c14-4545-8c8c-3b96373b302b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791527568 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.2791527568
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.4227786379
Short name T449
Test name
Test status
Simulation time 555281800 ps
CPU time 67.09 seconds
Started Jun 02 03:19:28 PM PDT 24
Finished Jun 02 03:20:36 PM PDT 24
Peak memory 265028 kb
Host smart-22a5a222-3a4f-47c4-b020-fc2cf0843d91
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227786379 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.4227786379
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.2252858298
Short name T742
Test name
Test status
Simulation time 17487000 ps
CPU time 51.77 seconds
Started Jun 02 03:19:14 PM PDT 24
Finished Jun 02 03:20:06 PM PDT 24
Peak memory 270416 kb
Host smart-ae1be6c8-d28d-4deb-8343-cce9a0ce13a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252858298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.2252858298
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.3273761196
Short name T575
Test name
Test status
Simulation time 18017600 ps
CPU time 25.71 seconds
Started Jun 02 03:19:14 PM PDT 24
Finished Jun 02 03:19:40 PM PDT 24
Peak memory 258844 kb
Host smart-496bfc44-867d-4c5b-86e7-978a1d34bb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273761196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.3273761196
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.3021729516
Short name T859
Test name
Test status
Simulation time 136837900 ps
CPU time 63.13 seconds
Started Jun 02 03:19:32 PM PDT 24
Finished Jun 02 03:20:35 PM PDT 24
Peak memory 259156 kb
Host smart-be4c0c7b-16ac-42c5-bf7c-bdf8da408740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021729516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.3021729516
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.3837102669
Short name T424
Test name
Test status
Simulation time 284113000 ps
CPU time 24.92 seconds
Started Jun 02 03:19:15 PM PDT 24
Finished Jun 02 03:19:41 PM PDT 24
Peak memory 261580 kb
Host smart-8e8f50c2-31c3-4523-aa92-68c2bbc4d734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837102669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3837102669
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.1520577655
Short name T728
Test name
Test status
Simulation time 2908838900 ps
CPU time 245.84 seconds
Started Jun 02 03:19:21 PM PDT 24
Finished Jun 02 03:23:27 PM PDT 24
Peak memory 259176 kb
Host smart-358b5139-d680-4cbb-b078-717b5a6a9c48
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520577655 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_wo.1520577655
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.847692325
Short name T1036
Test name
Test status
Simulation time 46022500 ps
CPU time 13.63 seconds
Started Jun 02 03:24:24 PM PDT 24
Finished Jun 02 03:24:38 PM PDT 24
Peak memory 264796 kb
Host smart-42f47620-d1d6-4a07-9f76-46670ae606b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847692325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.847692325
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.1560419951
Short name T444
Test name
Test status
Simulation time 28422200 ps
CPU time 15.37 seconds
Started Jun 02 03:24:26 PM PDT 24
Finished Jun 02 03:24:42 PM PDT 24
Peak memory 275784 kb
Host smart-90e42aef-84c3-4916-b756-476b754bd781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560419951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.1560419951
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.197063355
Short name T609
Test name
Test status
Simulation time 127106900 ps
CPU time 21.1 seconds
Started Jun 02 03:24:19 PM PDT 24
Finished Jun 02 03:24:41 PM PDT 24
Peak memory 273084 kb
Host smart-bbf7cf90-b91f-4af3-9690-a0c169144a69
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197063355 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.197063355
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.801462242
Short name T247
Test name
Test status
Simulation time 8081887000 ps
CPU time 130.87 seconds
Started Jun 02 03:24:20 PM PDT 24
Finished Jun 02 03:26:31 PM PDT 24
Peak memory 262344 kb
Host smart-9adb0152-38fc-42ba-acb1-6a44ebd74580
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801462242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_h
w_sec_otp.801462242
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.2309949700
Short name T752
Test name
Test status
Simulation time 1425046400 ps
CPU time 137.4 seconds
Started Jun 02 03:24:23 PM PDT 24
Finished Jun 02 03:26:40 PM PDT 24
Peak memory 289456 kb
Host smart-fd35a531-7f96-4150-91f7-1366e2df7b73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309949700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.2309949700
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.2196515191
Short name T847
Test name
Test status
Simulation time 11312652600 ps
CPU time 146.84 seconds
Started Jun 02 03:24:23 PM PDT 24
Finished Jun 02 03:26:51 PM PDT 24
Peak memory 292376 kb
Host smart-95df58ff-a0f1-4fe5-bd5f-3a09a7617929
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196515191 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.2196515191
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.1526578698
Short name T801
Test name
Test status
Simulation time 69890800 ps
CPU time 110.47 seconds
Started Jun 02 03:24:22 PM PDT 24
Finished Jun 02 03:26:13 PM PDT 24
Peak memory 263208 kb
Host smart-29b19599-ce05-4f48-8d4a-619edb1a7aae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526578698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.1526578698
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.876691638
Short name T582
Test name
Test status
Simulation time 32094900 ps
CPU time 31.6 seconds
Started Jun 02 03:24:20 PM PDT 24
Finished Jun 02 03:24:52 PM PDT 24
Peak memory 266840 kb
Host smart-50df8599-31a4-41e6-a5fe-fc913ddb7920
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876691638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_rw_evict.876691638
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.391505138
Short name T747
Test name
Test status
Simulation time 56460000 ps
CPU time 51.64 seconds
Started Jun 02 03:24:23 PM PDT 24
Finished Jun 02 03:25:15 PM PDT 24
Peak memory 270288 kb
Host smart-a0a46b15-520f-4e76-9a39-7ae642ad6fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391505138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.391505138
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.135810182
Short name T956
Test name
Test status
Simulation time 75446900 ps
CPU time 14.51 seconds
Started Jun 02 03:24:30 PM PDT 24
Finished Jun 02 03:24:45 PM PDT 24
Peak memory 257912 kb
Host smart-31f2aa77-b236-4ea8-91a5-5bfa2f07e510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135810182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.135810182
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.3164332336
Short name T805
Test name
Test status
Simulation time 14017300 ps
CPU time 15.7 seconds
Started Jun 02 03:24:31 PM PDT 24
Finished Jun 02 03:24:48 PM PDT 24
Peak memory 275384 kb
Host smart-35687755-c645-4c0c-b04c-e16aecde1ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164332336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3164332336
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.3610929559
Short name T81
Test name
Test status
Simulation time 41154800 ps
CPU time 22.44 seconds
Started Jun 02 03:24:32 PM PDT 24
Finished Jun 02 03:24:55 PM PDT 24
Peak memory 273280 kb
Host smart-7a6d4fb4-8d58-46b0-b441-19dcdc4c6a11
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610929559 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.3610929559
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3444883195
Short name T818
Test name
Test status
Simulation time 905469000 ps
CPU time 51.62 seconds
Started Jun 02 03:24:24 PM PDT 24
Finished Jun 02 03:25:16 PM PDT 24
Peak memory 261716 kb
Host smart-9d8ca42f-f1c8-46be-b9cd-d342347d3fb2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444883195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.3444883195
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.4264633118
Short name T711
Test name
Test status
Simulation time 7442254400 ps
CPU time 203.91 seconds
Started Jun 02 03:24:24 PM PDT 24
Finished Jun 02 03:27:49 PM PDT 24
Peak memory 289460 kb
Host smart-f1c87a08-c4f4-4f19-a883-9457529e89de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264633118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.4264633118
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.1187436987
Short name T828
Test name
Test status
Simulation time 5989912600 ps
CPU time 148.82 seconds
Started Jun 02 03:24:25 PM PDT 24
Finished Jun 02 03:26:54 PM PDT 24
Peak memory 292940 kb
Host smart-212460b7-40d7-4d8c-bcc1-684c4916b324
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187436987 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.1187436987
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.3068798246
Short name T641
Test name
Test status
Simulation time 142288500 ps
CPU time 128.19 seconds
Started Jun 02 03:24:26 PM PDT 24
Finished Jun 02 03:26:34 PM PDT 24
Peak memory 260736 kb
Host smart-2d9a888d-41b5-4aea-990f-7de76a2894f2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068798246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.3068798246
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.2195778238
Short name T1046
Test name
Test status
Simulation time 55026000 ps
CPU time 31.78 seconds
Started Jun 02 03:24:25 PM PDT 24
Finished Jun 02 03:24:57 PM PDT 24
Peak memory 273080 kb
Host smart-eeb0a193-7d3d-4f3b-8c63-1bbb8d60eab4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195778238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.2195778238
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.1682601550
Short name T832
Test name
Test status
Simulation time 45107800 ps
CPU time 28.28 seconds
Started Jun 02 03:24:30 PM PDT 24
Finished Jun 02 03:24:59 PM PDT 24
Peak memory 274348 kb
Host smart-3d10a6a1-893e-47a1-8831-8c31061ca98e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682601550 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.1682601550
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.2024291913
Short name T397
Test name
Test status
Simulation time 2574897800 ps
CPU time 80.77 seconds
Started Jun 02 03:24:31 PM PDT 24
Finished Jun 02 03:25:52 PM PDT 24
Peak memory 264268 kb
Host smart-eaac65ec-7f03-40d3-8af6-7dd5077cafc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024291913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.2024291913
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.3781933529
Short name T1045
Test name
Test status
Simulation time 213241100 ps
CPU time 51.89 seconds
Started Jun 02 03:24:24 PM PDT 24
Finished Jun 02 03:25:17 PM PDT 24
Peak memory 270348 kb
Host smart-d03fba62-d559-45c3-9ef2-927d19254908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781933529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.3781933529
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.2324183235
Short name T797
Test name
Test status
Simulation time 41221000 ps
CPU time 13.83 seconds
Started Jun 02 03:24:35 PM PDT 24
Finished Jun 02 03:24:50 PM PDT 24
Peak memory 257908 kb
Host smart-8908d607-a5d0-4b0f-88bf-19a20c7be7df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324183235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
2324183235
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.2247472966
Short name T537
Test name
Test status
Simulation time 30840600 ps
CPU time 15.67 seconds
Started Jun 02 03:24:35 PM PDT 24
Finished Jun 02 03:24:52 PM PDT 24
Peak memory 275880 kb
Host smart-a7cd1138-c680-446a-ac7f-e6bcbdc9793a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247472966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.2247472966
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.1880240700
Short name T541
Test name
Test status
Simulation time 22665900 ps
CPU time 21.44 seconds
Started Jun 02 03:24:37 PM PDT 24
Finished Jun 02 03:24:59 PM PDT 24
Peak memory 273332 kb
Host smart-7aa5c288-f773-45bf-b48d-c73e6d81a132
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880240700 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.1880240700
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.3999800037
Short name T935
Test name
Test status
Simulation time 6699740700 ps
CPU time 98.75 seconds
Started Jun 02 03:24:32 PM PDT 24
Finished Jun 02 03:26:11 PM PDT 24
Peak memory 262356 kb
Host smart-6e45c2ac-af43-4627-b8cf-99f29ca4e1cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999800037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.3999800037
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.2929089141
Short name T539
Test name
Test status
Simulation time 1654685000 ps
CPU time 127.36 seconds
Started Jun 02 03:24:29 PM PDT 24
Finished Jun 02 03:26:36 PM PDT 24
Peak memory 289460 kb
Host smart-02d003cd-43b7-4d74-8133-163d8eeb6304
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929089141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.2929089141
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1564689775
Short name T1071
Test name
Test status
Simulation time 110314547900 ps
CPU time 332.98 seconds
Started Jun 02 03:24:30 PM PDT 24
Finished Jun 02 03:30:04 PM PDT 24
Peak memory 291424 kb
Host smart-d1dc3594-5099-40e7-95d1-5b0a88dbf261
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564689775 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.1564689775
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.2425610914
Short name T1053
Test name
Test status
Simulation time 82552100 ps
CPU time 128.81 seconds
Started Jun 02 03:24:29 PM PDT 24
Finished Jun 02 03:26:38 PM PDT 24
Peak memory 259604 kb
Host smart-4d212635-5a7e-4966-8989-c675f8e80702
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425610914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_o
tp_reset.2425610914
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.2502347757
Short name T906
Test name
Test status
Simulation time 87588400 ps
CPU time 31.47 seconds
Started Jun 02 03:24:32 PM PDT 24
Finished Jun 02 03:25:04 PM PDT 24
Peak memory 273056 kb
Host smart-25412e49-e9d5-423b-8261-ff8e03a0fccc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502347757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl
ash_ctrl_rw_evict.2502347757
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.4220957023
Short name T964
Test name
Test status
Simulation time 2576658200 ps
CPU time 73.41 seconds
Started Jun 02 03:24:34 PM PDT 24
Finished Jun 02 03:25:48 PM PDT 24
Peak memory 262952 kb
Host smart-c4db6eaa-8dd9-4dba-90ed-5cda68c74906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220957023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.4220957023
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.1330120460
Short name T384
Test name
Test status
Simulation time 60293400 ps
CPU time 146.47 seconds
Started Jun 02 03:24:29 PM PDT 24
Finished Jun 02 03:26:56 PM PDT 24
Peak memory 276020 kb
Host smart-552ff27d-d2ed-4b45-a83d-bbab85e787f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330120460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.1330120460
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.2755031121
Short name T771
Test name
Test status
Simulation time 90394400 ps
CPU time 14.11 seconds
Started Jun 02 03:24:38 PM PDT 24
Finished Jun 02 03:24:53 PM PDT 24
Peak memory 264860 kb
Host smart-ae71ca38-aed1-427f-b554-386cbd721989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755031121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
2755031121
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.2789992858
Short name T682
Test name
Test status
Simulation time 47032700 ps
CPU time 13.49 seconds
Started Jun 02 03:24:34 PM PDT 24
Finished Jun 02 03:24:48 PM PDT 24
Peak memory 275324 kb
Host smart-1724879a-40fe-451b-83c5-3be469197118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789992858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2789992858
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.206011954
Short name T888
Test name
Test status
Simulation time 17226100 ps
CPU time 20.35 seconds
Started Jun 02 03:24:35 PM PDT 24
Finished Jun 02 03:24:56 PM PDT 24
Peak memory 264968 kb
Host smart-3661d5e9-0f48-4287-a3a6-1dc194d4d329
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206011954 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.206011954
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.3915892584
Short name T570
Test name
Test status
Simulation time 5330658200 ps
CPU time 222.42 seconds
Started Jun 02 03:24:36 PM PDT 24
Finished Jun 02 03:28:19 PM PDT 24
Peak memory 261760 kb
Host smart-f42ef28f-7cd5-41fa-9ce9-f0b85a3edf9b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915892584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.3915892584
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.3319439069
Short name T664
Test name
Test status
Simulation time 15176087900 ps
CPU time 252.29 seconds
Started Jun 02 03:24:37 PM PDT 24
Finished Jun 02 03:28:50 PM PDT 24
Peak memory 283552 kb
Host smart-833b389a-d216-4fd1-8f0c-6c59fd6f7dfb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319439069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.3319439069
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.4151157446
Short name T829
Test name
Test status
Simulation time 20226267700 ps
CPU time 139.21 seconds
Started Jun 02 03:24:36 PM PDT 24
Finished Jun 02 03:26:56 PM PDT 24
Peak memory 291568 kb
Host smart-0ef76e1d-be25-445f-8827-aa80c68d5b3b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151157446 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.4151157446
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.825010776
Short name T599
Test name
Test status
Simulation time 39293800 ps
CPU time 130.16 seconds
Started Jun 02 03:24:34 PM PDT 24
Finished Jun 02 03:26:44 PM PDT 24
Peak memory 259668 kb
Host smart-e30e38c7-06d8-4aec-a406-73b4fa002980
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825010776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ot
p_reset.825010776
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.1227998928
Short name T785
Test name
Test status
Simulation time 61650700 ps
CPU time 32.04 seconds
Started Jun 02 03:24:37 PM PDT 24
Finished Jun 02 03:25:09 PM PDT 24
Peak memory 274124 kb
Host smart-adae0d01-077a-4991-808d-ffbc7f71c075
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227998928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.1227998928
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.3070655629
Short name T933
Test name
Test status
Simulation time 49832400 ps
CPU time 31.83 seconds
Started Jun 02 03:24:36 PM PDT 24
Finished Jun 02 03:25:09 PM PDT 24
Peak memory 274404 kb
Host smart-31671a2f-289e-4738-ba35-24cebd312a3a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070655629 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.3070655629
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.3563346801
Short name T407
Test name
Test status
Simulation time 1537721900 ps
CPU time 56.73 seconds
Started Jun 02 03:24:34 PM PDT 24
Finished Jun 02 03:25:31 PM PDT 24
Peak memory 262908 kb
Host smart-96792153-e6c2-476f-a423-340dd2b6c9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563346801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.3563346801
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.434327072
Short name T1059
Test name
Test status
Simulation time 17772300 ps
CPU time 98.01 seconds
Started Jun 02 03:24:35 PM PDT 24
Finished Jun 02 03:26:14 PM PDT 24
Peak memory 276192 kb
Host smart-9d6d7ae9-feaa-4253-af3f-2ca022da6768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434327072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.434327072
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.808290417
Short name T440
Test name
Test status
Simulation time 148814000 ps
CPU time 13.55 seconds
Started Jun 02 03:24:41 PM PDT 24
Finished Jun 02 03:24:55 PM PDT 24
Peak memory 257876 kb
Host smart-05b9bba4-0d9d-42c7-97bc-474e6f9ec4bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808290417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.808290417
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.1517422544
Short name T489
Test name
Test status
Simulation time 151731300 ps
CPU time 13.48 seconds
Started Jun 02 03:24:41 PM PDT 24
Finished Jun 02 03:24:56 PM PDT 24
Peak memory 274732 kb
Host smart-cfd645f8-fc22-49d1-a9dd-9ea2f559b589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517422544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1517422544
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.1283352163
Short name T385
Test name
Test status
Simulation time 11717600 ps
CPU time 21.58 seconds
Started Jun 02 03:24:41 PM PDT 24
Finished Jun 02 03:25:04 PM PDT 24
Peak memory 279980 kb
Host smart-5107a188-c6c8-4c31-b470-57bc964cfbb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283352163 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.1283352163
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.2858488597
Short name T321
Test name
Test status
Simulation time 5513443900 ps
CPU time 94.91 seconds
Started Jun 02 03:24:35 PM PDT 24
Finished Jun 02 03:26:11 PM PDT 24
Peak memory 262356 kb
Host smart-9f68c756-917c-4f30-99da-d6ef3f43b6f6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858488597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.2858488597
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.1252328949
Short name T763
Test name
Test status
Simulation time 1477174400 ps
CPU time 194.18 seconds
Started Jun 02 03:24:33 PM PDT 24
Finished Jun 02 03:27:48 PM PDT 24
Peak memory 289476 kb
Host smart-ab4b4897-9039-42de-aa73-bae0efc232ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252328949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.1252328949
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.1640267976
Short name T551
Test name
Test status
Simulation time 12448480000 ps
CPU time 152.68 seconds
Started Jun 02 03:24:37 PM PDT 24
Finished Jun 02 03:27:10 PM PDT 24
Peak memory 292940 kb
Host smart-c67df314-56d5-4938-948c-6a23933fd2bd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640267976 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.1640267976
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.2129702591
Short name T132
Test name
Test status
Simulation time 78184200 ps
CPU time 112.24 seconds
Started Jun 02 03:24:36 PM PDT 24
Finished Jun 02 03:26:29 PM PDT 24
Peak memory 260960 kb
Host smart-e3956f47-5418-4778-a19b-f9457df69a1a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129702591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.2129702591
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.1291371268
Short name T622
Test name
Test status
Simulation time 37083300 ps
CPU time 30.52 seconds
Started Jun 02 03:24:35 PM PDT 24
Finished Jun 02 03:25:06 PM PDT 24
Peak memory 266976 kb
Host smart-396f37c0-d5f1-446e-bb45-219c5dcbb8ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291371268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.1291371268
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.1934610615
Short name T594
Test name
Test status
Simulation time 31776500 ps
CPU time 31.96 seconds
Started Jun 02 03:24:34 PM PDT 24
Finished Jun 02 03:25:07 PM PDT 24
Peak memory 274392 kb
Host smart-18867cd8-b8ab-4699-a32b-7db80b812d6a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934610615 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.1934610615
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.585252758
Short name T499
Test name
Test status
Simulation time 1113873000 ps
CPU time 65.66 seconds
Started Jun 02 03:24:41 PM PDT 24
Finished Jun 02 03:25:48 PM PDT 24
Peak memory 263008 kb
Host smart-b5cde00a-9698-4030-9826-a3b2bd41d467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585252758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.585252758
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.3243112678
Short name T426
Test name
Test status
Simulation time 75990300 ps
CPU time 167.55 seconds
Started Jun 02 03:24:37 PM PDT 24
Finished Jun 02 03:27:25 PM PDT 24
Peak memory 276424 kb
Host smart-fb3fcc62-b1c5-402e-8f6b-1cff76e85f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243112678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.3243112678
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.1591020632
Short name T517
Test name
Test status
Simulation time 73841500 ps
CPU time 13.72 seconds
Started Jun 02 03:24:44 PM PDT 24
Finished Jun 02 03:24:58 PM PDT 24
Peak memory 257852 kb
Host smart-97af353a-e393-49d7-9c0d-81c902fec47c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591020632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
1591020632
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.3559985832
Short name T415
Test name
Test status
Simulation time 43604700 ps
CPU time 13.5 seconds
Started Jun 02 03:24:41 PM PDT 24
Finished Jun 02 03:24:56 PM PDT 24
Peak memory 275944 kb
Host smart-e6943b00-33f8-43b8-9681-7adb6ae399b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559985832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.3559985832
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.984161496
Short name T389
Test name
Test status
Simulation time 14956000 ps
CPU time 22.26 seconds
Started Jun 02 03:24:41 PM PDT 24
Finished Jun 02 03:25:05 PM PDT 24
Peak memory 264880 kb
Host smart-77b8f4b0-f3fe-4ca3-972b-3eaf946c3c70
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984161496 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.984161496
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.128496692
Short name T513
Test name
Test status
Simulation time 2585622200 ps
CPU time 82.1 seconds
Started Jun 02 03:24:41 PM PDT 24
Finished Jun 02 03:26:04 PM PDT 24
Peak memory 262380 kb
Host smart-cc27fe36-2f5b-4bc5-9db3-6bee5edd274c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128496692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_h
w_sec_otp.128496692
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.1500446459
Short name T1012
Test name
Test status
Simulation time 1406559000 ps
CPU time 166.63 seconds
Started Jun 02 03:24:42 PM PDT 24
Finished Jun 02 03:27:30 PM PDT 24
Peak memory 293820 kb
Host smart-dd51d4cd-b84c-41a1-a045-9255db78c9e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500446459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_intr_rd.1500446459
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3942615376
Short name T955
Test name
Test status
Simulation time 14781536100 ps
CPU time 156.49 seconds
Started Jun 02 03:24:41 PM PDT 24
Finished Jun 02 03:27:19 PM PDT 24
Peak memory 292836 kb
Host smart-ac28cc11-6bc9-4b70-ae51-09cc801c74c1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942615376 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.3942615376
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.1826485684
Short name T606
Test name
Test status
Simulation time 495646200 ps
CPU time 131.94 seconds
Started Jun 02 03:24:43 PM PDT 24
Finished Jun 02 03:26:56 PM PDT 24
Peak memory 260984 kb
Host smart-b43916bd-2702-4575-b845-ed372b8a13d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826485684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.1826485684
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.4135892931
Short name T187
Test name
Test status
Simulation time 49045500 ps
CPU time 31.94 seconds
Started Jun 02 03:25:20 PM PDT 24
Finished Jun 02 03:25:53 PM PDT 24
Peak memory 274464 kb
Host smart-d749f158-0d2d-4427-aaec-02ba56f1edac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135892931 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.4135892931
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.2205129594
Short name T422
Test name
Test status
Simulation time 8558344700 ps
CPU time 78.3 seconds
Started Jun 02 03:24:43 PM PDT 24
Finished Jun 02 03:26:02 PM PDT 24
Peak memory 262920 kb
Host smart-ebb60390-2afa-4d04-a07f-bffc22d168f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205129594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.2205129594
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.3751500107
Short name T492
Test name
Test status
Simulation time 49937800 ps
CPU time 99.91 seconds
Started Jun 02 03:24:41 PM PDT 24
Finished Jun 02 03:26:22 PM PDT 24
Peak memory 274956 kb
Host smart-484b5f38-8c68-42b3-afd3-d42a1c7376da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751500107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.3751500107
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.3665515246
Short name T712
Test name
Test status
Simulation time 177212700 ps
CPU time 13.93 seconds
Started Jun 02 03:24:48 PM PDT 24
Finished Jun 02 03:25:03 PM PDT 24
Peak memory 264816 kb
Host smart-c2fedede-4e1e-46f4-9431-f65a668d1cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665515246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
3665515246
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.3283741841
Short name T382
Test name
Test status
Simulation time 14152600 ps
CPU time 15.54 seconds
Started Jun 02 03:24:48 PM PDT 24
Finished Jun 02 03:25:04 PM PDT 24
Peak memory 275888 kb
Host smart-51a3574a-f931-4d8b-90f3-6540455e1549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283741841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3283741841
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.4002628042
Short name T375
Test name
Test status
Simulation time 26240600 ps
CPU time 21.66 seconds
Started Jun 02 03:24:46 PM PDT 24
Finished Jun 02 03:25:09 PM PDT 24
Peak memory 273148 kb
Host smart-35e4a6a7-14a6-4459-b57c-912aead5cbb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002628042 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.4002628042
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.3885235995
Short name T634
Test name
Test status
Simulation time 4914903300 ps
CPU time 203.3 seconds
Started Jun 02 03:24:47 PM PDT 24
Finished Jun 02 03:28:11 PM PDT 24
Peak memory 262396 kb
Host smart-7a28f878-71b7-4ba1-ba4b-859b8e292ab0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885235995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.3885235995
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.2972415042
Short name T26
Test name
Test status
Simulation time 1515909300 ps
CPU time 237.88 seconds
Started Jun 02 03:24:47 PM PDT 24
Finished Jun 02 03:28:46 PM PDT 24
Peak memory 289448 kb
Host smart-841eb07c-8209-4e34-8b07-434cb8bbacc7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972415042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.2972415042
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.2650693720
Short name T1023
Test name
Test status
Simulation time 23349221800 ps
CPU time 299.43 seconds
Started Jun 02 03:24:46 PM PDT 24
Finished Jun 02 03:29:46 PM PDT 24
Peak memory 292800 kb
Host smart-f144fbe2-762b-4262-9f76-e83147f7e01a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650693720 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.2650693720
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.3729402457
Short name T623
Test name
Test status
Simulation time 75964800 ps
CPU time 133.03 seconds
Started Jun 02 03:24:45 PM PDT 24
Finished Jun 02 03:26:58 PM PDT 24
Peak memory 264112 kb
Host smart-2a4e7a20-5f95-47cf-9660-c758f5e9c277
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729402457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.3729402457
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.3350932511
Short name T966
Test name
Test status
Simulation time 49055100 ps
CPU time 30.38 seconds
Started Jun 02 03:24:47 PM PDT 24
Finished Jun 02 03:25:18 PM PDT 24
Peak memory 273152 kb
Host smart-7e0827e4-c6f8-4b49-9a11-3ed39b38a859
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350932511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.3350932511
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.4139399095
Short name T285
Test name
Test status
Simulation time 32090400 ps
CPU time 31.3 seconds
Started Jun 02 03:24:46 PM PDT 24
Finished Jun 02 03:25:18 PM PDT 24
Peak memory 274476 kb
Host smart-747d9b9f-8f5a-474c-a446-8548a6824165
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139399095 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.4139399095
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.101571211
Short name T593
Test name
Test status
Simulation time 11896137600 ps
CPU time 84.6 seconds
Started Jun 02 03:24:45 PM PDT 24
Finished Jun 02 03:26:10 PM PDT 24
Peak memory 262728 kb
Host smart-66aad922-5186-4315-a912-e3755c831e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101571211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.101571211
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.2076209678
Short name T543
Test name
Test status
Simulation time 57109300 ps
CPU time 97.92 seconds
Started Jun 02 03:24:48 PM PDT 24
Finished Jun 02 03:26:27 PM PDT 24
Peak memory 276032 kb
Host smart-2e0537bb-dc26-4355-882f-6d24568d2500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076209678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2076209678
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.2159759713
Short name T650
Test name
Test status
Simulation time 87671200 ps
CPU time 13.75 seconds
Started Jun 02 03:24:54 PM PDT 24
Finished Jun 02 03:25:08 PM PDT 24
Peak memory 257776 kb
Host smart-8370e4da-b50c-4941-ae77-f3ba3813013e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159759713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
2159759713
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.3445351360
Short name T540
Test name
Test status
Simulation time 102670900 ps
CPU time 15.77 seconds
Started Jun 02 03:24:55 PM PDT 24
Finished Jun 02 03:25:12 PM PDT 24
Peak memory 275556 kb
Host smart-2fe2c14e-3317-46ba-9701-c78c7dff88cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445351360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.3445351360
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.612893425
Short name T940
Test name
Test status
Simulation time 16793800 ps
CPU time 21.97 seconds
Started Jun 02 03:24:51 PM PDT 24
Finished Jun 02 03:25:14 PM PDT 24
Peak memory 273132 kb
Host smart-9f57cb68-9483-430f-be1b-67e1215423b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612893425 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.612893425
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.3941481663
Short name T476
Test name
Test status
Simulation time 1648075300 ps
CPU time 82.71 seconds
Started Jun 02 03:24:50 PM PDT 24
Finished Jun 02 03:26:14 PM PDT 24
Peak memory 262208 kb
Host smart-47209aec-0fed-4459-a859-342b8530cb8b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941481663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.3941481663
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.2139217919
Short name T358
Test name
Test status
Simulation time 2660460800 ps
CPU time 139.81 seconds
Started Jun 02 03:24:52 PM PDT 24
Finished Jun 02 03:27:13 PM PDT 24
Peak memory 292628 kb
Host smart-f4a3f2f1-aa8a-46c7-a5ff-50bd6cf17c08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139217919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.2139217919
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.3233558785
Short name T241
Test name
Test status
Simulation time 23328683700 ps
CPU time 156.35 seconds
Started Jun 02 03:24:50 PM PDT 24
Finished Jun 02 03:27:27 PM PDT 24
Peak memory 291612 kb
Host smart-ddcb8735-e54a-4a2a-ba06-870d76f349e2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233558785 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.3233558785
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.2065948734
Short name T617
Test name
Test status
Simulation time 131636400 ps
CPU time 133.88 seconds
Started Jun 02 03:24:51 PM PDT 24
Finished Jun 02 03:27:06 PM PDT 24
Peak memory 259596 kb
Host smart-1398705d-85bc-4452-bdc5-5ac2b241c670
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065948734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.2065948734
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.2513182739
Short name T787
Test name
Test status
Simulation time 29870600 ps
CPU time 30.83 seconds
Started Jun 02 03:24:51 PM PDT 24
Finished Jun 02 03:25:23 PM PDT 24
Peak memory 272996 kb
Host smart-388f6de0-2f8b-4ccb-9641-23100a1183db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513182739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.2513182739
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.2673349016
Short name T967
Test name
Test status
Simulation time 74538000 ps
CPU time 31.91 seconds
Started Jun 02 03:24:51 PM PDT 24
Finished Jun 02 03:25:24 PM PDT 24
Peak memory 269052 kb
Host smart-58318f7b-d3eb-4a86-83d2-1731b49ac673
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673349016 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.2673349016
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.3580664890
Short name T381
Test name
Test status
Simulation time 648818100 ps
CPU time 69.94 seconds
Started Jun 02 03:24:50 PM PDT 24
Finished Jun 02 03:26:01 PM PDT 24
Peak memory 262916 kb
Host smart-4b31201a-5a79-449b-acd9-8c145159b10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580664890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.3580664890
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.3964391714
Short name T610
Test name
Test status
Simulation time 89132500 ps
CPU time 76.94 seconds
Started Jun 02 03:24:46 PM PDT 24
Finished Jun 02 03:26:03 PM PDT 24
Peak memory 274768 kb
Host smart-53fabffd-5034-49da-bcb3-e5480655fba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964391714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.3964391714
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.3218216064
Short name T939
Test name
Test status
Simulation time 42857400 ps
CPU time 13.76 seconds
Started Jun 02 03:25:01 PM PDT 24
Finished Jun 02 03:25:16 PM PDT 24
Peak memory 264812 kb
Host smart-d4aa0455-5d02-44a6-b4c4-3d2a8a40b652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218216064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
3218216064
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.3208385202
Short name T970
Test name
Test status
Simulation time 40172600 ps
CPU time 15.65 seconds
Started Jun 02 03:25:02 PM PDT 24
Finished Jun 02 03:25:18 PM PDT 24
Peak memory 275860 kb
Host smart-f904da57-7f83-43d1-8ebb-abb45c28eb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208385202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.3208385202
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.3542707188
Short name T640
Test name
Test status
Simulation time 15422100 ps
CPU time 22.06 seconds
Started Jun 02 03:24:56 PM PDT 24
Finished Jun 02 03:25:18 PM PDT 24
Peak memory 273264 kb
Host smart-6a66575c-fbf2-44a4-9d1e-7d006c9e2984
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542707188 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.3542707188
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.3338017934
Short name T588
Test name
Test status
Simulation time 4506850700 ps
CPU time 132.71 seconds
Started Jun 02 03:24:57 PM PDT 24
Finished Jun 02 03:27:10 PM PDT 24
Peak memory 262248 kb
Host smart-d676ebb8-b805-4cf5-ba1d-0bffb9b373db
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338017934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.3338017934
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.4224276996
Short name T360
Test name
Test status
Simulation time 9361470500 ps
CPU time 173.03 seconds
Started Jun 02 03:24:57 PM PDT 24
Finished Jun 02 03:27:51 PM PDT 24
Peak memory 292852 kb
Host smart-bf620851-c3a2-4613-b17a-8a88c5180478
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224276996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.4224276996
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.2530242192
Short name T583
Test name
Test status
Simulation time 11763230500 ps
CPU time 242.73 seconds
Started Jun 02 03:24:57 PM PDT 24
Finished Jun 02 03:29:00 PM PDT 24
Peak memory 291752 kb
Host smart-46e9b9e3-fda7-4aa4-983c-8cf5f583c191
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530242192 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.2530242192
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.3506087068
Short name T863
Test name
Test status
Simulation time 38589100 ps
CPU time 131.12 seconds
Started Jun 02 03:24:58 PM PDT 24
Finished Jun 02 03:27:09 PM PDT 24
Peak memory 259728 kb
Host smart-01f855e0-5796-4ef6-9679-e7841d6a0e87
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506087068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.3506087068
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.891940387
Short name T950
Test name
Test status
Simulation time 44358500 ps
CPU time 30.95 seconds
Started Jun 02 03:24:58 PM PDT 24
Finished Jun 02 03:25:30 PM PDT 24
Peak memory 274420 kb
Host smart-d1a513bb-c9b5-4bc0-b1bf-1cb66e9e541a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891940387 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.891940387
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.1995694850
Short name T398
Test name
Test status
Simulation time 4951621300 ps
CPU time 69.21 seconds
Started Jun 02 03:25:02 PM PDT 24
Finished Jun 02 03:26:12 PM PDT 24
Peak memory 262840 kb
Host smart-17a10f45-2759-41d3-95e1-b0608e29e94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995694850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.1995694850
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.1745329830
Short name T555
Test name
Test status
Simulation time 29357900 ps
CPU time 75.57 seconds
Started Jun 02 03:24:57 PM PDT 24
Finished Jun 02 03:26:14 PM PDT 24
Peak memory 275928 kb
Host smart-e7640dfd-0e31-4da7-95e4-08498661c392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745329830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.1745329830
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.3371186533
Short name T668
Test name
Test status
Simulation time 42607600 ps
CPU time 13.52 seconds
Started Jun 02 03:25:01 PM PDT 24
Finished Jun 02 03:25:16 PM PDT 24
Peak memory 264836 kb
Host smart-056a4eac-20c2-4b0a-8200-38e9073d0219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371186533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
3371186533
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.825868974
Short name T794
Test name
Test status
Simulation time 14524300 ps
CPU time 15.72 seconds
Started Jun 02 03:25:02 PM PDT 24
Finished Jun 02 03:25:18 PM PDT 24
Peak memory 275864 kb
Host smart-1dedcda7-52c2-46eb-8e15-ca49336f6ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825868974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.825868974
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.2274016553
Short name T798
Test name
Test status
Simulation time 39103000 ps
CPU time 20.29 seconds
Started Jun 02 03:25:00 PM PDT 24
Finished Jun 02 03:25:21 PM PDT 24
Peak memory 273164 kb
Host smart-7ab034ae-f907-4b4a-832d-91844f654890
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274016553 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.2274016553
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.3202503920
Short name T411
Test name
Test status
Simulation time 14840147600 ps
CPU time 114.34 seconds
Started Jun 02 03:25:03 PM PDT 24
Finished Jun 02 03:26:58 PM PDT 24
Peak memory 262404 kb
Host smart-e4ada231-fd8b-4d41-b093-ed71977fc3f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202503920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.3202503920
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.2607373064
Short name T33
Test name
Test status
Simulation time 851765700 ps
CPU time 115.82 seconds
Started Jun 02 03:24:59 PM PDT 24
Finished Jun 02 03:26:56 PM PDT 24
Peak memory 292720 kb
Host smart-1adf4797-7873-47e9-b5ed-bd30d1499748
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607373064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.2607373064
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.2398285881
Short name T1062
Test name
Test status
Simulation time 37695400 ps
CPU time 131.06 seconds
Started Jun 02 03:25:01 PM PDT 24
Finished Jun 02 03:27:13 PM PDT 24
Peak memory 263928 kb
Host smart-56ba9cea-fa13-4fd7-8342-4770315807e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398285881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.2398285881
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.1162711430
Short name T980
Test name
Test status
Simulation time 27050300 ps
CPU time 30.73 seconds
Started Jun 02 03:25:03 PM PDT 24
Finished Jun 02 03:25:35 PM PDT 24
Peak memory 268448 kb
Host smart-33390f16-bc32-44c6-9284-e4cc2048d229
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162711430 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.1162711430
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.4025612397
Short name T396
Test name
Test status
Simulation time 1311215400 ps
CPU time 67.56 seconds
Started Jun 02 03:25:01 PM PDT 24
Finished Jun 02 03:26:09 PM PDT 24
Peak memory 263044 kb
Host smart-3b14f72a-9b71-42a8-b090-1c65c0a5e64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025612397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.4025612397
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.3874368176
Short name T992
Test name
Test status
Simulation time 40434000 ps
CPU time 98.4 seconds
Started Jun 02 03:25:00 PM PDT 24
Finished Jun 02 03:26:39 PM PDT 24
Peak memory 276376 kb
Host smart-1adbc8a8-4437-435e-bb71-6a5e990d71ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874368176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.3874368176
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.1442556838
Short name T1030
Test name
Test status
Simulation time 239787700 ps
CPU time 13.99 seconds
Started Jun 02 03:20:05 PM PDT 24
Finished Jun 02 03:20:20 PM PDT 24
Peak memory 263860 kb
Host smart-6d0627a6-db26-4bc2-841e-441c96b94c80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442556838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.1
442556838
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.871850306
Short name T373
Test name
Test status
Simulation time 117424200 ps
CPU time 13.78 seconds
Started Jun 02 03:19:58 PM PDT 24
Finished Jun 02 03:20:13 PM PDT 24
Peak memory 264788 kb
Host smart-07656e5e-b701-407d-bc68-28f90c6a42d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871850306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
flash_ctrl_config_regwen.871850306
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.430116134
Short name T875
Test name
Test status
Simulation time 54510100 ps
CPU time 15.42 seconds
Started Jun 02 03:20:00 PM PDT 24
Finished Jun 02 03:20:16 PM PDT 24
Peak memory 275784 kb
Host smart-a2523891-9fdb-412a-998d-4e2a3b628a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430116134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.430116134
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.2813611111
Short name T362
Test name
Test status
Simulation time 318618300 ps
CPU time 103.28 seconds
Started Jun 02 03:19:53 PM PDT 24
Finished Jun 02 03:21:37 PM PDT 24
Peak memory 281276 kb
Host smart-b249dbb5-716b-4c32-b78f-14a2a88fe0ba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813611111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.2813611111
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.561605255
Short name T379
Test name
Test status
Simulation time 68738100 ps
CPU time 20.86 seconds
Started Jun 02 03:19:58 PM PDT 24
Finished Jun 02 03:20:19 PM PDT 24
Peak memory 264896 kb
Host smart-34b9ec43-fe0d-42af-8fec-13b05fb39412
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561605255 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.561605255
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.2338078266
Short name T332
Test name
Test status
Simulation time 3524923300 ps
CPU time 297.96 seconds
Started Jun 02 03:19:40 PM PDT 24
Finished Jun 02 03:24:39 PM PDT 24
Peak memory 261024 kb
Host smart-ef394161-4304-4fa4-986a-14b37cdbda9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2338078266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2338078266
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.2448708525
Short name T811
Test name
Test status
Simulation time 8641069100 ps
CPU time 2650.01 seconds
Started Jun 02 03:19:45 PM PDT 24
Finished Jun 02 04:03:56 PM PDT 24
Peak memory 264296 kb
Host smart-dd02dd46-037b-40b9-82e8-9c505fea19c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448708525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.2448708525
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.3359434492
Short name T171
Test name
Test status
Simulation time 1562066300 ps
CPU time 2382.08 seconds
Started Jun 02 03:19:45 PM PDT 24
Finished Jun 02 03:59:28 PM PDT 24
Peak memory 263896 kb
Host smart-0b242105-b48a-40df-a1f5-1a0a4adb80cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359434492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.3359434492
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.199285132
Short name T689
Test name
Test status
Simulation time 3186110600 ps
CPU time 1034.68 seconds
Started Jun 02 03:19:44 PM PDT 24
Finished Jun 02 03:37:00 PM PDT 24
Peak memory 273024 kb
Host smart-1cd77cea-4114-4119-8a37-c5188e8670f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199285132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.199285132
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.561668433
Short name T48
Test name
Test status
Simulation time 725678400 ps
CPU time 23.59 seconds
Started Jun 02 03:19:41 PM PDT 24
Finished Jun 02 03:20:05 PM PDT 24
Peak memory 264888 kb
Host smart-745a23f4-bcf1-40cb-9cba-c86c783da019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561668433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.561668433
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.2337305843
Short name T484
Test name
Test status
Simulation time 1385919700 ps
CPU time 39.01 seconds
Started Jun 02 03:20:00 PM PDT 24
Finished Jun 02 03:20:40 PM PDT 24
Peak memory 264808 kb
Host smart-7b256fe8-39cd-4f24-a907-292a54fe0606
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337305843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.2337305843
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.4137494604
Short name T924
Test name
Test status
Simulation time 78232139800 ps
CPU time 2862.77 seconds
Started Jun 02 03:19:46 PM PDT 24
Finished Jun 02 04:07:30 PM PDT 24
Peak memory 261784 kb
Host smart-e7390acc-110f-4ab0-b653-2a273cdb6064
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137494604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.4137494604
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.3230580571
Short name T989
Test name
Test status
Simulation time 572034063700 ps
CPU time 1995.68 seconds
Started Jun 02 03:19:39 PM PDT 24
Finished Jun 02 03:52:55 PM PDT 24
Peak memory 264776 kb
Host smart-4dea39b5-3e29-4648-a93c-16bd61d5dff8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230580571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.3230580571
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.381784114
Short name T589
Test name
Test status
Simulation time 432796500 ps
CPU time 103.07 seconds
Started Jun 02 03:19:41 PM PDT 24
Finished Jun 02 03:21:24 PM PDT 24
Peak memory 262260 kb
Host smart-ac27bf69-fd7a-4882-a6cf-71e213a9d45f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=381784114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.381784114
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1741866724
Short name T677
Test name
Test status
Simulation time 10012993600 ps
CPU time 119.29 seconds
Started Jun 02 03:19:58 PM PDT 24
Finished Jun 02 03:21:58 PM PDT 24
Peak memory 340432 kb
Host smart-4766d4fb-4344-4085-bc3f-ccfb2c893fca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741866724 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1741866724
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.1320898389
Short name T124
Test name
Test status
Simulation time 160176745500 ps
CPU time 960.6 seconds
Started Jun 02 03:19:42 PM PDT 24
Finished Jun 02 03:35:43 PM PDT 24
Peak memory 263100 kb
Host smart-90822fe7-a2c7-4124-866c-1e67be4217c0
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320898389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.1320898389
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.2699622817
Short name T243
Test name
Test status
Simulation time 3628349200 ps
CPU time 237.12 seconds
Started Jun 02 03:19:39 PM PDT 24
Finished Jun 02 03:23:36 PM PDT 24
Peak memory 261800 kb
Host smart-062debcb-3753-40a9-8669-bae298eabb39
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699622817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.2699622817
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.3602590188
Short name T249
Test name
Test status
Simulation time 3496889600 ps
CPU time 590.89 seconds
Started Jun 02 03:19:53 PM PDT 24
Finished Jun 02 03:29:45 PM PDT 24
Peak memory 331904 kb
Host smart-79b51a51-b3a3-4a41-a25d-84fad9c93bb8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602590188 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.3602590188
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.2398932942
Short name T776
Test name
Test status
Simulation time 6629557800 ps
CPU time 151.86 seconds
Started Jun 02 03:19:52 PM PDT 24
Finished Jun 02 03:22:24 PM PDT 24
Peak memory 293840 kb
Host smart-07b1b65b-a41c-4808-b5c5-8dc02fac93e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398932942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.2398932942
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.2826134676
Short name T158
Test name
Test status
Simulation time 25178724100 ps
CPU time 138.77 seconds
Started Jun 02 03:19:53 PM PDT 24
Finished Jun 02 03:22:12 PM PDT 24
Peak memory 293016 kb
Host smart-97081e30-bf43-46b0-82bb-d5458246f207
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826134676 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.2826134676
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.2944240578
Short name T965
Test name
Test status
Simulation time 8033008100 ps
CPU time 70.17 seconds
Started Jun 02 03:19:53 PM PDT 24
Finished Jun 02 03:21:04 PM PDT 24
Peak memory 264860 kb
Host smart-94d10ac2-40f6-423f-abb9-330e0efb21e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944240578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.2944240578
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1404779950
Short name T674
Test name
Test status
Simulation time 72116627300 ps
CPU time 211.31 seconds
Started Jun 02 03:19:52 PM PDT 24
Finished Jun 02 03:23:24 PM PDT 24
Peak memory 260088 kb
Host smart-08b96004-5cc9-4750-a39e-4d908fbed8ef
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140
4779950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.1404779950
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.1047851763
Short name T639
Test name
Test status
Simulation time 4851790800 ps
CPU time 92.3 seconds
Started Jun 02 03:19:45 PM PDT 24
Finished Jun 02 03:21:18 PM PDT 24
Peak memory 259524 kb
Host smart-77a2e64e-9bd0-4f9d-8c90-072f8ce6db63
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047851763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.1047851763
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.687334707
Short name T121
Test name
Test status
Simulation time 15655300 ps
CPU time 13.74 seconds
Started Jun 02 03:20:00 PM PDT 24
Finished Jun 02 03:20:14 PM PDT 24
Peak memory 260152 kb
Host smart-5650a110-35da-4045-b40b-baac8c9ad493
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687334707 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.687334707
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.1220176072
Short name T66
Test name
Test status
Simulation time 645686000 ps
CPU time 72.66 seconds
Started Jun 02 03:19:47 PM PDT 24
Finished Jun 02 03:21:00 PM PDT 24
Peak memory 259724 kb
Host smart-4ed0225f-e244-4658-be60-071a63f32cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220176072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.1220176072
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.1507531628
Short name T760
Test name
Test status
Simulation time 12165700000 ps
CPU time 212.17 seconds
Started Jun 02 03:19:39 PM PDT 24
Finished Jun 02 03:23:12 PM PDT 24
Peak memory 262532 kb
Host smart-6d5974e2-ab21-4a19-9630-5d85aaf0c80e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507531628 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_mp_regions.1507531628
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.4092314186
Short name T525
Test name
Test status
Simulation time 86887800 ps
CPU time 134.28 seconds
Started Jun 02 03:19:39 PM PDT 24
Finished Jun 02 03:21:54 PM PDT 24
Peak memory 259956 kb
Host smart-a423c0f8-5224-408b-ba1c-60463da219ad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092314186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.4092314186
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.2527756326
Short name T58
Test name
Test status
Simulation time 44028000 ps
CPU time 14.14 seconds
Started Jun 02 03:19:58 PM PDT 24
Finished Jun 02 03:20:13 PM PDT 24
Peak memory 276344 kb
Host smart-ae305b6d-c8e3-4d86-80bd-51757540eda5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2527756326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2527756326
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.349862283
Short name T812
Test name
Test status
Simulation time 341898900 ps
CPU time 389.01 seconds
Started Jun 02 03:19:39 PM PDT 24
Finished Jun 02 03:26:09 PM PDT 24
Peak memory 262100 kb
Host smart-3fbd51e5-1086-43b9-af0b-e24b3f63ad99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349862283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.349862283
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.4012900427
Short name T79
Test name
Test status
Simulation time 916452300 ps
CPU time 20.2 seconds
Started Jun 02 03:19:57 PM PDT 24
Finished Jun 02 03:20:18 PM PDT 24
Peak memory 263104 kb
Host smart-53282273-160d-4246-8cd5-bc378f108f9e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012900427 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.4012900427
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.3174737931
Short name T1035
Test name
Test status
Simulation time 55760600 ps
CPU time 297.57 seconds
Started Jun 02 03:19:43 PM PDT 24
Finished Jun 02 03:24:41 PM PDT 24
Peak memory 281236 kb
Host smart-4bd205ca-2f69-454d-9346-1cd31315d813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174737931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.3174737931
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2634663812
Short name T62
Test name
Test status
Simulation time 85272700 ps
CPU time 99.25 seconds
Started Jun 02 03:19:41 PM PDT 24
Finished Jun 02 03:21:21 PM PDT 24
Peak memory 264956 kb
Host smart-0fb84330-6f7b-4a3a-b68b-33ecc6d54208
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2634663812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2634663812
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.2889505314
Short name T897
Test name
Test status
Simulation time 98660100 ps
CPU time 35.54 seconds
Started Jun 02 03:20:00 PM PDT 24
Finished Jun 02 03:20:36 PM PDT 24
Peak memory 273108 kb
Host smart-8c490f00-d0a7-47af-b8a5-4c6c665f9beb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889505314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.2889505314
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.3751759035
Short name T625
Test name
Test status
Simulation time 32950000 ps
CPU time 23.09 seconds
Started Jun 02 03:19:52 PM PDT 24
Finished Jun 02 03:20:16 PM PDT 24
Peak memory 264820 kb
Host smart-0a7dbf2f-a874-4453-9ecd-0969e8d9fd33
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751759035 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.3751759035
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.3220944667
Short name T413
Test name
Test status
Simulation time 57043300 ps
CPU time 22.36 seconds
Started Jun 02 03:19:44 PM PDT 24
Finished Jun 02 03:20:07 PM PDT 24
Peak memory 264796 kb
Host smart-c9b1459b-fb03-4931-ba5d-fe33b4de60f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220944667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.3220944667
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.2762820189
Short name T521
Test name
Test status
Simulation time 526825200 ps
CPU time 141.57 seconds
Started Jun 02 03:19:47 PM PDT 24
Finished Jun 02 03:22:09 PM PDT 24
Peak memory 288880 kb
Host smart-3959793d-a241-4d03-ab9f-5632ffbbb3e2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762820189 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_ro.2762820189
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.1679619890
Short name T255
Test name
Test status
Simulation time 535373500 ps
CPU time 127.95 seconds
Started Jun 02 03:19:52 PM PDT 24
Finished Jun 02 03:22:01 PM PDT 24
Peak memory 281220 kb
Host smart-068566db-0d6c-4eee-b49a-e70f23911bf3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1679619890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.1679619890
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.3717198285
Short name T549
Test name
Test status
Simulation time 1259999300 ps
CPU time 145.88 seconds
Started Jun 02 03:19:47 PM PDT 24
Finished Jun 02 03:22:13 PM PDT 24
Peak memory 294040 kb
Host smart-fef550db-2fa7-4552-983f-5ab0127c3073
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717198285 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.3717198285
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.3240603563
Short name T740
Test name
Test status
Simulation time 3506939400 ps
CPU time 585.97 seconds
Started Jun 02 03:19:45 PM PDT 24
Finished Jun 02 03:29:32 PM PDT 24
Peak memory 314056 kb
Host smart-90eae0f2-b89f-4846-b614-76733973ef41
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240603563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_rw.3240603563
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.2418658504
Short name T342
Test name
Test status
Simulation time 134935000 ps
CPU time 28.14 seconds
Started Jun 02 03:19:54 PM PDT 24
Finished Jun 02 03:20:23 PM PDT 24
Peak memory 274204 kb
Host smart-aece8f69-5b64-4c71-91db-2756c5c40e19
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418658504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_rw_evict.2418658504
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.1808177265
Short name T561
Test name
Test status
Simulation time 81852100 ps
CPU time 28.24 seconds
Started Jun 02 03:19:58 PM PDT 24
Finished Jun 02 03:20:27 PM PDT 24
Peak memory 268784 kb
Host smart-79ccb1e9-d9f8-4391-98c1-245e2c523590
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808177265 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.1808177265
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.309409944
Short name T544
Test name
Test status
Simulation time 11052114700 ps
CPU time 529.42 seconds
Started Jun 02 03:19:45 PM PDT 24
Finished Jun 02 03:28:36 PM PDT 24
Peak memory 311956 kb
Host smart-d86e61a9-ec81-47f2-ac7c-4fb27d21eaea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309409944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_se
rr.309409944
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.3995838076
Short name T685
Test name
Test status
Simulation time 588062200 ps
CPU time 62.14 seconds
Started Jun 02 03:19:58 PM PDT 24
Finished Jun 02 03:21:01 PM PDT 24
Peak memory 264296 kb
Host smart-1f94137c-ce3e-464b-9db9-125e8b056f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995838076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.3995838076
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.1195482407
Short name T782
Test name
Test status
Simulation time 916002100 ps
CPU time 85.35 seconds
Started Jun 02 03:19:48 PM PDT 24
Finished Jun 02 03:21:14 PM PDT 24
Peak memory 264900 kb
Host smart-80b8f6d6-505e-4ea8-ae7f-a729c12357fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195482407 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.1195482407
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.3894596193
Short name T883
Test name
Test status
Simulation time 1530402500 ps
CPU time 86.5 seconds
Started Jun 02 03:19:45 PM PDT 24
Finished Jun 02 03:21:13 PM PDT 24
Peak memory 265000 kb
Host smart-8cce4b0c-60cd-41ea-aa53-8eea4856b2d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894596193 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_serr_counter.3894596193
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.2116162854
Short name T7
Test name
Test status
Simulation time 56891300 ps
CPU time 192.17 seconds
Started Jun 02 03:19:40 PM PDT 24
Finished Jun 02 03:22:53 PM PDT 24
Peak memory 280064 kb
Host smart-b5dcf4c9-4ddb-49e7-9157-2496aedf31cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116162854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.2116162854
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.1609945440
Short name T220
Test name
Test status
Simulation time 25531800 ps
CPU time 24.14 seconds
Started Jun 02 03:19:39 PM PDT 24
Finished Jun 02 03:20:03 PM PDT 24
Peak memory 258840 kb
Host smart-b9f49157-69c6-41f6-b606-528a42f6887c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609945440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.1609945440
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.3112765886
Short name T844
Test name
Test status
Simulation time 143093300 ps
CPU time 235.56 seconds
Started Jun 02 03:20:01 PM PDT 24
Finished Jun 02 03:23:57 PM PDT 24
Peak memory 281308 kb
Host smart-a728cb86-5c56-40b5-9b06-f203c62f801e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112765886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.3112765886
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.2472185277
Short name T852
Test name
Test status
Simulation time 23267700 ps
CPU time 24.17 seconds
Started Jun 02 03:19:39 PM PDT 24
Finished Jun 02 03:20:04 PM PDT 24
Peak memory 261388 kb
Host smart-4ccc9633-50ed-4eb1-8392-996ec3d0f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472185277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2472185277
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.2044424294
Short name T643
Test name
Test status
Simulation time 3358397800 ps
CPU time 219.52 seconds
Started Jun 02 03:19:45 PM PDT 24
Finished Jun 02 03:23:25 PM PDT 24
Peak memory 264784 kb
Host smart-a9802abd-6d58-469f-9c21-d8f0166f1503
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044424294 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_wo.2044424294
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.3372157217
Short name T686
Test name
Test status
Simulation time 95715200 ps
CPU time 13.98 seconds
Started Jun 02 03:25:06 PM PDT 24
Finished Jun 02 03:25:20 PM PDT 24
Peak memory 257820 kb
Host smart-0e5c7439-1fd9-408d-968c-d3979acfa870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372157217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
3372157217
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.1408582397
Short name T1072
Test name
Test status
Simulation time 15028200 ps
CPU time 13.11 seconds
Started Jun 02 03:25:06 PM PDT 24
Finished Jun 02 03:25:19 PM PDT 24
Peak memory 275940 kb
Host smart-10ffa25f-383c-499a-b631-6ae0db042bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408582397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.1408582397
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.3828988104
Short name T149
Test name
Test status
Simulation time 34517900 ps
CPU time 21.89 seconds
Started Jun 02 03:25:06 PM PDT 24
Finished Jun 02 03:25:28 PM PDT 24
Peak memory 273168 kb
Host smart-84ca8665-e243-440c-8f96-6869ffef7f26
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828988104 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.3828988104
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.633055359
Short name T1003
Test name
Test status
Simulation time 4458132700 ps
CPU time 101.91 seconds
Started Jun 02 03:25:01 PM PDT 24
Finished Jun 02 03:26:44 PM PDT 24
Peak memory 262356 kb
Host smart-66ce5a60-79f3-4a95-92b4-564762bb472e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633055359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_h
w_sec_otp.633055359
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.2232968394
Short name T709
Test name
Test status
Simulation time 38203300 ps
CPU time 131.23 seconds
Started Jun 02 03:25:02 PM PDT 24
Finished Jun 02 03:27:14 PM PDT 24
Peak memory 259740 kb
Host smart-84f3137d-de70-48ad-8a0c-818b088ed512
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232968394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.2232968394
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.4040104144
Short name T743
Test name
Test status
Simulation time 1466719000 ps
CPU time 74.76 seconds
Started Jun 02 03:25:06 PM PDT 24
Finished Jun 02 03:26:22 PM PDT 24
Peak memory 262680 kb
Host smart-fcd513a8-cfb9-480c-9993-336a14d0e38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040104144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.4040104144
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.2277582356
Short name T235
Test name
Test status
Simulation time 64856800 ps
CPU time 121.52 seconds
Started Jun 02 03:25:00 PM PDT 24
Finished Jun 02 03:27:02 PM PDT 24
Peak memory 275276 kb
Host smart-eff4adc0-e5fd-49c3-89db-3ddb194ffd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277582356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2277582356
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.381705741
Short name T969
Test name
Test status
Simulation time 95002800 ps
CPU time 14.03 seconds
Started Jun 02 03:25:14 PM PDT 24
Finished Jun 02 03:25:28 PM PDT 24
Peak memory 264764 kb
Host smart-2b3069bf-21aa-4ef1-96c8-c0f7119f072a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381705741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.381705741
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.891185272
Short name T813
Test name
Test status
Simulation time 49603600 ps
CPU time 16.04 seconds
Started Jun 02 03:25:13 PM PDT 24
Finished Jun 02 03:25:30 PM PDT 24
Peak memory 275856 kb
Host smart-37ca85a9-64fd-46c6-bbc7-dc74a2e3576c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891185272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.891185272
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.3507664961
Short name T681
Test name
Test status
Simulation time 11057200 ps
CPU time 21.93 seconds
Started Jun 02 03:25:12 PM PDT 24
Finished Jun 02 03:25:34 PM PDT 24
Peak memory 273404 kb
Host smart-720abf2f-8855-4094-ad2e-0cca7c342197
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507664961 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.3507664961
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.2604047238
Short name T1077
Test name
Test status
Simulation time 13862297800 ps
CPU time 222.23 seconds
Started Jun 02 03:25:06 PM PDT 24
Finished Jun 02 03:28:49 PM PDT 24
Peak memory 262232 kb
Host smart-f5af7a7e-d79f-4f43-bea1-6230d367f20d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604047238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.2604047238
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.2511402692
Short name T1049
Test name
Test status
Simulation time 57968800 ps
CPU time 130.28 seconds
Started Jun 02 03:25:07 PM PDT 24
Finished Jun 02 03:27:18 PM PDT 24
Peak memory 259480 kb
Host smart-60fa2637-f0ab-447f-bda7-9fa77c414af9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511402692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.2511402692
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.2128802678
Short name T1063
Test name
Test status
Simulation time 5175577000 ps
CPU time 64.47 seconds
Started Jun 02 03:25:12 PM PDT 24
Finished Jun 02 03:26:18 PM PDT 24
Peak memory 262048 kb
Host smart-412d7687-fb65-4ed4-8e71-129572253804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128802678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2128802678
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.3877759790
Short name T629
Test name
Test status
Simulation time 69801500 ps
CPU time 52.03 seconds
Started Jun 02 03:25:06 PM PDT 24
Finished Jun 02 03:25:58 PM PDT 24
Peak memory 270404 kb
Host smart-67c32990-1f1f-4d10-9a0c-5ad6b1692a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877759790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.3877759790
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.4119418871
Short name T655
Test name
Test status
Simulation time 46329200 ps
CPU time 13.68 seconds
Started Jun 02 03:25:10 PM PDT 24
Finished Jun 02 03:25:25 PM PDT 24
Peak memory 257824 kb
Host smart-47d7672e-d2f1-41e7-ac8d-72c897eb8e10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119418871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
4119418871
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.3134130892
Short name T632
Test name
Test status
Simulation time 69379100 ps
CPU time 20.26 seconds
Started Jun 02 03:25:10 PM PDT 24
Finished Jun 02 03:25:31 PM PDT 24
Peak memory 264872 kb
Host smart-febed2cf-8777-438f-9873-695fdb8c6708
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134130892 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.3134130892
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.67881980
Short name T715
Test name
Test status
Simulation time 6361432300 ps
CPU time 252.22 seconds
Started Jun 02 03:25:13 PM PDT 24
Finished Jun 02 03:29:26 PM PDT 24
Peak memory 262188 kb
Host smart-dc752f85-93bd-4f24-b6d3-bb70026d1f07
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67881980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw
_sec_otp.67881980
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.2484949269
Short name T461
Test name
Test status
Simulation time 130228000 ps
CPU time 133.12 seconds
Started Jun 02 03:25:13 PM PDT 24
Finished Jun 02 03:27:27 PM PDT 24
Peak memory 259500 kb
Host smart-5f50b66d-c469-42f4-9960-873eead75b27
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484949269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.2484949269
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.492396020
Short name T393
Test name
Test status
Simulation time 3094867300 ps
CPU time 68.46 seconds
Started Jun 02 03:25:13 PM PDT 24
Finished Jun 02 03:26:22 PM PDT 24
Peak memory 264692 kb
Host smart-c342c8b4-57a9-4c65-8828-e8082776266f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492396020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.492396020
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.3564942084
Short name T644
Test name
Test status
Simulation time 42521200 ps
CPU time 193.14 seconds
Started Jun 02 03:25:12 PM PDT 24
Finished Jun 02 03:28:26 PM PDT 24
Peak memory 277028 kb
Host smart-b391cfec-20de-4fe6-9e70-9004b6a90ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564942084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.3564942084
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.2940615568
Short name T199
Test name
Test status
Simulation time 99388200 ps
CPU time 13.77 seconds
Started Jun 02 03:25:18 PM PDT 24
Finished Jun 02 03:25:33 PM PDT 24
Peak memory 264736 kb
Host smart-488d90f6-ebfc-4c6b-ba45-2bff1d3d3424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940615568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
2940615568
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.3869850131
Short name T481
Test name
Test status
Simulation time 124175600 ps
CPU time 15.86 seconds
Started Jun 02 03:25:19 PM PDT 24
Finished Jun 02 03:25:36 PM PDT 24
Peak memory 275420 kb
Host smart-b2f93d12-d510-441f-8f53-3389db554d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869850131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3869850131
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.565593939
Short name T152
Test name
Test status
Simulation time 10036600 ps
CPU time 20.56 seconds
Started Jun 02 03:25:18 PM PDT 24
Finished Jun 02 03:25:40 PM PDT 24
Peak memory 273180 kb
Host smart-05b72e9e-cab1-499b-9d2f-87861f266a1e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565593939 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.565593939
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.2963094498
Short name T317
Test name
Test status
Simulation time 40468900 ps
CPU time 132.13 seconds
Started Jun 02 03:25:18 PM PDT 24
Finished Jun 02 03:27:31 PM PDT 24
Peak memory 259804 kb
Host smart-44e64ea0-94d6-4070-97a1-eba7653e780d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963094498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.2963094498
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.2648352530
Short name T214
Test name
Test status
Simulation time 4017886700 ps
CPU time 66.56 seconds
Started Jun 02 03:25:16 PM PDT 24
Finished Jun 02 03:26:24 PM PDT 24
Peak memory 261596 kb
Host smart-37a9d4f2-62a6-4428-a77c-fba45be9f245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648352530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.2648352530
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.1097968371
Short name T780
Test name
Test status
Simulation time 24811500 ps
CPU time 216.14 seconds
Started Jun 02 03:25:10 PM PDT 24
Finished Jun 02 03:28:47 PM PDT 24
Peak memory 279296 kb
Host smart-1d76aee6-cd76-4346-b5c4-10fb7734cba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097968371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.1097968371
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.1626615966
Short name T871
Test name
Test status
Simulation time 24784700 ps
CPU time 13.58 seconds
Started Jun 02 03:25:17 PM PDT 24
Finished Jun 02 03:25:32 PM PDT 24
Peak memory 257904 kb
Host smart-e688a256-be8e-469a-b39c-6e8b7fc1df32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626615966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
1626615966
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.2709583153
Short name T1074
Test name
Test status
Simulation time 16203800 ps
CPU time 15.98 seconds
Started Jun 02 03:25:18 PM PDT 24
Finished Jun 02 03:25:35 PM PDT 24
Peak memory 275424 kb
Host smart-e1195a0a-2217-4806-8699-fee4afe175ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709583153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.2709583153
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.1681587669
Short name T204
Test name
Test status
Simulation time 160226800 ps
CPU time 21.14 seconds
Started Jun 02 03:25:16 PM PDT 24
Finished Jun 02 03:25:39 PM PDT 24
Peak memory 273132 kb
Host smart-65c3eaa4-17a3-4a0d-9208-b197874deb98
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681587669 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.1681587669
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1562210211
Short name T329
Test name
Test status
Simulation time 1153006600 ps
CPU time 107.69 seconds
Started Jun 02 03:25:18 PM PDT 24
Finished Jun 02 03:27:06 PM PDT 24
Peak memory 262292 kb
Host smart-78f7717a-867b-4d12-879a-f52426621bc2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562210211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.1562210211
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.3299900050
Short name T936
Test name
Test status
Simulation time 41109800 ps
CPU time 132.17 seconds
Started Jun 02 03:25:18 PM PDT 24
Finished Jun 02 03:27:32 PM PDT 24
Peak memory 260860 kb
Host smart-d6d19c46-581e-4240-917f-c07729ef7be8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299900050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.3299900050
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.4026830061
Short name T605
Test name
Test status
Simulation time 5135451500 ps
CPU time 73.15 seconds
Started Jun 02 03:25:18 PM PDT 24
Finished Jun 02 03:26:33 PM PDT 24
Peak memory 261796 kb
Host smart-539993c7-ee4b-49b5-bd35-d89b7c4bedb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026830061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.4026830061
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.4177553326
Short name T861
Test name
Test status
Simulation time 39786400 ps
CPU time 49.84 seconds
Started Jun 02 03:25:19 PM PDT 24
Finished Jun 02 03:26:10 PM PDT 24
Peak memory 270340 kb
Host smart-64ee0c10-35c8-4571-902f-b967dfd3544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177553326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.4177553326
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.3636235371
Short name T909
Test name
Test status
Simulation time 138739600 ps
CPU time 14.01 seconds
Started Jun 02 03:25:26 PM PDT 24
Finished Jun 02 03:25:41 PM PDT 24
Peak memory 257824 kb
Host smart-9b9bae82-310a-48f1-a200-1c50d0256d7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636235371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
3636235371
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.1284131150
Short name T566
Test name
Test status
Simulation time 23645100 ps
CPU time 15.69 seconds
Started Jun 02 03:25:23 PM PDT 24
Finished Jun 02 03:25:40 PM PDT 24
Peak memory 275860 kb
Host smart-467508f4-163b-4f76-b90c-2b4f6b452a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284131150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.1284131150
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.2353577093
Short name T661
Test name
Test status
Simulation time 10810600 ps
CPU time 21.91 seconds
Started Jun 02 03:25:22 PM PDT 24
Finished Jun 02 03:25:45 PM PDT 24
Peak memory 273140 kb
Host smart-b8511a50-2ade-45bb-8dbb-21e54aa8711f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353577093 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.2353577093
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.2510816635
Short name T949
Test name
Test status
Simulation time 2311885000 ps
CPU time 79.07 seconds
Started Jun 02 03:25:23 PM PDT 24
Finished Jun 02 03:26:43 PM PDT 24
Peak memory 262156 kb
Host smart-8b3499c2-087c-475d-bcf0-b7e8a1de25e5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510816635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.2510816635
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.1244293082
Short name T621
Test name
Test status
Simulation time 72173200 ps
CPU time 129.64 seconds
Started Jun 02 03:25:24 PM PDT 24
Finished Jun 02 03:27:35 PM PDT 24
Peak memory 260936 kb
Host smart-02b0b19b-24f2-4a62-8c4f-8276989c107a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244293082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.1244293082
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.1395662063
Short name T694
Test name
Test status
Simulation time 138412500 ps
CPU time 75.44 seconds
Started Jun 02 03:25:17 PM PDT 24
Finished Jun 02 03:26:34 PM PDT 24
Peak memory 274752 kb
Host smart-ec48f04a-4f03-4393-8cff-374c484ca745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395662063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1395662063
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.2165045131
Short name T729
Test name
Test status
Simulation time 104357700 ps
CPU time 13.57 seconds
Started Jun 02 03:25:27 PM PDT 24
Finished Jun 02 03:25:41 PM PDT 24
Peak memory 264800 kb
Host smart-b411973b-f39b-44f2-9935-23ea3c9c306c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165045131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
2165045131
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.2497451725
Short name T573
Test name
Test status
Simulation time 23342200 ps
CPU time 15.6 seconds
Started Jun 02 03:25:22 PM PDT 24
Finished Jun 02 03:25:39 PM PDT 24
Peak memory 274976 kb
Host smart-8aab314f-7245-4038-b2dd-e58927907242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497451725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.2497451725
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.2536343860
Short name T974
Test name
Test status
Simulation time 24428900 ps
CPU time 19.98 seconds
Started Jun 02 03:25:22 PM PDT 24
Finished Jun 02 03:25:43 PM PDT 24
Peak memory 273180 kb
Host smart-6fd1f070-1b86-4038-8220-71443188c6b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536343860 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.2536343860
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.794295276
Short name T519
Test name
Test status
Simulation time 8230291600 ps
CPU time 141.72 seconds
Started Jun 02 03:25:22 PM PDT 24
Finished Jun 02 03:27:45 PM PDT 24
Peak memory 262360 kb
Host smart-dbba1ef9-a0a5-48b5-b05d-4e0fff5da9dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794295276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_h
w_sec_otp.794295276
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.4155942405
Short name T523
Test name
Test status
Simulation time 69984000 ps
CPU time 132.09 seconds
Started Jun 02 03:25:23 PM PDT 24
Finished Jun 02 03:27:36 PM PDT 24
Peak memory 259760 kb
Host smart-4f7e7269-835e-4256-8752-58d2a3a9f0f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155942405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.4155942405
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.952934
Short name T213
Test name
Test status
Simulation time 525238800 ps
CPU time 63.73 seconds
Started Jun 02 03:25:23 PM PDT 24
Finished Jun 02 03:26:28 PM PDT 24
Peak memory 261408 kb
Host smart-fef44dfe-5ef8-475b-a8b7-9608f27c174f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.952934
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.3537242723
Short name T666
Test name
Test status
Simulation time 50609700 ps
CPU time 96.48 seconds
Started Jun 02 03:25:22 PM PDT 24
Finished Jun 02 03:26:59 PM PDT 24
Peak memory 275160 kb
Host smart-aa257af4-eeed-443d-ac65-2f5dfe0ef6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537242723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3537242723
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.3005776910
Short name T510
Test name
Test status
Simulation time 198723000 ps
CPU time 13.64 seconds
Started Jun 02 03:25:25 PM PDT 24
Finished Jun 02 03:25:40 PM PDT 24
Peak memory 257860 kb
Host smart-802f6064-60b5-4fde-85ba-f18a4b35ae10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005776910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
3005776910
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.284325953
Short name T987
Test name
Test status
Simulation time 52665500 ps
CPU time 15.96 seconds
Started Jun 02 03:25:26 PM PDT 24
Finished Jun 02 03:25:42 PM PDT 24
Peak memory 275432 kb
Host smart-cca86e90-2734-4e61-87a0-45871dcb7d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284325953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.284325953
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.3651075444
Short name T831
Test name
Test status
Simulation time 15651200 ps
CPU time 21.7 seconds
Started Jun 02 03:25:25 PM PDT 24
Finished Jun 02 03:25:47 PM PDT 24
Peak memory 264900 kb
Host smart-94cdde8a-9571-4636-a297-060b4b50dbb1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651075444 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.3651075444
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.2350920167
Short name T1020
Test name
Test status
Simulation time 1337318400 ps
CPU time 59.15 seconds
Started Jun 02 03:25:24 PM PDT 24
Finished Jun 02 03:26:24 PM PDT 24
Peak memory 262344 kb
Host smart-5c81e024-75b6-47a8-a13e-1814187b2bd1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350920167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.2350920167
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.2238769963
Short name T141
Test name
Test status
Simulation time 77789400 ps
CPU time 132.64 seconds
Started Jun 02 03:25:25 PM PDT 24
Finished Jun 02 03:27:38 PM PDT 24
Peak memory 260632 kb
Host smart-5f691f0f-121e-474e-8434-48418b03f54b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238769963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.2238769963
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.2015194826
Short name T560
Test name
Test status
Simulation time 76338900 ps
CPU time 169.81 seconds
Started Jun 02 03:25:24 PM PDT 24
Finished Jun 02 03:28:15 PM PDT 24
Peak memory 276624 kb
Host smart-c4207074-059f-4463-805a-1daa773e3992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015194826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.2015194826
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.1385144069
Short name T501
Test name
Test status
Simulation time 87220500 ps
CPU time 13.72 seconds
Started Jun 02 03:25:28 PM PDT 24
Finished Jun 02 03:25:42 PM PDT 24
Peak memory 264812 kb
Host smart-cc0b03ac-dc9c-4ac7-bb48-1d52c63f6be1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385144069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
1385144069
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.1779883046
Short name T842
Test name
Test status
Simulation time 15352400 ps
CPU time 15.49 seconds
Started Jun 02 03:25:26 PM PDT 24
Finished Jun 02 03:25:42 PM PDT 24
Peak memory 275376 kb
Host smart-11be2b48-eeac-4085-8599-059076671735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779883046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.1779883046
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.77513570
Short name T147
Test name
Test status
Simulation time 10248100 ps
CPU time 21.98 seconds
Started Jun 02 03:25:28 PM PDT 24
Finished Jun 02 03:25:51 PM PDT 24
Peak memory 273232 kb
Host smart-4ccc2bcd-05dc-4e9c-ba49-294ff97eba20
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77513570 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.flash_ctrl_disable.77513570
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.433863385
Short name T789
Test name
Test status
Simulation time 1534542400 ps
CPU time 65.06 seconds
Started Jun 02 03:25:27 PM PDT 24
Finished Jun 02 03:26:33 PM PDT 24
Peak memory 261712 kb
Host smart-b7849dc8-7fab-48f4-878e-747aa9c3b611
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433863385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_h
w_sec_otp.433863385
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.2873985930
Short name T45
Test name
Test status
Simulation time 141943200 ps
CPU time 111.32 seconds
Started Jun 02 03:25:26 PM PDT 24
Finished Jun 02 03:27:18 PM PDT 24
Peak memory 259608 kb
Host smart-6a1ecdf3-8f3c-499e-a4dd-a95255256d0b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873985930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.2873985930
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.1415848923
Short name T395
Test name
Test status
Simulation time 5609022100 ps
CPU time 62.94 seconds
Started Jun 02 03:25:25 PM PDT 24
Finished Jun 02 03:26:29 PM PDT 24
Peak memory 263084 kb
Host smart-cb6c420e-0aef-465e-8ca8-88a73ed7db3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415848923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.1415848923
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.2998804484
Short name T420
Test name
Test status
Simulation time 32197100 ps
CPU time 98.53 seconds
Started Jun 02 03:25:27 PM PDT 24
Finished Jun 02 03:27:06 PM PDT 24
Peak memory 276216 kb
Host smart-2ca33385-cd3c-41d0-ae5d-255d6ab18080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998804484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.2998804484
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.3516814488
Short name T200
Test name
Test status
Simulation time 82626600 ps
CPU time 13.85 seconds
Started Jun 02 03:25:35 PM PDT 24
Finished Jun 02 03:25:49 PM PDT 24
Peak memory 257940 kb
Host smart-8df7b33f-e6f8-4290-9500-a71ff6a05ad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516814488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
3516814488
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.778251615
Short name T587
Test name
Test status
Simulation time 56462700 ps
CPU time 15.69 seconds
Started Jun 02 03:25:33 PM PDT 24
Finished Jun 02 03:25:50 PM PDT 24
Peak memory 275544 kb
Host smart-35518fa7-2bac-4d06-b017-932eb864a005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778251615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.778251615
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.560029094
Short name T590
Test name
Test status
Simulation time 37389600 ps
CPU time 22.36 seconds
Started Jun 02 03:25:33 PM PDT 24
Finished Jun 02 03:25:56 PM PDT 24
Peak memory 273312 kb
Host smart-ff460af4-a7cb-492c-a167-e1d9ffcdce31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560029094 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.560029094
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.821316862
Short name T991
Test name
Test status
Simulation time 3241592100 ps
CPU time 138.03 seconds
Started Jun 02 03:25:26 PM PDT 24
Finished Jun 02 03:27:45 PM PDT 24
Peak memory 262236 kb
Host smart-515ccf57-3f2e-4412-88e3-481dfaafe9ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821316862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_h
w_sec_otp.821316862
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.2503380368
Short name T870
Test name
Test status
Simulation time 137750200 ps
CPU time 112.48 seconds
Started Jun 02 03:25:27 PM PDT 24
Finished Jun 02 03:27:21 PM PDT 24
Peak memory 263164 kb
Host smart-d4ae0e15-3a08-4de4-9de0-cc5dc0d1fc6a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503380368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.2503380368
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.3661760320
Short name T814
Test name
Test status
Simulation time 5163638400 ps
CPU time 67.88 seconds
Started Jun 02 03:25:34 PM PDT 24
Finished Jun 02 03:26:43 PM PDT 24
Peak memory 263280 kb
Host smart-1aca3ba1-eb86-461b-ba3e-880bcaf45677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661760320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.3661760320
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.3236494407
Short name T258
Test name
Test status
Simulation time 24280600 ps
CPU time 150.14 seconds
Started Jun 02 03:25:27 PM PDT 24
Finished Jun 02 03:27:58 PM PDT 24
Peak memory 278212 kb
Host smart-10dadbbe-b9dc-42a7-a3d7-5856b4e30085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236494407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.3236494407
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.1700554444
Short name T452
Test name
Test status
Simulation time 75888600 ps
CPU time 13.38 seconds
Started Jun 02 03:20:18 PM PDT 24
Finished Jun 02 03:20:31 PM PDT 24
Peak memory 257844 kb
Host smart-4568473a-3846-4f18-95a9-e5102996c895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700554444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.1
700554444
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.526902574
Short name T488
Test name
Test status
Simulation time 51595800 ps
CPU time 15.56 seconds
Started Jun 02 03:20:12 PM PDT 24
Finished Jun 02 03:20:28 PM PDT 24
Peak memory 275484 kb
Host smart-124fdb2b-9273-43e4-bff5-682d38c5e315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526902574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.526902574
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.1622414587
Short name T150
Test name
Test status
Simulation time 11283800 ps
CPU time 21.74 seconds
Started Jun 02 03:20:10 PM PDT 24
Finished Jun 02 03:20:33 PM PDT 24
Peak memory 264840 kb
Host smart-1c76a5d6-6ba4-4730-a86a-129f5bf3a873
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622414587 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.1622414587
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.1634187261
Short name T224
Test name
Test status
Simulation time 9612218700 ps
CPU time 2408.07 seconds
Started Jun 02 03:20:06 PM PDT 24
Finished Jun 02 04:00:15 PM PDT 24
Peak memory 263976 kb
Host smart-136ae4f2-0bac-4f8b-bea8-ea47f7092677
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634187261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.1634187261
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.2622716955
Short name T667
Test name
Test status
Simulation time 1391097700 ps
CPU time 859.98 seconds
Started Jun 02 03:20:06 PM PDT 24
Finished Jun 02 03:34:27 PM PDT 24
Peak memory 273732 kb
Host smart-9447206d-8d6a-42c1-9140-af27688db3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622716955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2622716955
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3807002068
Short name T2
Test name
Test status
Simulation time 10019016600 ps
CPU time 78.82 seconds
Started Jun 02 03:20:16 PM PDT 24
Finished Jun 02 03:21:36 PM PDT 24
Peak memory 291520 kb
Host smart-9eae0252-60fd-44c1-90f6-51c14d67439c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807002068 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.3807002068
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.4229786826
Short name T364
Test name
Test status
Simulation time 15917000 ps
CPU time 13.58 seconds
Started Jun 02 03:20:17 PM PDT 24
Finished Jun 02 03:20:31 PM PDT 24
Peak memory 264780 kb
Host smart-324759f6-914c-4495-b1fa-992defa9a712
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229786826 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.4229786826
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.2360817042
Short name T754
Test name
Test status
Simulation time 70128391000 ps
CPU time 827.89 seconds
Started Jun 02 03:20:06 PM PDT 24
Finished Jun 02 03:33:55 PM PDT 24
Peak memory 263208 kb
Host smart-02ac4123-cd00-46e5-a21e-4908597c3699
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360817042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.2360817042
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.691949972
Short name T322
Test name
Test status
Simulation time 4035750600 ps
CPU time 62.89 seconds
Started Jun 02 03:20:05 PM PDT 24
Finished Jun 02 03:21:09 PM PDT 24
Peak memory 259952 kb
Host smart-b0f932ce-a336-4b39-8e93-9bdcce7ba909
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691949972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw
_sec_otp.691949972
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.2897309355
Short name T359
Test name
Test status
Simulation time 1511392200 ps
CPU time 134.31 seconds
Started Jun 02 03:20:10 PM PDT 24
Finished Jun 02 03:22:25 PM PDT 24
Peak memory 292660 kb
Host smart-d019f21f-fd2a-42c1-8642-b73b359397a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897309355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.2897309355
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.571133648
Short name T984
Test name
Test status
Simulation time 24378120200 ps
CPU time 266.02 seconds
Started Jun 02 03:20:12 PM PDT 24
Finished Jun 02 03:24:38 PM PDT 24
Peak memory 283968 kb
Host smart-c555a4a0-8aeb-40ad-8570-f4bad2fbbba0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571133648 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.571133648
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.3893599625
Short name T879
Test name
Test status
Simulation time 2533886600 ps
CPU time 69.24 seconds
Started Jun 02 03:20:12 PM PDT 24
Finished Jun 02 03:21:22 PM PDT 24
Peak memory 264636 kb
Host smart-91260a03-091c-4911-b4f3-c30c0ff1f368
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893599625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.3893599625
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3625102008
Short name T595
Test name
Test status
Simulation time 42339906100 ps
CPU time 180.5 seconds
Started Jun 02 03:20:11 PM PDT 24
Finished Jun 02 03:23:12 PM PDT 24
Peak memory 264852 kb
Host smart-3d3b9ef2-f5d8-4410-8f4e-cd666d82fd97
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362
5102008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.3625102008
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.3246179938
Short name T297
Test name
Test status
Simulation time 25542400 ps
CPU time 13.42 seconds
Started Jun 02 03:20:17 PM PDT 24
Finished Jun 02 03:20:31 PM PDT 24
Peak memory 260128 kb
Host smart-a59d42b8-7d3d-4013-af57-1cf820def08e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246179938 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.3246179938
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.1430314239
Short name T744
Test name
Test status
Simulation time 121616893100 ps
CPU time 331.87 seconds
Started Jun 02 03:20:06 PM PDT 24
Finished Jun 02 03:25:39 PM PDT 24
Peak memory 272448 kb
Host smart-b08f4890-4612-41d8-8153-38e6a6d3b575
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430314239 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.1430314239
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.185749128
Short name T737
Test name
Test status
Simulation time 172815000 ps
CPU time 113.28 seconds
Started Jun 02 03:20:03 PM PDT 24
Finished Jun 02 03:21:57 PM PDT 24
Peak memory 263192 kb
Host smart-09e70004-c6d9-472b-8c3f-8917aa8efaf5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185749128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp
_reset.185749128
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.987443089
Short name T174
Test name
Test status
Simulation time 69655200 ps
CPU time 155.73 seconds
Started Jun 02 03:20:04 PM PDT 24
Finished Jun 02 03:22:41 PM PDT 24
Peak memory 262140 kb
Host smart-9b3d85d7-ca5c-44d1-94f4-7c62c8eb9245
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=987443089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.987443089
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.3933703514
Short name T412
Test name
Test status
Simulation time 18740200 ps
CPU time 13.61 seconds
Started Jun 02 03:20:11 PM PDT 24
Finished Jun 02 03:20:25 PM PDT 24
Peak memory 264784 kb
Host smart-24680622-daad-4fd8-b1d6-0381f8d9a4a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933703514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.3933703514
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.3418186287
Short name T713
Test name
Test status
Simulation time 497854700 ps
CPU time 866.39 seconds
Started Jun 02 03:20:04 PM PDT 24
Finished Jun 02 03:34:32 PM PDT 24
Peak memory 284560 kb
Host smart-65ed8426-4afa-4aeb-aceb-41aca5e4d4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418186287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.3418186287
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.2396308074
Short name T442
Test name
Test status
Simulation time 96511800 ps
CPU time 32.87 seconds
Started Jun 02 03:20:10 PM PDT 24
Finished Jun 02 03:20:44 PM PDT 24
Peak memory 273108 kb
Host smart-8a7da703-bd88-4988-a07c-94fb94ec3b6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396308074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.2396308074
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.2221588336
Short name T993
Test name
Test status
Simulation time 2085007400 ps
CPU time 140.05 seconds
Started Jun 02 03:20:04 PM PDT 24
Finished Jun 02 03:22:25 PM PDT 24
Peak memory 296616 kb
Host smart-0dc23007-0b2f-49b4-b3b8-bd16da8e82ef
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221588336 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_ro.2221588336
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.2336070550
Short name T1042
Test name
Test status
Simulation time 1122428300 ps
CPU time 143 seconds
Started Jun 02 03:20:10 PM PDT 24
Finished Jun 02 03:22:34 PM PDT 24
Peak memory 281240 kb
Host smart-b3633fa0-135f-4adc-8735-af8721f72d2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2336070550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.2336070550
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.2157244910
Short name T697
Test name
Test status
Simulation time 2037214800 ps
CPU time 120.23 seconds
Started Jun 02 03:20:04 PM PDT 24
Finished Jun 02 03:22:06 PM PDT 24
Peak memory 281248 kb
Host smart-6d479989-db17-4b87-950e-8d98dadf6625
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157244910 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.2157244910
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.1331555392
Short name T334
Test name
Test status
Simulation time 135304400 ps
CPU time 31.31 seconds
Started Jun 02 03:20:10 PM PDT 24
Finished Jun 02 03:20:42 PM PDT 24
Peak memory 273104 kb
Host smart-9265b95a-4303-4433-a5df-5aba5d495f8b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331555392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_rw_evict.1331555392
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.2590723280
Short name T779
Test name
Test status
Simulation time 51134700 ps
CPU time 31.26 seconds
Started Jun 02 03:20:10 PM PDT 24
Finished Jun 02 03:20:42 PM PDT 24
Peak memory 272640 kb
Host smart-b9921801-060a-479e-928d-ada1bed7a80d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590723280 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.2590723280
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.1685808665
Short name T978
Test name
Test status
Simulation time 6296670900 ps
CPU time 595.19 seconds
Started Jun 02 03:20:11 PM PDT 24
Finished Jun 02 03:30:07 PM PDT 24
Peak memory 319864 kb
Host smart-7e318feb-97a4-4f66-a368-96408f62365c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685808665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.1685808665
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.2303749738
Short name T405
Test name
Test status
Simulation time 2805282900 ps
CPU time 67.79 seconds
Started Jun 02 03:20:10 PM PDT 24
Finished Jun 02 03:21:18 PM PDT 24
Peak memory 262716 kb
Host smart-5ccf0525-63c9-47d5-8b28-70d38f1f83f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303749738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.2303749738
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.1311576657
Short name T41
Test name
Test status
Simulation time 25910200 ps
CPU time 98.08 seconds
Started Jun 02 03:20:03 PM PDT 24
Finished Jun 02 03:21:42 PM PDT 24
Peak memory 274968 kb
Host smart-3f8b652c-ebaa-4c33-ade1-645be3779390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311576657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.1311576657
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.891908061
Short name T647
Test name
Test status
Simulation time 1843851200 ps
CPU time 149.59 seconds
Started Jun 02 03:20:05 PM PDT 24
Finished Jun 02 03:22:35 PM PDT 24
Peak memory 259124 kb
Host smart-85931923-a7fc-4369-90c7-9821296d9fc7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891908061 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.flash_ctrl_wo.891908061
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.2664274490
Short name T693
Test name
Test status
Simulation time 47715100 ps
CPU time 15.85 seconds
Started Jun 02 03:25:31 PM PDT 24
Finished Jun 02 03:25:47 PM PDT 24
Peak memory 274768 kb
Host smart-a5f9a6ad-25ed-4e80-b8ad-84fd91a2a057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664274490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.2664274490
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.674617027
Short name T1082
Test name
Test status
Simulation time 41545000 ps
CPU time 110.22 seconds
Started Jun 02 03:25:32 PM PDT 24
Finished Jun 02 03:27:23 PM PDT 24
Peak memory 260728 kb
Host smart-2ac478e9-bfd6-44cd-a70e-09a57fee391c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674617027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_ot
p_reset.674617027
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.2495883453
Short name T46
Test name
Test status
Simulation time 27554500 ps
CPU time 13.57 seconds
Started Jun 02 03:25:33 PM PDT 24
Finished Jun 02 03:25:47 PM PDT 24
Peak memory 275028 kb
Host smart-1f0f29ca-6755-4239-8c8e-eab4c181d934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495883453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.2495883453
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.9354251
Short name T938
Test name
Test status
Simulation time 59950700 ps
CPU time 129.81 seconds
Started Jun 02 03:25:32 PM PDT 24
Finished Jun 02 03:27:43 PM PDT 24
Peak memory 259960 kb
Host smart-97379b49-e0c1-40b1-b338-62a486ef9651
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9354251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp_
reset.9354251
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.1334772950
Short name T1083
Test name
Test status
Simulation time 27751300 ps
CPU time 15.65 seconds
Started Jun 02 03:25:34 PM PDT 24
Finished Jun 02 03:25:50 PM PDT 24
Peak memory 275504 kb
Host smart-7c3493f3-164e-4873-921c-23dd27968bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334772950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1334772950
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.1814629795
Short name T138
Test name
Test status
Simulation time 36948400 ps
CPU time 128.66 seconds
Started Jun 02 03:25:32 PM PDT 24
Finished Jun 02 03:27:42 PM PDT 24
Peak memory 264480 kb
Host smart-6ebb9e43-2d10-431d-b069-7f9e33630ca8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814629795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.1814629795
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.1791997897
Short name T462
Test name
Test status
Simulation time 21857000 ps
CPU time 15.7 seconds
Started Jun 02 03:25:33 PM PDT 24
Finished Jun 02 03:25:49 PM PDT 24
Peak memory 275532 kb
Host smart-00799a0f-1a46-487e-87f7-473497509002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791997897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.1791997897
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.2968218748
Short name T491
Test name
Test status
Simulation time 93199100 ps
CPU time 130.48 seconds
Started Jun 02 03:25:32 PM PDT 24
Finished Jun 02 03:27:44 PM PDT 24
Peak memory 259700 kb
Host smart-950addf1-d015-48fe-b2b4-d2e24f55562a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968218748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.2968218748
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.1258514004
Short name T432
Test name
Test status
Simulation time 28824900 ps
CPU time 15.43 seconds
Started Jun 02 03:25:34 PM PDT 24
Finished Jun 02 03:25:51 PM PDT 24
Peak memory 275884 kb
Host smart-b7b3ca5f-987a-4ed5-b84f-351670f9f456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258514004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1258514004
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.922677037
Short name T534
Test name
Test status
Simulation time 70183400 ps
CPU time 130.18 seconds
Started Jun 02 03:25:32 PM PDT 24
Finished Jun 02 03:27:43 PM PDT 24
Peak memory 259524 kb
Host smart-282f376b-dfc7-4979-af3b-dd8e2f451b1f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922677037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_ot
p_reset.922677037
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.805108240
Short name T830
Test name
Test status
Simulation time 29036800 ps
CPU time 15.97 seconds
Started Jun 02 03:25:33 PM PDT 24
Finished Jun 02 03:25:49 PM PDT 24
Peak memory 274724 kb
Host smart-c9c6b3da-0324-4638-ad4e-ba0ea2d213f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805108240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.805108240
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.2227273800
Short name T246
Test name
Test status
Simulation time 23641200 ps
CPU time 13.33 seconds
Started Jun 02 03:25:41 PM PDT 24
Finished Jun 02 03:25:55 PM PDT 24
Peak memory 275584 kb
Host smart-d55fbcd4-1def-4796-9bd0-733c0511a490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227273800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2227273800
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.3316630315
Short name T961
Test name
Test status
Simulation time 46794400 ps
CPU time 111.71 seconds
Started Jun 02 03:25:38 PM PDT 24
Finished Jun 02 03:27:31 PM PDT 24
Peak memory 260948 kb
Host smart-f8ed3cb8-9eaf-4d50-b72a-357119875ee3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316630315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.3316630315
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.1743321385
Short name T767
Test name
Test status
Simulation time 39632300 ps
CPU time 15.6 seconds
Started Jun 02 03:25:37 PM PDT 24
Finished Jun 02 03:25:53 PM PDT 24
Peak memory 275928 kb
Host smart-741bbaed-aa2c-4e75-bbd2-308156ec5435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743321385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.1743321385
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.2403354628
Short name T14
Test name
Test status
Simulation time 148543800 ps
CPU time 128.57 seconds
Started Jun 02 03:25:37 PM PDT 24
Finished Jun 02 03:27:46 PM PDT 24
Peak memory 264660 kb
Host smart-deef87cd-cf46-4558-96cb-1c75ddf9e014
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403354628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.2403354628
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.4244139492
Short name T554
Test name
Test status
Simulation time 34253300 ps
CPU time 15.75 seconds
Started Jun 02 03:25:41 PM PDT 24
Finished Jun 02 03:25:57 PM PDT 24
Peak memory 275964 kb
Host smart-db20c5ab-6b5a-4d95-97b9-442d8a1fbe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244139492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.4244139492
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.3153133247
Short name T563
Test name
Test status
Simulation time 36083200 ps
CPU time 130.78 seconds
Started Jun 02 03:25:38 PM PDT 24
Finished Jun 02 03:27:49 PM PDT 24
Peak memory 259668 kb
Host smart-d5565f50-2c53-4541-8765-2499d66fddae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153133247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.3153133247
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.2704661618
Short name T968
Test name
Test status
Simulation time 54482400 ps
CPU time 15.98 seconds
Started Jun 02 03:25:36 PM PDT 24
Finished Jun 02 03:25:53 PM PDT 24
Peak memory 275420 kb
Host smart-8ab2e8ec-ba83-4ab3-a26a-c010ae979ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704661618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.2704661618
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.1701492705
Short name T1001
Test name
Test status
Simulation time 37085200 ps
CPU time 110.45 seconds
Started Jun 02 03:25:37 PM PDT 24
Finished Jun 02 03:27:28 PM PDT 24
Peak memory 260856 kb
Host smart-f6303e7b-e000-4bfc-8572-638e0008bf54
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701492705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.1701492705
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.3740410754
Short name T959
Test name
Test status
Simulation time 28669800 ps
CPU time 13.55 seconds
Started Jun 02 03:20:28 PM PDT 24
Finished Jun 02 03:20:42 PM PDT 24
Peak memory 257736 kb
Host smart-be03ef41-6af9-4797-be3b-63b8316ad4b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740410754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3
740410754
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.592949798
Short name T816
Test name
Test status
Simulation time 51402000 ps
CPU time 15.53 seconds
Started Jun 02 03:20:30 PM PDT 24
Finished Jun 02 03:20:46 PM PDT 24
Peak memory 274220 kb
Host smart-204cc356-a943-4fcc-9f35-e51c0339baf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592949798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.592949798
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.2424077985
Short name T721
Test name
Test status
Simulation time 22295700 ps
CPU time 21.7 seconds
Started Jun 02 03:20:28 PM PDT 24
Finished Jun 02 03:20:51 PM PDT 24
Peak memory 273200 kb
Host smart-00a9a420-f1c7-4262-b49f-2a512c18d9c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424077985 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.2424077985
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.94966606
Short name T223
Test name
Test status
Simulation time 16078350500 ps
CPU time 2554.51 seconds
Started Jun 02 03:20:17 PM PDT 24
Finished Jun 02 04:02:52 PM PDT 24
Peak memory 264536 kb
Host smart-b78d0789-e213-4777-bc7e-113067175877
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94966606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error
_mp.94966606
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.995950259
Short name T1075
Test name
Test status
Simulation time 832751900 ps
CPU time 1105.87 seconds
Started Jun 02 03:20:17 PM PDT 24
Finished Jun 02 03:38:44 PM PDT 24
Peak memory 273020 kb
Host smart-6ce561fb-69e1-407f-8615-40bf30de930a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995950259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.995950259
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.484855306
Short name T49
Test name
Test status
Simulation time 422283200 ps
CPU time 27.7 seconds
Started Jun 02 03:20:16 PM PDT 24
Finished Jun 02 03:20:44 PM PDT 24
Peak memory 264904 kb
Host smart-568fa4d4-b20d-4b05-9cc7-d06ae9ad586e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484855306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.484855306
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1465907348
Short name T295
Test name
Test status
Simulation time 10012631000 ps
CPU time 111.37 seconds
Started Jun 02 03:20:29 PM PDT 24
Finished Jun 02 03:22:21 PM PDT 24
Peak memory 297116 kb
Host smart-16d7a7a0-c791-4623-9aaf-859b05c0e458
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465907348 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.1465907348
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.4003253903
Short name T791
Test name
Test status
Simulation time 15980600 ps
CPU time 13.29 seconds
Started Jun 02 03:20:30 PM PDT 24
Finished Jun 02 03:20:44 PM PDT 24
Peak memory 257284 kb
Host smart-eb190939-927d-40d1-a079-73cf08cf400b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003253903 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.4003253903
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.1515274450
Short name T127
Test name
Test status
Simulation time 380267908400 ps
CPU time 1246.56 seconds
Started Jun 02 03:20:15 PM PDT 24
Finished Jun 02 03:41:03 PM PDT 24
Peak memory 263372 kb
Host smart-3d845595-3257-40af-8363-bf775744f059
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515274450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.1515274450
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.1853572590
Short name T901
Test name
Test status
Simulation time 16031267600 ps
CPU time 196.77 seconds
Started Jun 02 03:20:17 PM PDT 24
Finished Jun 02 03:23:35 PM PDT 24
Peak memory 262488 kb
Host smart-8edfa712-2d08-4473-ad0e-5acb3d579922
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853572590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.1853572590
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.2839514436
Short name T356
Test name
Test status
Simulation time 7886639000 ps
CPU time 158.05 seconds
Started Jun 02 03:20:23 PM PDT 24
Finished Jun 02 03:23:02 PM PDT 24
Peak memory 292860 kb
Host smart-3730d7d4-d9f3-406e-bcca-1bb4ddefba0d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839514436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.2839514436
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.2848586823
Short name T723
Test name
Test status
Simulation time 12934928700 ps
CPU time 272.93 seconds
Started Jun 02 03:20:23 PM PDT 24
Finished Jun 02 03:24:57 PM PDT 24
Peak memory 292888 kb
Host smart-5aabe710-3a2c-4601-a5ee-1eca3db62051
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848586823 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.2848586823
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.3008043074
Short name T983
Test name
Test status
Simulation time 2501078500 ps
CPU time 77.79 seconds
Started Jun 02 03:20:23 PM PDT 24
Finished Jun 02 03:21:41 PM PDT 24
Peak memory 264820 kb
Host smart-0ee010f6-612f-49dc-9e57-c3086c106530
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008043074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.3008043074
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2872064719
Short name T869
Test name
Test status
Simulation time 24305921800 ps
CPU time 198.85 seconds
Started Jun 02 03:20:24 PM PDT 24
Finished Jun 02 03:23:44 PM PDT 24
Peak memory 260028 kb
Host smart-36a3d067-c47d-4282-bde0-fd22400384eb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287
2064719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.2872064719
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.3110117221
Short name T486
Test name
Test status
Simulation time 46933200 ps
CPU time 13.41 seconds
Started Jun 02 03:20:32 PM PDT 24
Finished Jun 02 03:20:45 PM PDT 24
Peak memory 260048 kb
Host smart-c13b628e-435a-4f77-83aa-c7fdef3d74b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110117221 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.3110117221
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.72033281
Short name T657
Test name
Test status
Simulation time 15568063900 ps
CPU time 169.81 seconds
Started Jun 02 03:20:16 PM PDT 24
Finished Jun 02 03:23:07 PM PDT 24
Peak memory 262432 kb
Host smart-d9c23093-ad03-406a-bc12-71c7b757cda2
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72033281 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_mp_regions.72033281
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.45542526
Short name T139
Test name
Test status
Simulation time 74814000 ps
CPU time 131.51 seconds
Started Jun 02 03:20:16 PM PDT 24
Finished Jun 02 03:22:29 PM PDT 24
Peak memory 259540 kb
Host smart-88e127ac-fbf1-4576-b627-e0f6ed5929e9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45542526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp_
reset.45542526
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.3607492342
Short name T473
Test name
Test status
Simulation time 130945900 ps
CPU time 249.2 seconds
Started Jun 02 03:20:17 PM PDT 24
Finished Jun 02 03:24:27 PM PDT 24
Peak memory 261432 kb
Host smart-887cf1ed-9426-4a51-bb95-ccdb122079e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3607492342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.3607492342
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.122302486
Short name T745
Test name
Test status
Simulation time 18235900 ps
CPU time 13.48 seconds
Started Jun 02 03:20:23 PM PDT 24
Finished Jun 02 03:20:37 PM PDT 24
Peak memory 258376 kb
Host smart-8d669b9e-e6b5-44d0-83e5-8484017e0d6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122302486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_rese
t.122302486
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.1268371899
Short name T611
Test name
Test status
Simulation time 259606400 ps
CPU time 297.15 seconds
Started Jun 02 03:20:17 PM PDT 24
Finished Jun 02 03:25:15 PM PDT 24
Peak memory 281216 kb
Host smart-c13f07aa-f2d7-484f-bb1d-92ccc20409c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268371899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.1268371899
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.3083910035
Short name T1052
Test name
Test status
Simulation time 146263100 ps
CPU time 35.63 seconds
Started Jun 02 03:20:28 PM PDT 24
Finished Jun 02 03:21:04 PM PDT 24
Peak memory 273116 kb
Host smart-adc313e5-c425-4117-b5e4-df6ae779853c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083910035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.3083910035
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.4062769075
Short name T687
Test name
Test status
Simulation time 2314798500 ps
CPU time 106.61 seconds
Started Jun 02 03:20:23 PM PDT 24
Finished Jun 02 03:22:10 PM PDT 24
Peak memory 281332 kb
Host smart-48139cdc-1cc3-4e57-9e21-9667f9ffe91a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062769075 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_ro.4062769075
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.2397832571
Short name T518
Test name
Test status
Simulation time 1944646100 ps
CPU time 148.37 seconds
Started Jun 02 03:20:29 PM PDT 24
Finished Jun 02 03:22:58 PM PDT 24
Peak memory 281132 kb
Host smart-360a8397-0c64-4500-9997-1eec37d00617
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2397832571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.2397832571
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.1566261883
Short name T826
Test name
Test status
Simulation time 3395178000 ps
CPU time 154.65 seconds
Started Jun 02 03:20:23 PM PDT 24
Finished Jun 02 03:22:59 PM PDT 24
Peak memory 281176 kb
Host smart-9f29325b-8abb-4d90-a5e4-7bbc0535fe97
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566261883 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.1566261883
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.37898044
Short name T27
Test name
Test status
Simulation time 30222700 ps
CPU time 28.88 seconds
Started Jun 02 03:20:28 PM PDT 24
Finished Jun 02 03:20:58 PM PDT 24
Peak memory 273148 kb
Host smart-99f56de5-b043-4aa7-8b54-66dd67344533
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37898044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_rw_evict.37898044
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.3002525554
Short name T337
Test name
Test status
Simulation time 27704000 ps
CPU time 30.29 seconds
Started Jun 02 03:20:30 PM PDT 24
Finished Jun 02 03:21:01 PM PDT 24
Peak memory 275156 kb
Host smart-41b47280-2897-4608-86f9-a7296d2aeda8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002525554 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.3002525554
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.2457662819
Short name T399
Test name
Test status
Simulation time 1282104300 ps
CPU time 50.03 seconds
Started Jun 02 03:20:30 PM PDT 24
Finished Jun 02 03:21:20 PM PDT 24
Peak memory 262012 kb
Host smart-6c1beab9-538d-4327-8ea5-2aede27f1382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457662819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.2457662819
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.3898393532
Short name T675
Test name
Test status
Simulation time 58890500 ps
CPU time 52.13 seconds
Started Jun 02 03:20:16 PM PDT 24
Finished Jun 02 03:21:09 PM PDT 24
Peak memory 270284 kb
Host smart-013783c5-a1fc-4442-8bb8-07a597e09e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898393532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3898393532
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.1269607660
Short name T946
Test name
Test status
Simulation time 1641927800 ps
CPU time 123.63 seconds
Started Jun 02 03:20:23 PM PDT 24
Finished Jun 02 03:22:27 PM PDT 24
Peak memory 258936 kb
Host smart-a5dcaf91-3f82-486e-a43c-125290192709
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269607660 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.flash_ctrl_wo.1269607660
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.1551971311
Short name T416
Test name
Test status
Simulation time 14687700 ps
CPU time 13.14 seconds
Started Jun 02 03:25:37 PM PDT 24
Finished Jun 02 03:25:51 PM PDT 24
Peak memory 275948 kb
Host smart-df0ecd61-a964-4cfb-8f0c-02e0743b25e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551971311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.1551971311
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.2348703196
Short name T480
Test name
Test status
Simulation time 278864800 ps
CPU time 131.84 seconds
Started Jun 02 03:25:36 PM PDT 24
Finished Jun 02 03:27:48 PM PDT 24
Peak memory 264052 kb
Host smart-8f30a2cf-bb11-495a-94df-e30380e98293
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348703196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.2348703196
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.1578441576
Short name T893
Test name
Test status
Simulation time 26908700 ps
CPU time 16.24 seconds
Started Jun 02 03:25:37 PM PDT 24
Finished Jun 02 03:25:54 PM PDT 24
Peak memory 275552 kb
Host smart-7c2b5763-2aa1-4244-bcfa-a85721a6bc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578441576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.1578441576
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.3054083304
Short name T145
Test name
Test status
Simulation time 88740400 ps
CPU time 130.76 seconds
Started Jun 02 03:25:37 PM PDT 24
Finished Jun 02 03:27:49 PM PDT 24
Peak memory 259460 kb
Host smart-4708f04c-0f9e-45eb-b02f-7238dad67278
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054083304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.3054083304
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.1583257546
Short name T1028
Test name
Test status
Simulation time 16209100 ps
CPU time 15.36 seconds
Started Jun 02 03:25:44 PM PDT 24
Finished Jun 02 03:26:00 PM PDT 24
Peak memory 275768 kb
Host smart-caa3512f-b809-4963-8f90-cf466f432fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583257546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.1583257546
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.1767586249
Short name T529
Test name
Test status
Simulation time 246035100 ps
CPU time 132.11 seconds
Started Jun 02 03:25:37 PM PDT 24
Finished Jun 02 03:27:49 PM PDT 24
Peak memory 259792 kb
Host smart-eaa7f63c-63da-434c-9278-475d5d5b06de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767586249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.1767586249
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.1842925855
Short name T877
Test name
Test status
Simulation time 17282400 ps
CPU time 15.6 seconds
Started Jun 02 03:25:42 PM PDT 24
Finished Jun 02 03:25:58 PM PDT 24
Peak memory 275520 kb
Host smart-1891f836-da08-4fda-ba20-dce7d3363b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842925855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.1842925855
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.2989259671
Short name T821
Test name
Test status
Simulation time 20663600 ps
CPU time 15.52 seconds
Started Jun 02 03:25:46 PM PDT 24
Finished Jun 02 03:26:02 PM PDT 24
Peak memory 274756 kb
Host smart-5b0f987f-6479-4e85-9164-5cb34ec6b89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989259671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.2989259671
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.3066451601
Short name T703
Test name
Test status
Simulation time 132121500 ps
CPU time 132.74 seconds
Started Jun 02 03:25:43 PM PDT 24
Finished Jun 02 03:27:56 PM PDT 24
Peak memory 263992 kb
Host smart-4064b524-ea0a-4cc3-bbcf-8221b925484f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066451601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.3066451601
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.3793692364
Short name T383
Test name
Test status
Simulation time 40397700 ps
CPU time 16.29 seconds
Started Jun 02 03:25:42 PM PDT 24
Finished Jun 02 03:25:59 PM PDT 24
Peak memory 274748 kb
Host smart-5d33699b-294c-4216-ac1a-d1f9fc86547c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793692364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.3793692364
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.3701353579
Short name T468
Test name
Test status
Simulation time 155190300 ps
CPU time 133.19 seconds
Started Jun 02 03:25:42 PM PDT 24
Finished Jun 02 03:27:55 PM PDT 24
Peak memory 259704 kb
Host smart-6fd921f3-a2bb-455b-b62b-2cb1f89044ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701353579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.3701353579
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.1738436051
Short name T726
Test name
Test status
Simulation time 42131900 ps
CPU time 15.84 seconds
Started Jun 02 03:25:46 PM PDT 24
Finished Jun 02 03:26:03 PM PDT 24
Peak memory 275828 kb
Host smart-c146bc4b-fc3d-4d33-906b-dc18ab037f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738436051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.1738436051
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.1371108258
Short name T123
Test name
Test status
Simulation time 128410300 ps
CPU time 110.69 seconds
Started Jun 02 03:25:44 PM PDT 24
Finished Jun 02 03:27:35 PM PDT 24
Peak memory 259748 kb
Host smart-41c5a9d0-aed7-425e-9850-04140d31ad86
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371108258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.1371108258
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.1657810389
Short name T1037
Test name
Test status
Simulation time 14368600 ps
CPU time 15.38 seconds
Started Jun 02 03:25:43 PM PDT 24
Finished Jun 02 03:25:59 PM PDT 24
Peak memory 275464 kb
Host smart-b0cb198d-1640-4387-96f9-35eac5ffd45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657810389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1657810389
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.3901001232
Short name T472
Test name
Test status
Simulation time 37802400 ps
CPU time 128.52 seconds
Started Jun 02 03:25:45 PM PDT 24
Finished Jun 02 03:27:54 PM PDT 24
Peak memory 259544 kb
Host smart-8635db16-4fcd-4e0a-96fc-466d2b5edf17
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901001232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.3901001232
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.4285471195
Short name T17
Test name
Test status
Simulation time 17959500 ps
CPU time 15.87 seconds
Started Jun 02 03:25:42 PM PDT 24
Finished Jun 02 03:25:58 PM PDT 24
Peak memory 274732 kb
Host smart-68fbe7c6-4cae-4311-9588-46315477fff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285471195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.4285471195
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.2323017418
Short name T937
Test name
Test status
Simulation time 68316500 ps
CPU time 133.12 seconds
Started Jun 02 03:25:43 PM PDT 24
Finished Jun 02 03:27:56 PM PDT 24
Peak memory 259824 kb
Host smart-3d18c0b0-0b6b-486b-ae16-7a924748a2fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323017418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.2323017418
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.4205641517
Short name T656
Test name
Test status
Simulation time 15792400 ps
CPU time 15.6 seconds
Started Jun 02 03:25:49 PM PDT 24
Finished Jun 02 03:26:06 PM PDT 24
Peak memory 275912 kb
Host smart-6693afef-9504-422f-9a2e-8a337142a0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205641517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.4205641517
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.3243784598
Short name T998
Test name
Test status
Simulation time 102510200 ps
CPU time 110.66 seconds
Started Jun 02 03:25:43 PM PDT 24
Finished Jun 02 03:27:34 PM PDT 24
Peak memory 260772 kb
Host smart-7141b30f-7439-47c5-9573-8ab7c2b7bd82
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243784598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.3243784598
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.3630752485
Short name T973
Test name
Test status
Simulation time 38696400 ps
CPU time 13.9 seconds
Started Jun 02 03:20:48 PM PDT 24
Finished Jun 02 03:21:03 PM PDT 24
Peak memory 264780 kb
Host smart-37552bae-1cbc-4005-a7e5-25080efb7e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630752485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.3
630752485
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.979215095
Short name T212
Test name
Test status
Simulation time 15565500 ps
CPU time 13.26 seconds
Started Jun 02 03:20:47 PM PDT 24
Finished Jun 02 03:21:01 PM PDT 24
Peak memory 275416 kb
Host smart-7af7274d-8c74-473b-85f4-9e6177ca5bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979215095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.979215095
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.3590489584
Short name T40
Test name
Test status
Simulation time 116107500 ps
CPU time 20.49 seconds
Started Jun 02 03:20:47 PM PDT 24
Finished Jun 02 03:21:08 PM PDT 24
Peak memory 273092 kb
Host smart-037ffa27-2bd3-4585-a515-870c66c777ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590489584 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.3590489584
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.3406506040
Short name T730
Test name
Test status
Simulation time 112724643200 ps
CPU time 2797.17 seconds
Started Jun 02 03:20:34 PM PDT 24
Finished Jun 02 04:07:13 PM PDT 24
Peak memory 264020 kb
Host smart-368d7f1f-feeb-4e73-a626-c0f37b0d3bae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406506040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.3406506040
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.3517010743
Short name T854
Test name
Test status
Simulation time 835694500 ps
CPU time 847.93 seconds
Started Jun 02 03:20:35 PM PDT 24
Finished Jun 02 03:34:44 PM PDT 24
Peak memory 273000 kb
Host smart-9a56293c-5b85-4011-b382-feed928cabb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517010743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3517010743
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.616002941
Short name T50
Test name
Test status
Simulation time 314057300 ps
CPU time 27.06 seconds
Started Jun 02 03:20:34 PM PDT 24
Finished Jun 02 03:21:02 PM PDT 24
Peak memory 264824 kb
Host smart-b05c959a-eda1-43b9-9a2b-5f053b3d5a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616002941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.616002941
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.450370599
Short name T819
Test name
Test status
Simulation time 10032353600 ps
CPU time 60.29 seconds
Started Jun 02 03:20:47 PM PDT 24
Finished Jun 02 03:21:48 PM PDT 24
Peak memory 293640 kb
Host smart-906903f8-97a9-4ab8-8e00-fe36f77f1f56
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450370599 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.450370599
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.2436937712
Short name T419
Test name
Test status
Simulation time 20796800 ps
CPU time 13.37 seconds
Started Jun 02 03:20:48 PM PDT 24
Finished Jun 02 03:21:02 PM PDT 24
Peak memory 258084 kb
Host smart-291ea12a-4f8f-4719-bca2-f2c79a5effe0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436937712 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.2436937712
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.3006032634
Short name T531
Test name
Test status
Simulation time 80147934900 ps
CPU time 824.31 seconds
Started Jun 02 03:20:32 PM PDT 24
Finished Jun 02 03:34:16 PM PDT 24
Peak memory 262864 kb
Host smart-7bef53d4-8d66-42c7-9333-4fdc57c9a2fb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006032634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.3006032634
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.827821245
Short name T202
Test name
Test status
Simulation time 6035138500 ps
CPU time 251.78 seconds
Started Jun 02 03:20:29 PM PDT 24
Finished Jun 02 03:24:42 PM PDT 24
Peak memory 262240 kb
Host smart-3d8a8f47-1362-4f74-a345-cbe9283c6200
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827821245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw
_sec_otp.827821245
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3758827079
Short name T357
Test name
Test status
Simulation time 12198106100 ps
CPU time 283.13 seconds
Started Jun 02 03:20:40 PM PDT 24
Finished Jun 02 03:25:24 PM PDT 24
Peak memory 292976 kb
Host smart-2d29cf6f-8a77-4631-bbd3-703ef03fdde8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758827079 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.3758827079
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.3243299858
Short name T479
Test name
Test status
Simulation time 9208376200 ps
CPU time 70.78 seconds
Started Jun 02 03:20:41 PM PDT 24
Finished Jun 02 03:21:53 PM PDT 24
Peak memory 264880 kb
Host smart-f488a909-5161-4fc0-8893-96b0d5f92735
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243299858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.3243299858
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1525805989
Short name T994
Test name
Test status
Simulation time 65693291500 ps
CPU time 225.74 seconds
Started Jun 02 03:20:41 PM PDT 24
Finished Jun 02 03:24:28 PM PDT 24
Peak memory 264772 kb
Host smart-78588a8d-c53b-4c3b-8540-209e3495f806
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152
5805989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.1525805989
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.2707034869
Short name T1009
Test name
Test status
Simulation time 4583820700 ps
CPU time 66.02 seconds
Started Jun 02 03:20:36 PM PDT 24
Finished Jun 02 03:21:43 PM PDT 24
Peak memory 260448 kb
Host smart-c9de5e32-3461-4588-8d97-6866b11e6386
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707034869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2707034869
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.472693779
Short name T120
Test name
Test status
Simulation time 15509600 ps
CPU time 13.55 seconds
Started Jun 02 03:20:46 PM PDT 24
Finished Jun 02 03:21:00 PM PDT 24
Peak memory 259204 kb
Host smart-0e0e58b0-b0c7-46f8-a50c-e1bc9e754114
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472693779 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.472693779
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.1562253985
Short name T94
Test name
Test status
Simulation time 46552428700 ps
CPU time 341.04 seconds
Started Jun 02 03:20:34 PM PDT 24
Finished Jun 02 03:26:16 PM PDT 24
Peak memory 273156 kb
Host smart-e47c68d3-5b04-45b0-9edd-f6f96c78916b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562253985 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.1562253985
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.1147125630
Short name T624
Test name
Test status
Simulation time 46744500 ps
CPU time 132.89 seconds
Started Jun 02 03:20:28 PM PDT 24
Finished Jun 02 03:22:42 PM PDT 24
Peak memory 260868 kb
Host smart-1b678247-7799-48b4-b9c0-938c36458aa2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147125630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.1147125630
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.900163935
Short name T880
Test name
Test status
Simulation time 9931127900 ps
CPU time 534.39 seconds
Started Jun 02 03:20:28 PM PDT 24
Finished Jun 02 03:29:24 PM PDT 24
Peak memory 264856 kb
Host smart-8779ba4d-4d37-4822-842b-9d3c91f0c5c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=900163935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.900163935
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.4060733630
Short name T725
Test name
Test status
Simulation time 21667400 ps
CPU time 13.38 seconds
Started Jun 02 03:20:40 PM PDT 24
Finished Jun 02 03:20:54 PM PDT 24
Peak memory 258336 kb
Host smart-ae7777e2-5321-4996-9982-be677921ad23
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060733630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.4060733630
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.1368646888
Short name T896
Test name
Test status
Simulation time 463588300 ps
CPU time 946.56 seconds
Started Jun 02 03:20:28 PM PDT 24
Finished Jun 02 03:36:16 PM PDT 24
Peak memory 287312 kb
Host smart-acbefeba-98d9-4d2b-a95c-ecc66e840f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368646888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.1368646888
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.2711080360
Short name T286
Test name
Test status
Simulation time 117796300 ps
CPU time 35.29 seconds
Started Jun 02 03:20:46 PM PDT 24
Finished Jun 02 03:21:22 PM PDT 24
Peak memory 266968 kb
Host smart-458e7d3f-0fec-4c5b-a677-24cf57a96edf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711080360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.2711080360
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.1936181808
Short name T59
Test name
Test status
Simulation time 2083727000 ps
CPU time 102.01 seconds
Started Jun 02 03:20:34 PM PDT 24
Finished Jun 02 03:22:17 PM PDT 24
Peak memory 288856 kb
Host smart-f2158652-2280-47c7-a9db-2ea8f70487aa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936181808 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.1936181808
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.1091041542
Short name T695
Test name
Test status
Simulation time 744527200 ps
CPU time 143.41 seconds
Started Jun 02 03:20:41 PM PDT 24
Finished Jun 02 03:23:05 PM PDT 24
Peak memory 281808 kb
Host smart-42512a35-fe34-45bf-be83-3b0426fd935c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1091041542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.1091041542
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.3382636397
Short name T538
Test name
Test status
Simulation time 1957906500 ps
CPU time 111.37 seconds
Started Jun 02 03:20:42 PM PDT 24
Finished Jun 02 03:22:33 PM PDT 24
Peak memory 281272 kb
Host smart-b724ff9f-b8a7-4096-8167-bfedb9b38d18
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382636397 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.3382636397
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.2571998538
Short name T579
Test name
Test status
Simulation time 3413271900 ps
CPU time 420.3 seconds
Started Jun 02 03:20:40 PM PDT 24
Finished Jun 02 03:27:41 PM PDT 24
Peak memory 309024 kb
Host smart-cf43744e-cabc-4883-a296-dc11df7a983f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571998538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.flash_ctrl_rw.2571998538
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.438875793
Short name T733
Test name
Test status
Simulation time 72441100 ps
CPU time 28.23 seconds
Started Jun 02 03:20:42 PM PDT 24
Finished Jun 02 03:21:11 PM PDT 24
Peak memory 273100 kb
Host smart-c31fcc33-6f1b-4c1f-9789-2455563071d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438875793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_rw_evict.438875793
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.3364135074
Short name T408
Test name
Test status
Simulation time 3406919900 ps
CPU time 70.31 seconds
Started Jun 02 03:20:47 PM PDT 24
Finished Jun 02 03:21:58 PM PDT 24
Peak memory 262104 kb
Host smart-02b19da5-f50f-4112-96ee-147c327015fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364135074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.3364135074
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.402207587
Short name T155
Test name
Test status
Simulation time 197125300 ps
CPU time 172.16 seconds
Started Jun 02 03:20:32 PM PDT 24
Finished Jun 02 03:23:24 PM PDT 24
Peak memory 278572 kb
Host smart-8acac73b-dbff-4ea5-b3e4-9958ad4af6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402207587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.402207587
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.3803590441
Short name T89
Test name
Test status
Simulation time 33137791200 ps
CPU time 172.2 seconds
Started Jun 02 03:20:35 PM PDT 24
Finished Jun 02 03:23:28 PM PDT 24
Peak memory 259232 kb
Host smart-083cdfb6-beda-4329-ac8f-d5ea8690969c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803590441 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.flash_ctrl_wo.3803590441
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.4065275282
Short name T793
Test name
Test status
Simulation time 14792300 ps
CPU time 13.13 seconds
Started Jun 02 03:25:47 PM PDT 24
Finished Jun 02 03:26:01 PM PDT 24
Peak memory 275788 kb
Host smart-28a5edef-15ac-4431-a95e-ff10b8c92e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065275282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.4065275282
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.3142674567
Short name T898
Test name
Test status
Simulation time 133448600 ps
CPU time 129.85 seconds
Started Jun 02 03:25:47 PM PDT 24
Finished Jun 02 03:27:57 PM PDT 24
Peak memory 264776 kb
Host smart-9283b149-5701-4f1f-8ae9-e85242a231bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142674567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.3142674567
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.1042462476
Short name T466
Test name
Test status
Simulation time 80247100 ps
CPU time 15.93 seconds
Started Jun 02 03:25:49 PM PDT 24
Finished Jun 02 03:26:06 PM PDT 24
Peak memory 275572 kb
Host smart-fd080d31-2417-4f01-8ba9-822c5a64b0e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042462476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.1042462476
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.131865440
Short name T530
Test name
Test status
Simulation time 408943200 ps
CPU time 133.52 seconds
Started Jun 02 03:25:46 PM PDT 24
Finished Jun 02 03:28:00 PM PDT 24
Peak memory 259780 kb
Host smart-f75c4130-3cd7-4dfb-9b05-fa5b4687bb3a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131865440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_ot
p_reset.131865440
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.3122742302
Short name T497
Test name
Test status
Simulation time 38148700 ps
CPU time 15.53 seconds
Started Jun 02 03:25:52 PM PDT 24
Finished Jun 02 03:26:08 PM PDT 24
Peak memory 275536 kb
Host smart-6732d659-3089-4273-85b3-3dda25a84f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122742302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.3122742302
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.3265609911
Short name T133
Test name
Test status
Simulation time 140115100 ps
CPU time 111.72 seconds
Started Jun 02 03:25:52 PM PDT 24
Finished Jun 02 03:27:44 PM PDT 24
Peak memory 260924 kb
Host smart-b77cb395-bb68-47be-9a99-092e355176d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265609911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.3265609911
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.1337157825
Short name T1055
Test name
Test status
Simulation time 16827300 ps
CPU time 15.62 seconds
Started Jun 02 03:25:48 PM PDT 24
Finished Jun 02 03:26:04 PM PDT 24
Peak memory 275072 kb
Host smart-a804cc56-5922-4c8b-aa81-5f218dcaef29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337157825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.1337157825
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.1508694927
Short name T738
Test name
Test status
Simulation time 63865900 ps
CPU time 129.69 seconds
Started Jun 02 03:25:52 PM PDT 24
Finished Jun 02 03:28:02 PM PDT 24
Peak memory 260772 kb
Host smart-b6af07cb-1161-4ec2-9f42-79b3fca83985
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508694927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.1508694927
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.262052269
Short name T453
Test name
Test status
Simulation time 34711500 ps
CPU time 15.87 seconds
Started Jun 02 03:25:48 PM PDT 24
Finished Jun 02 03:26:04 PM PDT 24
Peak memory 275804 kb
Host smart-fdc0ef5b-aa90-40a0-8411-39ea7387fad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262052269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.262052269
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.2660083851
Short name T807
Test name
Test status
Simulation time 135795100 ps
CPU time 135.11 seconds
Started Jun 02 03:25:47 PM PDT 24
Finished Jun 02 03:28:03 PM PDT 24
Peak memory 259776 kb
Host smart-cdc17075-439e-4791-ad95-39e8310406c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660083851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.2660083851
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.500897743
Short name T804
Test name
Test status
Simulation time 16268500 ps
CPU time 13.44 seconds
Started Jun 02 03:25:54 PM PDT 24
Finished Jun 02 03:26:08 PM PDT 24
Peak memory 275876 kb
Host smart-e2242425-55c0-4ce7-818b-33491fd542e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500897743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.500897743
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.2822898347
Short name T887
Test name
Test status
Simulation time 40351400 ps
CPU time 133.9 seconds
Started Jun 02 03:25:55 PM PDT 24
Finished Jun 02 03:28:10 PM PDT 24
Peak memory 259932 kb
Host smart-e969f5f0-e16d-42ed-9a22-39d8de4040ae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822898347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.2822898347
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.1293764688
Short name T908
Test name
Test status
Simulation time 13799000 ps
CPU time 15.6 seconds
Started Jun 02 03:25:54 PM PDT 24
Finished Jun 02 03:26:11 PM PDT 24
Peak memory 275712 kb
Host smart-a5493772-2746-4502-a8aa-aea16e1c8199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293764688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.1293764688
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.195392579
Short name T1068
Test name
Test status
Simulation time 41149500 ps
CPU time 113.3 seconds
Started Jun 02 03:25:55 PM PDT 24
Finished Jun 02 03:27:48 PM PDT 24
Peak memory 261932 kb
Host smart-e2e17e46-1d5d-42c0-8dc3-b5e83bb2174f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195392579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_ot
p_reset.195392579
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.1253185720
Short name T915
Test name
Test status
Simulation time 24889000 ps
CPU time 15.8 seconds
Started Jun 02 03:25:57 PM PDT 24
Finished Jun 02 03:26:13 PM PDT 24
Peak memory 275836 kb
Host smart-4abb8412-729b-4aa8-987f-8d46cedcfb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253185720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.1253185720
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.1128824171
Short name T244
Test name
Test status
Simulation time 679350100 ps
CPU time 111.08 seconds
Started Jun 02 03:25:54 PM PDT 24
Finished Jun 02 03:27:46 PM PDT 24
Peak memory 260988 kb
Host smart-f2e5ee7b-6bf5-4443-9e13-2a4de840889f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128824171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.1128824171
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.1134290095
Short name T211
Test name
Test status
Simulation time 18656400 ps
CPU time 16.29 seconds
Started Jun 02 03:25:55 PM PDT 24
Finished Jun 02 03:26:12 PM PDT 24
Peak memory 274796 kb
Host smart-e206b1d4-b108-463d-b822-71ab3f65a517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134290095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.1134290095
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.876173123
Short name T122
Test name
Test status
Simulation time 79154900 ps
CPU time 129.61 seconds
Started Jun 02 03:25:54 PM PDT 24
Finished Jun 02 03:28:04 PM PDT 24
Peak memory 264432 kb
Host smart-43cc4e24-4783-4c0c-b001-87150c2ac5f2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876173123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_ot
p_reset.876173123
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.1491650026
Short name T894
Test name
Test status
Simulation time 45537000 ps
CPU time 15.75 seconds
Started Jun 02 03:25:54 PM PDT 24
Finished Jun 02 03:26:10 PM PDT 24
Peak memory 274932 kb
Host smart-a60cef64-d970-4aa7-8ae3-577fcf243166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491650026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.1491650026
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.1783976500
Short name T445
Test name
Test status
Simulation time 92924900 ps
CPU time 133.27 seconds
Started Jun 02 03:25:54 PM PDT 24
Finished Jun 02 03:28:08 PM PDT 24
Peak memory 260068 kb
Host smart-b0ef9cd2-3f45-4fe7-99d4-eceb832ba34d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783976500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.1783976500
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.1364977318
Short name T654
Test name
Test status
Simulation time 46124400 ps
CPU time 13.51 seconds
Started Jun 02 03:21:06 PM PDT 24
Finished Jun 02 03:21:20 PM PDT 24
Peak memory 264764 kb
Host smart-869e1f3e-f895-45cd-b3df-7f522b7e9667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364977318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.1
364977318
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.569030370
Short name T482
Test name
Test status
Simulation time 15156100 ps
CPU time 15.75 seconds
Started Jun 02 03:21:09 PM PDT 24
Finished Jun 02 03:21:25 PM PDT 24
Peak memory 275528 kb
Host smart-2086a577-0613-462e-8a7d-169c821f423d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569030370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.569030370
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.1511274186
Short name T374
Test name
Test status
Simulation time 24723900 ps
CPU time 20.34 seconds
Started Jun 02 03:21:06 PM PDT 24
Finished Jun 02 03:21:27 PM PDT 24
Peak memory 273292 kb
Host smart-a62e14f6-e92b-4718-9d6b-adb748fc7137
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511274186 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.1511274186
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.3198694367
Short name T42
Test name
Test status
Simulation time 2873778700 ps
CPU time 2252.43 seconds
Started Jun 02 03:20:54 PM PDT 24
Finished Jun 02 03:58:27 PM PDT 24
Peak memory 264232 kb
Host smart-06838cfb-4f58-4551-9476-c499f9139f67
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198694367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.3198694367
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.1658518699
Short name T884
Test name
Test status
Simulation time 741560000 ps
CPU time 960.89 seconds
Started Jun 02 03:20:53 PM PDT 24
Finished Jun 02 03:36:55 PM PDT 24
Peak memory 269912 kb
Host smart-a72e5703-c9c4-41eb-a92f-5a6186464189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658518699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.1658518699
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.2420089994
Short name T892
Test name
Test status
Simulation time 1102429600 ps
CPU time 22.99 seconds
Started Jun 02 03:20:53 PM PDT 24
Finished Jun 02 03:21:16 PM PDT 24
Peak memory 264952 kb
Host smart-fb2a7edc-5d40-41a9-b894-a2765b65ef38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420089994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.2420089994
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1791528973
Short name T845
Test name
Test status
Simulation time 10033294500 ps
CPU time 53.5 seconds
Started Jun 02 03:21:07 PM PDT 24
Finished Jun 02 03:22:01 PM PDT 24
Peak memory 269036 kb
Host smart-b972b603-e3ca-4062-bec7-3b6b6a65d995
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791528973 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.1791528973
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.1042631330
Short name T1051
Test name
Test status
Simulation time 15741800 ps
CPU time 13.49 seconds
Started Jun 02 03:21:06 PM PDT 24
Finished Jun 02 03:21:20 PM PDT 24
Peak memory 258056 kb
Host smart-8ff4ea6f-d99c-48aa-a99c-c06b7d6a0b68
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042631330 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.1042631330
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.2929842853
Short name T142
Test name
Test status
Simulation time 170205901300 ps
CPU time 800.38 seconds
Started Jun 02 03:20:47 PM PDT 24
Finished Jun 02 03:34:08 PM PDT 24
Peak memory 263108 kb
Host smart-220f52c3-fb9d-4ccf-bd05-0d7c9d7b99cd
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929842853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.2929842853
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.1980321556
Short name T417
Test name
Test status
Simulation time 2124579200 ps
CPU time 132.66 seconds
Started Jun 02 03:20:47 PM PDT 24
Finished Jun 02 03:23:00 PM PDT 24
Peak memory 262288 kb
Host smart-9e3ab81f-5d23-488a-b134-35a16ac3761b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980321556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.1980321556
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.384171599
Short name T918
Test name
Test status
Simulation time 13381971400 ps
CPU time 220.94 seconds
Started Jun 02 03:20:59 PM PDT 24
Finished Jun 02 03:24:41 PM PDT 24
Peak memory 289468 kb
Host smart-ef6f3d40-6620-424c-abe1-7ce890feb144
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384171599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_intr_rd.384171599
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.4180668295
Short name T354
Test name
Test status
Simulation time 30980548800 ps
CPU time 341.72 seconds
Started Jun 02 03:21:00 PM PDT 24
Finished Jun 02 03:26:42 PM PDT 24
Peak memory 292976 kb
Host smart-68152007-3720-4ffb-9603-cd6b342e4183
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180668295 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.4180668295
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.793209650
Short name T29
Test name
Test status
Simulation time 4059502500 ps
CPU time 76.34 seconds
Started Jun 02 03:21:00 PM PDT 24
Finished Jun 02 03:22:17 PM PDT 24
Peak memory 264836 kb
Host smart-e9a3b243-2d5a-498d-99aa-1a77e4210c5d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793209650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.flash_ctrl_intr_wr.793209650
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.1728147541
Short name T692
Test name
Test status
Simulation time 78133739200 ps
CPU time 257.43 seconds
Started Jun 02 03:21:00 PM PDT 24
Finished Jun 02 03:25:18 PM PDT 24
Peak memory 264844 kb
Host smart-78c3bed7-8875-40f8-a223-fcb0fc5c4e6d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172
8147541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.1728147541
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.1149404133
Short name T574
Test name
Test status
Simulation time 3270922300 ps
CPU time 70.62 seconds
Started Jun 02 03:20:54 PM PDT 24
Finished Jun 02 03:22:05 PM PDT 24
Peak memory 260296 kb
Host smart-c38f59eb-a095-495a-988f-c4cd362a00e6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149404133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.1149404133
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.36724501
Short name T1004
Test name
Test status
Simulation time 15091800 ps
CPU time 13.58 seconds
Started Jun 02 03:21:06 PM PDT 24
Finished Jun 02 03:21:20 PM PDT 24
Peak memory 264764 kb
Host smart-8ed53e1e-7824-4384-a618-22b7ed5e903c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36724501 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.36724501
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.2563581692
Short name T112
Test name
Test status
Simulation time 46798641200 ps
CPU time 242.77 seconds
Started Jun 02 03:20:52 PM PDT 24
Finished Jun 02 03:24:55 PM PDT 24
Peak memory 274052 kb
Host smart-7addf4c0-f0f4-4060-8a28-0e7ca56e7dd2
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563581692 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.2563581692
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.3181966306
Short name T146
Test name
Test status
Simulation time 159278900 ps
CPU time 133.2 seconds
Started Jun 02 03:20:53 PM PDT 24
Finished Jun 02 03:23:06 PM PDT 24
Peak memory 263400 kb
Host smart-2f352862-1ebd-4d9b-92cf-631e1fad0783
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181966306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.3181966306
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.3957631899
Short name T962
Test name
Test status
Simulation time 60233600 ps
CPU time 111.56 seconds
Started Jun 02 03:20:48 PM PDT 24
Finished Jun 02 03:22:40 PM PDT 24
Peak memory 262248 kb
Host smart-d18d9dd1-d420-4e02-848c-b0aee02ecce6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3957631899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3957631899
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.3247041726
Short name T56
Test name
Test status
Simulation time 38869400 ps
CPU time 14.17 seconds
Started Jun 02 03:20:59 PM PDT 24
Finished Jun 02 03:21:14 PM PDT 24
Peak memory 264688 kb
Host smart-1bb9e407-17b8-479f-a7c8-391393aa4fba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247041726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.3247041726
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.877997594
Short name T118
Test name
Test status
Simulation time 433633000 ps
CPU time 1306.16 seconds
Started Jun 02 03:20:46 PM PDT 24
Finished Jun 02 03:42:33 PM PDT 24
Peak memory 286892 kb
Host smart-75d1f2d3-8ff3-4a89-a820-cb5300ae31d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877997594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.877997594
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.742300376
Short name T101
Test name
Test status
Simulation time 116128300 ps
CPU time 39.38 seconds
Started Jun 02 03:21:06 PM PDT 24
Finished Jun 02 03:21:46 PM PDT 24
Peak memory 273192 kb
Host smart-5baf031b-8ba7-4c1d-bfc3-a20ff9730595
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742300376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_re_evict.742300376
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.3272898539
Short name T291
Test name
Test status
Simulation time 1732837300 ps
CPU time 92.96 seconds
Started Jun 02 03:20:53 PM PDT 24
Finished Jun 02 03:22:26 PM PDT 24
Peak memory 281272 kb
Host smart-6d18ec56-dbf2-4582-bf58-af9d40dac6a3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272898539 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_ro.3272898539
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.2440259457
Short name T722
Test name
Test status
Simulation time 578209900 ps
CPU time 161.12 seconds
Started Jun 02 03:21:00 PM PDT 24
Finished Jun 02 03:23:42 PM PDT 24
Peak memory 281240 kb
Host smart-e2cb5dc2-007c-4052-9994-82dbd7cbcc7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2440259457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2440259457
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.3758754589
Short name T193
Test name
Test status
Simulation time 1089284800 ps
CPU time 114.22 seconds
Started Jun 02 03:20:52 PM PDT 24
Finished Jun 02 03:22:47 PM PDT 24
Peak memory 281188 kb
Host smart-73b5d83f-503e-4d95-b9e2-00c85984316d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758754589 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.3758754589
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.2568983732
Short name T659
Test name
Test status
Simulation time 13833723900 ps
CPU time 654.35 seconds
Started Jun 02 03:21:00 PM PDT 24
Finished Jun 02 03:31:55 PM PDT 24
Peak memory 335232 kb
Host smart-db6f7759-4da0-4096-940a-797bf7b754e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568983732 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_rw_derr.2568983732
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.1892278995
Short name T848
Test name
Test status
Simulation time 49261800 ps
CPU time 31.67 seconds
Started Jun 02 03:21:00 PM PDT 24
Finished Jun 02 03:21:32 PM PDT 24
Peak memory 273096 kb
Host smart-88c8b791-fc32-4923-82f3-d916f78cc832
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892278995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.1892278995
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.694940093
Short name T891
Test name
Test status
Simulation time 4128349100 ps
CPU time 86.92 seconds
Started Jun 02 03:21:06 PM PDT 24
Finished Jun 02 03:22:33 PM PDT 24
Peak memory 263516 kb
Host smart-677ce34d-e85b-4259-b4a9-9d399bcbe4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694940093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.694940093
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.1264618173
Short name T257
Test name
Test status
Simulation time 24303400 ps
CPU time 75.39 seconds
Started Jun 02 03:20:49 PM PDT 24
Finished Jun 02 03:22:04 PM PDT 24
Peak memory 275148 kb
Host smart-dd4c2e8b-ae7c-44cb-9d67-700753652c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264618173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.1264618173
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.1775549286
Short name T103
Test name
Test status
Simulation time 7173206700 ps
CPU time 183.43 seconds
Started Jun 02 03:20:54 PM PDT 24
Finished Jun 02 03:23:57 PM PDT 24
Peak memory 258880 kb
Host smart-54fffbb3-b299-4a76-b531-ce007ac37fa3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775549286 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.flash_ctrl_wo.1775549286
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.1291542457
Short name T578
Test name
Test status
Simulation time 57311900 ps
CPU time 13.47 seconds
Started Jun 02 03:21:22 PM PDT 24
Finished Jun 02 03:21:36 PM PDT 24
Peak memory 264804 kb
Host smart-2827f391-fc0f-4e57-8879-a306e8c1d924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291542457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.1
291542457
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.854877101
Short name T954
Test name
Test status
Simulation time 47296200 ps
CPU time 15.72 seconds
Started Jun 02 03:21:21 PM PDT 24
Finished Jun 02 03:21:37 PM PDT 24
Peak memory 275632 kb
Host smart-acaaa00c-2356-4e97-a50e-08a4bf04b27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854877101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.854877101
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.2015304676
Short name T469
Test name
Test status
Simulation time 11909900 ps
CPU time 21.43 seconds
Started Jun 02 03:21:20 PM PDT 24
Finished Jun 02 03:21:42 PM PDT 24
Peak memory 273068 kb
Host smart-7dc13bd5-6d1d-4062-bf64-63a471bcd091
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015304676 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.2015304676
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.3627248520
Short name T799
Test name
Test status
Simulation time 7316122700 ps
CPU time 2440.95 seconds
Started Jun 02 03:21:14 PM PDT 24
Finished Jun 02 04:01:55 PM PDT 24
Peak memory 264900 kb
Host smart-7e4f12a3-bbca-4122-bd9f-5ecca82d05d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627248520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.3627248520
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.2626180282
Short name T300
Test name
Test status
Simulation time 794448900 ps
CPU time 1127.69 seconds
Started Jun 02 03:21:14 PM PDT 24
Finished Jun 02 03:40:02 PM PDT 24
Peak memory 273012 kb
Host smart-41e7ba47-c44e-4f52-b042-df0733df652c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626180282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.2626180282
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.4073910867
Short name T47
Test name
Test status
Simulation time 168668900 ps
CPU time 25.41 seconds
Started Jun 02 03:21:14 PM PDT 24
Finished Jun 02 03:21:40 PM PDT 24
Peak memory 264876 kb
Host smart-58094835-5732-44d5-a38a-cd3bdf869080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073910867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.4073910867
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.3846734548
Short name T256
Test name
Test status
Simulation time 10019620500 ps
CPU time 79.94 seconds
Started Jun 02 03:21:19 PM PDT 24
Finished Jun 02 03:22:40 PM PDT 24
Peak memory 313908 kb
Host smart-f9e33f60-b9d6-4e90-9d43-027c5e926369
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846734548 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.3846734548
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.3438626456
Short name T293
Test name
Test status
Simulation time 95748900 ps
CPU time 13.71 seconds
Started Jun 02 03:21:23 PM PDT 24
Finished Jun 02 03:21:37 PM PDT 24
Peak memory 258052 kb
Host smart-7694088f-1df5-4349-8254-5d1faafe3c64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438626456 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.3438626456
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.83147496
Short name T153
Test name
Test status
Simulation time 80148786200 ps
CPU time 864.77 seconds
Started Jun 02 03:21:05 PM PDT 24
Finished Jun 02 03:35:30 PM PDT 24
Peak memory 264092 kb
Host smart-e2eda4b6-1d61-4cbf-a04e-e4a7323f1c55
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83147496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 9.flash_ctrl_hw_rma_reset.83147496
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.2961327668
Short name T324
Test name
Test status
Simulation time 4915673900 ps
CPU time 269.15 seconds
Started Jun 02 03:21:06 PM PDT 24
Finished Jun 02 03:25:35 PM PDT 24
Peak memory 262372 kb
Host smart-f71529ae-2ac1-40cc-8f6a-05ddee440119
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961327668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.2961327668
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.3300685945
Short name T584
Test name
Test status
Simulation time 1704753200 ps
CPU time 128.43 seconds
Started Jun 02 03:21:14 PM PDT 24
Finished Jun 02 03:23:23 PM PDT 24
Peak memory 291932 kb
Host smart-a4235803-3ee9-402e-bb5f-bf8516316c8a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300685945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.3300685945
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.285889440
Short name T326
Test name
Test status
Simulation time 75397232900 ps
CPU time 274.2 seconds
Started Jun 02 03:21:14 PM PDT 24
Finished Jun 02 03:25:49 PM PDT 24
Peak memory 291772 kb
Host smart-dd05647d-7da8-49a8-86ef-40729036c451
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285889440 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.285889440
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.2980503210
Short name T28
Test name
Test status
Simulation time 6368674100 ps
CPU time 66.73 seconds
Started Jun 02 03:21:13 PM PDT 24
Finished Jun 02 03:22:20 PM PDT 24
Peak memory 258960 kb
Host smart-619d2318-700b-42ff-8447-88fb0bf79ef4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980503210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.2980503210
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.115610811
Short name T762
Test name
Test status
Simulation time 19428071600 ps
CPU time 157.8 seconds
Started Jun 02 03:21:21 PM PDT 24
Finished Jun 02 03:23:59 PM PDT 24
Peak memory 259948 kb
Host smart-c64454d6-9307-440b-bb7b-950dd761ede5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115
610811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.115610811
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.934537139
Short name T1067
Test name
Test status
Simulation time 2104521500 ps
CPU time 66.8 seconds
Started Jun 02 03:21:14 PM PDT 24
Finished Jun 02 03:22:21 PM PDT 24
Peak memory 260324 kb
Host smart-6b9a9550-adcc-498b-921f-b3ec00f6d3ce
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934537139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.934537139
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.950049365
Short name T948
Test name
Test status
Simulation time 1697203400 ps
CPU time 165.31 seconds
Started Jun 02 03:21:14 PM PDT 24
Finished Jun 02 03:24:00 PM PDT 24
Peak memory 262500 kb
Host smart-ca5dd6f8-c07f-49d5-b003-d95bba416c31
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950049365 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_mp_regions.950049365
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.631410480
Short name T447
Test name
Test status
Simulation time 138550100 ps
CPU time 132.37 seconds
Started Jun 02 03:21:15 PM PDT 24
Finished Jun 02 03:23:28 PM PDT 24
Peak memory 259552 kb
Host smart-f6e5b1ae-ac22-4d81-ba38-9ed4e9eb8d4f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631410480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp
_reset.631410480
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.1849210272
Short name T175
Test name
Test status
Simulation time 501629200 ps
CPU time 149.42 seconds
Started Jun 02 03:21:05 PM PDT 24
Finished Jun 02 03:23:35 PM PDT 24
Peak memory 262256 kb
Host smart-4f28a61c-7c45-4a64-bb2b-87f59466334b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849210272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.1849210272
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.3703011183
Short name T64
Test name
Test status
Simulation time 4904983500 ps
CPU time 159.59 seconds
Started Jun 02 03:21:19 PM PDT 24
Finished Jun 02 03:23:59 PM PDT 24
Peak memory 259260 kb
Host smart-7cb9c9eb-7f7f-47aa-8b95-53dd7079f545
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703011183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.3703011183
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.2983715802
Short name T1027
Test name
Test status
Simulation time 668920000 ps
CPU time 651.88 seconds
Started Jun 02 03:21:07 PM PDT 24
Finished Jun 02 03:31:59 PM PDT 24
Peak memory 281772 kb
Host smart-f432d2d5-0a06-459b-a74a-0811d2dd9f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983715802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.2983715802
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.1680975250
Short name T778
Test name
Test status
Simulation time 199382800 ps
CPU time 34.84 seconds
Started Jun 02 03:21:23 PM PDT 24
Finished Jun 02 03:21:58 PM PDT 24
Peak memory 274084 kb
Host smart-f3aae567-0e67-4527-b5ab-97e0443e2d43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680975250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.1680975250
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.3435765043
Short name T191
Test name
Test status
Simulation time 488847900 ps
CPU time 125.5 seconds
Started Jun 02 03:21:14 PM PDT 24
Finished Jun 02 03:23:20 PM PDT 24
Peak memory 281244 kb
Host smart-3cfd65db-f138-4abf-82f3-e7634ba82de6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435765043 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_ro.3435765043
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.2965035626
Short name T36
Test name
Test status
Simulation time 3970833100 ps
CPU time 170.85 seconds
Started Jun 02 03:21:14 PM PDT 24
Finished Jun 02 03:24:06 PM PDT 24
Peak memory 281716 kb
Host smart-9b86ffce-548d-46bf-b3c9-146ee9911b43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2965035626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.2965035626
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.1522169448
Short name T597
Test name
Test status
Simulation time 613974800 ps
CPU time 160.75 seconds
Started Jun 02 03:21:14 PM PDT 24
Finished Jun 02 03:23:56 PM PDT 24
Peak memory 293696 kb
Host smart-8041f60e-c725-4bd2-b26c-3f66f9cabe24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522169448 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.1522169448
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.1413944927
Short name T178
Test name
Test status
Simulation time 11639582500 ps
CPU time 578.11 seconds
Started Jun 02 03:21:16 PM PDT 24
Finished Jun 02 03:30:55 PM PDT 24
Peak memory 309172 kb
Host smart-2ae4d0a0-3334-4e39-9545-46fd0494601f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413944927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.flash_ctrl_rw.1413944927
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.80894911
Short name T576
Test name
Test status
Simulation time 43386500 ps
CPU time 28.01 seconds
Started Jun 02 03:21:20 PM PDT 24
Finished Jun 02 03:21:48 PM PDT 24
Peak memory 275764 kb
Host smart-d7da85c5-3e5c-4875-979d-4f925d96fb74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80894911 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.80894911
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.2605681877
Short name T1065
Test name
Test status
Simulation time 17605275600 ps
CPU time 636.2 seconds
Started Jun 02 03:21:15 PM PDT 24
Finished Jun 02 03:31:52 PM PDT 24
Peak memory 319852 kb
Host smart-23df572b-cffa-4f09-98fb-a108539e165b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605681877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s
err.2605681877
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.45405856
Short name T391
Test name
Test status
Simulation time 1976842700 ps
CPU time 71.83 seconds
Started Jun 02 03:21:18 PM PDT 24
Finished Jun 02 03:22:31 PM PDT 24
Peak memory 262604 kb
Host smart-1e04b4fc-f859-4732-810e-31d5f70a22cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45405856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.45405856
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.2660706737
Short name T678
Test name
Test status
Simulation time 222107400 ps
CPU time 171.27 seconds
Started Jun 02 03:21:06 PM PDT 24
Finished Jun 02 03:23:58 PM PDT 24
Peak memory 276432 kb
Host smart-c8ade88e-9286-4845-99b1-8e742c7153cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660706737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2660706737
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.670656082
Short name T923
Test name
Test status
Simulation time 2214920900 ps
CPU time 190.79 seconds
Started Jun 02 03:21:13 PM PDT 24
Finished Jun 02 03:24:25 PM PDT 24
Peak memory 264820 kb
Host smart-7cff6474-1f91-4327-9e5b-464fec5865d8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670656082 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.flash_ctrl_wo.670656082
Directory /workspace/9.flash_ctrl_wo/latest
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