Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	351217	1		T1	1		T2	1		T3	2
all_values[1]	351217	1		T1	1		T2	1		T3	2
all_values[2]	351217	1		T1	1		T2	1		T3	2
all_values[3]	351217	1		T1	1		T2	1		T3	2
all_values[4]	351217	1		T1	1		T2	1		T3	2
all_values[5]	351217	1		T1	1		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	708629	1		T1	6		T2	6		T3	12
auto[1]	1398673	1		T26	6148		T22	20724		T39	22848

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1029578	1		T1	4		T2	4		T3	7
auto[1]	1077724	1		T1	2		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	351087	1		T1	1		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	130	1		T252	4		T253	4		T254	3
all_values[1]	auto[0]	auto[1]	351063	1		T1	1		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	154	1		T252	5		T253	6		T254	2
all_values[2]	auto[0]	auto[0]	1570	1		T1	1		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	44	1		T253	2		T254	1		T337	1
all_values[2]	auto[1]	auto[0]	349540	1		T26	1537		T22	5181		T39	5712
all_values[2]	auto[1]	auto[1]	63	1		T254	1		T337	3		T338	4
all_values[3]	auto[0]	auto[0]	1571	1		T1	1		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	64	1		T252	3		T337	4		T339	3
all_values[3]	auto[1]	auto[0]	81698	1		T26	1537		T22	1727		T39	1904
all_values[3]	auto[1]	auto[1]	267884	1		T22	3454		T39	3808		T40	1622
all_values[4]	auto[0]	auto[0]	1121	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	502	1		T3	1		T5	1		T18	1
all_values[4]	auto[1]	auto[0]	243032	1		T26	1		T22	3454		T39	3808
all_values[4]	auto[1]	auto[1]	106562	1		T26	1536		T22	1727		T39	1904
all_values[5]	auto[0]	auto[0]	1488	1		T1	1		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	119	1		T5	1		T23	1		T41	1
all_values[5]	auto[1]	auto[0]	349558	1		T26	1537		T22	5181		T39	5712
all_values[5]	auto[1]	auto[1]	52	1		T337	1		T338	1		T341	2