Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	249491	1		T3	1		T4	52		T5	1326
auto[FlashEraseBank]	275850	1		T4	20		T5	1890		T9	11

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	260775	1		T3	1		T4	41		T5	1329
auto[FlashOpProgram]	244550	1		T5	1887		T9	14		T20	3
auto[FlashOpErase]	16016	1		T4	31		T18	30		T48	30
auto[FlashOpInvalid]	4000	1		T193	200		T102	200		T104	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	260775	1		T3	1		T4	41		T5	1329
op[FlashOpProgram]	244550	1		T5	1887		T9	14		T20	3
op[FlashOpErase]	16016	1		T4	31		T18	30		T48	30
read_erase_read	652	1		T4	31		T30	29		T185	2
read_prog_read	757	1		T5	5		T6	1		T27	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	385016	1		T3	1		T4	3		T5	2779
auto[FlashPartInfo]	136990	1		T4	69		T5	407		T9	13
auto[FlashPartInfo1]	829	1		T5	6		T6	2		T97	2
auto[FlashPartInfo2]	2506	1		T5	24		T6	3		T26	6

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	191018	1		T3	1		T4	3		T5	1048
auto[FlashPartData]	auto[FlashOpProgram]	186331	1		T5	1731		T9	1		T20	3
auto[FlashPartData]	auto[FlashOpErase]	3755	1		T18	28		T48	30		T33	2
auto[FlashPartData]	auto[FlashOpInvalid]	3912	1		T193	198		T102	198		T104	196
auto[FlashPartInfo]	auto[FlashOpRead]	67553	1		T4	38		T5	259		T19	1
auto[FlashPartInfo]	auto[FlashOpProgram]	57135	1		T5	148		T9	13		T26	220
auto[FlashPartInfo]	auto[FlashOpErase]	12226	1		T4	31		T18	2		T33	3
auto[FlashPartInfo]	auto[FlashOpInvalid]	76	1		T193	2		T102	2		T104	4
auto[FlashPartInfo1]	auto[FlashOpRead]	660	1		T5	6		T6	2		T97	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T81	32		T113	32		T291	1
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T84	1		T87	1		T399	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T399	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1544	1		T5	16		T6	1		T7	5
auto[FlashPartInfo2]	auto[FlashOpProgram]	921	1		T5	8		T6	2		T26	6
auto[FlashPartInfo2]	auto[FlashOpErase]	31	1		T35	2		T99	17		T112	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T400	2		T401	2		T402	2