Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	8	24	75.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	8	24	75.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30839	1		T18	4		T48	4		T185	32
auto[1]	8	1		T23	1		T169	2		T322	1
auto[2]	20	1		T18	4		T48	8		T323	4
auto[3]	64	1		T27	1		T30	13		T99	4

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7732	1		T18	2		T48	3		T30	4
evic_idx[1]	7739	1		T18	2		T48	3		T23	1
evic_idx[2]	7734	1		T18	2		T48	3		T27	1
evic_idx[3]	7726	1		T18	2		T48	3		T30	3

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30098	1		T30	13		T185	12		T99	4
evic_op[2]	313	1		T27	1		T23	1		T185	16

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	8	24	75.00	8

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1] - auto[2]]	--	--	8

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7518	1		T185	3		T193	100		T102	100
evic_idx[0]	evic_op[1]	auto[3]	6	1		T30	4		T99	1		T324	1
evic_idx[0]	evic_op[2]	auto[0]	66	1		T185	4		T35	2		T105	2
evic_idx[0]	evic_op[2]	auto[1]	1	1		T169	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	1	1		T323	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	10	1		T188	1		T325	1		T326	1
evic_idx[1]	evic_op[1]	auto[0]	7518	1		T185	3		T193	100		T102	100
evic_idx[1]	evic_op[1]	auto[3]	6	1		T30	2		T99	1		T327	1
evic_idx[1]	evic_op[2]	auto[0]	67	1		T185	4		T35	2		T105	2
evic_idx[1]	evic_op[2]	auto[1]	2	1		T23	1		T328	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	1	1		T323	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	15	1		T28	1		T43	1		T329	1
evic_idx[2]	evic_op[1]	auto[0]	7519	1		T185	3		T193	100		T102	100
evic_idx[2]	evic_op[1]	auto[3]	9	1		T30	4		T99	1		T330	1
evic_idx[2]	evic_op[2]	auto[0]	66	1		T185	4		T35	2		T105	2
evic_idx[2]	evic_op[2]	auto[1]	2	1		T322	1		T331	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	1	1		T323	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	7	1		T27	1		T332	1		T333	1
evic_idx[3]	evic_op[1]	auto[0]	7517	1		T185	3		T193	100		T102	100
evic_idx[3]	evic_op[1]	auto[3]	5	1		T30	3		T99	1		T324	1
evic_idx[3]	evic_op[2]	auto[0]	64	1		T185	4		T35	2		T105	2
evic_idx[3]	evic_op[2]	auto[1]	3	1		T169	1		T334	1		T335	1
evic_idx[3]	evic_op[2]	auto[2]	1	1		T323	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	6	1		T325	1		T326	1		T336	1