Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	33332	1		T343	15143		T344	2459		T345	2622
rd_lvl[2]	47456	1		T194	5851		T346	5975		T200	1207
rd_lvl[3]	15404	1		T194	243		T346	153		T200	351
rd_lvl[4]	25546	1		T200	42		T347	3751		T348	123
rd_lvl[5]	15443	1		T194	1		T346	2		T200	166
rd_lvl[6]	24044	1		T39	3808		T200	128		T349	621
rd_lvl[7]	10158	1		T22	1892		T200	27		T349	155
rd_lvl[8]	24314	1		T22	1562		T200	29		T350	2734
rd_lvl[9]	8305	1		T200	27		T350	474		T349	114
rd_lvl[10]	9575	1		T194	1		T346	1		T351	1197
rd_lvl[11]	2893	1		T40	430		T351	347		T274	161
rd_lvl[12]	6748	1		T40	1192		T36	60		T194	1
rd_lvl[13]	1622	1		T36	18		T276	570		T346	1
rd_lvl[14]	5999	1		T276	988		T37	1243		T352	159
rd_lvl[15]	3768	1		T36	1		T37	405		T38	139