Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	351217	1		T1	1		T2	1		T3	2
all_pins[1]	351217	1		T1	1		T2	1		T3	2
all_pins[2]	351217	1		T1	1		T2	1		T3	2
all_pins[3]	351217	1		T1	1		T2	1		T3	2
all_pins[4]	351217	1		T1	1		T2	1		T3	2
all_pins[5]	351217	1		T1	1		T2	1		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1751208	1		T1	6		T2	6		T3	12
values[0x1]	356094	1		T26	1536		T22	5181		T39	5712
transitions[0x0=>0x1]	319367	1		T26	1536		T22	5181		T39	5712
transitions[0x1=>0x0]	319351	1		T26	1536		T22	5181		T39	5712

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	351087	1		T1	1		T2	1		T3	2
all_pins[0]	values[0x1]	130	1		T252	4		T253	4		T254	3
all_pins[0]	transitions[0x0=>0x1]	55	1		T252	1		T254	1		T337	4
all_pins[0]	transitions[0x1=>0x0]	79	1		T252	2		T253	2		T337	1
all_pins[1]	values[0x0]	351063	1		T1	1		T2	1		T3	2
all_pins[1]	values[0x1]	154	1		T252	5		T253	6		T254	2
all_pins[1]	transitions[0x0=>0x1]	121	1		T252	5		T253	6		T254	2
all_pins[1]	transitions[0x1=>0x0]	2542	1		T38	1323		T355	208		T171	6
all_pins[2]	values[0x0]	348642	1		T1	1		T2	1		T3	2
all_pins[2]	values[0x1]	2575	1		T38	1323		T355	208		T171	6
all_pins[2]	transitions[0x0=>0x1]	41	1		T254	1		T337	3		T338	1
all_pins[2]	transitions[0x1=>0x0]	234723	1		T22	3454		T39	3808		T40	1622
all_pins[3]	values[0x0]	113960	1		T1	1		T2	1		T3	2
all_pins[3]	values[0x1]	237257	1		T22	3454		T39	3808		T40	1622
all_pins[3]	transitions[0x0=>0x1]	203208	1		T22	3454		T39	3808		T40	1622
all_pins[3]	transitions[0x1=>0x0]	81877	1		T26	1536		T22	1727		T39	1904
all_pins[4]	values[0x0]	235291	1		T1	1		T2	1		T3	2
all_pins[4]	values[0x1]	115926	1		T26	1536		T22	1727		T39	1904
all_pins[4]	transitions[0x0=>0x1]	115914	1		T26	1536		T22	1727		T39	1904
all_pins[4]	transitions[0x1=>0x0]	40	1		T337	1		T338	1		T341	2
all_pins[5]	values[0x0]	351165	1		T1	1		T2	1		T3	2
all_pins[5]	values[0x1]	52	1		T337	1		T338	1		T341	2
all_pins[5]	transitions[0x0=>0x1]	28	1		T338	1		T341	1		T356	2
all_pins[5]	transitions[0x1=>0x0]	90	1		T252	3		T253	3		T254	2