Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1		T252	7		T253	7		T254	4
all_values[1]	272	1		T252	7		T253	7		T254	4
all_values[2]	272	1		T252	7		T253	7		T254	4
all_values[3]	272	1		T252	7		T253	7		T254	4
all_values[4]	272	1		T252	7		T253	7		T254	4
all_values[5]	272	1		T252	7		T253	7		T254	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	914	1		T252	22		T253	19		T254	13
auto[1]	718	1		T252	20		T253	23		T254	11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	553	1		T252	20		T253	15		T254	9
auto[1]	1079	1		T252	22		T253	27		T254	15

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	966	1		T252	32		T253	25		T254	14
auto[1]	666	1		T252	10		T253	17		T254	10

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	93	1		T252	3		T253	1		T254	1
all_values[0]	auto[0]	auto[1]	auto[1]	69	1		T252	2		T253	2		T254	1
all_values[0]	auto[1]	auto[0]	auto[1]	80	1		T252	2		T253	3		T254	1
all_values[0]	auto[1]	auto[1]	auto[1]	30	1		T253	1		T254	1		T337	3
all_values[1]	auto[0]	auto[0]	auto[1]	87	1		T252	2		T253	1		T254	2
all_values[1]	auto[0]	auto[1]	auto[1]	68	1		T252	4		T253	2		T254	1
all_values[1]	auto[1]	auto[0]	auto[1]	70	1		T252	1		T253	1		T254	1
all_values[1]	auto[1]	auto[1]	auto[1]	47	1		T253	3		T337	2		T338	1
all_values[2]	auto[0]	auto[0]	auto[0]	91	1		T252	4		T253	4		T337	1
all_values[2]	auto[0]	auto[1]	auto[0]	74	1		T252	3		T253	1		T254	2
all_values[2]	auto[1]	auto[0]	auto[1]	51	1		T253	1		T254	2		T337	2
all_values[2]	auto[1]	auto[1]	auto[1]	56	1		T253	1		T337	2		T338	2
all_values[3]	auto[0]	auto[0]	auto[0]	87	1		T252	1		T253	2		T337	2
all_values[3]	auto[0]	auto[1]	auto[0]	59	1		T252	2		T253	3		T254	2
all_values[3]	auto[1]	auto[0]	auto[1]	74	1		T252	2		T253	1		T254	2
all_values[3]	auto[1]	auto[1]	auto[1]	52	1		T252	2		T253	1		T337	1
all_values[4]	auto[0]	auto[0]	auto[0]	60	1		T252	1		T254	1		T338	2
all_values[4]	auto[0]	auto[0]	auto[1]	24	1		T252	1		T253	1		T337	4
all_values[4]	auto[0]	auto[1]	auto[0]	50	1		T252	2		T253	1		T254	1
all_values[4]	auto[0]	auto[1]	auto[1]	28	1		T253	2		T337	1		T338	1
all_values[4]	auto[1]	auto[0]	auto[1]	56	1		T252	2		T253	1		T254	1
all_values[4]	auto[1]	auto[1]	auto[1]	54	1		T252	1		T253	2		T254	1
all_values[5]	auto[0]	auto[0]	auto[0]	64	1		T252	3		T254	1		T337	1
all_values[5]	auto[0]	auto[0]	auto[1]	25	1		T253	1		T339	1		T340	2
all_values[5]	auto[0]	auto[1]	auto[0]	68	1		T252	4		T253	4		T254	2
all_values[5]	auto[0]	auto[1]	auto[1]	19	1		T339	1		T341	1		T342	1
all_values[5]	auto[1]	auto[0]	auto[1]	52	1		T253	2		T254	1		T337	2
all_values[5]	auto[1]	auto[1]	auto[1]	44	1		T337	1		T338	2		T342	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal