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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.54 95.84 94.19 98.85 92.52 98.24 98.11 98.00


Total test records in report: 1237
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T1072 /workspace/coverage/default/28.flash_ctrl_prog_reset.3406378088 Jun 04 02:55:52 PM PDT 24 Jun 04 02:59:15 PM PDT 24 2299446500 ps
T1073 /workspace/coverage/default/0.flash_ctrl_sw_op.3501727116 Jun 04 02:39:32 PM PDT 24 Jun 04 02:40:00 PM PDT 24 83720800 ps
T1074 /workspace/coverage/default/2.flash_ctrl_stress_all.2989278915 Jun 04 02:43:39 PM PDT 24 Jun 04 03:05:16 PM PDT 24 610891200 ps
T1075 /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.1282290706 Jun 04 02:50:05 PM PDT 24 Jun 04 02:50:19 PM PDT 24 34250300 ps
T1076 /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.1122512783 Jun 04 02:52:54 PM PDT 24 Jun 04 02:53:08 PM PDT 24 21447800 ps
T1077 /workspace/coverage/default/42.flash_ctrl_smoke.3871012659 Jun 04 02:57:42 PM PDT 24 Jun 04 03:00:08 PM PDT 24 34318600 ps
T1078 /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.2397238230 Jun 04 02:39:40 PM PDT 24 Jun 04 02:42:18 PM PDT 24 8123360900 ps
T1079 /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.2642230829 Jun 04 02:42:54 PM PDT 24 Jun 04 02:45:17 PM PDT 24 1440246700 ps
T133 /workspace/coverage/default/1.flash_ctrl_mid_op_rst.1249576514 Jun 04 02:41:57 PM PDT 24 Jun 04 02:43:08 PM PDT 24 826409800 ps
T1080 /workspace/coverage/default/52.flash_ctrl_otp_reset.2405671968 Jun 04 02:58:15 PM PDT 24 Jun 04 03:00:29 PM PDT 24 40397500 ps
T1081 /workspace/coverage/default/48.flash_ctrl_otp_reset.3900985292 Jun 04 02:58:07 PM PDT 24 Jun 04 03:00:00 PM PDT 24 37701300 ps
T1082 /workspace/coverage/default/8.flash_ctrl_error_prog_win.3594151656 Jun 04 02:48:49 PM PDT 24 Jun 04 03:01:53 PM PDT 24 356786800 ps
T1083 /workspace/coverage/default/5.flash_ctrl_re_evict.1563939484 Jun 04 02:47:05 PM PDT 24 Jun 04 02:47:43 PM PDT 24 147090700 ps
T1084 /workspace/coverage/default/0.flash_ctrl_read_word_sweep.2420127676 Jun 04 02:40:08 PM PDT 24 Jun 04 02:40:22 PM PDT 24 26362600 ps
T1085 /workspace/coverage/default/5.flash_ctrl_rw.3146652772 Jun 04 02:46:49 PM PDT 24 Jun 04 02:58:22 PM PDT 24 4116988700 ps
T1086 /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.1235514939 Jun 04 02:48:54 PM PDT 24 Jun 04 03:02:59 PM PDT 24 80145216800 ps
T1087 /workspace/coverage/default/8.flash_ctrl_wo.96048718 Jun 04 02:48:55 PM PDT 24 Jun 04 02:51:45 PM PDT 24 3964646300 ps
T315 /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.2825436581 Jun 04 02:57:49 PM PDT 24 Jun 04 02:58:45 PM PDT 24 6159336000 ps
T1088 /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.464711602 Jun 04 02:43:38 PM PDT 24 Jun 04 02:46:01 PM PDT 24 16228570400 ps
T1089 /workspace/coverage/default/36.flash_ctrl_rw_evict.2987255165 Jun 04 02:57:03 PM PDT 24 Jun 04 02:57:34 PM PDT 24 27005900 ps
T1090 /workspace/coverage/default/37.flash_ctrl_otp_reset.4030673713 Jun 04 02:57:13 PM PDT 24 Jun 04 02:59:26 PM PDT 24 195255500 ps
T1091 /workspace/coverage/default/1.flash_ctrl_rand_ops.1704827644 Jun 04 02:41:29 PM PDT 24 Jun 04 02:46:32 PM PDT 24 101256200 ps
T1092 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3082281196 Jun 04 01:19:38 PM PDT 24 Jun 04 01:19:54 PM PDT 24 18433700 ps
T69 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3476106024 Jun 04 01:20:15 PM PDT 24 Jun 04 01:20:34 PM PDT 24 75215600 ps
T70 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1779181085 Jun 04 01:19:47 PM PDT 24 Jun 04 01:20:07 PM PDT 24 108454800 ps
T252 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.4070084981 Jun 04 01:20:32 PM PDT 24 Jun 04 01:20:46 PM PDT 24 45675200 ps
T71 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.799253235 Jun 04 01:20:00 PM PDT 24 Jun 04 01:20:22 PM PDT 24 497492600 ps
T253 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3101083810 Jun 04 01:20:30 PM PDT 24 Jun 04 01:20:44 PM PDT 24 27344800 ps
T1093 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3807692581 Jun 04 01:19:39 PM PDT 24 Jun 04 01:19:55 PM PDT 24 21109600 ps
T254 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2021128105 Jun 04 01:20:29 PM PDT 24 Jun 04 01:20:43 PM PDT 24 73228900 ps
T206 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.235040092 Jun 04 01:20:00 PM PDT 24 Jun 04 01:34:46 PM PDT 24 2837503400 ps
T239 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3527079109 Jun 04 01:20:15 PM PDT 24 Jun 04 01:20:34 PM PDT 24 81355200 ps
T337 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2603232355 Jun 04 01:19:44 PM PDT 24 Jun 04 01:19:59 PM PDT 24 107240100 ps
T338 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1318559079 Jun 04 01:20:29 PM PDT 24 Jun 04 01:20:44 PM PDT 24 16216200 ps
T246 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.861027292 Jun 04 01:19:38 PM PDT 24 Jun 04 01:20:14 PM PDT 24 465608300 ps
T209 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1873208216 Jun 04 01:19:47 PM PDT 24 Jun 04 01:20:06 PM PDT 24 668979500 ps
T1094 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.627162775 Jun 04 01:20:27 PM PDT 24 Jun 04 01:20:42 PM PDT 24 54477100 ps
T339 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2207330009 Jun 04 01:19:44 PM PDT 24 Jun 04 01:19:59 PM PDT 24 18600100 ps
T1095 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2159662438 Jun 04 01:20:07 PM PDT 24 Jun 04 01:20:25 PM PDT 24 46418600 ps
T207 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.705851283 Jun 04 01:19:53 PM PDT 24 Jun 04 01:32:25 PM PDT 24 716382900 ps
T1096 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4225384601 Jun 04 01:19:34 PM PDT 24 Jun 04 01:19:48 PM PDT 24 48743600 ps
T240 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.942173331 Jun 04 01:19:46 PM PDT 24 Jun 04 01:20:04 PM PDT 24 45210200 ps
T224 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2465673961 Jun 04 01:19:46 PM PDT 24 Jun 04 01:20:06 PM PDT 24 703315900 ps
T341 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.459882668 Jun 04 01:20:29 PM PDT 24 Jun 04 01:20:44 PM PDT 24 27965700 ps
T1097 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.387111185 Jun 04 01:19:47 PM PDT 24 Jun 04 01:20:03 PM PDT 24 14130300 ps
T1098 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.4150649250 Jun 04 01:19:39 PM PDT 24 Jun 04 01:19:54 PM PDT 24 50388800 ps
T1099 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.976854994 Jun 04 01:19:46 PM PDT 24 Jun 04 01:20:03 PM PDT 24 84660700 ps
T208 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2145385878 Jun 04 01:19:46 PM PDT 24 Jun 04 01:20:07 PM PDT 24 259242800 ps
T342 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2144695629 Jun 04 01:20:30 PM PDT 24 Jun 04 01:20:44 PM PDT 24 18047300 ps
T241 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3165787608 Jun 04 01:19:47 PM PDT 24 Jun 04 01:20:03 PM PDT 24 34132600 ps
T304 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3592092708 Jun 04 01:19:34 PM PDT 24 Jun 04 01:20:01 PM PDT 24 172167800 ps
T225 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2835242922 Jun 04 01:19:32 PM PDT 24 Jun 04 01:19:51 PM PDT 24 155330200 ps
T242 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3326200075 Jun 04 01:19:39 PM PDT 24 Jun 04 01:19:54 PM PDT 24 39327400 ps
T356 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3896983263 Jun 04 01:20:14 PM PDT 24 Jun 04 01:20:29 PM PDT 24 22412800 ps
T226 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3949912942 Jun 04 01:20:02 PM PDT 24 Jun 04 01:20:19 PM PDT 24 35321900 ps
T227 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.528705231 Jun 04 01:19:45 PM PDT 24 Jun 04 01:27:20 PM PDT 24 852142300 ps
T243 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.502014126 Jun 04 01:19:45 PM PDT 24 Jun 04 01:20:02 PM PDT 24 110358600 ps
T1100 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2470568713 Jun 04 01:20:01 PM PDT 24 Jun 04 01:20:19 PM PDT 24 277101400 ps
T1101 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2842422815 Jun 04 01:20:06 PM PDT 24 Jun 04 01:20:22 PM PDT 24 26064300 ps
T1102 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1062147634 Jun 04 01:20:16 PM PDT 24 Jun 04 01:20:30 PM PDT 24 44242500 ps
T340 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.616309063 Jun 04 01:20:06 PM PDT 24 Jun 04 01:20:21 PM PDT 24 18633700 ps
T1103 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2791427178 Jun 04 01:19:54 PM PDT 24 Jun 04 01:20:09 PM PDT 24 52737800 ps
T1104 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2373917712 Jun 04 01:19:40 PM PDT 24 Jun 04 01:19:54 PM PDT 24 14546700 ps
T229 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.640391236 Jun 04 01:19:33 PM PDT 24 Jun 04 01:34:35 PM PDT 24 354301300 ps
T1105 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.921797581 Jun 04 01:20:21 PM PDT 24 Jun 04 01:20:35 PM PDT 24 45045700 ps
T1106 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.100434779 Jun 04 01:19:47 PM PDT 24 Jun 04 01:20:03 PM PDT 24 21761300 ps
T228 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1455414934 Jun 04 01:19:41 PM PDT 24 Jun 04 01:20:00 PM PDT 24 255135200 ps
T262 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1417664823 Jun 04 01:20:07 PM PDT 24 Jun 04 01:27:38 PM PDT 24 727216000 ps
T1107 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.4260825467 Jun 04 01:20:01 PM PDT 24 Jun 04 01:20:18 PM PDT 24 13269400 ps
T1108 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.488903074 Jun 04 01:20:28 PM PDT 24 Jun 04 01:20:42 PM PDT 24 16695900 ps
T1109 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1263280916 Jun 04 01:19:47 PM PDT 24 Jun 04 01:20:06 PM PDT 24 250377700 ps
T256 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3068120301 Jun 04 01:19:46 PM PDT 24 Jun 04 01:32:25 PM PDT 24 8163985700 ps
T251 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.987024882 Jun 04 01:20:05 PM PDT 24 Jun 04 01:20:21 PM PDT 24 76993700 ps
T1110 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2905822352 Jun 04 01:19:32 PM PDT 24 Jun 04 01:19:47 PM PDT 24 15038900 ps
T247 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1315242962 Jun 04 01:20:00 PM PDT 24 Jun 04 01:20:19 PM PDT 24 227278400 ps
T1111 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2562614211 Jun 04 01:19:40 PM PDT 24 Jun 04 01:20:19 PM PDT 24 1996889100 ps
T1112 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1731280231 Jun 04 01:20:28 PM PDT 24 Jun 04 01:20:43 PM PDT 24 25326400 ps
T1113 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3261819133 Jun 04 01:20:07 PM PDT 24 Jun 04 01:20:22 PM PDT 24 96727600 ps
T1114 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1203631950 Jun 04 01:19:32 PM PDT 24 Jun 04 01:19:48 PM PDT 24 30879500 ps
T1115 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.971694455 Jun 04 01:19:52 PM PDT 24 Jun 04 01:20:12 PM PDT 24 48634400 ps
T293 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3332222432 Jun 04 01:19:33 PM PDT 24 Jun 04 01:19:53 PM PDT 24 93280800 ps
T261 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.4074143107 Jun 04 01:19:53 PM PDT 24 Jun 04 01:34:46 PM PDT 24 1478988600 ps
T1116 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1689706506 Jun 04 01:20:28 PM PDT 24 Jun 04 01:20:43 PM PDT 24 16159500 ps
T248 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3292387470 Jun 04 01:20:06 PM PDT 24 Jun 04 01:20:24 PM PDT 24 86646900 ps
T257 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3941863903 Jun 04 01:19:36 PM PDT 24 Jun 04 01:32:12 PM PDT 24 1358543300 ps
T249 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2854640001 Jun 04 01:19:58 PM PDT 24 Jun 04 01:20:17 PM PDT 24 190785400 ps
T1117 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.473851638 Jun 04 01:20:00 PM PDT 24 Jun 04 01:20:17 PM PDT 24 302678500 ps
T1118 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1884537114 Jun 04 01:19:34 PM PDT 24 Jun 04 01:19:52 PM PDT 24 50792000 ps
T1119 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3552643494 Jun 04 01:20:15 PM PDT 24 Jun 04 01:20:30 PM PDT 24 21115200 ps
T1120 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.4165609985 Jun 04 01:20:22 PM PDT 24 Jun 04 01:20:36 PM PDT 24 48650700 ps
T1121 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2276594435 Jun 04 01:20:32 PM PDT 24 Jun 04 01:20:46 PM PDT 24 60338200 ps
T1122 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.698999948 Jun 04 01:20:06 PM PDT 24 Jun 04 01:20:21 PM PDT 24 17947300 ps
T255 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.485057127 Jun 04 01:19:31 PM PDT 24 Jun 04 01:19:51 PM PDT 24 56251000 ps
T265 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2393239438 Jun 04 01:19:45 PM PDT 24 Jun 04 01:34:34 PM PDT 24 698892500 ps
T294 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1529285803 Jun 04 01:19:48 PM PDT 24 Jun 04 01:20:08 PM PDT 24 832271600 ps
T1123 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3775299805 Jun 04 01:19:45 PM PDT 24 Jun 04 01:20:02 PM PDT 24 13641300 ps
T1124 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1759631147 Jun 04 01:19:33 PM PDT 24 Jun 04 01:20:11 PM PDT 24 326138700 ps
T1125 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2529332862 Jun 04 01:19:54 PM PDT 24 Jun 04 01:20:12 PM PDT 24 33350300 ps
T1126 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.899128273 Jun 04 01:20:08 PM PDT 24 Jun 04 01:20:24 PM PDT 24 37116300 ps
T1127 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.823519977 Jun 04 01:20:00 PM PDT 24 Jun 04 01:20:17 PM PDT 24 14692800 ps
T1128 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2988786172 Jun 04 01:19:33 PM PDT 24 Jun 04 01:20:05 PM PDT 24 122227700 ps
T1129 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3746444777 Jun 04 01:20:16 PM PDT 24 Jun 04 01:20:31 PM PDT 24 21496500 ps
T1130 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2289502620 Jun 04 01:20:07 PM PDT 24 Jun 04 01:20:28 PM PDT 24 190551800 ps
T1131 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2727107177 Jun 04 01:20:07 PM PDT 24 Jun 04 01:20:25 PM PDT 24 30445700 ps
T263 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2367689037 Jun 04 01:19:45 PM PDT 24 Jun 04 01:34:54 PM PDT 24 1339849400 ps
T1132 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1367702230 Jun 04 01:19:58 PM PDT 24 Jun 04 01:20:13 PM PDT 24 15161100 ps
T1133 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2555023278 Jun 04 01:20:28 PM PDT 24 Jun 04 01:20:43 PM PDT 24 38271900 ps
T295 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2923132871 Jun 04 01:19:39 PM PDT 24 Jun 04 01:20:29 PM PDT 24 1652219700 ps
T1134 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1687232701 Jun 04 01:20:02 PM PDT 24 Jun 04 01:20:19 PM PDT 24 23245200 ps
T1135 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.255516861 Jun 04 01:19:33 PM PDT 24 Jun 04 01:19:48 PM PDT 24 29811500 ps
T1136 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1782838128 Jun 04 01:19:32 PM PDT 24 Jun 04 01:19:47 PM PDT 24 24192200 ps
T1137 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3788863017 Jun 04 01:20:06 PM PDT 24 Jun 04 01:20:21 PM PDT 24 25199400 ps
T1138 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.456481521 Jun 04 01:19:44 PM PDT 24 Jun 04 01:19:58 PM PDT 24 196857100 ps
T1139 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.483740679 Jun 04 01:19:41 PM PDT 24 Jun 04 01:19:59 PM PDT 24 104605100 ps
T296 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.322227052 Jun 04 01:20:01 PM PDT 24 Jun 04 01:27:48 PM PDT 24 647746300 ps
T1140 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3574120423 Jun 04 01:19:59 PM PDT 24 Jun 04 01:20:15 PM PDT 24 90671000 ps
T1141 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3151783106 Jun 04 01:19:54 PM PDT 24 Jun 04 01:20:11 PM PDT 24 42562100 ps
T250 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2483148396 Jun 04 01:19:30 PM PDT 24 Jun 04 01:19:48 PM PDT 24 35644300 ps
T1142 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3518825400 Jun 04 01:19:44 PM PDT 24 Jun 04 01:19:58 PM PDT 24 17874800 ps
T269 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.55739872 Jun 04 01:20:08 PM PDT 24 Jun 04 01:27:42 PM PDT 24 807530400 ps
T1143 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1540489282 Jun 04 01:20:29 PM PDT 24 Jun 04 01:20:43 PM PDT 24 15999400 ps
T1144 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1224056512 Jun 04 01:19:39 PM PDT 24 Jun 04 01:19:53 PM PDT 24 47513900 ps
T1145 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1647602211 Jun 04 01:19:32 PM PDT 24 Jun 04 01:20:10 PM PDT 24 4166770200 ps
T1146 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1797997635 Jun 04 01:19:45 PM PDT 24 Jun 04 01:20:01 PM PDT 24 22598900 ps
T1147 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2765534947 Jun 04 01:19:39 PM PDT 24 Jun 04 01:19:55 PM PDT 24 11558400 ps
T1148 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1737169402 Jun 04 01:20:07 PM PDT 24 Jun 04 01:20:22 PM PDT 24 13629800 ps
T357 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1666310432 Jun 04 01:20:07 PM PDT 24 Jun 04 01:27:45 PM PDT 24 662325200 ps
T231 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.534058128 Jun 04 01:19:34 PM PDT 24 Jun 04 01:19:49 PM PDT 24 29947700 ps
T1149 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1924394688 Jun 04 01:19:32 PM PDT 24 Jun 04 01:20:19 PM PDT 24 28088400 ps
T1150 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1109823092 Jun 04 01:19:52 PM PDT 24 Jun 04 01:20:07 PM PDT 24 14733000 ps
T268 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2556514629 Jun 04 01:19:52 PM PDT 24 Jun 04 01:26:13 PM PDT 24 713508100 ps
T258 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.599560685 Jun 04 01:19:39 PM PDT 24 Jun 04 01:20:01 PM PDT 24 232512700 ps
T1151 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2240738448 Jun 04 01:20:21 PM PDT 24 Jun 04 01:20:35 PM PDT 24 24084300 ps
T1152 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4196119657 Jun 04 01:20:06 PM PDT 24 Jun 04 01:20:24 PM PDT 24 56887400 ps
T1153 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1966853828 Jun 04 01:19:32 PM PDT 24 Jun 04 01:19:48 PM PDT 24 18586400 ps
T1154 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2934761847 Jun 04 01:19:47 PM PDT 24 Jun 04 01:20:04 PM PDT 24 14951600 ps
T1155 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.560513628 Jun 04 01:20:21 PM PDT 24 Jun 04 01:20:35 PM PDT 24 14933000 ps
T259 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2537123388 Jun 04 01:19:59 PM PDT 24 Jun 04 01:20:17 PM PDT 24 189858400 ps
T1156 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3003860815 Jun 04 01:19:59 PM PDT 24 Jun 04 01:20:35 PM PDT 24 60598500 ps
T1157 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3043809196 Jun 04 01:20:15 PM PDT 24 Jun 04 01:20:30 PM PDT 24 26227000 ps
T1158 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.84885599 Jun 04 01:19:39 PM PDT 24 Jun 04 01:20:23 PM PDT 24 1342806100 ps
T1159 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3091051463 Jun 04 01:20:06 PM PDT 24 Jun 04 01:20:23 PM PDT 24 42459900 ps
T264 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3390120514 Jun 04 01:19:46 PM PDT 24 Jun 04 01:20:07 PM PDT 24 264993200 ps
T1160 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2591003522 Jun 04 01:19:39 PM PDT 24 Jun 04 01:34:35 PM PDT 24 679114300 ps
T1161 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.530721105 Jun 04 01:19:46 PM PDT 24 Jun 04 01:20:03 PM PDT 24 13739000 ps
T1162 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2469139652 Jun 04 01:19:41 PM PDT 24 Jun 04 01:19:56 PM PDT 24 34340300 ps
T1163 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.44738721 Jun 04 01:19:47 PM PDT 24 Jun 04 01:20:04 PM PDT 24 21989200 ps
T1164 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2253615477 Jun 04 01:20:07 PM PDT 24 Jun 04 01:20:25 PM PDT 24 11856000 ps
T260 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1956116854 Jun 04 01:19:53 PM PDT 24 Jun 04 01:20:15 PM PDT 24 603268700 ps
T1165 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1538014816 Jun 04 01:19:53 PM PDT 24 Jun 04 01:20:12 PM PDT 24 31008000 ps
T1166 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2545395166 Jun 04 01:19:52 PM PDT 24 Jun 04 01:20:06 PM PDT 24 100351800 ps
T1167 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1162257761 Jun 04 01:19:53 PM PDT 24 Jun 04 01:20:09 PM PDT 24 18783300 ps
T232 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.509740988 Jun 04 01:19:32 PM PDT 24 Jun 04 01:19:47 PM PDT 24 21014900 ps
T1168 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3456063992 Jun 04 01:20:00 PM PDT 24 Jun 04 01:20:17 PM PDT 24 17769100 ps
T1169 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.66527039 Jun 04 01:19:32 PM PDT 24 Jun 04 01:19:46 PM PDT 24 16693100 ps
T1170 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2727086114 Jun 04 01:19:59 PM PDT 24 Jun 04 01:20:21 PM PDT 24 153315600 ps
T297 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3743239086 Jun 04 01:19:39 PM PDT 24 Jun 04 01:20:01 PM PDT 24 1096860500 ps
T1171 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.117306011 Jun 04 01:20:28 PM PDT 24 Jun 04 01:20:43 PM PDT 24 127254200 ps
T1172 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1677812291 Jun 04 01:20:07 PM PDT 24 Jun 04 01:20:27 PM PDT 24 107027800 ps
T1173 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4246134940 Jun 04 01:20:30 PM PDT 24 Jun 04 01:20:44 PM PDT 24 66669200 ps
T1174 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2003679947 Jun 04 01:19:46 PM PDT 24 Jun 04 01:20:02 PM PDT 24 15336400 ps
T1175 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1784263069 Jun 04 01:20:23 PM PDT 24 Jun 04 01:20:38 PM PDT 24 15622900 ps
T1176 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.4104906515 Jun 04 01:20:01 PM PDT 24 Jun 04 01:20:19 PM PDT 24 133916900 ps
T1177 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4245896406 Jun 04 01:20:02 PM PDT 24 Jun 04 01:20:16 PM PDT 24 25185100 ps
T1178 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.346053871 Jun 04 01:19:40 PM PDT 24 Jun 04 01:19:56 PM PDT 24 11157900 ps
T1179 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1599933827 Jun 04 01:19:40 PM PDT 24 Jun 04 01:20:07 PM PDT 24 58396800 ps
T298 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1679871707 Jun 04 01:19:40 PM PDT 24 Jun 04 01:19:57 PM PDT 24 383094800 ps
T299 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1552355673 Jun 04 01:19:39 PM PDT 24 Jun 04 01:21:12 PM PDT 24 23902321700 ps
T1180 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1930657192 Jun 04 01:19:31 PM PDT 24 Jun 04 01:19:48 PM PDT 24 42521400 ps
T358 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2095977149 Jun 04 01:20:08 PM PDT 24 Jun 04 01:35:04 PM PDT 24 3187971900 ps
T300 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.803576945 Jun 04 01:19:48 PM PDT 24 Jun 04 01:20:24 PM PDT 24 201071000 ps
T301 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2072488738 Jun 04 01:19:52 PM PDT 24 Jun 04 01:20:11 PM PDT 24 236261800 ps
T266 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2055971733 Jun 04 01:19:52 PM PDT 24 Jun 04 01:20:11 PM PDT 24 107020800 ps
T1181 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2337510638 Jun 04 01:19:52 PM PDT 24 Jun 04 01:20:08 PM PDT 24 244180200 ps
T1182 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1011587587 Jun 04 01:19:39 PM PDT 24 Jun 04 01:19:58 PM PDT 24 293014800 ps
T1183 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1061294175 Jun 04 01:20:29 PM PDT 24 Jun 04 01:20:43 PM PDT 24 31012600 ps
T1184 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1397274620 Jun 04 01:19:31 PM PDT 24 Jun 04 01:19:51 PM PDT 24 375059600 ps
T1185 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1753383826 Jun 04 01:19:41 PM PDT 24 Jun 04 01:20:12 PM PDT 24 30072700 ps
T267 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.4095794891 Jun 04 01:19:38 PM PDT 24 Jun 04 01:34:41 PM PDT 24 897771800 ps
T1186 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.535340573 Jun 04 01:19:31 PM PDT 24 Jun 04 01:20:35 PM PDT 24 4197458900 ps
T1187 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3582609038 Jun 04 01:19:42 PM PDT 24 Jun 04 01:19:58 PM PDT 24 87904700 ps
T233 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2987946887 Jun 04 01:19:32 PM PDT 24 Jun 04 01:19:47 PM PDT 24 17866100 ps
T1188 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3077068650 Jun 04 01:19:34 PM PDT 24 Jun 04 01:19:48 PM PDT 24 29030900 ps
T1189 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3287687100 Jun 04 01:19:53 PM PDT 24 Jun 04 01:20:12 PM PDT 24 48378500 ps
T1190 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.497683972 Jun 04 01:19:38 PM PDT 24 Jun 04 01:20:12 PM PDT 24 303830000 ps
T1191 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1241698561 Jun 04 01:20:05 PM PDT 24 Jun 04 01:20:24 PM PDT 24 101316200 ps
T302 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2121765146 Jun 04 01:19:53 PM PDT 24 Jun 04 01:20:13 PM PDT 24 467931600 ps
T1192 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1408110138 Jun 04 01:19:46 PM PDT 24 Jun 04 01:20:07 PM PDT 24 59993600 ps
T1193 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2706102024 Jun 04 01:19:52 PM PDT 24 Jun 04 01:20:07 PM PDT 24 13414300 ps
T1194 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2597778802 Jun 04 01:19:52 PM PDT 24 Jun 04 01:20:10 PM PDT 24 82910000 ps
T234 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1593773126 Jun 04 01:19:42 PM PDT 24 Jun 04 01:19:55 PM PDT 24 49590200 ps
T1195 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.840658264 Jun 04 01:20:00 PM PDT 24 Jun 04 01:20:15 PM PDT 24 18541200 ps
T303 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1945364693 Jun 04 01:19:45 PM PDT 24 Jun 04 01:20:22 PM PDT 24 900112800 ps
T1196 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1446070953 Jun 04 01:19:31 PM PDT 24 Jun 04 01:19:45 PM PDT 24 14061400 ps
T1197 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2281340205 Jun 04 01:19:52 PM PDT 24 Jun 04 01:20:07 PM PDT 24 32026000 ps
T1198 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3861975457 Jun 04 01:20:00 PM PDT 24 Jun 04 01:20:16 PM PDT 24 34769600 ps
T1199 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.877536526 Jun 04 01:20:22 PM PDT 24 Jun 04 01:20:37 PM PDT 24 27826700 ps
T1200 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1702836447 Jun 04 01:20:01 PM PDT 24 Jun 04 01:20:16 PM PDT 24 29055900 ps
T1201 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.235805663 Jun 04 01:20:06 PM PDT 24 Jun 04 01:20:27 PM PDT 24 535398400 ps
T1202 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2066714162 Jun 04 01:20:01 PM PDT 24 Jun 04 01:20:22 PM PDT 24 62309800 ps
T1203 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3998974394 Jun 04 01:19:45 PM PDT 24 Jun 04 01:19:59 PM PDT 24 44024000 ps
T1204 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3710299684 Jun 04 01:19:45 PM PDT 24 Jun 04 01:20:03 PM PDT 24 221525200 ps
T230 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3197114312 Jun 04 01:19:40 PM PDT 24 Jun 04 01:19:55 PM PDT 24 15324300 ps
T1205 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3463778837 Jun 04 01:19:33 PM PDT 24 Jun 04 01:19:49 PM PDT 24 153760900 ps
T359 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3934918499 Jun 04 01:19:48 PM PDT 24 Jun 04 01:34:56 PM PDT 24 573100800 ps
T1206 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3868944292 Jun 04 01:19:32 PM PDT 24 Jun 04 01:19:49 PM PDT 24 23733100 ps
T1207 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1961898813 Jun 04 01:19:45 PM PDT 24 Jun 04 01:20:04 PM PDT 24 55973700 ps
T1208 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2554088500 Jun 04 01:20:08 PM PDT 24 Jun 04 01:20:33 PM PDT 24 2824596800 ps
T1209 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1285294777 Jun 04 01:19:38 PM PDT 24 Jun 04 01:19:56 PM PDT 24 392006400 ps
T1210 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1411100709 Jun 04 01:20:00 PM PDT 24 Jun 04 01:20:19 PM PDT 24 49948300 ps
T1211 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.4060878333 Jun 04 01:20:08 PM PDT 24 Jun 04 01:20:27 PM PDT 24 121930400 ps
T1212 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.630089516 Jun 04 01:20:00 PM PDT 24 Jun 04 01:20:14 PM PDT 24 62794000 ps
T1213 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3826446877 Jun 04 01:19:36 PM PDT 24 Jun 04 01:20:11 PM PDT 24 212165400 ps
T1214 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1207687203 Jun 04 01:19:33 PM PDT 24 Jun 04 01:26:00 PM PDT 24 167118300 ps
T1215 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.712637397 Jun 04 01:19:33 PM PDT 24 Jun 04 01:19:53 PM PDT 24 50522200 ps
T1216 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3731694709 Jun 04 01:20:06 PM PDT 24 Jun 04 01:20:23 PM PDT 24 11025100 ps
T1217 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3656153230 Jun 04 01:20:05 PM PDT 24 Jun 04 01:20:23 PM PDT 24 37945900 ps
T1218 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.177061102 Jun 04 01:20:07 PM PDT 24 Jun 04 01:20:27 PM PDT 24 130134200 ps
T1219 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.205006732 Jun 04 01:19:41 PM PDT 24 Jun 04 01:19:55 PM PDT 24 30158600 ps
T1220 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.959381855 Jun 04 01:19:32 PM PDT 24 Jun 04 01:20:06 PM PDT 24 1044460700 ps
T1221 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2534719302 Jun 04 01:19:45 PM PDT 24 Jun 04 01:20:04 PM PDT 24 878015100 ps
T1222 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.392581994 Jun 04 01:19:53 PM PDT 24 Jun 04 01:20:13 PM PDT 24 156424900 ps
T1223 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2857456216 Jun 04 01:19:54 PM PDT 24 Jun 04 01:20:15 PM PDT 24 303177500 ps
T1224 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2048725737 Jun 04 01:19:48 PM PDT 24 Jun 04 01:20:08 PM PDT 24 351180000 ps
T1225 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2158207308 Jun 04 01:20:30 PM PDT 24 Jun 04 01:20:44 PM PDT 24 65378100 ps
T1226 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.421706016 Jun 04 01:20:21 PM PDT 24 Jun 04 01:20:35 PM PDT 24 16459800 ps
T1227 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2268777461 Jun 04 01:19:49 PM PDT 24 Jun 04 01:20:03 PM PDT 24 32074700 ps
T1228 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3778611247 Jun 04 01:20:06 PM PDT 24 Jun 04 01:20:20 PM PDT 24 11912700 ps
T1229 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.804958185 Jun 04 01:20:20 PM PDT 24 Jun 04 01:20:34 PM PDT 24 28479700 ps
T1230 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1207238308 Jun 04 01:20:08 PM PDT 24 Jun 04 01:20:27 PM PDT 24 72577200 ps
T1231 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1437797714 Jun 04 01:19:46 PM PDT 24 Jun 04 01:20:05 PM PDT 24 158634000 ps
T1232 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2822549231 Jun 04 01:19:32 PM PDT 24 Jun 04 01:19:49 PM PDT 24 124934100 ps
T1233 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.693379086 Jun 04 01:19:59 PM PDT 24 Jun 04 01:20:20 PM PDT 24 91846700 ps
T1234 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3760471399 Jun 04 01:20:00 PM PDT 24 Jun 04 01:27:31 PM PDT 24 708009700 ps
T1235 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3559832651 Jun 04 01:19:39 PM PDT 24 Jun 04 01:19:56 PM PDT 24 69356000 ps
T1236 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.894613118 Jun 04 01:19:39 PM PDT 24 Jun 04 01:20:20 PM PDT 24 1310240700 ps
T1237 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.20462729 Jun 04 01:19:52 PM PDT 24 Jun 04 01:20:07 PM PDT 24 57346200 ps

Test location /workspace/coverage/default/3.flash_ctrl_rw_serr.3310584146
Short name T5
Test name
Test status
Simulation time 33555571700 ps
CPU time 467.96 seconds
Started Jun 04 02:44:47 PM PDT 24
Finished Jun 04 02:52:36 PM PDT 24
Peak memory 319872 kb
Host smart-c7917cca-fa2e-4841-9273-a57e2daeeae4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310584146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_s
err.3310584146
Directory /workspace/3.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.1148332475
Short name T33
Test name
Test status
Simulation time 42167313800 ps
CPU time 860.02 seconds
Started Jun 04 02:41:20 PM PDT 24
Finished Jun 04 02:55:41 PM PDT 24
Peak memory 259156 kb
Host smart-0d7a45a5-7b06-4694-8b8c-454b6732c8aa
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148332475 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.1148332475
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.705851283
Short name T207
Test name
Test status
Simulation time 716382900 ps
CPU time 750.28 seconds
Started Jun 04 01:19:53 PM PDT 24
Finished Jun 04 01:32:25 PM PDT 24
Peak memory 264252 kb
Host smart-4ff7f2ec-7dd7-4dd4-900e-62f5b2814083
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705851283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl
_tl_intg_err.705851283
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.1688992758
Short name T35
Test name
Test status
Simulation time 5173867200 ps
CPU time 148.57 seconds
Started Jun 04 02:52:15 PM PDT 24
Finished Jun 04 02:54:44 PM PDT 24
Peak memory 261692 kb
Host smart-46f1a22c-584d-41e4-9cb5-31ee7287cfaf
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688992758 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.1688992758
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.3762488913
Short name T47
Test name
Test status
Simulation time 38015500 ps
CPU time 129.92 seconds
Started Jun 04 02:58:32 PM PDT 24
Finished Jun 04 03:00:43 PM PDT 24
Peak memory 263920 kb
Host smart-4ee36a8d-c393-419d-b865-e0dbbd4d9cb7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762488913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.3762488913
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.1516148807
Short name T18
Test name
Test status
Simulation time 8511180000 ps
CPU time 405.27 seconds
Started Jun 04 02:45:28 PM PDT 24
Finished Jun 04 02:52:14 PM PDT 24
Peak memory 262720 kb
Host smart-2325f22a-d82c-49e6-81ff-4e66a44f8dd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516148807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.1516148807
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1779181085
Short name T70
Test name
Test status
Simulation time 108454800 ps
CPU time 18.9 seconds
Started Jun 04 01:19:47 PM PDT 24
Finished Jun 04 01:20:07 PM PDT 24
Peak memory 270416 kb
Host smart-a2a16dea-7f33-4e27-bc62-8f9b2922b770
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779181085 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.1779181085
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.2368315425
Short name T16
Test name
Test status
Simulation time 4023014200 ps
CPU time 4846.99 seconds
Started Jun 04 02:46:09 PM PDT 24
Finished Jun 04 04:06:57 PM PDT 24
Peak memory 283280 kb
Host smart-a95f450c-60ee-4651-8bd2-b883d8d9e72b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368315425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.2368315425
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.1620555862
Short name T56
Test name
Test status
Simulation time 5032032300 ps
CPU time 561.02 seconds
Started Jun 04 02:44:55 PM PDT 24
Finished Jun 04 02:54:17 PM PDT 24
Peak memory 324328 kb
Host smart-403bfdec-0af6-4075-8de9-f7e5669c022d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620555862 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_integrity.1620555862
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.3108413522
Short name T132
Test name
Test status
Simulation time 13646903500 ps
CPU time 81.62 seconds
Started Jun 04 02:45:45 PM PDT 24
Finished Jun 04 02:47:07 PM PDT 24
Peak memory 259784 kb
Host smart-11c827bf-e683-40ec-8f92-827606c94fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108413522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.3108413522
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.3469933735
Short name T126
Test name
Test status
Simulation time 350296514500 ps
CPU time 1100.38 seconds
Started Jun 04 02:54:17 PM PDT 24
Finished Jun 04 03:12:38 PM PDT 24
Peak memory 263040 kb
Host smart-d9ca1a81-acf8-4ac8-9ac6-f367eec81e6d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469933735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.3469933735
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.3783459850
Short name T22
Test name
Test status
Simulation time 7868486500 ps
CPU time 266.01 seconds
Started Jun 04 02:51:55 PM PDT 24
Finished Jun 04 02:56:22 PM PDT 24
Peak memory 289480 kb
Host smart-492c4fa2-05a5-4e91-bb0c-4ed83521ca9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783459850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.3783459850
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.525259174
Short name T12
Test name
Test status
Simulation time 24407900 ps
CPU time 13.74 seconds
Started Jun 04 02:43:52 PM PDT 24
Finished Jun 04 02:44:06 PM PDT 24
Peak memory 264960 kb
Host smart-5259ec00-148c-4e5d-a20c-f903ca80fef3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525259174 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.525259174
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.387143627
Short name T13
Test name
Test status
Simulation time 10012589600 ps
CPU time 118.06 seconds
Started Jun 04 02:41:20 PM PDT 24
Finished Jun 04 02:43:18 PM PDT 24
Peak memory 331664 kb
Host smart-186483cb-5d77-418e-b8e4-7faaf4a0ff47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387143627 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.387143627
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.401579380
Short name T306
Test name
Test status
Simulation time 13346437100 ps
CPU time 122.23 seconds
Started Jun 04 02:42:56 PM PDT 24
Finished Jun 04 02:44:58 PM PDT 24
Peak memory 262304 kb
Host smart-71e6084b-4b5f-47b0-92ce-3da7303b8afe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401579380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw
_sec_otp.401579380
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1318559079
Short name T338
Test name
Test status
Simulation time 16216200 ps
CPU time 13.55 seconds
Started Jun 04 01:20:29 PM PDT 24
Finished Jun 04 01:20:44 PM PDT 24
Peak memory 262552 kb
Host smart-d0dafa4c-ec6d-4762-a2e2-abdaf6f54218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318559079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
1318559079
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.3276310590
Short name T77
Test name
Test status
Simulation time 66072200 ps
CPU time 132.19 seconds
Started Jun 04 02:56:55 PM PDT 24
Finished Jun 04 02:59:07 PM PDT 24
Peak memory 259572 kb
Host smart-3a10e8a0-49c1-426e-b241-5ce771a5db89
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276310590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.3276310590
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.2196853845
Short name T120
Test name
Test status
Simulation time 273732800 ps
CPU time 129.69 seconds
Started Jun 04 02:51:45 PM PDT 24
Finished Jun 04 02:53:55 PM PDT 24
Peak memory 263348 kb
Host smart-4b9974e5-df49-4305-aba7-75e46803e919
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196853845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.2196853845
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.737426221
Short name T79
Test name
Test status
Simulation time 197408300 ps
CPU time 111.72 seconds
Started Jun 04 02:58:25 PM PDT 24
Finished Jun 04 03:00:17 PM PDT 24
Peak memory 259600 kb
Host smart-16bc5a11-8c21-4cf8-afbf-0361f887a6c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737426221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_ot
p_reset.737426221
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.3247398552
Short name T24
Test name
Test status
Simulation time 23206500 ps
CPU time 20.24 seconds
Started Jun 04 02:56:47 PM PDT 24
Finished Jun 04 02:57:07 PM PDT 24
Peak memory 264956 kb
Host smart-2ef73c87-5612-4f92-a862-2428f5210c9c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247398552 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.3247398552
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.3035842462
Short name T270
Test name
Test status
Simulation time 3466969000 ps
CPU time 75.95 seconds
Started Jun 04 02:43:40 PM PDT 24
Finished Jun 04 02:44:56 PM PDT 24
Peak memory 262604 kb
Host smart-89d3dd9b-0ca3-40b8-b10a-8d000329090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035842462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.3035842462
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.3812151434
Short name T95
Test name
Test status
Simulation time 720841322300 ps
CPU time 2389.37 seconds
Started Jun 04 02:41:51 PM PDT 24
Finished Jun 04 03:21:41 PM PDT 24
Peak memory 264648 kb
Host smart-63d8099c-4ace-4460-82dc-98e73d18917d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812151434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.3812151434
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.599560685
Short name T258
Test name
Test status
Simulation time 232512700 ps
CPU time 20.48 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:20:01 PM PDT 24
Peak memory 264168 kb
Host smart-19172420-cdd4-41fd-8e6a-f8fa1b31fffd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599560685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.599560685
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.1055808838
Short name T174
Test name
Test status
Simulation time 287655000 ps
CPU time 14.29 seconds
Started Jun 04 02:57:02 PM PDT 24
Finished Jun 04 02:57:17 PM PDT 24
Peak memory 264816 kb
Host smart-da6d121f-78f7-4ed6-b52a-6293df02a13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055808838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
1055808838
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.2519702808
Short name T58
Test name
Test status
Simulation time 667974800 ps
CPU time 24.44 seconds
Started Jun 04 02:46:40 PM PDT 24
Finished Jun 04 02:47:05 PM PDT 24
Peak memory 264788 kb
Host smart-c5121dbb-732a-49b5-a497-a4d4be42a36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519702808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.2519702808
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.3921898087
Short name T123
Test name
Test status
Simulation time 2564090900 ps
CPU time 71.09 seconds
Started Jun 04 02:43:16 PM PDT 24
Finished Jun 04 02:44:28 PM PDT 24
Peak memory 260548 kb
Host smart-d403c02a-1bba-4b63-a7f6-25cdec58d240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921898087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.3921898087
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.2495481713
Short name T99
Test name
Test status
Simulation time 82791900 ps
CPU time 30.38 seconds
Started Jun 04 02:54:24 PM PDT 24
Finished Jun 04 02:54:55 PM PDT 24
Peak memory 269320 kb
Host smart-014a0316-d405-4858-80a2-a1bdd1547f57
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495481713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.2495481713
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.3535254571
Short name T83
Test name
Test status
Simulation time 35206613300 ps
CPU time 543.39 seconds
Started Jun 04 02:45:40 PM PDT 24
Finished Jun 04 02:54:44 PM PDT 24
Peak memory 274296 kb
Host smart-50bc2b57-37da-4fd1-a778-239c8c8b5999
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535254571 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_mp_regions.3535254571
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.201116400
Short name T190
Test name
Test status
Simulation time 5127496200 ps
CPU time 581.09 seconds
Started Jun 04 02:44:46 PM PDT 24
Finished Jun 04 02:54:28 PM PDT 24
Peak memory 320208 kb
Host smart-ce3826ff-7fbe-4850-9ebf-2078f1a91cfe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201116400 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.flash_ctrl_rw_derr.201116400
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.329365117
Short name T194
Test name
Test status
Simulation time 16506520300 ps
CPU time 245.29 seconds
Started Jun 04 02:43:32 PM PDT 24
Finished Jun 04 02:47:38 PM PDT 24
Peak memory 291464 kb
Host smart-f7305360-43e7-47a1-9ebb-dfbd4f41b856
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329365117 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.329365117
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.3010461244
Short name T164
Test name
Test status
Simulation time 785392200 ps
CPU time 2114.63 seconds
Started Jun 04 02:44:24 PM PDT 24
Finished Jun 04 03:19:40 PM PDT 24
Peak memory 264720 kb
Host smart-c674a913-cb36-49a3-bde2-102d388602a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010461244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.3010461244
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3197114312
Short name T230
Test name
Test status
Simulation time 15324300 ps
CPU time 13.35 seconds
Started Jun 04 01:19:40 PM PDT 24
Finished Jun 04 01:19:55 PM PDT 24
Peak memory 263984 kb
Host smart-d047150f-7378-4b36-9fa1-6869d20aa325
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197114312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.3197114312
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.1787793175
Short name T138
Test name
Test status
Simulation time 15178400 ps
CPU time 13.58 seconds
Started Jun 04 02:51:02 PM PDT 24
Finished Jun 04 02:51:16 PM PDT 24
Peak memory 263952 kb
Host smart-fbd910b7-da5e-42af-bc8a-7fdb840a573f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787793175 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.1787793175
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2145385878
Short name T208
Test name
Test status
Simulation time 259242800 ps
CPU time 19.83 seconds
Started Jun 04 01:19:46 PM PDT 24
Finished Jun 04 01:20:07 PM PDT 24
Peak memory 264168 kb
Host smart-e86eaafa-11e9-4036-8633-bb474a20e3af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145385878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.2
145385878
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.3589029311
Short name T55
Test name
Test status
Simulation time 916125600 ps
CPU time 20.42 seconds
Started Jun 04 02:46:15 PM PDT 24
Finished Jun 04 02:46:36 PM PDT 24
Peak memory 264960 kb
Host smart-1c595b76-efd2-463d-b38c-0a8c41c974e1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589029311 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.3589029311
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.1112102013
Short name T102
Test name
Test status
Simulation time 2498407300 ps
CPU time 73.39 seconds
Started Jun 04 02:46:38 PM PDT 24
Finished Jun 04 02:47:52 PM PDT 24
Peak memory 260436 kb
Host smart-555d4ccb-4676-43a7-b78d-6d585a34ef62
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112102013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1112102013
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.235040092
Short name T206
Test name
Test status
Simulation time 2837503400 ps
CPU time 885.26 seconds
Started Jun 04 01:20:00 PM PDT 24
Finished Jun 04 01:34:46 PM PDT 24
Peak memory 260704 kb
Host smart-479b0b59-7cb7-446e-8fce-7fa18d2f4a31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235040092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl
_tl_intg_err.235040092
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.3906713780
Short name T64
Test name
Test status
Simulation time 80131499500 ps
CPU time 783.61 seconds
Started Jun 04 02:52:15 PM PDT 24
Finished Jun 04 03:05:19 PM PDT 24
Peak memory 264328 kb
Host smart-3a5fdb51-b39f-4c51-9943-9011451142f5
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906713780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.3906713780
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2207330009
Short name T339
Test name
Test status
Simulation time 18600100 ps
CPU time 13.41 seconds
Started Jun 04 01:19:44 PM PDT 24
Finished Jun 04 01:19:59 PM PDT 24
Peak memory 262724 kb
Host smart-80628322-db33-41e8-92fa-af1e4a0ef9f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207330009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.2
207330009
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.3934369645
Short name T10
Test name
Test status
Simulation time 309466100 ps
CPU time 15.47 seconds
Started Jun 04 02:41:07 PM PDT 24
Finished Jun 04 02:41:23 PM PDT 24
Peak memory 264744 kb
Host smart-e0356b4a-aedb-4b9b-b3f9-054462cbe340
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934369645 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.3934369645
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2367689037
Short name T263
Test name
Test status
Simulation time 1339849400 ps
CPU time 907.43 seconds
Started Jun 04 01:19:45 PM PDT 24
Finished Jun 04 01:34:54 PM PDT 24
Peak memory 264212 kb
Host smart-8589cdc2-ecd2-4ca6-b8c3-81d7b214d7d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367689037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.2367689037
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.945434147
Short name T200
Test name
Test status
Simulation time 495893500 ps
CPU time 133.45 seconds
Started Jun 04 02:56:53 PM PDT 24
Finished Jun 04 02:59:06 PM PDT 24
Peak memory 291804 kb
Host smart-7d32e1c8-0f8b-4793-99d3-d5b1fdacce7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945434147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flas
h_ctrl_intr_rd.945434147
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.3662173154
Short name T189
Test name
Test status
Simulation time 1164929800 ps
CPU time 156.5 seconds
Started Jun 04 02:46:00 PM PDT 24
Finished Jun 04 02:48:37 PM PDT 24
Peak memory 281700 kb
Host smart-609e19ff-7871-4354-8f76-ec13f69a2b73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3662173154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.3662173154
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.327474706
Short name T326
Test name
Test status
Simulation time 45929200 ps
CPU time 31.09 seconds
Started Jun 04 02:54:42 PM PDT 24
Finished Jun 04 02:55:14 PM PDT 24
Peak memory 275160 kb
Host smart-6804fecc-2ff3-4aa3-ada1-bc1c02fa87f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327474706 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.327474706
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.3981815
Short name T14
Test name
Test status
Simulation time 1383046900 ps
CPU time 4846.72 seconds
Started Jun 04 02:40:59 PM PDT 24
Finished Jun 04 04:01:46 PM PDT 24
Peak memory 286340 kb
Host smart-def3a8d7-df96-4fa8-8ef2-2a3425d8bad4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.3981815
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.707062463
Short name T61
Test name
Test status
Simulation time 17230500 ps
CPU time 13.41 seconds
Started Jun 04 02:57:13 PM PDT 24
Finished Jun 04 02:57:27 PM PDT 24
Peak memory 274724 kb
Host smart-f07ab6d1-8d29-43f3-be17-4598d057b2cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707062463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.707062463
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3101702193
Short name T171
Test name
Test status
Simulation time 8750976600 ps
CPU time 197.42 seconds
Started Jun 04 02:50:40 PM PDT 24
Finished Jun 04 02:53:57 PM PDT 24
Peak memory 292876 kb
Host smart-646f6547-f8e3-427f-8560-483dfd04740e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101702193 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.3101702193
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1008095798
Short name T323
Test name
Test status
Simulation time 37397700 ps
CPU time 32.12 seconds
Started Jun 04 02:55:52 PM PDT 24
Finished Jun 04 02:56:25 PM PDT 24
Peak memory 275164 kb
Host smart-8d1a4d10-45ba-4d4e-8882-fe55153d856b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008095798 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1008095798
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.2043871913
Short name T169
Test name
Test status
Simulation time 294931700 ps
CPU time 35.08 seconds
Started Jun 04 02:42:33 PM PDT 24
Finished Jun 04 02:43:08 PM PDT 24
Peak memory 261876 kb
Host smart-f4fbc01b-1364-433f-8a44-00a1f79bc7b8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043871913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.2043871913
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1956116854
Short name T260
Test name
Test status
Simulation time 603268700 ps
CPU time 21.12 seconds
Started Jun 04 01:19:53 PM PDT 24
Finished Jun 04 01:20:15 PM PDT 24
Peak memory 264056 kb
Host smart-cd016cd5-8168-4544-8fc6-df191e90825e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956116854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
1956116854
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.1984944504
Short name T214
Test name
Test status
Simulation time 17173800 ps
CPU time 13.91 seconds
Started Jun 04 02:43:52 PM PDT 24
Finished Jun 04 02:44:06 PM PDT 24
Peak memory 260564 kb
Host smart-26eae712-4e7c-460f-8992-2faf10fae26c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1984944504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.1984944504
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.2698456039
Short name T316
Test name
Test status
Simulation time 73046414500 ps
CPU time 242.86 seconds
Started Jun 04 02:54:50 PM PDT 24
Finished Jun 04 02:58:54 PM PDT 24
Peak memory 262264 kb
Host smart-63cb7f06-b5e6-4917-b572-ce7d4d7b772e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698456039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.2698456039
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.917477132
Short name T191
Test name
Test status
Simulation time 3907857100 ps
CPU time 759.3 seconds
Started Jun 04 02:40:23 PM PDT 24
Finished Jun 04 02:53:03 PM PDT 24
Peak memory 334956 kb
Host smart-0044a279-f704-4533-99c3-e98999e51179
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917477132 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.flash_ctrl_rw_derr.917477132
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.3558145388
Short name T278
Test name
Test status
Simulation time 917129000 ps
CPU time 181.61 seconds
Started Jun 04 02:43:30 PM PDT 24
Finished Jun 04 02:46:32 PM PDT 24
Peak memory 293552 kb
Host smart-19c0e3a1-4210-4a73-ab36-141a5c2df158
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558145388 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.3558145388
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.1768830611
Short name T149
Test name
Test status
Simulation time 50424200 ps
CPU time 132.13 seconds
Started Jun 04 02:58:44 PM PDT 24
Finished Jun 04 03:00:57 PM PDT 24
Peak memory 263172 kb
Host smart-10c99a8e-5ed4-4036-a445-43256b9ea519
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768830611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.1768830611
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1666310432
Short name T357
Test name
Test status
Simulation time 662325200 ps
CPU time 456.74 seconds
Started Jun 04 01:20:07 PM PDT 24
Finished Jun 04 01:27:45 PM PDT 24
Peak memory 264152 kb
Host smart-a110b102-e297-4e14-87c9-b5de9379b702
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666310432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.1666310432
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.39277449
Short name T486
Test name
Test status
Simulation time 15036700 ps
CPU time 13.83 seconds
Started Jun 04 02:50:30 PM PDT 24
Finished Jun 04 02:50:44 PM PDT 24
Peak memory 258788 kb
Host smart-95a448d8-adec-46e9-ae57-21f057c2fab4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39277449 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.39277449
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.2114787762
Short name T399
Test name
Test status
Simulation time 2227584100 ps
CPU time 76.08 seconds
Started Jun 04 02:53:18 PM PDT 24
Finished Jun 04 02:54:35 PM PDT 24
Peak memory 259512 kb
Host smart-3508fe74-9760-44d2-b375-254280fca1ce
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114787762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.2
114787762
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.1915268277
Short name T25
Test name
Test status
Simulation time 12578800 ps
CPU time 13.88 seconds
Started Jun 04 02:41:07 PM PDT 24
Finished Jun 04 02:41:22 PM PDT 24
Peak memory 264824 kb
Host smart-c81f662e-ecbe-4a8b-a2ec-31cc3ec0c9d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915268277 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.1915268277
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.4061850637
Short name T514
Test name
Test status
Simulation time 15335000 ps
CPU time 13.84 seconds
Started Jun 04 02:54:23 PM PDT 24
Finished Jun 04 02:54:38 PM PDT 24
Peak memory 260068 kb
Host smart-42e1fbf2-da32-4ca4-9765-5f91da6e556d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061850637 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.4061850637
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.3453056051
Short name T179
Test name
Test status
Simulation time 15962400 ps
CPU time 20.96 seconds
Started Jun 04 02:52:25 PM PDT 24
Finished Jun 04 02:52:47 PM PDT 24
Peak memory 273112 kb
Host smart-86173e10-9da1-4a01-84c9-93b896619b0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453056051 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.3453056051
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1331164522
Short name T26
Test name
Test status
Simulation time 21076206400 ps
CPU time 175.93 seconds
Started Jun 04 02:42:20 PM PDT 24
Finished Jun 04 02:45:17 PM PDT 24
Peak memory 260040 kb
Host smart-f46fa550-e0d2-4c7f-ac83-6063b64c0e47
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133
1164522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.1331164522
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.3350272978
Short name T281
Test name
Test status
Simulation time 15393200 ps
CPU time 13.55 seconds
Started Jun 04 02:41:25 PM PDT 24
Finished Jun 04 02:41:39 PM PDT 24
Peak memory 258064 kb
Host smart-281cd154-23f9-4562-8061-030605f7ac68
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350272978 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.3350272978
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.3384332788
Short name T145
Test name
Test status
Simulation time 10031714600 ps
CPU time 49.24 seconds
Started Jun 04 02:42:48 PM PDT 24
Finished Jun 04 02:43:38 PM PDT 24
Peak memory 264580 kb
Host smart-032507d7-ab06-43e4-8acc-ec4c3312a2cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384332788 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.3384332788
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.975749768
Short name T816
Test name
Test status
Simulation time 10033873800 ps
CPU time 109.03 seconds
Started Jun 04 02:50:30 PM PDT 24
Finished Jun 04 02:52:19 PM PDT 24
Peak memory 273812 kb
Host smart-31ad5822-071d-4738-b736-0fad0eaa44c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975749768 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.975749768
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.3155197900
Short name T360
Test name
Test status
Simulation time 1183118000 ps
CPU time 70.63 seconds
Started Jun 04 02:53:19 PM PDT 24
Finished Jun 04 02:54:30 PM PDT 24
Peak memory 262420 kb
Host smart-4a5fd8e4-8193-4412-95f0-7955fd47b221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155197900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3155197900
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.4167521869
Short name T384
Test name
Test status
Simulation time 13341871400 ps
CPU time 75.59 seconds
Started Jun 04 02:53:45 PM PDT 24
Finished Jun 04 02:55:01 PM PDT 24
Peak memory 262712 kb
Host smart-36137a42-0357-4775-bf6b-e0a6014f9133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167521869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.4167521869
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.3439435518
Short name T381
Test name
Test status
Simulation time 3286612600 ps
CPU time 69.03 seconds
Started Jun 04 02:57:30 PM PDT 24
Finished Jun 04 02:58:39 PM PDT 24
Peak memory 262968 kb
Host smart-c8229970-8b77-4339-883f-e2352aee0fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439435518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.3439435518
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.696198595
Short name T272
Test name
Test status
Simulation time 2911717600 ps
CPU time 157.88 seconds
Started Jun 04 02:41:35 PM PDT 24
Finished Jun 04 02:44:13 PM PDT 24
Peak memory 264940 kb
Host smart-ea4d6702-7f32-4782-9ea3-89e542bf66e0
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=696198595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.696198595
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.3346630966
Short name T63
Test name
Test status
Simulation time 46763600 ps
CPU time 14.15 seconds
Started Jun 04 02:46:17 PM PDT 24
Finished Jun 04 02:46:31 PM PDT 24
Peak memory 276448 kb
Host smart-c6798f56-9878-4456-a49a-59c30d04385f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3346630966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.3346630966
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.3317653970
Short name T27
Test name
Test status
Simulation time 29568500 ps
CPU time 31.68 seconds
Started Jun 04 02:46:08 PM PDT 24
Finished Jun 04 02:46:40 PM PDT 24
Peak memory 275136 kb
Host smart-ad7865a3-0102-4e80-b3f3-277e52fab882
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317653970 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.3317653970
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.875140055
Short name T80
Test name
Test status
Simulation time 830401100 ps
CPU time 20.14 seconds
Started Jun 04 02:41:14 PM PDT 24
Finished Jun 04 02:41:35 PM PDT 24
Peak memory 262792 kb
Host smart-853c131d-fcc1-4f9a-b690-d91c7b95a8cb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875140055 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.875140055
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.3018731654
Short name T160
Test name
Test status
Simulation time 444473816400 ps
CPU time 1720.82 seconds
Started Jun 04 02:39:46 PM PDT 24
Finished Jun 04 03:08:27 PM PDT 24
Peak memory 263784 kb
Host smart-f8d327a3-0e5d-42d7-ac15-57fc3dcf149d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018731654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.3018731654
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2556514629
Short name T268
Test name
Test status
Simulation time 713508100 ps
CPU time 379.08 seconds
Started Jun 04 01:19:52 PM PDT 24
Finished Jun 04 01:26:13 PM PDT 24
Peak memory 260596 kb
Host smart-3c94eca0-1a10-4336-8dc0-94280437a0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556514629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.2556514629
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3261819133
Short name T1113
Test name
Test status
Simulation time 96727600 ps
CPU time 13.25 seconds
Started Jun 04 01:20:07 PM PDT 24
Finished Jun 04 01:20:22 PM PDT 24
Peak memory 262716 kb
Host smart-5a33447d-ccaa-4e25-baa8-06822979fb8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261819133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
3261819133
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.728836196
Short name T245
Test name
Test status
Simulation time 23314200 ps
CPU time 13.77 seconds
Started Jun 04 02:41:21 PM PDT 24
Finished Jun 04 02:41:35 PM PDT 24
Peak memory 261252 kb
Host smart-fcc81fcb-5fe7-45fe-b322-75fdcd23cfca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728836196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
flash_ctrl_config_regwen.728836196
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.1412557875
Short name T821
Test name
Test status
Simulation time 20754700 ps
CPU time 20.91 seconds
Started Jun 04 02:42:24 PM PDT 24
Finished Jun 04 02:42:46 PM PDT 24
Peak memory 273056 kb
Host smart-ac1dae78-dafc-4cfe-85be-5ff73669f37a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412557875 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.1412557875
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.1269378717
Short name T344
Test name
Test status
Simulation time 3323976000 ps
CPU time 326.14 seconds
Started Jun 04 02:50:40 PM PDT 24
Finished Jun 04 02:56:07 PM PDT 24
Peak memory 283768 kb
Host smart-7873300b-3736-4a37-a8e1-37fd0c4bf892
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269378717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.1269378717
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.1488230116
Short name T378
Test name
Test status
Simulation time 1757670600 ps
CPU time 59.7 seconds
Started Jun 04 02:50:53 PM PDT 24
Finished Jun 04 02:51:53 PM PDT 24
Peak memory 262820 kb
Host smart-57dd5b71-bd83-43ef-8572-b4305c020147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488230116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.1488230116
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.434558072
Short name T40
Test name
Test status
Simulation time 1752845200 ps
CPU time 221.24 seconds
Started Jun 04 02:51:17 PM PDT 24
Finished Jun 04 02:54:59 PM PDT 24
Peak memory 290500 kb
Host smart-9e3e538e-0a7e-4df2-83db-33e28cd51865
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434558072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flas
h_ctrl_intr_rd.434558072
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.680828443
Short name T400
Test name
Test status
Simulation time 2141892200 ps
CPU time 63.06 seconds
Started Jun 04 02:51:09 PM PDT 24
Finished Jun 04 02:52:13 PM PDT 24
Peak memory 262784 kb
Host smart-5bdac018-4b91-4bcf-896a-a0bc8d95157d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680828443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.680828443
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.2946489477
Short name T387
Test name
Test status
Simulation time 7639265200 ps
CPU time 66.29 seconds
Started Jun 04 02:52:43 PM PDT 24
Finished Jun 04 02:53:50 PM PDT 24
Peak memory 264228 kb
Host smart-08ca115e-1ebd-4a95-9ea6-6eb5796e24b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946489477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.2946489477
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.4081221352
Short name T908
Test name
Test status
Simulation time 52769700 ps
CPU time 20.45 seconds
Started Jun 04 02:53:18 PM PDT 24
Finished Jun 04 02:53:39 PM PDT 24
Peak memory 273196 kb
Host smart-57649cb1-7e5b-43f8-bb2d-a89da2590158
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081221352 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.4081221352
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.3576550105
Short name T365
Test name
Test status
Simulation time 128272400 ps
CPU time 21.85 seconds
Started Jun 04 02:53:44 PM PDT 24
Finished Jun 04 02:54:07 PM PDT 24
Peak memory 264880 kb
Host smart-567f8052-59e2-44c7-82a5-1e1f2b04cfa6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576550105 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.3576550105
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.831459278
Short name T322
Test name
Test status
Simulation time 48541600 ps
CPU time 28.24 seconds
Started Jun 04 02:55:07 PM PDT 24
Finished Jun 04 02:55:36 PM PDT 24
Peak memory 274464 kb
Host smart-d19a21bb-bd62-4445-aa35-88dcc3bd31c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831459278 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.831459278
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.2441155314
Short name T89
Test name
Test status
Simulation time 36482100 ps
CPU time 22.45 seconds
Started Jun 04 02:55:44 PM PDT 24
Finished Jun 04 02:56:07 PM PDT 24
Peak memory 273080 kb
Host smart-9a06bc8a-acf9-462b-83e2-6b2c8e583ce9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441155314 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.2441155314
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.2844855265
Short name T379
Test name
Test status
Simulation time 31173394000 ps
CPU time 69.65 seconds
Started Jun 04 02:55:48 PM PDT 24
Finished Jun 04 02:56:58 PM PDT 24
Peak memory 262856 kb
Host smart-c26b5640-a345-46c3-ad23-cc44e326aaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844855265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2844855265
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.3612390350
Short name T392
Test name
Test status
Simulation time 3763053300 ps
CPU time 83.49 seconds
Started Jun 04 02:56:11 PM PDT 24
Finished Jun 04 02:57:34 PM PDT 24
Peak memory 262988 kb
Host smart-2a6212db-2ca4-4cc4-9f93-cb84bd41a0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612390350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.3612390350
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.4073678159
Short name T23
Test name
Test status
Simulation time 788674900 ps
CPU time 37.6 seconds
Started Jun 04 02:44:53 PM PDT 24
Finished Jun 04 02:45:31 PM PDT 24
Peak memory 261820 kb
Host smart-7816291b-5c7d-40e9-a79c-efa0292d6e65
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073678159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.4073678159
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2483148396
Short name T250
Test name
Test status
Simulation time 35644300 ps
CPU time 17.43 seconds
Started Jun 04 01:19:30 PM PDT 24
Finished Jun 04 01:19:48 PM PDT 24
Peak memory 264212 kb
Host smart-84f9aad6-fc7d-4faa-af28-7bb4467cfe95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483148396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.2
483148396
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.4222776674
Short name T141
Test name
Test status
Simulation time 350284195400 ps
CPU time 911.89 seconds
Started Jun 04 02:53:19 PM PDT 24
Finished Jun 04 03:08:32 PM PDT 24
Peak memory 263180 kb
Host smart-5b26e774-01c0-4946-b318-33fcdc22029c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222776674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.4222776674
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2857456216
Short name T1223
Test name
Test status
Simulation time 303177500 ps
CPU time 19.26 seconds
Started Jun 04 01:19:54 PM PDT 24
Finished Jun 04 01:20:15 PM PDT 24
Peak memory 264108 kb
Host smart-99c418f1-508a-4c2e-9648-7f4f51e60510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857456216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
2857456216
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.1385529108
Short name T519
Test name
Test status
Simulation time 5401606900 ps
CPU time 2307.96 seconds
Started Jun 04 02:40:02 PM PDT 24
Finished Jun 04 03:18:31 PM PDT 24
Peak memory 264456 kb
Host smart-4af763c3-f26f-4f7d-aa6c-4987c710e109
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385529108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.1385529108
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.1858599376
Short name T1065
Test name
Test status
Simulation time 3051459800 ps
CPU time 753.94 seconds
Started Jun 04 02:39:55 PM PDT 24
Finished Jun 04 02:52:29 PM PDT 24
Peak memory 273016 kb
Host smart-7b232f16-d44f-4a43-ab8c-e93c0a65a2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858599376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.1858599376
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.690170711
Short name T196
Test name
Test status
Simulation time 434758427900 ps
CPU time 2405.38 seconds
Started Jun 04 02:39:54 PM PDT 24
Finished Jun 04 03:20:00 PM PDT 24
Peak memory 264852 kb
Host smart-52cea481-e08e-4b5d-a723-a9ee16eb82da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690170711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.flash_ctrl_host_ctrl_arb.690170711
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.515839713
Short name T11
Test name
Test status
Simulation time 39537900 ps
CPU time 13.93 seconds
Started Jun 04 02:42:35 PM PDT 24
Finished Jun 04 02:42:49 PM PDT 24
Peak memory 260864 kb
Host smart-f5197f94-ecd5-40ec-83a3-0c80689cebf7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515839713 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.515839713
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.426193506
Short name T113
Test name
Test status
Simulation time 99802072700 ps
CPU time 3806.98 seconds
Started Jun 04 02:41:56 PM PDT 24
Finished Jun 04 03:45:24 PM PDT 24
Peak memory 264912 kb
Host smart-3a58afa3-f1aa-4d67-818b-572c45a0c52b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426193506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_full_mem_access.426193506
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.3222870994
Short name T54
Test name
Test status
Simulation time 817738400 ps
CPU time 15.35 seconds
Started Jun 04 02:42:34 PM PDT 24
Finished Jun 04 02:42:50 PM PDT 24
Peak memory 260504 kb
Host smart-19ed23bd-6c64-4832-b6c5-4d9570a5c900
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222870994 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.3222870994
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.2857493770
Short name T279
Test name
Test status
Simulation time 13858732100 ps
CPU time 589.97 seconds
Started Jun 04 02:42:04 PM PDT 24
Finished Jun 04 02:51:55 PM PDT 24
Peak memory 309040 kb
Host smart-8630d993-4ce5-414b-b22b-3ab466ecd8f2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857493770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.flash_ctrl_rw.2857493770
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3219807987
Short name T152
Test name
Test status
Simulation time 346143876600 ps
CPU time 2355.55 seconds
Started Jun 04 02:43:02 PM PDT 24
Finished Jun 04 03:22:18 PM PDT 24
Peak memory 262136 kb
Host smart-f7f0b782-03d6-4ef8-a01a-5ff5b26da35f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219807987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.3219807987
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.2621157938
Short name T213
Test name
Test status
Simulation time 756471500 ps
CPU time 23.51 seconds
Started Jun 04 02:43:45 PM PDT 24
Finished Jun 04 02:44:09 PM PDT 24
Peak memory 264532 kb
Host smart-cf886d71-c964-48fa-95e2-a84911e7e22d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621157938 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.2621157938
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.2083462514
Short name T21
Test name
Test status
Simulation time 70287300 ps
CPU time 15.01 seconds
Started Jun 04 02:43:46 PM PDT 24
Finished Jun 04 02:44:01 PM PDT 24
Peak memory 264676 kb
Host smart-ab8dcda7-957a-41d5-933e-6f0d6dddbbd4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083462514 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.2083462514
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.2677370426
Short name T212
Test name
Test status
Simulation time 76493900 ps
CPU time 132.68 seconds
Started Jun 04 02:57:23 PM PDT 24
Finished Jun 04 02:59:36 PM PDT 24
Peak memory 263744 kb
Host smart-507aab58-48d2-48d2-bb5d-f2fef2c0d5c1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677370426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.2677370426
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.803187624
Short name T192
Test name
Test status
Simulation time 714818100 ps
CPU time 164.45 seconds
Started Jun 04 02:49:01 PM PDT 24
Finished Jun 04 02:51:46 PM PDT 24
Peak memory 281248 kb
Host smart-1c2780c7-5b90-49f1-a92d-6928c84ee901
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
803187624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.803187624
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1647602211
Short name T1145
Test name
Test status
Simulation time 4166770200 ps
CPU time 36.4 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:20:10 PM PDT 24
Peak memory 260424 kb
Host smart-179db430-a3b5-4159-a24c-925c95daac7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647602211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.1647602211
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.535340573
Short name T1186
Test name
Test status
Simulation time 4197458900 ps
CPU time 63.01 seconds
Started Jun 04 01:19:31 PM PDT 24
Finished Jun 04 01:20:35 PM PDT 24
Peak memory 260500 kb
Host smart-6926d67c-bb1a-4f15-b771-e26ea1dea590
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535340573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_bit_bash.535340573
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1924394688
Short name T1149
Test name
Test status
Simulation time 28088400 ps
CPU time 45.44 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:20:19 PM PDT 24
Peak memory 260432 kb
Host smart-db99aae7-ee78-456c-bd45-a7b2e3c06aac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924394688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.1924394688
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2835242922
Short name T225
Test name
Test status
Simulation time 155330200 ps
CPU time 17.76 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:19:51 PM PDT 24
Peak memory 272172 kb
Host smart-befafa0a-f5c4-44bc-987a-c7424b27ed6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835242922 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.2835242922
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1884537114
Short name T1118
Test name
Test status
Simulation time 50792000 ps
CPU time 17.32 seconds
Started Jun 04 01:19:34 PM PDT 24
Finished Jun 04 01:19:52 PM PDT 24
Peak memory 260520 kb
Host smart-52d4461c-3c6d-4904-bdd4-264561226281
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884537114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.1884537114
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1966853828
Short name T1153
Test name
Test status
Simulation time 18586400 ps
CPU time 13.7 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:19:48 PM PDT 24
Peak memory 262492 kb
Host smart-833044de-4ac5-4a0a-a6c7-db643d9285d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966853828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.1
966853828
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.534058128
Short name T231
Test name
Test status
Simulation time 29947700 ps
CPU time 13.63 seconds
Started Jun 04 01:19:34 PM PDT 24
Finished Jun 04 01:19:49 PM PDT 24
Peak memory 264008 kb
Host smart-535ff71f-2c13-4a3f-ae55-2c90f89e4e49
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534058128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_mem_partial_access.534058128
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.255516861
Short name T1135
Test name
Test status
Simulation time 29811500 ps
CPU time 13.42 seconds
Started Jun 04 01:19:33 PM PDT 24
Finished Jun 04 01:19:48 PM PDT 24
Peak memory 262808 kb
Host smart-506cd805-fb5b-461d-a9f9-ca412ebdac69
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255516861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem
_walk.255516861
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3826446877
Short name T1213
Test name
Test status
Simulation time 212165400 ps
CPU time 34.73 seconds
Started Jun 04 01:19:36 PM PDT 24
Finished Jun 04 01:20:11 PM PDT 24
Peak memory 260552 kb
Host smart-a36273a0-9ced-4fc0-b573-7bab0f507d77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826446877 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.3826446877
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1446070953
Short name T1196
Test name
Test status
Simulation time 14061400 ps
CPU time 13.02 seconds
Started Jun 04 01:19:31 PM PDT 24
Finished Jun 04 01:19:45 PM PDT 24
Peak memory 260612 kb
Host smart-852f5ae3-e34d-4f73-87cb-03d0a0b01f44
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446070953 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.1446070953
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3868944292
Short name T1206
Test name
Test status
Simulation time 23733100 ps
CPU time 15.34 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:19:49 PM PDT 24
Peak memory 260352 kb
Host smart-7ef24d73-2444-488a-b898-da92b63f170e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868944292 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.3868944292
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.712637397
Short name T1215
Test name
Test status
Simulation time 50522200 ps
CPU time 18.67 seconds
Started Jun 04 01:19:33 PM PDT 24
Finished Jun 04 01:19:53 PM PDT 24
Peak memory 264156 kb
Host smart-047aa54a-e8ad-4c63-9867-873b8a790155
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712637397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.712637397
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1207687203
Short name T1214
Test name
Test status
Simulation time 167118300 ps
CPU time 385.5 seconds
Started Jun 04 01:19:33 PM PDT 24
Finished Jun 04 01:26:00 PM PDT 24
Peak memory 264156 kb
Host smart-6c9b9a65-2c6e-4c50-8a11-42668f5bddc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207687203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.1207687203
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.959381855
Short name T1220
Test name
Test status
Simulation time 1044460700 ps
CPU time 32.48 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:20:06 PM PDT 24
Peak memory 260400 kb
Host smart-6ecdb455-f038-4459-ba7f-13577b23d256
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959381855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_aliasing.959381855
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1759631147
Short name T1124
Test name
Test status
Simulation time 326138700 ps
CPU time 36.44 seconds
Started Jun 04 01:19:33 PM PDT 24
Finished Jun 04 01:20:11 PM PDT 24
Peak memory 260608 kb
Host smart-6ebfd91b-daae-43aa-90f8-178bd33f5aad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759631147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.1759631147
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2988786172
Short name T1128
Test name
Test status
Simulation time 122227700 ps
CPU time 30.62 seconds
Started Jun 04 01:19:33 PM PDT 24
Finished Jun 04 01:20:05 PM PDT 24
Peak memory 260536 kb
Host smart-d5655e34-6c0d-4f42-b8c2-4b838f78f56a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988786172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.2988786172
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1397274620
Short name T1184
Test name
Test status
Simulation time 375059600 ps
CPU time 19.27 seconds
Started Jun 04 01:19:31 PM PDT 24
Finished Jun 04 01:19:51 PM PDT 24
Peak memory 272328 kb
Host smart-21211454-c23b-466c-b0df-5bcbeb322288
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397274620 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.1397274620
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3463778837
Short name T1205
Test name
Test status
Simulation time 153760900 ps
CPU time 14.4 seconds
Started Jun 04 01:19:33 PM PDT 24
Finished Jun 04 01:19:49 PM PDT 24
Peak memory 260532 kb
Host smart-ab8d22be-7448-4f0e-a789-0a6dfefcbc9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463778837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.3463778837
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.1203631950
Short name T1114
Test name
Test status
Simulation time 30879500 ps
CPU time 13.7 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:19:48 PM PDT 24
Peak memory 262716 kb
Host smart-2fc43427-b425-4bd7-8d2d-7394982be476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203631950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.1
203631950
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2987946887
Short name T233
Test name
Test status
Simulation time 17866100 ps
CPU time 13.4 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:19:47 PM PDT 24
Peak memory 263940 kb
Host smart-3fcae264-b44a-4021-baf7-716cb8087311
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987946887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.2987946887
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1782838128
Short name T1136
Test name
Test status
Simulation time 24192200 ps
CPU time 13.44 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:19:47 PM PDT 24
Peak memory 262836 kb
Host smart-e21b01e1-a87c-43f2-bbdf-701ba493070c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782838128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.1782838128
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3332222432
Short name T293
Test name
Test status
Simulation time 93280800 ps
CPU time 18.05 seconds
Started Jun 04 01:19:33 PM PDT 24
Finished Jun 04 01:19:53 PM PDT 24
Peak memory 260648 kb
Host smart-cf6afe0a-038b-42e0-98a2-f8019ebe8a06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332222432 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.3332222432
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1930657192
Short name T1180
Test name
Test status
Simulation time 42521400 ps
CPU time 15.83 seconds
Started Jun 04 01:19:31 PM PDT 24
Finished Jun 04 01:19:48 PM PDT 24
Peak memory 260544 kb
Host smart-8f303205-a828-4c76-bd11-95b831ee3539
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930657192 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.1930657192
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2822549231
Short name T1232
Test name
Test status
Simulation time 124934100 ps
CPU time 15.7 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:19:49 PM PDT 24
Peak memory 260512 kb
Host smart-0f3d71ba-9844-4034-8958-4936d3dadf2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822549231 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.2822549231
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3941863903
Short name T257
Test name
Test status
Simulation time 1358543300 ps
CPU time 754.96 seconds
Started Jun 04 01:19:36 PM PDT 24
Finished Jun 04 01:32:12 PM PDT 24
Peak memory 264140 kb
Host smart-0f11bff7-afe3-453e-bb97-2ff10fe87625
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941863903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.3941863903
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.971694455
Short name T1115
Test name
Test status
Simulation time 48634400 ps
CPU time 17.69 seconds
Started Jun 04 01:19:52 PM PDT 24
Finished Jun 04 01:20:12 PM PDT 24
Peak memory 270848 kb
Host smart-66315d3e-0b57-4408-ab62-b37eb8135e38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971694455 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.971694455
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1538014816
Short name T1165
Test name
Test status
Simulation time 31008000 ps
CPU time 16.36 seconds
Started Jun 04 01:19:53 PM PDT 24
Finished Jun 04 01:20:12 PM PDT 24
Peak memory 260588 kb
Host smart-e1e2986a-0466-440d-b2bb-e4522b1f3609
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538014816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.1538014816
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2791427178
Short name T1103
Test name
Test status
Simulation time 52737800 ps
CPU time 13.25 seconds
Started Jun 04 01:19:54 PM PDT 24
Finished Jun 04 01:20:09 PM PDT 24
Peak memory 262848 kb
Host smart-52d37a00-d90d-41b7-8aab-5bec10ca6dad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791427178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
2791427178
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2121765146
Short name T302
Test name
Test status
Simulation time 467931600 ps
CPU time 18.1 seconds
Started Jun 04 01:19:53 PM PDT 24
Finished Jun 04 01:20:13 PM PDT 24
Peak memory 260568 kb
Host smart-8801416c-aada-4d29-9057-81de3461228b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121765146 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.2121765146
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1109823092
Short name T1150
Test name
Test status
Simulation time 14733000 ps
CPU time 13.34 seconds
Started Jun 04 01:19:52 PM PDT 24
Finished Jun 04 01:20:07 PM PDT 24
Peak memory 260496 kb
Host smart-077b0571-d21f-4d71-ab16-a112f32b56ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109823092 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.1109823092
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1162257761
Short name T1167
Test name
Test status
Simulation time 18783300 ps
CPU time 15.32 seconds
Started Jun 04 01:19:53 PM PDT 24
Finished Jun 04 01:20:09 PM PDT 24
Peak memory 260564 kb
Host smart-fc34bdb2-b84a-48dd-bfb9-b514ca1bef6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162257761 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.1162257761
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2337510638
Short name T1181
Test name
Test status
Simulation time 244180200 ps
CPU time 15.16 seconds
Started Jun 04 01:19:52 PM PDT 24
Finished Jun 04 01:20:08 PM PDT 24
Peak memory 270712 kb
Host smart-9b67d99d-717c-49b2-a586-bfebd07aaefe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337510638 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.2337510638
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2597778802
Short name T1194
Test name
Test status
Simulation time 82910000 ps
CPU time 16.57 seconds
Started Jun 04 01:19:52 PM PDT 24
Finished Jun 04 01:20:10 PM PDT 24
Peak memory 260508 kb
Host smart-bd9c9621-17d7-4f9b-9fb5-5dfbeea44b5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597778802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.2597778802
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.20462729
Short name T1237
Test name
Test status
Simulation time 57346200 ps
CPU time 13.51 seconds
Started Jun 04 01:19:52 PM PDT 24
Finished Jun 04 01:20:07 PM PDT 24
Peak memory 262652 kb
Host smart-7f2b27d1-704e-4b36-8874-512b2d5b018d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20462729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.20462729
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.392581994
Short name T1222
Test name
Test status
Simulation time 156424900 ps
CPU time 18.59 seconds
Started Jun 04 01:19:53 PM PDT 24
Finished Jun 04 01:20:13 PM PDT 24
Peak memory 260584 kb
Host smart-33488b80-bfff-4b45-a16e-f8fc6f844b87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392581994 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.392581994
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2529332862
Short name T1125
Test name
Test status
Simulation time 33350300 ps
CPU time 15.71 seconds
Started Jun 04 01:19:54 PM PDT 24
Finished Jun 04 01:20:12 PM PDT 24
Peak memory 260512 kb
Host smart-2ac8a3c3-0f3b-4677-8344-033815cfa28c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529332862 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.2529332862
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2545395166
Short name T1166
Test name
Test status
Simulation time 100351800 ps
CPU time 13.18 seconds
Started Jun 04 01:19:52 PM PDT 24
Finished Jun 04 01:20:06 PM PDT 24
Peak memory 260476 kb
Host smart-89ceaf30-a350-471e-9202-5afd5927ce64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545395166 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.2545395166
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.4074143107
Short name T261
Test name
Test status
Simulation time 1478988600 ps
CPU time 891.21 seconds
Started Jun 04 01:19:53 PM PDT 24
Finished Jun 04 01:34:46 PM PDT 24
Peak memory 264168 kb
Host smart-983ba2ec-c951-42a5-9bc4-b3fd2a82c7ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074143107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.4074143107
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.799253235
Short name T71
Test name
Test status
Simulation time 497492600 ps
CPU time 19.83 seconds
Started Jun 04 01:20:00 PM PDT 24
Finished Jun 04 01:20:22 PM PDT 24
Peak memory 272344 kb
Host smart-62e3c365-1a9d-4efd-80c5-b7ba7fd06759
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799253235 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.799253235
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3287687100
Short name T1189
Test name
Test status
Simulation time 48378500 ps
CPU time 17.14 seconds
Started Jun 04 01:19:53 PM PDT 24
Finished Jun 04 01:20:12 PM PDT 24
Peak memory 260888 kb
Host smart-aebc49b0-cddc-4f01-9c67-c59214ac3e8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287687100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.3287687100
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2281340205
Short name T1197
Test name
Test status
Simulation time 32026000 ps
CPU time 13.33 seconds
Started Jun 04 01:19:52 PM PDT 24
Finished Jun 04 01:20:07 PM PDT 24
Peak memory 262820 kb
Host smart-3102860f-ad00-4811-a6a7-aa2c8ef00473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281340205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
2281340205
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3003860815
Short name T1156
Test name
Test status
Simulation time 60598500 ps
CPU time 34.98 seconds
Started Jun 04 01:19:59 PM PDT 24
Finished Jun 04 01:20:35 PM PDT 24
Peak memory 263952 kb
Host smart-baa1ccd7-04bc-48d2-bccd-04c35b38c428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003860815 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.3003860815
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3151783106
Short name T1141
Test name
Test status
Simulation time 42562100 ps
CPU time 15.66 seconds
Started Jun 04 01:19:54 PM PDT 24
Finished Jun 04 01:20:11 PM PDT 24
Peak memory 260628 kb
Host smart-7f1a2011-00b7-4c3b-90fd-54079c501ddd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151783106 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.3151783106
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2706102024
Short name T1193
Test name
Test status
Simulation time 13414300 ps
CPU time 13.1 seconds
Started Jun 04 01:19:52 PM PDT 24
Finished Jun 04 01:20:07 PM PDT 24
Peak memory 260568 kb
Host smart-82b6e2c7-f4b8-4b9b-a00b-29158d7025f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706102024 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.2706102024
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2055971733
Short name T266
Test name
Test status
Simulation time 107020800 ps
CPU time 16.73 seconds
Started Jun 04 01:19:52 PM PDT 24
Finished Jun 04 01:20:11 PM PDT 24
Peak memory 264136 kb
Host smart-eb4d0544-c072-43fc-b861-b756272bd29b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055971733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
2055971733
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2066714162
Short name T1202
Test name
Test status
Simulation time 62309800 ps
CPU time 18.83 seconds
Started Jun 04 01:20:01 PM PDT 24
Finished Jun 04 01:20:22 PM PDT 24
Peak memory 271924 kb
Host smart-22461861-791f-488a-b2b2-7e07a50a965b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066714162 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.2066714162
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.4104906515
Short name T1176
Test name
Test status
Simulation time 133916900 ps
CPU time 16.44 seconds
Started Jun 04 01:20:01 PM PDT 24
Finished Jun 04 01:20:19 PM PDT 24
Peak memory 260656 kb
Host smart-62ef4087-6da5-4771-bf25-060865487b36
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104906515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.4104906515
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1702836447
Short name T1200
Test name
Test status
Simulation time 29055900 ps
CPU time 13.37 seconds
Started Jun 04 01:20:01 PM PDT 24
Finished Jun 04 01:20:16 PM PDT 24
Peak memory 262876 kb
Host smart-d389e920-584a-4afb-94a2-eb7dc859b2b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702836447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
1702836447
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3574120423
Short name T1140
Test name
Test status
Simulation time 90671000 ps
CPU time 15.25 seconds
Started Jun 04 01:19:59 PM PDT 24
Finished Jun 04 01:20:15 PM PDT 24
Peak memory 264168 kb
Host smart-094a3d6c-cfe8-49ff-bb8d-0715dd4c2eae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574120423 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.3574120423
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.823519977
Short name T1127
Test name
Test status
Simulation time 14692800 ps
CPU time 15.56 seconds
Started Jun 04 01:20:00 PM PDT 24
Finished Jun 04 01:20:17 PM PDT 24
Peak memory 260588 kb
Host smart-f97e16f8-2a16-4de2-b954-a11f592a722b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823519977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.823519977
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3456063992
Short name T1168
Test name
Test status
Simulation time 17769100 ps
CPU time 15.84 seconds
Started Jun 04 01:20:00 PM PDT 24
Finished Jun 04 01:20:17 PM PDT 24
Peak memory 260464 kb
Host smart-a0973d69-5f3f-4b48-acc1-69a30d85041d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456063992 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.3456063992
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.693379086
Short name T1233
Test name
Test status
Simulation time 91846700 ps
CPU time 21 seconds
Started Jun 04 01:19:59 PM PDT 24
Finished Jun 04 01:20:20 PM PDT 24
Peak memory 264152 kb
Host smart-f3da3579-ecf7-4b9a-b978-dc195938ad95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693379086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.693379086
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3760471399
Short name T1234
Test name
Test status
Simulation time 708009700 ps
CPU time 450.15 seconds
Started Jun 04 01:20:00 PM PDT 24
Finished Jun 04 01:27:31 PM PDT 24
Peak memory 263980 kb
Host smart-bc385269-a804-4bfa-8cc1-7c1df993ad1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760471399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.3760471399
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1411100709
Short name T1210
Test name
Test status
Simulation time 49948300 ps
CPU time 17.29 seconds
Started Jun 04 01:20:00 PM PDT 24
Finished Jun 04 01:20:19 PM PDT 24
Peak memory 276792 kb
Host smart-8aea6afc-c408-4bdd-b1ab-990a85b60d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411100709 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.1411100709
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2470568713
Short name T1100
Test name
Test status
Simulation time 277101400 ps
CPU time 16.88 seconds
Started Jun 04 01:20:01 PM PDT 24
Finished Jun 04 01:20:19 PM PDT 24
Peak memory 260652 kb
Host smart-3041ec3e-282f-4068-a424-129f5f9b4dc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470568713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.2470568713
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1367702230
Short name T1132
Test name
Test status
Simulation time 15161100 ps
CPU time 13.96 seconds
Started Jun 04 01:19:58 PM PDT 24
Finished Jun 04 01:20:13 PM PDT 24
Peak memory 262884 kb
Host smart-d3a75bfc-89f4-4e98-b6e2-466d28ea4371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367702230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
1367702230
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.473851638
Short name T1117
Test name
Test status
Simulation time 302678500 ps
CPU time 15.05 seconds
Started Jun 04 01:20:00 PM PDT 24
Finished Jun 04 01:20:17 PM PDT 24
Peak memory 260572 kb
Host smart-1b5f305a-69cb-4c8a-b5f7-84881dc6bbfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473851638 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.473851638
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4245896406
Short name T1177
Test name
Test status
Simulation time 25185100 ps
CPU time 13.29 seconds
Started Jun 04 01:20:02 PM PDT 24
Finished Jun 04 01:20:16 PM PDT 24
Peak memory 260552 kb
Host smart-2d1afdc5-1573-47a2-9d2a-bf0a99ae5a5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245896406 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.4245896406
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3861975457
Short name T1198
Test name
Test status
Simulation time 34769600 ps
CPU time 15.44 seconds
Started Jun 04 01:20:00 PM PDT 24
Finished Jun 04 01:20:16 PM PDT 24
Peak memory 260496 kb
Host smart-f19384cf-1173-4266-b723-f4538dbfa904
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861975457 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.3861975457
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1315242962
Short name T247
Test name
Test status
Simulation time 227278400 ps
CPU time 16.94 seconds
Started Jun 04 01:20:00 PM PDT 24
Finished Jun 04 01:20:19 PM PDT 24
Peak memory 264148 kb
Host smart-0da03d4e-22bb-4c3f-aeee-3e4c2e1c28b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315242962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
1315242962
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.322227052
Short name T296
Test name
Test status
Simulation time 647746300 ps
CPU time 465.75 seconds
Started Jun 04 01:20:01 PM PDT 24
Finished Jun 04 01:27:48 PM PDT 24
Peak memory 264164 kb
Host smart-f2e53afa-68ba-4aec-a7b1-e6c3763f29ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322227052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl
_tl_intg_err.322227052
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2537123388
Short name T259
Test name
Test status
Simulation time 189858400 ps
CPU time 17.41 seconds
Started Jun 04 01:19:59 PM PDT 24
Finished Jun 04 01:20:17 PM PDT 24
Peak memory 263128 kb
Host smart-a08bc786-a86c-428f-b63f-fee0b74a5b84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537123388 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.2537123388
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.630089516
Short name T1212
Test name
Test status
Simulation time 62794000 ps
CPU time 13.95 seconds
Started Jun 04 01:20:00 PM PDT 24
Finished Jun 04 01:20:14 PM PDT 24
Peak memory 260484 kb
Host smart-21355c71-783a-4ca1-83b0-45c440f6b6a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630089516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.flash_ctrl_csr_rw.630089516
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.840658264
Short name T1195
Test name
Test status
Simulation time 18541200 ps
CPU time 13.38 seconds
Started Jun 04 01:20:00 PM PDT 24
Finished Jun 04 01:20:15 PM PDT 24
Peak memory 262512 kb
Host smart-95b20d2a-deef-4021-9211-ed221daa5fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840658264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.840658264
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2727086114
Short name T1170
Test name
Test status
Simulation time 153315600 ps
CPU time 21.23 seconds
Started Jun 04 01:19:59 PM PDT 24
Finished Jun 04 01:20:21 PM PDT 24
Peak memory 262480 kb
Host smart-98ec7a01-f9ae-4928-b351-beef9e7c97b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727086114 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.2727086114
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1687232701
Short name T1134
Test name
Test status
Simulation time 23245200 ps
CPU time 15.98 seconds
Started Jun 04 01:20:02 PM PDT 24
Finished Jun 04 01:20:19 PM PDT 24
Peak memory 260488 kb
Host smart-749efd85-ea19-4604-8fd1-78294480ee37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687232701 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.1687232701
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.4260825467
Short name T1107
Test name
Test status
Simulation time 13269400 ps
CPU time 15.37 seconds
Started Jun 04 01:20:01 PM PDT 24
Finished Jun 04 01:20:18 PM PDT 24
Peak memory 260572 kb
Host smart-d6d6d1fc-1b1e-471d-a314-4ae045bf2204
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260825467 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.4260825467
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3949912942
Short name T226
Test name
Test status
Simulation time 35321900 ps
CPU time 16.2 seconds
Started Jun 04 01:20:02 PM PDT 24
Finished Jun 04 01:20:19 PM PDT 24
Peak memory 264320 kb
Host smart-e96e1576-7540-4db4-95ee-beec69c833e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949912942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
3949912942
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.235805663
Short name T1201
Test name
Test status
Simulation time 535398400 ps
CPU time 18.89 seconds
Started Jun 04 01:20:06 PM PDT 24
Finished Jun 04 01:20:27 PM PDT 24
Peak memory 270664 kb
Host smart-5e246215-a3ee-4332-bdd9-6fb68b1d1cee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235805663 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.235805663
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4196119657
Short name T1152
Test name
Test status
Simulation time 56887400 ps
CPU time 16.66 seconds
Started Jun 04 01:20:06 PM PDT 24
Finished Jun 04 01:20:24 PM PDT 24
Peak memory 260572 kb
Host smart-95a01dc8-cd23-4f4b-9632-f51d14f49d23
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196119657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.4196119657
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2554088500
Short name T1208
Test name
Test status
Simulation time 2824596800 ps
CPU time 22.6 seconds
Started Jun 04 01:20:08 PM PDT 24
Finished Jun 04 01:20:33 PM PDT 24
Peak memory 262020 kb
Host smart-37658470-6c45-41e7-a57b-97915b38ef75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554088500 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.2554088500
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2727107177
Short name T1131
Test name
Test status
Simulation time 30445700 ps
CPU time 15.66 seconds
Started Jun 04 01:20:07 PM PDT 24
Finished Jun 04 01:20:25 PM PDT 24
Peak memory 260508 kb
Host smart-267c3929-d472-483d-aeed-b0230350d3c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727107177 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.2727107177
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3731694709
Short name T1216
Test name
Test status
Simulation time 11025100 ps
CPU time 15.43 seconds
Started Jun 04 01:20:06 PM PDT 24
Finished Jun 04 01:20:23 PM PDT 24
Peak memory 260572 kb
Host smart-9db0bd5e-04da-49d5-a908-be1a2b43aef3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731694709 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.3731694709
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2854640001
Short name T249
Test name
Test status
Simulation time 190785400 ps
CPU time 18.05 seconds
Started Jun 04 01:19:58 PM PDT 24
Finished Jun 04 01:20:17 PM PDT 24
Peak memory 264136 kb
Host smart-828302a1-5e35-461a-8c15-1dedb92d7231
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854640001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
2854640001
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.55739872
Short name T269
Test name
Test status
Simulation time 807530400 ps
CPU time 451.81 seconds
Started Jun 04 01:20:08 PM PDT 24
Finished Jun 04 01:27:42 PM PDT 24
Peak memory 260640 kb
Host smart-5d3fea8d-42cd-4933-913c-fdb1a269a9d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55739872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
tl_intg_err.55739872
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.177061102
Short name T1218
Test name
Test status
Simulation time 130134200 ps
CPU time 17.71 seconds
Started Jun 04 01:20:07 PM PDT 24
Finished Jun 04 01:20:27 PM PDT 24
Peak memory 276056 kb
Host smart-c66fbb37-c90f-4b05-8867-285dbeedc3ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177061102 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.177061102
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1241698561
Short name T1191
Test name
Test status
Simulation time 101316200 ps
CPU time 18.33 seconds
Started Jun 04 01:20:05 PM PDT 24
Finished Jun 04 01:20:24 PM PDT 24
Peak memory 260492 kb
Host smart-973abf1a-7ce4-45ad-a422-490e8abd43fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241698561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.1241698561
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.616309063
Short name T340
Test name
Test status
Simulation time 18633700 ps
CPU time 13.21 seconds
Started Jun 04 01:20:06 PM PDT 24
Finished Jun 04 01:20:21 PM PDT 24
Peak memory 262908 kb
Host smart-d936ca62-9c5f-4304-bf36-5e475237e848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616309063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.616309063
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2289502620
Short name T1130
Test name
Test status
Simulation time 190551800 ps
CPU time 19.22 seconds
Started Jun 04 01:20:07 PM PDT 24
Finished Jun 04 01:20:28 PM PDT 24
Peak memory 262176 kb
Host smart-846cb74c-fb0f-4461-8a4b-b2aff29a28c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289502620 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.2289502620
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1737169402
Short name T1148
Test name
Test status
Simulation time 13629800 ps
CPU time 13.06 seconds
Started Jun 04 01:20:07 PM PDT 24
Finished Jun 04 01:20:22 PM PDT 24
Peak memory 260520 kb
Host smart-0700e1e6-76f4-4501-b42d-c03780f3d4c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737169402 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.1737169402
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2842422815
Short name T1101
Test name
Test status
Simulation time 26064300 ps
CPU time 15.54 seconds
Started Jun 04 01:20:06 PM PDT 24
Finished Jun 04 01:20:22 PM PDT 24
Peak memory 260592 kb
Host smart-5afd2ce9-1472-47e0-848e-71c77a907b9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842422815 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.2842422815
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1207238308
Short name T1230
Test name
Test status
Simulation time 72577200 ps
CPU time 16.81 seconds
Started Jun 04 01:20:08 PM PDT 24
Finished Jun 04 01:20:27 PM PDT 24
Peak memory 264156 kb
Host smart-a4609ddf-4c72-4116-8d78-135849b1aa36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207238308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
1207238308
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3091051463
Short name T1159
Test name
Test status
Simulation time 42459900 ps
CPU time 16.17 seconds
Started Jun 04 01:20:06 PM PDT 24
Finished Jun 04 01:20:23 PM PDT 24
Peak memory 279692 kb
Host smart-237edc86-1d63-47ad-afd9-55476b3849cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091051463 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.3091051463
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3656153230
Short name T1217
Test name
Test status
Simulation time 37945900 ps
CPU time 16.4 seconds
Started Jun 04 01:20:05 PM PDT 24
Finished Jun 04 01:20:23 PM PDT 24
Peak memory 260652 kb
Host smart-24658670-be3f-4008-b4e6-fcc752df16a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656153230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.3656153230
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.899128273
Short name T1126
Test name
Test status
Simulation time 37116300 ps
CPU time 13.45 seconds
Started Jun 04 01:20:08 PM PDT 24
Finished Jun 04 01:20:24 PM PDT 24
Peak memory 262736 kb
Host smart-e28ced54-b606-412e-8be5-ca62f4d4fc60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899128273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.899128273
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.4060878333
Short name T1211
Test name
Test status
Simulation time 121930400 ps
CPU time 17.43 seconds
Started Jun 04 01:20:08 PM PDT 24
Finished Jun 04 01:20:27 PM PDT 24
Peak memory 262280 kb
Host smart-705b7b64-6d65-479f-9b1d-24059df8302d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060878333 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.4060878333
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2253615477
Short name T1164
Test name
Test status
Simulation time 11856000 ps
CPU time 15.54 seconds
Started Jun 04 01:20:07 PM PDT 24
Finished Jun 04 01:20:25 PM PDT 24
Peak memory 260612 kb
Host smart-b2f2d531-d2ac-471a-a009-48224efbb762
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253615477 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.2253615477
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3778611247
Short name T1228
Test name
Test status
Simulation time 11912700 ps
CPU time 12.94 seconds
Started Jun 04 01:20:06 PM PDT 24
Finished Jun 04 01:20:20 PM PDT 24
Peak memory 260616 kb
Host smart-f034d15f-4252-45b4-825a-198dd02d520b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778611247 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.3778611247
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.987024882
Short name T251
Test name
Test status
Simulation time 76993700 ps
CPU time 15.92 seconds
Started Jun 04 01:20:05 PM PDT 24
Finished Jun 04 01:20:21 PM PDT 24
Peak memory 264108 kb
Host smart-82741053-66a6-4961-9876-0ae701111103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987024882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.987024882
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2095977149
Short name T358
Test name
Test status
Simulation time 3187971900 ps
CPU time 894.1 seconds
Started Jun 04 01:20:08 PM PDT 24
Finished Jun 04 01:35:04 PM PDT 24
Peak memory 264172 kb
Host smart-a9752234-c705-42c2-a6d1-b8316efe0f8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095977149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.2095977149
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3476106024
Short name T69
Test name
Test status
Simulation time 75215600 ps
CPU time 18.01 seconds
Started Jun 04 01:20:15 PM PDT 24
Finished Jun 04 01:20:34 PM PDT 24
Peak memory 278068 kb
Host smart-1fd741d2-cd3f-4ece-91af-707e68133d1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476106024 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.3476106024
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1677812291
Short name T1172
Test name
Test status
Simulation time 107027800 ps
CPU time 18.04 seconds
Started Jun 04 01:20:07 PM PDT 24
Finished Jun 04 01:20:27 PM PDT 24
Peak memory 260440 kb
Host smart-d60647bf-3adb-453d-942f-d6123f87dd41
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677812291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.1677812291
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.698999948
Short name T1122
Test name
Test status
Simulation time 17947300 ps
CPU time 13.73 seconds
Started Jun 04 01:20:06 PM PDT 24
Finished Jun 04 01:20:21 PM PDT 24
Peak memory 262624 kb
Host smart-919ead3a-40c9-408a-a577-594813dffaaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698999948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.698999948
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3527079109
Short name T239
Test name
Test status
Simulation time 81355200 ps
CPU time 17.7 seconds
Started Jun 04 01:20:15 PM PDT 24
Finished Jun 04 01:20:34 PM PDT 24
Peak memory 260580 kb
Host smart-722d1d09-80d6-448b-ac8c-ac6d357fbbea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527079109 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.3527079109
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3788863017
Short name T1137
Test name
Test status
Simulation time 25199400 ps
CPU time 13.37 seconds
Started Jun 04 01:20:06 PM PDT 24
Finished Jun 04 01:20:21 PM PDT 24
Peak memory 260540 kb
Host smart-a0d714b2-b4d7-4b3c-a994-1e6361a1c65b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788863017 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3788863017
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2159662438
Short name T1095
Test name
Test status
Simulation time 46418600 ps
CPU time 15.74 seconds
Started Jun 04 01:20:07 PM PDT 24
Finished Jun 04 01:20:25 PM PDT 24
Peak memory 260460 kb
Host smart-1a969b1d-62ca-4e1d-ae83-3c67dc8719fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159662438 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2159662438
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3292387470
Short name T248
Test name
Test status
Simulation time 86646900 ps
CPU time 16.72 seconds
Started Jun 04 01:20:06 PM PDT 24
Finished Jun 04 01:20:24 PM PDT 24
Peak memory 264184 kb
Host smart-7742f9c3-6148-4234-b86b-453a29252e3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292387470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
3292387470
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1417664823
Short name T262
Test name
Test status
Simulation time 727216000 ps
CPU time 449.4 seconds
Started Jun 04 01:20:07 PM PDT 24
Finished Jun 04 01:27:38 PM PDT 24
Peak memory 261936 kb
Host smart-631aa606-7483-4289-9e3c-d2abfffa87b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417664823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.1417664823
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.894613118
Short name T1236
Test name
Test status
Simulation time 1310240700 ps
CPU time 39.69 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:20:20 PM PDT 24
Peak memory 260528 kb
Host smart-bc5c54b4-299f-4e4b-a50c-9f9eccc94770
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894613118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_aliasing.894613118
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.84885599
Short name T1158
Test name
Test status
Simulation time 1342806100 ps
CPU time 43.29 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:20:23 PM PDT 24
Peak memory 262448 kb
Host smart-cedea274-459f-4df2-8cc9-96e3c04eeb2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84885599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.flash_ctrl_csr_bit_bash.84885599
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3592092708
Short name T304
Test name
Test status
Simulation time 172167800 ps
CPU time 25.75 seconds
Started Jun 04 01:19:34 PM PDT 24
Finished Jun 04 01:20:01 PM PDT 24
Peak memory 260532 kb
Host smart-95ca97bb-309f-46a0-8462-cea87c72681a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592092708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.3592092708
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1285294777
Short name T1209
Test name
Test status
Simulation time 392006400 ps
CPU time 17.3 seconds
Started Jun 04 01:19:38 PM PDT 24
Finished Jun 04 01:19:56 PM PDT 24
Peak memory 272328 kb
Host smart-89c63180-0df4-4b90-b8cb-687c06b0ac6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285294777 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.1285294777
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.483740679
Short name T1139
Test name
Test status
Simulation time 104605100 ps
CPU time 17.19 seconds
Started Jun 04 01:19:41 PM PDT 24
Finished Jun 04 01:19:59 PM PDT 24
Peak memory 260456 kb
Host smart-b476d74f-732b-4ac7-9ca2-793063a8cddd
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483740679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_csr_rw.483740679
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.66527039
Short name T1169
Test name
Test status
Simulation time 16693100 ps
CPU time 13.48 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:19:46 PM PDT 24
Peak memory 262492 kb
Host smart-68d34137-a06c-4c60-b016-879564bba68b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66527039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.66527039
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.509740988
Short name T232
Test name
Test status
Simulation time 21014900 ps
CPU time 13.24 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:19:47 PM PDT 24
Peak memory 263748 kb
Host smart-d6c2654f-7cb8-469e-a63b-b755de5d1ab4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509740988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_mem_partial_access.509740988
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4225384601
Short name T1096
Test name
Test status
Simulation time 48743600 ps
CPU time 13.54 seconds
Started Jun 04 01:19:34 PM PDT 24
Finished Jun 04 01:19:48 PM PDT 24
Peak memory 262768 kb
Host smart-a707c35b-94ae-4169-800c-4d36d293dcfa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225384601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.4225384601
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.497683972
Short name T1190
Test name
Test status
Simulation time 303830000 ps
CPU time 33.46 seconds
Started Jun 04 01:19:38 PM PDT 24
Finished Jun 04 01:20:12 PM PDT 24
Peak memory 262232 kb
Host smart-0b177c1b-8754-479a-b452-1d87fd8bc3c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497683972 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.497683972
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2905822352
Short name T1110
Test name
Test status
Simulation time 15038900 ps
CPU time 14.03 seconds
Started Jun 04 01:19:32 PM PDT 24
Finished Jun 04 01:19:47 PM PDT 24
Peak memory 260552 kb
Host smart-e7b7a2ca-c3c1-44b0-b9db-8a25041471cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905822352 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2905822352
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3077068650
Short name T1188
Test name
Test status
Simulation time 29030900 ps
CPU time 13.43 seconds
Started Jun 04 01:19:34 PM PDT 24
Finished Jun 04 01:19:48 PM PDT 24
Peak memory 260484 kb
Host smart-caf9bc52-2251-46af-9978-c2af1e5aaf83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077068650 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.3077068650
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.485057127
Short name T255
Test name
Test status
Simulation time 56251000 ps
CPU time 19.92 seconds
Started Jun 04 01:19:31 PM PDT 24
Finished Jun 04 01:19:51 PM PDT 24
Peak memory 264152 kb
Host smart-4540c785-94c4-420d-a1f0-5dac4c9fbfce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485057127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.485057127
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.640391236
Short name T229
Test name
Test status
Simulation time 354301300 ps
CPU time 900.66 seconds
Started Jun 04 01:19:33 PM PDT 24
Finished Jun 04 01:34:35 PM PDT 24
Peak memory 264116 kb
Host smart-cff848a0-c9db-4483-9e8a-7e05774bb9ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640391236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_
tl_intg_err.640391236
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3043809196
Short name T1157
Test name
Test status
Simulation time 26227000 ps
CPU time 13.24 seconds
Started Jun 04 01:20:15 PM PDT 24
Finished Jun 04 01:20:30 PM PDT 24
Peak memory 262652 kb
Host smart-5c54f73b-bd1a-4aa0-b6b7-5311d48da488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043809196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
3043809196
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3746444777
Short name T1129
Test name
Test status
Simulation time 21496500 ps
CPU time 13.54 seconds
Started Jun 04 01:20:16 PM PDT 24
Finished Jun 04 01:20:31 PM PDT 24
Peak memory 262644 kb
Host smart-b57275b4-a9f7-4fdf-8a99-c1e59d145cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746444777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
3746444777
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3896983263
Short name T356
Test name
Test status
Simulation time 22412800 ps
CPU time 13.4 seconds
Started Jun 04 01:20:14 PM PDT 24
Finished Jun 04 01:20:29 PM PDT 24
Peak memory 262724 kb
Host smart-8bee429b-c082-4c18-a32e-0b1e3225e9a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896983263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
3896983263
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1062147634
Short name T1102
Test name
Test status
Simulation time 44242500 ps
CPU time 13.24 seconds
Started Jun 04 01:20:16 PM PDT 24
Finished Jun 04 01:20:30 PM PDT 24
Peak memory 262968 kb
Host smart-fdb2e68b-1d63-4e1e-8192-2a29b14ecc34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062147634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
1062147634
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3552643494
Short name T1119
Test name
Test status
Simulation time 21115200 ps
CPU time 13.7 seconds
Started Jun 04 01:20:15 PM PDT 24
Finished Jun 04 01:20:30 PM PDT 24
Peak memory 261900 kb
Host smart-5b489c94-33a1-4683-a5c8-24ed6830acf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552643494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
3552643494
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1784263069
Short name T1175
Test name
Test status
Simulation time 15622900 ps
CPU time 13.67 seconds
Started Jun 04 01:20:23 PM PDT 24
Finished Jun 04 01:20:38 PM PDT 24
Peak memory 262588 kb
Host smart-c9b449a5-8be8-4b27-9ab4-f4fac82375cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784263069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
1784263069
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2240738448
Short name T1151
Test name
Test status
Simulation time 24084300 ps
CPU time 13.61 seconds
Started Jun 04 01:20:21 PM PDT 24
Finished Jun 04 01:20:35 PM PDT 24
Peak memory 262856 kb
Host smart-8716b1fc-5da8-4347-be26-74973d2e6e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240738448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
2240738448
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.560513628
Short name T1155
Test name
Test status
Simulation time 14933000 ps
CPU time 13.25 seconds
Started Jun 04 01:20:21 PM PDT 24
Finished Jun 04 01:20:35 PM PDT 24
Peak memory 262944 kb
Host smart-b83b54a3-1ded-4d6a-a7dd-24eb13f90ece
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560513628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.560513628
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.921797581
Short name T1105
Test name
Test status
Simulation time 45045700 ps
CPU time 13.82 seconds
Started Jun 04 01:20:21 PM PDT 24
Finished Jun 04 01:20:35 PM PDT 24
Peak memory 262600 kb
Host smart-41779962-98ee-42a2-92f3-860a6e82da29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921797581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.921797581
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.421706016
Short name T1226
Test name
Test status
Simulation time 16459800 ps
CPU time 13.61 seconds
Started Jun 04 01:20:21 PM PDT 24
Finished Jun 04 01:20:35 PM PDT 24
Peak memory 262916 kb
Host smart-49a20d65-d57d-4fa8-8374-7c95eda9bf48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421706016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.421706016
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2562614211
Short name T1111
Test name
Test status
Simulation time 1996889100 ps
CPU time 37.74 seconds
Started Jun 04 01:19:40 PM PDT 24
Finished Jun 04 01:20:19 PM PDT 24
Peak memory 260504 kb
Host smart-fc431679-03a4-43c8-a240-16ed898a9348
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562614211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.2562614211
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1552355673
Short name T299
Test name
Test status
Simulation time 23902321700 ps
CPU time 91.86 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:21:12 PM PDT 24
Peak memory 262768 kb
Host smart-f2488c0b-7222-43c7-b0ac-21e78a6da017
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552355673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.1552355673
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1753383826
Short name T1185
Test name
Test status
Simulation time 30072700 ps
CPU time 30.48 seconds
Started Jun 04 01:19:41 PM PDT 24
Finished Jun 04 01:20:12 PM PDT 24
Peak memory 260576 kb
Host smart-67e96163-1e99-4d8c-8f9d-9ff0c7fb484f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753383826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.1753383826
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1011587587
Short name T1182
Test name
Test status
Simulation time 293014800 ps
CPU time 18.01 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:19:58 PM PDT 24
Peak memory 272420 kb
Host smart-f126966f-13dd-48c0-be04-a60157f291ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011587587 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.1011587587
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3326200075
Short name T242
Test name
Test status
Simulation time 39327400 ps
CPU time 14.45 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:19:54 PM PDT 24
Peak memory 260584 kb
Host smart-8528541c-9063-4235-bb9e-23785f9b8e85
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326200075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.3326200075
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.205006732
Short name T1219
Test name
Test status
Simulation time 30158600 ps
CPU time 13.45 seconds
Started Jun 04 01:19:41 PM PDT 24
Finished Jun 04 01:19:55 PM PDT 24
Peak memory 262844 kb
Host smart-0c44d298-025f-45f5-8419-d1fcfd0a7f0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205006732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.205006732
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1224056512
Short name T1144
Test name
Test status
Simulation time 47513900 ps
CPU time 13.41 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:19:53 PM PDT 24
Peak memory 262868 kb
Host smart-f9e74b3e-6810-44f3-a0e9-081dd816232f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224056512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.1224056512
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3582609038
Short name T1187
Test name
Test status
Simulation time 87904700 ps
CPU time 15.3 seconds
Started Jun 04 01:19:42 PM PDT 24
Finished Jun 04 01:19:58 PM PDT 24
Peak memory 262644 kb
Host smart-8b6bac0d-0eae-4a79-aae3-153de4decd5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582609038 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.3582609038
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3807692581
Short name T1093
Test name
Test status
Simulation time 21109600 ps
CPU time 15.52 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:19:55 PM PDT 24
Peak memory 260376 kb
Host smart-970c7490-b6d5-48e3-969e-d455df9e92ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807692581 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.3807692581
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2765534947
Short name T1147
Test name
Test status
Simulation time 11558400 ps
CPU time 15.54 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:19:55 PM PDT 24
Peak memory 260360 kb
Host smart-91820db2-3400-4d58-b0d1-61f630acec36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765534947 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.2765534947
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.4095794891
Short name T267
Test name
Test status
Simulation time 897771800 ps
CPU time 901.66 seconds
Started Jun 04 01:19:38 PM PDT 24
Finished Jun 04 01:34:41 PM PDT 24
Peak memory 261680 kb
Host smart-9b398b53-7fa3-4f9f-96e5-d7755c352a42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095794891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.4095794891
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.4165609985
Short name T1120
Test name
Test status
Simulation time 48650700 ps
CPU time 13.46 seconds
Started Jun 04 01:20:22 PM PDT 24
Finished Jun 04 01:20:36 PM PDT 24
Peak memory 262892 kb
Host smart-72fe2a1a-d1c2-42a5-ae6a-426eab0f7ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165609985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
4165609985
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.877536526
Short name T1199
Test name
Test status
Simulation time 27826700 ps
CPU time 13.37 seconds
Started Jun 04 01:20:22 PM PDT 24
Finished Jun 04 01:20:37 PM PDT 24
Peak memory 261892 kb
Host smart-ee84c2f3-07cc-44be-8c7b-7cc55f44d4f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877536526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.877536526
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.804958185
Short name T1229
Test name
Test status
Simulation time 28479700 ps
CPU time 13.38 seconds
Started Jun 04 01:20:20 PM PDT 24
Finished Jun 04 01:20:34 PM PDT 24
Peak memory 262780 kb
Host smart-2392b67c-3da6-47f2-95c6-b6edd0de3d7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804958185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.804958185
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.4070084981
Short name T252
Test name
Test status
Simulation time 45675200 ps
CPU time 13.38 seconds
Started Jun 04 01:20:32 PM PDT 24
Finished Jun 04 01:20:46 PM PDT 24
Peak memory 262680 kb
Host smart-27df0a17-aa6a-4a76-9c92-8a121a70b029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070084981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
4070084981
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3101083810
Short name T253
Test name
Test status
Simulation time 27344800 ps
CPU time 13.57 seconds
Started Jun 04 01:20:30 PM PDT 24
Finished Jun 04 01:20:44 PM PDT 24
Peak memory 262640 kb
Host smart-7399f29d-0a12-47c7-8a28-0df12977d8d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101083810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
3101083810
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1061294175
Short name T1183
Test name
Test status
Simulation time 31012600 ps
CPU time 13.5 seconds
Started Jun 04 01:20:29 PM PDT 24
Finished Jun 04 01:20:43 PM PDT 24
Peak memory 262628 kb
Host smart-0fafc987-978c-49ec-95b1-c3db579f545b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061294175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
1061294175
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.627162775
Short name T1094
Test name
Test status
Simulation time 54477100 ps
CPU time 13.65 seconds
Started Jun 04 01:20:27 PM PDT 24
Finished Jun 04 01:20:42 PM PDT 24
Peak memory 262920 kb
Host smart-f79cfcea-bdc5-43c6-83e9-d3ac053a4e26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627162775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.627162775
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1689706506
Short name T1116
Test name
Test status
Simulation time 16159500 ps
CPU time 13.86 seconds
Started Jun 04 01:20:28 PM PDT 24
Finished Jun 04 01:20:43 PM PDT 24
Peak memory 262732 kb
Host smart-d3987353-6eb6-486f-85e9-63069bd95942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689706506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
1689706506
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.459882668
Short name T341
Test name
Test status
Simulation time 27965700 ps
CPU time 13.62 seconds
Started Jun 04 01:20:29 PM PDT 24
Finished Jun 04 01:20:44 PM PDT 24
Peak memory 262920 kb
Host smart-e8ea002a-da59-4065-9517-91cf1b23de38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459882668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.459882668
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.117306011
Short name T1171
Test name
Test status
Simulation time 127254200 ps
CPU time 13.48 seconds
Started Jun 04 01:20:28 PM PDT 24
Finished Jun 04 01:20:43 PM PDT 24
Peak memory 262948 kb
Host smart-e18bf9a7-17c8-45ea-94fd-1ce529e539ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117306011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.117306011
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.861027292
Short name T246
Test name
Test status
Simulation time 465608300 ps
CPU time 34.87 seconds
Started Jun 04 01:19:38 PM PDT 24
Finished Jun 04 01:20:14 PM PDT 24
Peak memory 260464 kb
Host smart-428b31f8-fbcf-4af5-bb8e-a23a4ca95fc5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861027292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_aliasing.861027292
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2923132871
Short name T295
Test name
Test status
Simulation time 1652219700 ps
CPU time 49.15 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:20:29 PM PDT 24
Peak memory 262332 kb
Host smart-7fae6663-d18e-4e78-99cd-583483ae36e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923132871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.2923132871
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1599933827
Short name T1179
Test name
Test status
Simulation time 58396800 ps
CPU time 26 seconds
Started Jun 04 01:19:40 PM PDT 24
Finished Jun 04 01:20:07 PM PDT 24
Peak memory 260504 kb
Host smart-c4e2e6f5-04d8-4c67-a8fb-d666349bb225
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599933827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.1599933827
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1679871707
Short name T298
Test name
Test status
Simulation time 383094800 ps
CPU time 16.06 seconds
Started Jun 04 01:19:40 PM PDT 24
Finished Jun 04 01:19:57 PM PDT 24
Peak memory 272276 kb
Host smart-e9c57ed8-a4ec-4b83-a896-8e7512b00baf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679871707 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1679871707
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2469139652
Short name T1162
Test name
Test status
Simulation time 34340300 ps
CPU time 14.19 seconds
Started Jun 04 01:19:41 PM PDT 24
Finished Jun 04 01:19:56 PM PDT 24
Peak memory 260620 kb
Host smart-d4dbe39f-9a27-490e-b4ec-c42c8e15d7f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469139652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.2469139652
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2373917712
Short name T1104
Test name
Test status
Simulation time 14546700 ps
CPU time 13.41 seconds
Started Jun 04 01:19:40 PM PDT 24
Finished Jun 04 01:19:54 PM PDT 24
Peak memory 262836 kb
Host smart-a4e662e7-fcd6-4d3a-9e80-3698145401ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373917712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2
373917712
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1593773126
Short name T234
Test name
Test status
Simulation time 49590200 ps
CPU time 13.3 seconds
Started Jun 04 01:19:42 PM PDT 24
Finished Jun 04 01:19:55 PM PDT 24
Peak memory 263640 kb
Host smart-f15bd858-e67c-4b2a-8868-f145a903e581
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593773126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.1593773126
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.4150649250
Short name T1098
Test name
Test status
Simulation time 50388800 ps
CPU time 13.42 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:19:54 PM PDT 24
Peak memory 262760 kb
Host smart-8f8fba7f-5a5f-421b-a988-cd608c145168
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150649250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.4150649250
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3743239086
Short name T297
Test name
Test status
Simulation time 1096860500 ps
CPU time 20.82 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:20:01 PM PDT 24
Peak memory 260608 kb
Host smart-4cd09cd1-c8fc-4c0c-b2df-60a4bb305754
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743239086 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.3743239086
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.3082281196
Short name T1092
Test name
Test status
Simulation time 18433700 ps
CPU time 15.41 seconds
Started Jun 04 01:19:38 PM PDT 24
Finished Jun 04 01:19:54 PM PDT 24
Peak memory 260608 kb
Host smart-91faa48e-4e5a-4b74-9e9a-256d2768f4ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082281196 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.3082281196
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.346053871
Short name T1178
Test name
Test status
Simulation time 11157900 ps
CPU time 15.44 seconds
Started Jun 04 01:19:40 PM PDT 24
Finished Jun 04 01:19:56 PM PDT 24
Peak memory 260560 kb
Host smart-ab014db0-b05a-4df3-b932-27c958ce388a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346053871 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.346053871
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3559832651
Short name T1235
Test name
Test status
Simulation time 69356000 ps
CPU time 16.78 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:19:56 PM PDT 24
Peak memory 264152 kb
Host smart-be5dae98-9688-4f90-bdf2-d6c3ebe902cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559832651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.3
559832651
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2591003522
Short name T1160
Test name
Test status
Simulation time 679114300 ps
CPU time 895.58 seconds
Started Jun 04 01:19:39 PM PDT 24
Finished Jun 04 01:34:35 PM PDT 24
Peak memory 264212 kb
Host smart-b7c77098-6f39-4b13-bad1-938ea77ee67f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591003522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.2591003522
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2555023278
Short name T1133
Test name
Test status
Simulation time 38271900 ps
CPU time 13.62 seconds
Started Jun 04 01:20:28 PM PDT 24
Finished Jun 04 01:20:43 PM PDT 24
Peak memory 262644 kb
Host smart-c511dfca-c552-4dc5-96a3-c0c39949457c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555023278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
2555023278
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1540489282
Short name T1143
Test name
Test status
Simulation time 15999400 ps
CPU time 13.4 seconds
Started Jun 04 01:20:29 PM PDT 24
Finished Jun 04 01:20:43 PM PDT 24
Peak memory 262732 kb
Host smart-5d8bb8f0-1f88-416f-8cc1-4e6f3a36fe08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540489282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
1540489282
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1731280231
Short name T1112
Test name
Test status
Simulation time 25326400 ps
CPU time 13.71 seconds
Started Jun 04 01:20:28 PM PDT 24
Finished Jun 04 01:20:43 PM PDT 24
Peak memory 262536 kb
Host smart-3fd145ed-79aa-41ed-a0b4-6c5824bef994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731280231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
1731280231
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4246134940
Short name T1173
Test name
Test status
Simulation time 66669200 ps
CPU time 13.21 seconds
Started Jun 04 01:20:30 PM PDT 24
Finished Jun 04 01:20:44 PM PDT 24
Peak memory 262940 kb
Host smart-172b322c-fee8-4566-a0f4-f287065102e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246134940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
4246134940
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2158207308
Short name T1225
Test name
Test status
Simulation time 65378100 ps
CPU time 13.36 seconds
Started Jun 04 01:20:30 PM PDT 24
Finished Jun 04 01:20:44 PM PDT 24
Peak memory 262900 kb
Host smart-57f4afe2-a124-481b-8eca-cf8c9082c2f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158207308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
2158207308
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.2144695629
Short name T342
Test name
Test status
Simulation time 18047300 ps
CPU time 13.32 seconds
Started Jun 04 01:20:30 PM PDT 24
Finished Jun 04 01:20:44 PM PDT 24
Peak memory 262740 kb
Host smart-191c78eb-4ec1-4509-8d9c-b7eb455f9784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144695629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
2144695629
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2276594435
Short name T1121
Test name
Test status
Simulation time 60338200 ps
CPU time 13.36 seconds
Started Jun 04 01:20:32 PM PDT 24
Finished Jun 04 01:20:46 PM PDT 24
Peak memory 262664 kb
Host smart-ca87174a-cf30-483e-baf2-ae6974c53f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276594435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
2276594435
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.488903074
Short name T1108
Test name
Test status
Simulation time 16695900 ps
CPU time 13.5 seconds
Started Jun 04 01:20:28 PM PDT 24
Finished Jun 04 01:20:42 PM PDT 24
Peak memory 262944 kb
Host smart-151842f4-3f99-43b3-8a5e-8a27451a38bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488903074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.488903074
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2021128105
Short name T254
Test name
Test status
Simulation time 73228900 ps
CPU time 13.37 seconds
Started Jun 04 01:20:29 PM PDT 24
Finished Jun 04 01:20:43 PM PDT 24
Peak memory 262712 kb
Host smart-e72f0fdb-9961-4f93-8771-893f3153c209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021128105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
2021128105
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2465673961
Short name T224
Test name
Test status
Simulation time 703315900 ps
CPU time 19.19 seconds
Started Jun 04 01:19:46 PM PDT 24
Finished Jun 04 01:20:06 PM PDT 24
Peak memory 272312 kb
Host smart-7d6694fc-535a-4d43-802b-bcd17e3af52f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465673961 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.2465673961
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3710299684
Short name T1204
Test name
Test status
Simulation time 221525200 ps
CPU time 17.57 seconds
Started Jun 04 01:19:45 PM PDT 24
Finished Jun 04 01:20:03 PM PDT 24
Peak memory 260580 kb
Host smart-36967105-79b3-4384-a1dc-87f3cb36b061
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710299684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.3710299684
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2603232355
Short name T337
Test name
Test status
Simulation time 107240100 ps
CPU time 13.47 seconds
Started Jun 04 01:19:44 PM PDT 24
Finished Jun 04 01:19:59 PM PDT 24
Peak memory 262448 kb
Host smart-bdd7303f-b3dc-4164-a4fc-ad7c4c7bb6c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603232355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2
603232355
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1945364693
Short name T303
Test name
Test status
Simulation time 900112800 ps
CPU time 35.41 seconds
Started Jun 04 01:19:45 PM PDT 24
Finished Jun 04 01:20:22 PM PDT 24
Peak memory 261928 kb
Host smart-d52f90f7-30e9-406b-a9b4-b7d882eb9ee9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945364693 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.1945364693
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.530721105
Short name T1161
Test name
Test status
Simulation time 13739000 ps
CPU time 15.22 seconds
Started Jun 04 01:19:46 PM PDT 24
Finished Jun 04 01:20:03 PM PDT 24
Peak memory 260556 kb
Host smart-ab60b20d-e166-4f77-936d-1af60c2f254f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530721105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.530721105
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.100434779
Short name T1106
Test name
Test status
Simulation time 21761300 ps
CPU time 15.28 seconds
Started Jun 04 01:19:47 PM PDT 24
Finished Jun 04 01:20:03 PM PDT 24
Peak memory 260616 kb
Host smart-df98df7b-3f7e-4c22-8d1c-f3e1b834ba7e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100434779 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.100434779
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1455414934
Short name T228
Test name
Test status
Simulation time 255135200 ps
CPU time 18.31 seconds
Started Jun 04 01:19:41 PM PDT 24
Finished Jun 04 01:20:00 PM PDT 24
Peak memory 264184 kb
Host smart-584d3957-4482-421f-95d0-cbbf81e358e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455414934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.1
455414934
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.528705231
Short name T227
Test name
Test status
Simulation time 852142300 ps
CPU time 453.96 seconds
Started Jun 04 01:19:45 PM PDT 24
Finished Jun 04 01:27:20 PM PDT 24
Peak memory 264136 kb
Host smart-bc9b5c23-4f67-4136-b1a1-abc38b10c06b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528705231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_
tl_intg_err.528705231
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1873208216
Short name T209
Test name
Test status
Simulation time 668979500 ps
CPU time 17.5 seconds
Started Jun 04 01:19:47 PM PDT 24
Finished Jun 04 01:20:06 PM PDT 24
Peak memory 270768 kb
Host smart-a77a50c4-4b55-4881-b4d1-f3a20db59bd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873208216 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.1873208216
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1263280916
Short name T1109
Test name
Test status
Simulation time 250377700 ps
CPU time 17.07 seconds
Started Jun 04 01:19:47 PM PDT 24
Finished Jun 04 01:20:06 PM PDT 24
Peak memory 260496 kb
Host smart-c385f736-ebba-4e6d-9f69-e2ffed9980e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263280916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.1263280916
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3998974394
Short name T1203
Test name
Test status
Simulation time 44024000 ps
CPU time 13.74 seconds
Started Jun 04 01:19:45 PM PDT 24
Finished Jun 04 01:19:59 PM PDT 24
Peak memory 262612 kb
Host smart-8de68945-1cfe-44c8-9117-5a7c68e4a69d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998974394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.3
998974394
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1529285803
Short name T294
Test name
Test status
Simulation time 832271600 ps
CPU time 19.19 seconds
Started Jun 04 01:19:48 PM PDT 24
Finished Jun 04 01:20:08 PM PDT 24
Peak memory 260532 kb
Host smart-447bffd3-7a37-493b-8d85-1f809503bd3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529285803 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.1529285803
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1797997635
Short name T1146
Test name
Test status
Simulation time 22598900 ps
CPU time 15.43 seconds
Started Jun 04 01:19:45 PM PDT 24
Finished Jun 04 01:20:01 PM PDT 24
Peak memory 260548 kb
Host smart-02c82729-0c6e-4a37-b07a-f7282f9037d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797997635 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.1797997635
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2003679947
Short name T1174
Test name
Test status
Simulation time 15336400 ps
CPU time 15.49 seconds
Started Jun 04 01:19:46 PM PDT 24
Finished Jun 04 01:20:02 PM PDT 24
Peak memory 260504 kb
Host smart-c99de722-a098-44f6-93f9-4d6751e9f89a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003679947 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.2003679947
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3068120301
Short name T256
Test name
Test status
Simulation time 8163985700 ps
CPU time 758.01 seconds
Started Jun 04 01:19:46 PM PDT 24
Finished Jun 04 01:32:25 PM PDT 24
Peak memory 264168 kb
Host smart-35872754-f93b-4538-aa89-62bf915ecc24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068120301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.3068120301
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.502014126
Short name T243
Test name
Test status
Simulation time 110358600 ps
CPU time 15.36 seconds
Started Jun 04 01:19:45 PM PDT 24
Finished Jun 04 01:20:02 PM PDT 24
Peak memory 260600 kb
Host smart-846d7216-26fa-40b3-85f1-e9012a78e65f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502014126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_csr_rw.502014126
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.456481521
Short name T1138
Test name
Test status
Simulation time 196857100 ps
CPU time 13.25 seconds
Started Jun 04 01:19:44 PM PDT 24
Finished Jun 04 01:19:58 PM PDT 24
Peak memory 262732 kb
Host smart-8d913a78-9149-401f-98e4-c84ef80e1d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456481521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.456481521
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3165787608
Short name T241
Test name
Test status
Simulation time 34132600 ps
CPU time 14.75 seconds
Started Jun 04 01:19:47 PM PDT 24
Finished Jun 04 01:20:03 PM PDT 24
Peak memory 260620 kb
Host smart-08161076-c350-4968-9d16-e31dcb882809
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165787608 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.3165787608
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.976854994
Short name T1099
Test name
Test status
Simulation time 84660700 ps
CPU time 15.72 seconds
Started Jun 04 01:19:46 PM PDT 24
Finished Jun 04 01:20:03 PM PDT 24
Peak memory 260500 kb
Host smart-d22a074a-c4b7-4d88-93a8-5c70c8058b7e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976854994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.976854994
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3775299805
Short name T1123
Test name
Test status
Simulation time 13641300 ps
CPU time 15.9 seconds
Started Jun 04 01:19:45 PM PDT 24
Finished Jun 04 01:20:02 PM PDT 24
Peak memory 260468 kb
Host smart-b3cdbb82-e959-4274-8e5b-7ac57deb3b61
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775299805 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.3775299805
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1961898813
Short name T1207
Test name
Test status
Simulation time 55973700 ps
CPU time 18.71 seconds
Started Jun 04 01:19:45 PM PDT 24
Finished Jun 04 01:20:04 PM PDT 24
Peak memory 264172 kb
Host smart-66905592-e98b-4987-8bd9-68a73e1e0fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961898813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.1
961898813
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2393239438
Short name T265
Test name
Test status
Simulation time 698892500 ps
CPU time 887.85 seconds
Started Jun 04 01:19:45 PM PDT 24
Finished Jun 04 01:34:34 PM PDT 24
Peak memory 261848 kb
Host smart-0cbaec3c-5a12-493c-b3b7-bacc724754af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393239438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.2393239438
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2048725737
Short name T1224
Test name
Test status
Simulation time 351180000 ps
CPU time 18.82 seconds
Started Jun 04 01:19:48 PM PDT 24
Finished Jun 04 01:20:08 PM PDT 24
Peak memory 272360 kb
Host smart-2f1009e3-9740-468e-b71b-152fdd06c7cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048725737 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.2048725737
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2534719302
Short name T1221
Test name
Test status
Simulation time 878015100 ps
CPU time 17.57 seconds
Started Jun 04 01:19:45 PM PDT 24
Finished Jun 04 01:20:04 PM PDT 24
Peak memory 260436 kb
Host smart-67ceff58-ae44-4fe0-8f82-86e0c1ebf9e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534719302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.2534719302
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2268777461
Short name T1227
Test name
Test status
Simulation time 32074700 ps
CPU time 13.55 seconds
Started Jun 04 01:19:49 PM PDT 24
Finished Jun 04 01:20:03 PM PDT 24
Peak memory 262900 kb
Host smart-f776c33c-a171-48fc-8aea-374dbd0e2cf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268777461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.2
268777461
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.803576945
Short name T300
Test name
Test status
Simulation time 201071000 ps
CPU time 34.87 seconds
Started Jun 04 01:19:48 PM PDT 24
Finished Jun 04 01:20:24 PM PDT 24
Peak memory 260644 kb
Host smart-8265d406-92d9-42cd-97ee-6c730b5d3014
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803576945 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.803576945
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3518825400
Short name T1142
Test name
Test status
Simulation time 17874800 ps
CPU time 13.02 seconds
Started Jun 04 01:19:44 PM PDT 24
Finished Jun 04 01:19:58 PM PDT 24
Peak memory 260520 kb
Host smart-be756ed1-81c5-4202-872e-30c90c88faec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518825400 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.3518825400
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.387111185
Short name T1097
Test name
Test status
Simulation time 14130300 ps
CPU time 15.45 seconds
Started Jun 04 01:19:47 PM PDT 24
Finished Jun 04 01:20:03 PM PDT 24
Peak memory 260512 kb
Host smart-f4258bc0-ff1d-422b-8168-86fca9817109
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387111185 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.387111185
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3390120514
Short name T264
Test name
Test status
Simulation time 264993200 ps
CPU time 19.48 seconds
Started Jun 04 01:19:46 PM PDT 24
Finished Jun 04 01:20:07 PM PDT 24
Peak memory 264216 kb
Host smart-8c62c015-eed9-4a4c-8220-d9dea7604ae7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390120514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3
390120514
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2072488738
Short name T301
Test name
Test status
Simulation time 236261800 ps
CPU time 17.18 seconds
Started Jun 04 01:19:52 PM PDT 24
Finished Jun 04 01:20:11 PM PDT 24
Peak memory 271404 kb
Host smart-312ced43-7b8b-4c0d-9536-bd61e3ab9cf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072488738 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.2072488738
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.942173331
Short name T240
Test name
Test status
Simulation time 45210200 ps
CPU time 16.93 seconds
Started Jun 04 01:19:46 PM PDT 24
Finished Jun 04 01:20:04 PM PDT 24
Peak memory 260500 kb
Host smart-8d0028d1-61c5-4228-9e87-710a0e76ca31
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942173331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_csr_rw.942173331
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1437797714
Short name T1231
Test name
Test status
Simulation time 158634000 ps
CPU time 17.72 seconds
Started Jun 04 01:19:46 PM PDT 24
Finished Jun 04 01:20:05 PM PDT 24
Peak memory 260572 kb
Host smart-ec650478-cca1-4b39-a181-df934ae78ef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437797714 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.1437797714
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.44738721
Short name T1163
Test name
Test status
Simulation time 21989200 ps
CPU time 15.63 seconds
Started Jun 04 01:19:47 PM PDT 24
Finished Jun 04 01:20:04 PM PDT 24
Peak memory 260476 kb
Host smart-40842bd3-39fd-482f-a6f3-397fe6543da3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44738721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.44738721
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2934761847
Short name T1154
Test name
Test status
Simulation time 14951600 ps
CPU time 15.71 seconds
Started Jun 04 01:19:47 PM PDT 24
Finished Jun 04 01:20:04 PM PDT 24
Peak memory 260464 kb
Host smart-f7385bfc-1209-4c60-8acf-6581796c8b6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934761847 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.2934761847
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1408110138
Short name T1192
Test name
Test status
Simulation time 59993600 ps
CPU time 19.41 seconds
Started Jun 04 01:19:46 PM PDT 24
Finished Jun 04 01:20:07 PM PDT 24
Peak memory 264164 kb
Host smart-9c264e7a-5319-4f40-91cc-3d898dfa45cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408110138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.1
408110138
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3934918499
Short name T359
Test name
Test status
Simulation time 573100800 ps
CPU time 906.59 seconds
Started Jun 04 01:19:48 PM PDT 24
Finished Jun 04 01:34:56 PM PDT 24
Peak memory 261588 kb
Host smart-94862237-4f8c-45ed-85e5-0b2508733b51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934918499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.3934918499
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.766498663
Short name T729
Test name
Test status
Simulation time 34728000 ps
CPU time 13.54 seconds
Started Jun 04 02:41:21 PM PDT 24
Finished Jun 04 02:41:35 PM PDT 24
Peak memory 257856 kb
Host smart-8fbf4243-cbe3-4e3f-adad-7baeed38fd23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766498663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.766498663
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.2002744037
Short name T186
Test name
Test status
Simulation time 13349100 ps
CPU time 15.81 seconds
Started Jun 04 02:40:59 PM PDT 24
Finished Jun 04 02:41:16 PM PDT 24
Peak memory 274756 kb
Host smart-bf060f15-12cb-463d-be14-78b26527535c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002744037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2002744037
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.1356135645
Short name T134
Test name
Test status
Simulation time 341638200 ps
CPU time 102.48 seconds
Started Jun 04 02:40:25 PM PDT 24
Finished Jun 04 02:42:08 PM PDT 24
Peak memory 273188 kb
Host smart-2d558334-d5ed-4576-bb5c-205e9dde0e17
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356135645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.1356135645
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.2723486187
Short name T569
Test name
Test status
Simulation time 20087500 ps
CPU time 21.64 seconds
Started Jun 04 02:41:00 PM PDT 24
Finished Jun 04 02:41:22 PM PDT 24
Peak memory 273192 kb
Host smart-64f59f6c-1d01-4963-b8d3-915deac012d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723486187 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.2723486187
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.182795525
Short name T1063
Test name
Test status
Simulation time 13940868200 ps
CPU time 481.91 seconds
Started Jun 04 02:39:46 PM PDT 24
Finished Jun 04 02:47:48 PM PDT 24
Peak memory 261092 kb
Host smart-4a92dcf9-69b1-42d4-b66b-3011652620e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=182795525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.182795525
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.1747057542
Short name T1066
Test name
Test status
Simulation time 677239800 ps
CPU time 2471.09 seconds
Started Jun 04 02:39:55 PM PDT 24
Finished Jun 04 03:21:07 PM PDT 24
Peak memory 264584 kb
Host smart-7cd5ec41-951a-4bbd-a972-f0f7329a96d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747057542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.1747057542
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.859892746
Short name T59
Test name
Test status
Simulation time 469991900 ps
CPU time 26.39 seconds
Started Jun 04 02:39:55 PM PDT 24
Finished Jun 04 02:40:22 PM PDT 24
Peak memory 264904 kb
Host smart-8784897c-1bbe-4212-abb4-c99823de0e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859892746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.859892746
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.3050011793
Short name T81
Test name
Test status
Simulation time 84131223800 ps
CPU time 4473.99 seconds
Started Jun 04 02:39:54 PM PDT 24
Finished Jun 04 03:54:30 PM PDT 24
Peak memory 264860 kb
Host smart-88060c1c-b977-4ecb-b9bf-4a119004258f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050011793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.3050011793
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.2007653243
Short name T472
Test name
Test status
Simulation time 115181600 ps
CPU time 102.27 seconds
Started Jun 04 02:39:36 PM PDT 24
Finished Jun 04 02:41:19 PM PDT 24
Peak memory 262252 kb
Host smart-08eae37b-806d-4691-bec9-4755e643f3e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2007653243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2007653243
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.280068456
Short name T651
Test name
Test status
Simulation time 70141394000 ps
CPU time 870.93 seconds
Started Jun 04 02:39:56 PM PDT 24
Finished Jun 04 02:54:27 PM PDT 24
Peak memory 263148 kb
Host smart-390f1e50-8d62-4964-b459-bb2959540e2b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280068456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_hw_rma_reset.280068456
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.867356060
Short name T957
Test name
Test status
Simulation time 6721902200 ps
CPU time 127.65 seconds
Started Jun 04 02:39:40 PM PDT 24
Finished Jun 04 02:41:49 PM PDT 24
Peak memory 262228 kb
Host smart-b1860343-8476-488b-b443-b52a355fb0f4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867356060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw
_sec_otp.867356060
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.2235698875
Short name T237
Test name
Test status
Simulation time 15628306300 ps
CPU time 564.87 seconds
Started Jun 04 02:40:38 PM PDT 24
Finished Jun 04 02:50:03 PM PDT 24
Peak memory 336656 kb
Host smart-108294dc-7b04-496b-92e8-f785994b80d9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235698875 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_integrity.2235698875
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.709368035
Short name T663
Test name
Test status
Simulation time 1765289300 ps
CPU time 208.75 seconds
Started Jun 04 02:40:37 PM PDT 24
Finished Jun 04 02:44:07 PM PDT 24
Peak memory 290484 kb
Host smart-94f976ca-62e0-4a5b-a728-c7351d538ec8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709368035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_intr_rd.709368035
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.1891750545
Short name T305
Test name
Test status
Simulation time 6743967400 ps
CPU time 163.79 seconds
Started Jun 04 02:40:38 PM PDT 24
Finished Jun 04 02:43:22 PM PDT 24
Peak memory 291628 kb
Host smart-e58281fd-5732-4a4e-9d38-3570b503d9ce
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891750545 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.1891750545
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.4039960326
Short name T451
Test name
Test status
Simulation time 1925024800 ps
CPU time 62.6 seconds
Started Jun 04 02:40:38 PM PDT 24
Finished Jun 04 02:41:41 PM PDT 24
Peak memory 259604 kb
Host smart-c5106929-dec7-40b1-aa7f-705b793f01db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039960326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.4039960326
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.1549572689
Short name T320
Test name
Test status
Simulation time 45463816600 ps
CPU time 185.96 seconds
Started Jun 04 02:40:39 PM PDT 24
Finished Jun 04 02:43:45 PM PDT 24
Peak memory 259988 kb
Host smart-2d07d6b1-76b8-47d0-a812-954ba3f5c0e4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154
9572689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.1549572689
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.89454322
Short name T813
Test name
Test status
Simulation time 6801670800 ps
CPU time 60.7 seconds
Started Jun 04 02:40:03 PM PDT 24
Finished Jun 04 02:41:04 PM PDT 24
Peak memory 260420 kb
Host smart-665e914e-e699-484f-97ff-1f9bf00ead41
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89454322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.89454322
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.1555573591
Short name T586
Test name
Test status
Simulation time 46878100 ps
CPU time 13.47 seconds
Started Jun 04 02:41:22 PM PDT 24
Finished Jun 04 02:41:36 PM PDT 24
Peak memory 259324 kb
Host smart-a1001195-6a57-4cfc-b217-859ca744e189
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555573591 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.1555573591
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.1247977868
Short name T124
Test name
Test status
Simulation time 16374373100 ps
CPU time 74.58 seconds
Started Jun 04 02:40:04 PM PDT 24
Finished Jun 04 02:41:18 PM PDT 24
Peak memory 260548 kb
Host smart-84cb8689-9c8b-4521-b50c-ec46c2d56295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247977868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.1247977868
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.981675017
Short name T85
Test name
Test status
Simulation time 8167884800 ps
CPU time 425.16 seconds
Started Jun 04 02:39:56 PM PDT 24
Finished Jun 04 02:47:02 PM PDT 24
Peak memory 274132 kb
Host smart-037a8bb9-1716-47ff-b2e7-68a71eb3e7a2
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981675017 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_mp_regions.981675017
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.1944142114
Short name T827
Test name
Test status
Simulation time 76479700 ps
CPU time 108.95 seconds
Started Jun 04 02:39:54 PM PDT 24
Finished Jun 04 02:41:44 PM PDT 24
Peak memory 259556 kb
Host smart-e445e5e2-d6c2-4411-887e-0e381c92d274
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944142114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.1944142114
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.2065254278
Short name T215
Test name
Test status
Simulation time 44650500 ps
CPU time 13.85 seconds
Started Jun 04 02:41:21 PM PDT 24
Finished Jun 04 02:41:36 PM PDT 24
Peak memory 264968 kb
Host smart-1ec0b389-1e21-41d0-850e-fab8235c1440
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2065254278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.2065254278
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.577723289
Short name T481
Test name
Test status
Simulation time 799005900 ps
CPU time 206.71 seconds
Started Jun 04 02:39:42 PM PDT 24
Finished Jun 04 02:43:10 PM PDT 24
Peak memory 262156 kb
Host smart-de9776d4-e323-4b88-8ca1-9775cfc87f07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=577723289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.577723289
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.3138400132
Short name T128
Test name
Test status
Simulation time 17634800 ps
CPU time 14.11 seconds
Started Jun 04 02:41:21 PM PDT 24
Finished Jun 04 02:41:36 PM PDT 24
Peak memory 261852 kb
Host smart-03e15167-8526-4cf4-887d-644f7478d8b8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138400132 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.3138400132
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.93347398
Short name T713
Test name
Test status
Simulation time 60931300 ps
CPU time 13.19 seconds
Started Jun 04 02:40:47 PM PDT 24
Finished Jun 04 02:41:00 PM PDT 24
Peak memory 258376 kb
Host smart-86ce66ff-b8e4-492f-aa43-469b837e4f48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93347398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_reset
.93347398
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.2012431397
Short name T715
Test name
Test status
Simulation time 252842700 ps
CPU time 343.76 seconds
Started Jun 04 02:39:35 PM PDT 24
Finished Jun 04 02:45:19 PM PDT 24
Peak memory 281216 kb
Host smart-66c45f1a-f65a-4532-a4f5-b8cf01abf236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012431397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.2012431397
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.2397238230
Short name T1078
Test name
Test status
Simulation time 8123360900 ps
CPU time 156.46 seconds
Started Jun 04 02:39:40 PM PDT 24
Finished Jun 04 02:42:18 PM PDT 24
Peak memory 264868 kb
Host smart-899be63e-6876-44f3-a989-b0cd95528e8a
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2397238230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.2397238230
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.1949898670
Short name T722
Test name
Test status
Simulation time 62888500 ps
CPU time 31.4 seconds
Started Jun 04 02:41:08 PM PDT 24
Finished Jun 04 02:41:39 PM PDT 24
Peak memory 278908 kb
Host smart-3a8aa9cf-32d8-425b-b7ec-6cb74fb0ab73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949898670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.1949898670
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.2988098316
Short name T740
Test name
Test status
Simulation time 116178900 ps
CPU time 44.43 seconds
Started Jun 04 02:41:21 PM PDT 24
Finished Jun 04 02:42:06 PM PDT 24
Peak memory 274176 kb
Host smart-87482fde-d94a-487b-8b50-93925a4e0d69
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988098316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.2988098316
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.15691030
Short name T1008
Test name
Test status
Simulation time 441658600 ps
CPU time 36.71 seconds
Started Jun 04 02:41:00 PM PDT 24
Finished Jun 04 02:41:37 PM PDT 24
Peak memory 273116 kb
Host smart-5702e79a-9de4-4413-9e3f-cad87dd57942
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15691030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_re_evict.15691030
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.2420127676
Short name T1084
Test name
Test status
Simulation time 26362600 ps
CPU time 13.22 seconds
Started Jun 04 02:40:08 PM PDT 24
Finished Jun 04 02:40:22 PM PDT 24
Peak memory 264792 kb
Host smart-f0eec25d-19df-4d6e-91ff-31f9dabc90e3
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2420127676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.2420127676
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.3765556785
Short name T1025
Test name
Test status
Simulation time 283763500 ps
CPU time 22.33 seconds
Started Jun 04 02:40:24 PM PDT 24
Finished Jun 04 02:40:47 PM PDT 24
Peak memory 264876 kb
Host smart-f9e9915c-dbe2-4902-a6bb-0eac8c7b821b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765556785 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.3765556785
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.3697956607
Short name T983
Test name
Test status
Simulation time 93937100 ps
CPU time 22.67 seconds
Started Jun 04 02:40:08 PM PDT 24
Finished Jun 04 02:40:32 PM PDT 24
Peak memory 264864 kb
Host smart-7dd9c469-655f-48ce-989f-2928923c849e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697956607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.3697956607
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.1446802473
Short name T496
Test name
Test status
Simulation time 1112869500 ps
CPU time 120.84 seconds
Started Jun 04 02:40:08 PM PDT 24
Finished Jun 04 02:42:10 PM PDT 24
Peak memory 281252 kb
Host smart-bd70685b-d950-48c9-8458-be2df51bc0db
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446802473 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.1446802473
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.617565724
Short name T919
Test name
Test status
Simulation time 963969500 ps
CPU time 142.4 seconds
Started Jun 04 02:40:25 PM PDT 24
Finished Jun 04 02:42:47 PM PDT 24
Peak memory 281232 kb
Host smart-1ec78e4b-921e-422b-8487-8aa96cefb399
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
617565724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.617565724
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.2672863972
Short name T807
Test name
Test status
Simulation time 523407800 ps
CPU time 122.31 seconds
Started Jun 04 02:40:16 PM PDT 24
Finished Jun 04 02:42:19 PM PDT 24
Peak memory 281216 kb
Host smart-a581d86c-4e5f-4397-a98e-4f6a050cb32c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672863972 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.2672863972
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.758941742
Short name T1013
Test name
Test status
Simulation time 19268127600 ps
CPU time 649.82 seconds
Started Jun 04 02:40:08 PM PDT 24
Finished Jun 04 02:50:58 PM PDT 24
Peak memory 313412 kb
Host smart-f266db72-5744-4e60-9498-258ebb9935ce
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758941742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.flash_ctrl_rw.758941742
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.3885669379
Short name T612
Test name
Test status
Simulation time 29724100 ps
CPU time 30.85 seconds
Started Jun 04 02:40:46 PM PDT 24
Finished Jun 04 02:41:17 PM PDT 24
Peak memory 273116 kb
Host smart-9adcdfc6-9757-4db2-90b0-2726f12d1065
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885669379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.3885669379
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.3073974237
Short name T895
Test name
Test status
Simulation time 30302700 ps
CPU time 30.94 seconds
Started Jun 04 02:40:54 PM PDT 24
Finished Jun 04 02:41:26 PM PDT 24
Peak memory 274516 kb
Host smart-34dd355a-b859-4683-9914-3345f14b9df6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073974237 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.3073974237
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.743840939
Short name T736
Test name
Test status
Simulation time 35347351900 ps
CPU time 690.81 seconds
Started Jun 04 02:40:16 PM PDT 24
Finished Jun 04 02:51:47 PM PDT 24
Peak memory 311936 kb
Host smart-6387eb6e-5682-4a5b-8750-2017f923db10
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743840939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_se
rr.743840939
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.1283669498
Short name T523
Test name
Test status
Simulation time 2827020600 ps
CPU time 69.84 seconds
Started Jun 04 02:41:00 PM PDT 24
Finished Jun 04 02:42:10 PM PDT 24
Peak memory 264764 kb
Host smart-bc827090-6ab5-4ece-acdb-0c979c48d11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283669498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.1283669498
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.339128155
Short name T801
Test name
Test status
Simulation time 9451424600 ps
CPU time 91.59 seconds
Started Jun 04 02:40:16 PM PDT 24
Finished Jun 04 02:41:48 PM PDT 24
Peak memory 264896 kb
Host smart-a729ad53-bda5-4f69-ae0f-6fdf7e4ad6f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339128155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_serr_address.339128155
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.3879415456
Short name T117
Test name
Test status
Simulation time 1538121800 ps
CPU time 76.02 seconds
Started Jun 04 02:40:14 PM PDT 24
Finished Jun 04 02:41:31 PM PDT 24
Peak memory 273148 kb
Host smart-79a6f118-9043-4d84-92d6-59eccabee8ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879415456 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.3879415456
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.3825672527
Short name T551
Test name
Test status
Simulation time 45868300 ps
CPU time 122.2 seconds
Started Jun 04 02:39:32 PM PDT 24
Finished Jun 04 02:41:35 PM PDT 24
Peak memory 276972 kb
Host smart-16a69d7a-b7b4-4251-a020-ce6049ffc8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825672527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.3825672527
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.3036907858
Short name T833
Test name
Test status
Simulation time 26514500 ps
CPU time 25.82 seconds
Started Jun 04 02:39:34 PM PDT 24
Finished Jun 04 02:40:00 PM PDT 24
Peak memory 258756 kb
Host smart-83e48518-cdff-4063-b3ae-3f98e9702310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036907858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.3036907858
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.3065114694
Short name T1037
Test name
Test status
Simulation time 337041600 ps
CPU time 1523.83 seconds
Started Jun 04 02:41:01 PM PDT 24
Finished Jun 04 03:06:25 PM PDT 24
Peak memory 289524 kb
Host smart-9a9c4ed9-139b-47bf-8636-967383a2ff3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065114694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.3065114694
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.3501727116
Short name T1073
Test name
Test status
Simulation time 83720800 ps
CPU time 26.82 seconds
Started Jun 04 02:39:32 PM PDT 24
Finished Jun 04 02:40:00 PM PDT 24
Peak memory 258748 kb
Host smart-d1a83f46-e624-47b3-b73f-de13836f805c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501727116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.3501727116
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.1459797532
Short name T485
Test name
Test status
Simulation time 1962784100 ps
CPU time 143.66 seconds
Started Jun 04 02:40:01 PM PDT 24
Finished Jun 04 02:42:26 PM PDT 24
Peak memory 258876 kb
Host smart-36f8dc46-47b3-4c16-95bd-8fe435bf5352
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459797532 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_wo.1459797532
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.1135365494
Short name T924
Test name
Test status
Simulation time 40767800 ps
CPU time 15 seconds
Started Jun 04 02:40:02 PM PDT 24
Finished Jun 04 02:40:18 PM PDT 24
Peak memory 258400 kb
Host smart-4befb107-9e74-4181-9127-340d031ef034
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1135365494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.1135365494
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.3820144140
Short name T176
Test name
Test status
Simulation time 82854900 ps
CPU time 13.69 seconds
Started Jun 04 02:42:48 PM PDT 24
Finished Jun 04 02:43:02 PM PDT 24
Peak memory 264784 kb
Host smart-16a1982c-954f-401a-bed7-1fd794c66624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820144140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.3
820144140
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.181149288
Short name T793
Test name
Test status
Simulation time 49104700 ps
CPU time 13.45 seconds
Started Jun 04 02:42:25 PM PDT 24
Finished Jun 04 02:42:39 PM PDT 24
Peak memory 275828 kb
Host smart-bda88240-41cc-47b5-b1f8-fdff52a1af8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181149288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.181149288
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.3632430867
Short name T716
Test name
Test status
Simulation time 221760800 ps
CPU time 109.28 seconds
Started Jun 04 02:42:17 PM PDT 24
Finished Jun 04 02:44:08 PM PDT 24
Peak memory 280840 kb
Host smart-be6dfdf0-a0f6-47e4-8b64-cec374d409ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632430867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.3632430867
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.713980319
Short name T125
Test name
Test status
Simulation time 4102583900 ps
CPU time 305.52 seconds
Started Jun 04 02:41:41 PM PDT 24
Finished Jun 04 02:46:47 PM PDT 24
Peak memory 260960 kb
Host smart-fe71ff21-ae3f-4ab2-8654-87b48358d799
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=713980319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.713980319
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.151183466
Short name T543
Test name
Test status
Simulation time 10243312700 ps
CPU time 2354.61 seconds
Started Jun 04 02:41:58 PM PDT 24
Finished Jun 04 03:21:14 PM PDT 24
Peak memory 263996 kb
Host smart-c1eefb9b-8b78-42e5-aa28-a27e4e4df66f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151183466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erro
r_mp.151183466
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.3182444775
Short name T170
Test name
Test status
Simulation time 798106300 ps
CPU time 1813.86 seconds
Started Jun 04 02:41:58 PM PDT 24
Finished Jun 04 03:12:13 PM PDT 24
Peak memory 264820 kb
Host smart-71b16a53-97e3-4f14-84c7-8bc0c65e0f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182444775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.3182444775
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.3705946297
Short name T292
Test name
Test status
Simulation time 2514891700 ps
CPU time 909.77 seconds
Started Jun 04 02:41:56 PM PDT 24
Finished Jun 04 02:57:06 PM PDT 24
Peak memory 273060 kb
Host smart-562e787c-b123-4229-9fee-856bad65d6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705946297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.3705946297
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.663253151
Short name T60
Test name
Test status
Simulation time 2317784700 ps
CPU time 25.51 seconds
Started Jun 04 02:41:57 PM PDT 24
Finished Jun 04 02:42:23 PM PDT 24
Peak memory 264896 kb
Host smart-37db32b3-d49b-4448-b1cf-259161808a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663253151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.663253151
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.3421409757
Short name T277
Test name
Test status
Simulation time 172778700 ps
CPU time 78.68 seconds
Started Jun 04 02:41:36 PM PDT 24
Finished Jun 04 02:42:55 PM PDT 24
Peak memory 262296 kb
Host smart-9398fc55-c076-45b3-8878-6298cf1c2fe2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3421409757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3421409757
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2853967292
Short name T283
Test name
Test status
Simulation time 15519500 ps
CPU time 13.43 seconds
Started Jun 04 02:42:42 PM PDT 24
Finished Jun 04 02:42:56 PM PDT 24
Peak memory 258060 kb
Host smart-59f61569-9f5c-4984-a6a3-bddd8dc23380
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853967292 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.2853967292
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.3497998900
Short name T818
Test name
Test status
Simulation time 105871116100 ps
CPU time 1992.22 seconds
Started Jun 04 02:41:44 PM PDT 24
Finished Jun 04 03:14:57 PM PDT 24
Peak memory 261832 kb
Host smart-54e2cf36-eaca-4f22-b830-b404a15a1fd1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497998900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.3497998900
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.1389068855
Short name T1021
Test name
Test status
Simulation time 40127330000 ps
CPU time 855.12 seconds
Started Jun 04 02:41:44 PM PDT 24
Finished Jun 04 02:56:00 PM PDT 24
Peak memory 262956 kb
Host smart-17fac8d7-9e33-4469-85ce-1a7132a49706
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389068855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.1389068855
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.2505461001
Short name T844
Test name
Test status
Simulation time 10037461100 ps
CPU time 207.42 seconds
Started Jun 04 02:41:42 PM PDT 24
Finished Jun 04 02:45:10 PM PDT 24
Peak memory 262344 kb
Host smart-1c034ac9-8ee7-4905-aa27-74f18db0652b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505461001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.2505461001
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.837120029
Short name T349
Test name
Test status
Simulation time 690942600 ps
CPU time 155.74 seconds
Started Jun 04 02:42:20 PM PDT 24
Finished Jun 04 02:44:57 PM PDT 24
Peak memory 292804 kb
Host smart-4b672229-d77a-403c-8377-1d460b131dcb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837120029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash
_ctrl_intr_rd.837120029
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2107987065
Short name T637
Test name
Test status
Simulation time 25635504000 ps
CPU time 248.51 seconds
Started Jun 04 02:42:19 PM PDT 24
Finished Jun 04 02:46:29 PM PDT 24
Peak memory 283868 kb
Host smart-f41e501c-a1cc-4f03-aa73-ae13fc63ed54
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107987065 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.2107987065
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.2655349264
Short name T642
Test name
Test status
Simulation time 3564143100 ps
CPU time 58.75 seconds
Started Jun 04 02:42:20 PM PDT 24
Finished Jun 04 02:43:19 PM PDT 24
Peak memory 259240 kb
Host smart-7f80c4f5-7483-4ba7-894d-cbfaf7147025
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655349264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.2655349264
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.3622055642
Short name T312
Test name
Test status
Simulation time 5184676900 ps
CPU time 70.95 seconds
Started Jun 04 02:41:57 PM PDT 24
Finished Jun 04 02:43:08 PM PDT 24
Peak memory 260488 kb
Host smart-629bb0dc-9b87-47af-ab7a-f2c9c1dd9727
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622055642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.3622055642
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.1369512767
Short name T982
Test name
Test status
Simulation time 63878800 ps
CPU time 13.78 seconds
Started Jun 04 02:42:41 PM PDT 24
Finished Jun 04 02:42:55 PM PDT 24
Peak memory 264828 kb
Host smart-b440b280-ab13-4766-9abe-36c7803b1b37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369512767 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.1369512767
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.1249576514
Short name T133
Test name
Test status
Simulation time 826409800 ps
CPU time 70.1 seconds
Started Jun 04 02:41:57 PM PDT 24
Finished Jun 04 02:43:08 PM PDT 24
Peak memory 259724 kb
Host smart-33ac9209-1007-4c81-b723-18832b7fb040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249576514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.1249576514
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.2516846341
Short name T1018
Test name
Test status
Simulation time 7612593700 ps
CPU time 172.13 seconds
Started Jun 04 02:41:48 PM PDT 24
Finished Jun 04 02:44:41 PM PDT 24
Peak memory 262500 kb
Host smart-1939efb7-830b-48ab-a308-d39b7ef8180d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516846341 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.2516846341
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.2368774138
Short name T1035
Test name
Test status
Simulation time 176872200 ps
CPU time 127.89 seconds
Started Jun 04 02:41:52 PM PDT 24
Finished Jun 04 02:44:00 PM PDT 24
Peak memory 259728 kb
Host smart-041db651-91d5-4ea3-bfb0-b3a81a7b2934
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368774138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.2368774138
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.3145675017
Short name T7
Test name
Test status
Simulation time 3184927900 ps
CPU time 208.54 seconds
Started Jun 04 02:42:18 PM PDT 24
Finished Jun 04 02:45:47 PM PDT 24
Peak memory 281164 kb
Host smart-cd9a0647-d8eb-44e5-8ce4-fdd91e5a0448
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145675017 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.3145675017
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.2660509170
Short name T1071
Test name
Test status
Simulation time 228598200 ps
CPU time 14.43 seconds
Started Jun 04 02:42:33 PM PDT 24
Finished Jun 04 02:42:48 PM PDT 24
Peak memory 260500 kb
Host smart-74243fd9-5b8c-474f-a871-ad2994473595
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2660509170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.2660509170
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.728480961
Short name T696
Test name
Test status
Simulation time 751179100 ps
CPU time 366.03 seconds
Started Jun 04 02:41:43 PM PDT 24
Finished Jun 04 02:47:49 PM PDT 24
Peak memory 264896 kb
Host smart-1e9c9da2-9dd7-4edd-8b5d-e1ef3b011aae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=728480961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.728480961
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.1227665836
Short name T841
Test name
Test status
Simulation time 83697300 ps
CPU time 13.92 seconds
Started Jun 04 02:42:33 PM PDT 24
Finished Jun 04 02:42:48 PM PDT 24
Peak memory 264964 kb
Host smart-fe8d15f1-651a-4866-81ec-6144c7de5e92
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227665836 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.1227665836
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.2642012830
Short name T823
Test name
Test status
Simulation time 55482200 ps
CPU time 13.38 seconds
Started Jun 04 02:42:24 PM PDT 24
Finished Jun 04 02:42:38 PM PDT 24
Peak memory 258328 kb
Host smart-d513ae00-e8f1-4a83-90d7-abc321ff0a83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642012830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.2642012830
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.1704827644
Short name T1091
Test name
Test status
Simulation time 101256200 ps
CPU time 302.67 seconds
Started Jun 04 02:41:29 PM PDT 24
Finished Jun 04 02:46:32 PM PDT 24
Peak memory 281200 kb
Host smart-d18ee456-dc61-492e-9a0f-e57edbae21ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704827644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.1704827644
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.1482549368
Short name T1001
Test name
Test status
Simulation time 70237400 ps
CPU time 28.64 seconds
Started Jun 04 02:42:24 PM PDT 24
Finished Jun 04 02:42:53 PM PDT 24
Peak memory 278688 kb
Host smart-d7b7eb1d-90fd-4d36-90fa-6e35874eb01f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482549368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.1482549368
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.3299618850
Short name T797
Test name
Test status
Simulation time 142049700 ps
CPU time 31.54 seconds
Started Jun 04 02:42:18 PM PDT 24
Finished Jun 04 02:42:50 PM PDT 24
Peak memory 270072 kb
Host smart-11177ce3-5283-49bf-a2c2-4c16af25e7c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299618850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.3299618850
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.1473658165
Short name T479
Test name
Test status
Simulation time 31562800 ps
CPU time 20.58 seconds
Started Jun 04 02:42:19 PM PDT 24
Finished Jun 04 02:42:41 PM PDT 24
Peak memory 264828 kb
Host smart-6ccfa5ee-000f-4bbf-9988-f64e63de2ebe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473658165 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.1473658165
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.2301107518
Short name T34
Test name
Test status
Simulation time 167215739600 ps
CPU time 992.97 seconds
Started Jun 04 02:42:34 PM PDT 24
Finished Jun 04 02:59:08 PM PDT 24
Peak memory 258992 kb
Host smart-5ea596a6-e1d3-440b-a0ff-1334f348f8d5
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301107518 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.2301107518
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.1430204047
Short name T450
Test name
Test status
Simulation time 1135574300 ps
CPU time 130.95 seconds
Started Jun 04 02:42:04 PM PDT 24
Finished Jun 04 02:44:15 PM PDT 24
Peak memory 296520 kb
Host smart-5188dcc7-efd0-4e53-951a-68eb257f931f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430204047 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_ro.1430204047
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.1409663686
Short name T803
Test name
Test status
Simulation time 834026100 ps
CPU time 154.49 seconds
Started Jun 04 02:42:19 PM PDT 24
Finished Jun 04 02:44:55 PM PDT 24
Peak memory 282672 kb
Host smart-9ae09df1-7682-4579-aa1a-d903906e1de6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1409663686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.1409663686
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.1970690100
Short name T673
Test name
Test status
Simulation time 520079500 ps
CPU time 159.13 seconds
Started Jun 04 02:42:04 PM PDT 24
Finished Jun 04 02:44:43 PM PDT 24
Peak memory 294128 kb
Host smart-2d81995b-f629-4a02-af20-8633c6dde065
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970690100 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.1970690100
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.785848547
Short name T431
Test name
Test status
Simulation time 72951600 ps
CPU time 28.19 seconds
Started Jun 04 02:42:18 PM PDT 24
Finished Jun 04 02:42:47 PM PDT 24
Peak memory 275904 kb
Host smart-2daa048a-8fba-43df-b914-3d80106a0f2a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785848547 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.785848547
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.1117615664
Short name T669
Test name
Test status
Simulation time 20090287400 ps
CPU time 681.88 seconds
Started Jun 04 02:42:04 PM PDT 24
Finished Jun 04 02:53:26 PM PDT 24
Peak memory 319844 kb
Host smart-24ccbc14-a643-4ec9-8c86-a479761a6557
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117615664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.1117615664
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.4052701771
Short name T62
Test name
Test status
Simulation time 1383663200 ps
CPU time 4887.27 seconds
Started Jun 04 02:42:24 PM PDT 24
Finished Jun 04 04:03:52 PM PDT 24
Peak memory 285968 kb
Host smart-9e155538-1801-42ff-8338-f7ac3d5f5438
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052701771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.4052701771
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.165409850
Short name T847
Test name
Test status
Simulation time 2013350500 ps
CPU time 69.76 seconds
Started Jun 04 02:42:26 PM PDT 24
Finished Jun 04 02:43:36 PM PDT 24
Peak memory 262688 kb
Host smart-c9068519-54af-4ee2-aea5-3da0292056dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165409850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.165409850
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.3858908425
Short name T655
Test name
Test status
Simulation time 7126893700 ps
CPU time 104.55 seconds
Started Jun 04 02:42:10 PM PDT 24
Finished Jun 04 02:43:55 PM PDT 24
Peak memory 264880 kb
Host smart-ea7e8ba5-d05b-4965-855b-70dc1d272c46
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858908425 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.3858908425
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.1549578131
Short name T430
Test name
Test status
Simulation time 544974100 ps
CPU time 62.94 seconds
Started Jun 04 02:42:11 PM PDT 24
Finished Jun 04 02:43:14 PM PDT 24
Peak memory 273144 kb
Host smart-93a17072-2de0-494c-8b2e-e130a84525de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549578131 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.1549578131
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.1287005685
Short name T368
Test name
Test status
Simulation time 22690600 ps
CPU time 121.41 seconds
Started Jun 04 02:41:22 PM PDT 24
Finished Jun 04 02:43:24 PM PDT 24
Peak memory 276796 kb
Host smart-b3c0c4fd-c2e7-450e-8fbc-985c492129b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287005685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.1287005685
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.3786683226
Short name T829
Test name
Test status
Simulation time 75355900 ps
CPU time 24.68 seconds
Started Jun 04 02:41:29 PM PDT 24
Finished Jun 04 02:41:54 PM PDT 24
Peak memory 258880 kb
Host smart-3680cf7b-0543-4b30-918c-e2a8d41cb564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786683226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.3786683226
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.274254950
Short name T672
Test name
Test status
Simulation time 391507300 ps
CPU time 865.43 seconds
Started Jun 04 02:42:24 PM PDT 24
Finished Jun 04 02:56:50 PM PDT 24
Peak memory 289536 kb
Host smart-9faa6ad0-bb39-4a62-8c88-1d00af6505b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274254950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress
_all.274254950
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.2620005505
Short name T1036
Test name
Test status
Simulation time 30552000 ps
CPU time 23.58 seconds
Started Jun 04 02:41:29 PM PDT 24
Finished Jun 04 02:41:53 PM PDT 24
Peak memory 261224 kb
Host smart-3bb076e8-7ca7-41bf-9a20-aa5c791c4578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620005505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2620005505
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.3893529737
Short name T49
Test name
Test status
Simulation time 23960315200 ps
CPU time 239.65 seconds
Started Jun 04 02:41:58 PM PDT 24
Finished Jun 04 02:45:58 PM PDT 24
Peak memory 259892 kb
Host smart-10f52943-dbcf-4a6a-8a08-ce37806c46be
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893529737 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_wo.3893529737
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.488750555
Short name T223
Test name
Test status
Simulation time 159243200 ps
CPU time 15.3 seconds
Started Jun 04 02:42:33 PM PDT 24
Finished Jun 04 02:42:49 PM PDT 24
Peak memory 264716 kb
Host smart-4c986f24-81fd-4644-8eb4-ec7dfae189d9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488750555 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.488750555
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.1914691662
Short name T516
Test name
Test status
Simulation time 30102100 ps
CPU time 13.45 seconds
Started Jun 04 02:50:29 PM PDT 24
Finished Jun 04 02:50:43 PM PDT 24
Peak memory 264804 kb
Host smart-32939afa-572f-459a-906d-7149120af9ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914691662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
1914691662
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.2543303956
Short name T475
Test name
Test status
Simulation time 159751400 ps
CPU time 13.45 seconds
Started Jun 04 02:50:29 PM PDT 24
Finished Jun 04 02:50:43 PM PDT 24
Peak memory 275936 kb
Host smart-256d6e2c-0b7e-48ca-8e93-a63707762353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543303956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.2543303956
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.3340819134
Short name T422
Test name
Test status
Simulation time 15221700 ps
CPU time 21.94 seconds
Started Jun 04 02:50:20 PM PDT 24
Finished Jun 04 02:50:42 PM PDT 24
Peak memory 273176 kb
Host smart-433ab7e1-da8e-4133-8241-d03ab083bbc9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340819134 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.3340819134
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.544395198
Short name T774
Test name
Test status
Simulation time 160203603100 ps
CPU time 931.24 seconds
Started Jun 04 02:50:10 PM PDT 24
Finished Jun 04 03:05:42 PM PDT 24
Peak memory 262856 kb
Host smart-4d71b2ca-c922-43bd-8b5e-bd78083f7e20
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544395198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.flash_ctrl_hw_rma_reset.544395198
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.1476178389
Short name T421
Test name
Test status
Simulation time 1669026000 ps
CPU time 159.17 seconds
Started Jun 04 02:50:12 PM PDT 24
Finished Jun 04 02:52:52 PM PDT 24
Peak memory 262296 kb
Host smart-7eaa5d89-1d9d-44cd-ae71-3aa5a9f7be1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476178389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.1476178389
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.2914600788
Short name T861
Test name
Test status
Simulation time 2065545400 ps
CPU time 226.81 seconds
Started Jun 04 02:50:23 PM PDT 24
Finished Jun 04 02:54:10 PM PDT 24
Peak memory 289440 kb
Host smart-7febc6ae-03ab-4ce5-b330-c1e05cf45a57
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914600788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.2914600788
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1407067913
Short name T798
Test name
Test status
Simulation time 23538507400 ps
CPU time 126.61 seconds
Started Jun 04 02:50:19 PM PDT 24
Finished Jun 04 02:52:27 PM PDT 24
Peak memory 291928 kb
Host smart-ca11213c-43ba-490a-905c-94a54a33cb69
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407067913 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.1407067913
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.48633320
Short name T777
Test name
Test status
Simulation time 8627970300 ps
CPU time 70.12 seconds
Started Jun 04 02:50:14 PM PDT 24
Finished Jun 04 02:51:24 PM PDT 24
Peak memory 259520 kb
Host smart-f635d0cc-5ea9-4042-a8b7-d345382c2675
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48633320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.48633320
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.630083621
Short name T288
Test name
Test status
Simulation time 126286300 ps
CPU time 13.6 seconds
Started Jun 04 02:50:30 PM PDT 24
Finished Jun 04 02:50:44 PM PDT 24
Peak memory 264792 kb
Host smart-d7be6e82-8b7f-42eb-a472-cd4ada5d25bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630083621 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.630083621
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.3803889506
Short name T731
Test name
Test status
Simulation time 25313082200 ps
CPU time 263.06 seconds
Started Jun 04 02:50:13 PM PDT 24
Finished Jun 04 02:54:37 PM PDT 24
Peak memory 274084 kb
Host smart-83c021d7-39c3-4691-95d0-c8ac509443c8
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803889506 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.3803889506
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.2428225414
Short name T410
Test name
Test status
Simulation time 37834100 ps
CPU time 110.15 seconds
Started Jun 04 02:50:12 PM PDT 24
Finished Jun 04 02:52:03 PM PDT 24
Peak memory 259588 kb
Host smart-096f6966-f7e7-4477-a1d9-076b9743d090
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428225414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.2428225414
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.2467028927
Short name T709
Test name
Test status
Simulation time 1727168300 ps
CPU time 212.11 seconds
Started Jun 04 02:50:13 PM PDT 24
Finished Jun 04 02:53:45 PM PDT 24
Peak memory 264864 kb
Host smart-8b51a3dd-c072-4e16-92b8-86bb355f98c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467028927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.2467028927
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.2513637290
Short name T1056
Test name
Test status
Simulation time 137949800 ps
CPU time 13.8 seconds
Started Jun 04 02:50:21 PM PDT 24
Finished Jun 04 02:50:35 PM PDT 24
Peak memory 258444 kb
Host smart-5f7d9b72-3e4d-48e2-b51d-1c622b8f0cd8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513637290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.2513637290
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.2086368460
Short name T720
Test name
Test status
Simulation time 716721200 ps
CPU time 1015.71 seconds
Started Jun 04 02:50:10 PM PDT 24
Finished Jun 04 03:07:07 PM PDT 24
Peak memory 283012 kb
Host smart-50c08b95-8c67-476f-95d6-3b6ce69a37e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086368460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2086368460
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.3176905057
Short name T745
Test name
Test status
Simulation time 184190200 ps
CPU time 31.76 seconds
Started Jun 04 02:50:19 PM PDT 24
Finished Jun 04 02:50:52 PM PDT 24
Peak memory 274220 kb
Host smart-f9b3af14-0f81-4a5e-a8bc-6c74a6c72fac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176905057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.3176905057
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.3350735355
Short name T656
Test name
Test status
Simulation time 446282400 ps
CPU time 92.44 seconds
Started Jun 04 02:50:11 PM PDT 24
Finished Jun 04 02:51:44 PM PDT 24
Peak memory 281312 kb
Host smart-0ce1caa1-1136-47a6-b8de-0607a709a6b4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350735355 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.flash_ctrl_ro.3350735355
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.4234903453
Short name T484
Test name
Test status
Simulation time 15780042300 ps
CPU time 640.44 seconds
Started Jun 04 02:50:21 PM PDT 24
Finished Jun 04 03:01:02 PM PDT 24
Peak memory 310988 kb
Host smart-4fcc3b64-aa1d-44a9-89cb-0313516f6e5a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234903453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.flash_ctrl_rw.4234903453
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.2987773443
Short name T188
Test name
Test status
Simulation time 29799800 ps
CPU time 28.34 seconds
Started Jun 04 02:50:20 PM PDT 24
Finished Jun 04 02:50:49 PM PDT 24
Peak memory 274412 kb
Host smart-64ef670b-2978-4166-8c49-f6f79cf717a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987773443 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.2987773443
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.1698292019
Short name T393
Test name
Test status
Simulation time 711324000 ps
CPU time 78.82 seconds
Started Jun 04 02:50:29 PM PDT 24
Finished Jun 04 02:51:48 PM PDT 24
Peak memory 262804 kb
Host smart-66ed9750-5cfe-41e5-9d3b-cab1d75992ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698292019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.1698292019
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.3711851304
Short name T600
Test name
Test status
Simulation time 198182300 ps
CPU time 192.5 seconds
Started Jun 04 02:50:04 PM PDT 24
Finished Jun 04 02:53:17 PM PDT 24
Peak memory 277856 kb
Host smart-8fbba1f1-25c2-4128-90a2-7ded548ed391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711851304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.3711851304
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.3274642860
Short name T1011
Test name
Test status
Simulation time 2976710100 ps
CPU time 144.48 seconds
Started Jun 04 02:50:11 PM PDT 24
Finished Jun 04 02:52:36 PM PDT 24
Peak memory 259216 kb
Host smart-a7cc8e0f-9d05-465c-8b0e-6990d129f7b4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274642860 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.flash_ctrl_wo.3274642860
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.889560328
Short name T606
Test name
Test status
Simulation time 111568600 ps
CPU time 14.38 seconds
Started Jun 04 02:51:01 PM PDT 24
Finished Jun 04 02:51:16 PM PDT 24
Peak memory 257772 kb
Host smart-48c380df-1842-4dbb-a801-fb93e0c2da6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889560328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.889560328
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.1308225533
Short name T461
Test name
Test status
Simulation time 26465800 ps
CPU time 15.63 seconds
Started Jun 04 02:50:52 PM PDT 24
Finished Jun 04 02:51:08 PM PDT 24
Peak memory 275952 kb
Host smart-5210f5ce-f59a-4366-bd7c-9b7b9f0df892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308225533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.1308225533
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.3573450299
Short name T712
Test name
Test status
Simulation time 13267200 ps
CPU time 20.37 seconds
Started Jun 04 02:50:54 PM PDT 24
Finished Jun 04 02:51:15 PM PDT 24
Peak memory 264484 kb
Host smart-0d00d5c2-4ffa-4958-a2e4-03752471e329
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573450299 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.3573450299
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.1535912160
Short name T158
Test name
Test status
Simulation time 10011736900 ps
CPU time 98.87 seconds
Started Jun 04 02:51:02 PM PDT 24
Finished Jun 04 02:52:41 PM PDT 24
Peak memory 298168 kb
Host smart-a68cdc9e-c254-43de-9443-b8ba20234bd9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535912160 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.1535912160
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.1316493302
Short name T1069
Test name
Test status
Simulation time 16159200 ps
CPU time 13.78 seconds
Started Jun 04 02:51:02 PM PDT 24
Finished Jun 04 02:51:16 PM PDT 24
Peak memory 258872 kb
Host smart-260a15ba-0241-4922-acbd-98ad548d6c24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316493302 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.1316493302
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3174059389
Short name T1019
Test name
Test status
Simulation time 40124752000 ps
CPU time 828.81 seconds
Started Jun 04 02:50:30 PM PDT 24
Finished Jun 04 03:04:19 PM PDT 24
Peak memory 263088 kb
Host smart-24971c86-9602-48d5-900c-8aa890fd4cce
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174059389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3174059389
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.2920190930
Short name T307
Test name
Test status
Simulation time 1917746200 ps
CPU time 164.22 seconds
Started Jun 04 02:50:29 PM PDT 24
Finished Jun 04 02:53:13 PM PDT 24
Peak memory 262280 kb
Host smart-a5184630-124f-4787-861a-4b2af80e2ef2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920190930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.2920190930
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.2439995642
Short name T104
Test name
Test status
Simulation time 11915541200 ps
CPU time 77.55 seconds
Started Jun 04 02:50:40 PM PDT 24
Finished Jun 04 02:51:58 PM PDT 24
Peak memory 259788 kb
Host smart-8557cbcc-1859-48f4-8ab0-52103cccb3f2
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439995642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.2
439995642
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.2523918608
Short name T105
Test name
Test status
Simulation time 6229606400 ps
CPU time 177.87 seconds
Started Jun 04 02:50:39 PM PDT 24
Finished Jun 04 02:53:37 PM PDT 24
Peak memory 264844 kb
Host smart-3d5f30c3-4717-45e7-9951-544f39fd9769
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523918608 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.2523918608
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.35520955
Short name T834
Test name
Test status
Simulation time 414530500 ps
CPU time 131.07 seconds
Started Jun 04 02:50:41 PM PDT 24
Finished Jun 04 02:52:53 PM PDT 24
Peak memory 259608 kb
Host smart-012cf283-b535-4701-b3fe-3f560e63e5c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35520955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp
_reset.35520955
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.2921640643
Short name T950
Test name
Test status
Simulation time 230431900 ps
CPU time 233.63 seconds
Started Jun 04 02:50:28 PM PDT 24
Finished Jun 04 02:54:22 PM PDT 24
Peak memory 262052 kb
Host smart-b016a9bb-a7b1-4f66-9eb0-e1e0e77548f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2921640643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.2921640643
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.2104761301
Short name T310
Test name
Test status
Simulation time 20039600 ps
CPU time 13.46 seconds
Started Jun 04 02:50:44 PM PDT 24
Finished Jun 04 02:50:58 PM PDT 24
Peak memory 258332 kb
Host smart-e68b39c0-4bab-4bc0-961c-6808138bf060
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104761301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.2104761301
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.970915869
Short name T107
Test name
Test status
Simulation time 566599700 ps
CPU time 1229.1 seconds
Started Jun 04 02:50:29 PM PDT 24
Finished Jun 04 03:10:59 PM PDT 24
Peak memory 286744 kb
Host smart-c1b1d56a-6494-4612-a4a1-35b06aef1834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970915869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.970915869
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.3638455372
Short name T280
Test name
Test status
Simulation time 225717400 ps
CPU time 38.35 seconds
Started Jun 04 02:50:52 PM PDT 24
Finished Jun 04 02:51:31 PM PDT 24
Peak memory 274108 kb
Host smart-86c6995e-75fa-48d1-a70c-0bb29f17aaf7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638455372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.3638455372
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.2505354613
Short name T1005
Test name
Test status
Simulation time 1724927500 ps
CPU time 139.53 seconds
Started Jun 04 02:50:42 PM PDT 24
Finished Jun 04 02:53:02 PM PDT 24
Peak memory 280636 kb
Host smart-cf1a6876-04be-4f01-bffe-62c057716829
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505354613 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.flash_ctrl_ro.2505354613
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.3727363375
Short name T617
Test name
Test status
Simulation time 4510062900 ps
CPU time 632.78 seconds
Started Jun 04 02:50:42 PM PDT 24
Finished Jun 04 03:01:15 PM PDT 24
Peak memory 313532 kb
Host smart-83008cc6-039d-4548-84fe-5b223d97f46a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727363375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_rw.3727363375
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.4168400779
Short name T808
Test name
Test status
Simulation time 49966200 ps
CPU time 30.94 seconds
Started Jun 04 02:50:45 PM PDT 24
Finished Jun 04 02:51:16 PM PDT 24
Peak memory 273044 kb
Host smart-65186ace-8536-4cd5-a903-f5b2b164f18f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168400779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.4168400779
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.60030981
Short name T555
Test name
Test status
Simulation time 40956000 ps
CPU time 30.88 seconds
Started Jun 04 02:50:43 PM PDT 24
Finished Jun 04 02:51:15 PM PDT 24
Peak memory 275212 kb
Host smart-83426232-cac9-437d-8dfa-a4a13b39e381
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60030981 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.60030981
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.1608743691
Short name T611
Test name
Test status
Simulation time 96116900 ps
CPU time 124.57 seconds
Started Jun 04 02:50:28 PM PDT 24
Finished Jun 04 02:52:33 PM PDT 24
Peak memory 275376 kb
Host smart-8548a8d1-552d-41df-a5cc-0dec78ac5765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608743691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.1608743691
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.562044842
Short name T1052
Test name
Test status
Simulation time 6114066600 ps
CPU time 227.22 seconds
Started Jun 04 02:50:41 PM PDT 24
Finished Jun 04 02:54:29 PM PDT 24
Peak memory 264824 kb
Host smart-51223f77-e936-4bf3-a439-2a29e62e6680
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562044842 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.flash_ctrl_wo.562044842
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.1476765536
Short name T790
Test name
Test status
Simulation time 20008100 ps
CPU time 13.87 seconds
Started Jun 04 02:51:33 PM PDT 24
Finished Jun 04 02:51:48 PM PDT 24
Peak memory 264724 kb
Host smart-8aeb66b4-bcd3-42cb-97a5-0d641f27b229
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476765536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
1476765536
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.986110708
Short name T418
Test name
Test status
Simulation time 22779400 ps
CPU time 15.82 seconds
Started Jun 04 02:51:26 PM PDT 24
Finished Jun 04 02:51:42 PM PDT 24
Peak memory 275552 kb
Host smart-ea4275d0-2566-4014-98df-c44a1816021c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986110708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.986110708
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.4081583296
Short name T592
Test name
Test status
Simulation time 39495700 ps
CPU time 21.77 seconds
Started Jun 04 02:51:26 PM PDT 24
Finished Jun 04 02:51:48 PM PDT 24
Peak memory 273236 kb
Host smart-be0fe6ad-3b01-442e-882f-fda2fe74e720
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081583296 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.4081583296
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1389779294
Short name T762
Test name
Test status
Simulation time 10015976000 ps
CPU time 93.26 seconds
Started Jun 04 02:51:26 PM PDT 24
Finished Jun 04 02:53:00 PM PDT 24
Peak memory 286976 kb
Host smart-70e6d6c6-30e7-4340-91dd-1904d6376f22
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389779294 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.1389779294
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.3615913189
Short name T1070
Test name
Test status
Simulation time 15698600 ps
CPU time 13.25 seconds
Started Jun 04 02:51:31 PM PDT 24
Finished Jun 04 02:51:44 PM PDT 24
Peak memory 264760 kb
Host smart-5e1f4a5e-46f0-4e59-b8f9-21b903d041e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615913189 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.3615913189
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.115999006
Short name T921
Test name
Test status
Simulation time 290266198500 ps
CPU time 842.17 seconds
Started Jun 04 02:51:10 PM PDT 24
Finished Jun 04 03:05:12 PM PDT 24
Peak memory 263084 kb
Host smart-e0d9edf3-9433-4b6a-b075-5fe67d44d2ce
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115999006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.flash_ctrl_hw_rma_reset.115999006
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.1921124888
Short name T436
Test name
Test status
Simulation time 10098004600 ps
CPU time 156.56 seconds
Started Jun 04 02:51:09 PM PDT 24
Finished Jun 04 02:53:46 PM PDT 24
Peak memory 262384 kb
Host smart-ab2eab33-8b0e-4935-bc48-ab0dae401145
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921124888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.1921124888
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.2645907467
Short name T531
Test name
Test status
Simulation time 5882188700 ps
CPU time 135.98 seconds
Started Jun 04 02:51:18 PM PDT 24
Finished Jun 04 02:53:35 PM PDT 24
Peak memory 291708 kb
Host smart-24f19d29-1b4e-4a84-b191-f0ebc27af272
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645907467 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.2645907467
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.2052606287
Short name T899
Test name
Test status
Simulation time 106586600 ps
CPU time 13.82 seconds
Started Jun 04 02:51:26 PM PDT 24
Finished Jun 04 02:51:40 PM PDT 24
Peak memory 264768 kb
Host smart-fea913e5-54a2-49ff-8ca0-7fe940d2797d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052606287 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.2052606287
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.1983490436
Short name T111
Test name
Test status
Simulation time 10159337600 ps
CPU time 273.75 seconds
Started Jun 04 02:51:10 PM PDT 24
Finished Jun 04 02:55:44 PM PDT 24
Peak memory 273332 kb
Host smart-0136d22e-43f2-4d2d-a117-f481e66267e7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983490436 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.1983490436
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.877291807
Short name T724
Test name
Test status
Simulation time 147988200 ps
CPU time 109.44 seconds
Started Jun 04 02:51:09 PM PDT 24
Finished Jun 04 02:52:59 PM PDT 24
Peak memory 261016 kb
Host smart-dd3e1ee7-b07b-45e1-8567-4bafa4e63123
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877291807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ot
p_reset.877291807
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.1191221271
Short name T839
Test name
Test status
Simulation time 707628300 ps
CPU time 333.17 seconds
Started Jun 04 02:51:02 PM PDT 24
Finished Jun 04 02:56:36 PM PDT 24
Peak memory 262076 kb
Host smart-f49deac3-e40a-44c7-9cc6-6d3b613c1fb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1191221271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1191221271
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.3017819122
Short name T235
Test name
Test status
Simulation time 64429000 ps
CPU time 13.54 seconds
Started Jun 04 02:51:17 PM PDT 24
Finished Jun 04 02:51:31 PM PDT 24
Peak memory 258348 kb
Host smart-aab6fe6c-73e4-4c5e-a925-e834e2c49728
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017819122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.3017819122
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.3755165907
Short name T444
Test name
Test status
Simulation time 297042700 ps
CPU time 291.65 seconds
Started Jun 04 02:51:01 PM PDT 24
Finished Jun 04 02:55:54 PM PDT 24
Peak memory 278380 kb
Host smart-e801beb0-0c46-40da-a785-dd5f602057e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755165907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.3755165907
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.224142065
Short name T865
Test name
Test status
Simulation time 67137900 ps
CPU time 31.44 seconds
Started Jun 04 02:51:25 PM PDT 24
Finished Jun 04 02:51:57 PM PDT 24
Peak memory 266924 kb
Host smart-4216caa8-f29f-4dc7-b5b6-5154929c8193
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224142065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_re_evict.224142065
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.3659341985
Short name T499
Test name
Test status
Simulation time 513230500 ps
CPU time 109.55 seconds
Started Jun 04 02:51:09 PM PDT 24
Finished Jun 04 02:52:59 PM PDT 24
Peak memory 280724 kb
Host smart-70e3f8e0-3ff8-4ea0-a2c1-ceed15ed31c3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659341985 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_ro.3659341985
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.2372800959
Short name T779
Test name
Test status
Simulation time 47499806100 ps
CPU time 643.79 seconds
Started Jun 04 02:51:09 PM PDT 24
Finished Jun 04 03:01:53 PM PDT 24
Peak memory 314144 kb
Host smart-82e94640-f626-494a-a0b9-f6471622fe6a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372800959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.2372800959
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.2228476468
Short name T1020
Test name
Test status
Simulation time 78944900 ps
CPU time 30.75 seconds
Started Jun 04 02:51:26 PM PDT 24
Finished Jun 04 02:51:57 PM PDT 24
Peak memory 275164 kb
Host smart-9fc50984-fb62-43d3-8b17-15513ebccca6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228476468 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.2228476468
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.2900104916
Short name T391
Test name
Test status
Simulation time 5312153200 ps
CPU time 71.46 seconds
Started Jun 04 02:51:25 PM PDT 24
Finished Jun 04 02:52:37 PM PDT 24
Peak memory 262940 kb
Host smart-35e0fc11-e6fe-4ace-bce6-1a194a8396e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900104916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.2900104916
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.3929755601
Short name T658
Test name
Test status
Simulation time 40215500 ps
CPU time 125.4 seconds
Started Jun 04 02:51:02 PM PDT 24
Finished Jun 04 02:53:08 PM PDT 24
Peak memory 276780 kb
Host smart-6adac7ea-7505-4142-aff5-76acccbf0028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929755601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.3929755601
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.531503572
Short name T587
Test name
Test status
Simulation time 4718558100 ps
CPU time 226.13 seconds
Started Jun 04 02:51:10 PM PDT 24
Finished Jun 04 02:54:56 PM PDT 24
Peak memory 264780 kb
Host smart-737fee5e-832e-4698-b8e1-14703605aff5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531503572 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.flash_ctrl_wo.531503572
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.3745838718
Short name T553
Test name
Test status
Simulation time 55661400 ps
CPU time 13.39 seconds
Started Jun 04 02:51:57 PM PDT 24
Finished Jun 04 02:52:11 PM PDT 24
Peak memory 264796 kb
Host smart-1a8c740c-5b6e-443b-bbe2-71366466ea6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745838718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
3745838718
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.2971177376
Short name T665
Test name
Test status
Simulation time 13403200 ps
CPU time 15.88 seconds
Started Jun 04 02:51:58 PM PDT 24
Finished Jun 04 02:52:15 PM PDT 24
Peak memory 274748 kb
Host smart-fa4f0214-eb8b-47a2-9037-453378a77ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971177376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.2971177376
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.3290434138
Short name T874
Test name
Test status
Simulation time 11382800 ps
CPU time 22.12 seconds
Started Jun 04 02:51:59 PM PDT 24
Finished Jun 04 02:52:22 PM PDT 24
Peak memory 273232 kb
Host smart-d254e554-e843-4fb2-8115-aebfa1b89fad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290434138 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.3290434138
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.1358128165
Short name T142
Test name
Test status
Simulation time 10018373600 ps
CPU time 176.22 seconds
Started Jun 04 02:51:57 PM PDT 24
Finished Jun 04 02:54:54 PM PDT 24
Peak memory 296468 kb
Host smart-f3a9e6a4-2df3-404a-b8d4-1cdeef11bda7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358128165 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.1358128165
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.3521533025
Short name T354
Test name
Test status
Simulation time 45566400 ps
CPU time 13.4 seconds
Started Jun 04 02:51:59 PM PDT 24
Finished Jun 04 02:52:13 PM PDT 24
Peak memory 258948 kb
Host smart-477ac80e-2c67-4bbe-8b06-571148414384
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521533025 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.3521533025
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.3259057502
Short name T143
Test name
Test status
Simulation time 80136628300 ps
CPU time 796.06 seconds
Started Jun 04 02:51:43 PM PDT 24
Finished Jun 04 03:05:00 PM PDT 24
Peak memory 264212 kb
Host smart-4c06b2bb-e061-402f-b5fe-74c3e9026608
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259057502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.3259057502
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.1781468945
Short name T548
Test name
Test status
Simulation time 4461496700 ps
CPU time 75.89 seconds
Started Jun 04 02:51:44 PM PDT 24
Finished Jun 04 02:53:01 PM PDT 24
Peak memory 262344 kb
Host smart-da7d5aae-18aa-4a7c-876b-748e82be9207
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781468945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.1781468945
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.3689789340
Short name T397
Test name
Test status
Simulation time 11613408500 ps
CPU time 142.13 seconds
Started Jun 04 02:51:58 PM PDT 24
Finished Jun 04 02:54:21 PM PDT 24
Peak memory 291688 kb
Host smart-6159cae6-1a39-4503-b193-9ae756ebdc47
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689789340 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.3689789340
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.776512498
Short name T889
Test name
Test status
Simulation time 8425178200 ps
CPU time 74.42 seconds
Started Jun 04 02:51:51 PM PDT 24
Finished Jun 04 02:53:06 PM PDT 24
Peak memory 259728 kb
Host smart-11c41bdd-c837-4b37-81dd-3bc5f54b9345
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776512498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.776512498
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.3937502588
Short name T542
Test name
Test status
Simulation time 25286600 ps
CPU time 13.73 seconds
Started Jun 04 02:51:58 PM PDT 24
Finished Jun 04 02:52:13 PM PDT 24
Peak memory 259236 kb
Host smart-e28e562c-02c7-44c5-9ef1-d7a550f05483
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937502588 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.3937502588
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.2038430961
Short name T1043
Test name
Test status
Simulation time 25268188600 ps
CPU time 331.49 seconds
Started Jun 04 02:51:43 PM PDT 24
Finished Jun 04 02:57:14 PM PDT 24
Peak memory 274108 kb
Host smart-a36661b8-cb30-42e2-88b0-0c883e50c482
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038430961 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_mp_regions.2038430961
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.3519336878
Short name T705
Test name
Test status
Simulation time 1504171600 ps
CPU time 387.66 seconds
Started Jun 04 02:51:33 PM PDT 24
Finished Jun 04 02:58:01 PM PDT 24
Peak memory 261456 kb
Host smart-64198072-5419-4a34-a822-77b3a4497468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519336878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.3519336878
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.2977342805
Short name T939
Test name
Test status
Simulation time 2327708700 ps
CPU time 199.41 seconds
Started Jun 04 02:51:58 PM PDT 24
Finished Jun 04 02:55:18 PM PDT 24
Peak memory 259268 kb
Host smart-14b2e711-2bcf-4bbf-bd7e-c070ddc7f204
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977342805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.2977342805
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.54630492
Short name T527
Test name
Test status
Simulation time 124392800 ps
CPU time 320.2 seconds
Started Jun 04 02:51:32 PM PDT 24
Finished Jun 04 02:56:52 PM PDT 24
Peak memory 281256 kb
Host smart-0bc7f1cd-3c29-4449-b50c-6838f84fa209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54630492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.54630492
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.2690562149
Short name T424
Test name
Test status
Simulation time 62510000 ps
CPU time 35.19 seconds
Started Jun 04 02:52:00 PM PDT 24
Finished Jun 04 02:52:36 PM PDT 24
Peak memory 274104 kb
Host smart-40d67fed-1be2-4982-bb2c-e8bcf8f8e827
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690562149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.2690562149
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.2691207982
Short name T702
Test name
Test status
Simulation time 586000100 ps
CPU time 118.45 seconds
Started Jun 04 02:51:50 PM PDT 24
Finished Jun 04 02:53:49 PM PDT 24
Peak memory 281260 kb
Host smart-6baa37d2-0efc-441b-8b5e-88e61f9ba58b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691207982 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.flash_ctrl_ro.2691207982
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.901738803
Short name T50
Test name
Test status
Simulation time 38057223300 ps
CPU time 602.73 seconds
Started Jun 04 02:51:50 PM PDT 24
Finished Jun 04 03:01:53 PM PDT 24
Peak memory 313292 kb
Host smart-a67ecccd-fbea-48c2-b7a8-9f4ee28b4882
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901738803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.flash_ctrl_rw.901738803
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.1350326460
Short name T782
Test name
Test status
Simulation time 47996400 ps
CPU time 31.23 seconds
Started Jun 04 02:51:59 PM PDT 24
Finished Jun 04 02:52:32 PM PDT 24
Peak memory 273076 kb
Host smart-b0b4155e-dfda-46d8-a0f7-6b7d4a4aa800
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350326460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.1350326460
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.1285999075
Short name T679
Test name
Test status
Simulation time 28451500 ps
CPU time 31.42 seconds
Started Jun 04 02:51:59 PM PDT 24
Finished Jun 04 02:52:32 PM PDT 24
Peak memory 275228 kb
Host smart-997e90a4-70b5-4dee-baa2-3035b61aa22f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285999075 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.1285999075
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.3058844987
Short name T211
Test name
Test status
Simulation time 7892620200 ps
CPU time 80.51 seconds
Started Jun 04 02:51:59 PM PDT 24
Finished Jun 04 02:53:21 PM PDT 24
Peak memory 262344 kb
Host smart-348f4722-311f-4d07-89f9-e970bd48d63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058844987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.3058844987
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.1772638522
Short name T566
Test name
Test status
Simulation time 102856200 ps
CPU time 119.54 seconds
Started Jun 04 02:51:36 PM PDT 24
Finished Jun 04 02:53:36 PM PDT 24
Peak memory 275348 kb
Host smart-9fcaddfc-cb2e-4e24-9210-0c70600e2392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772638522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.1772638522
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.4031843194
Short name T845
Test name
Test status
Simulation time 2595421700 ps
CPU time 223.81 seconds
Started Jun 04 02:51:51 PM PDT 24
Finished Jun 04 02:55:35 PM PDT 24
Peak memory 264704 kb
Host smart-c554fc19-61ef-44fd-873a-3f4bd2b8dce9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031843194 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.flash_ctrl_wo.4031843194
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.3659829759
Short name T468
Test name
Test status
Simulation time 112384200 ps
CPU time 13.84 seconds
Started Jun 04 02:52:25 PM PDT 24
Finished Jun 04 02:52:40 PM PDT 24
Peak memory 257876 kb
Host smart-0b5a1df9-0d0b-4e58-8471-4a49ea9a16ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659829759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
3659829759
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.741082657
Short name T65
Test name
Test status
Simulation time 76898800 ps
CPU time 13.67 seconds
Started Jun 04 02:52:25 PM PDT 24
Finished Jun 04 02:52:39 PM PDT 24
Peak memory 275772 kb
Host smart-8f49afd6-1363-43b5-9be5-5dd2392a83bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741082657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.741082657
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2183624705
Short name T1062
Test name
Test status
Simulation time 10018234200 ps
CPU time 93.19 seconds
Started Jun 04 02:52:24 PM PDT 24
Finished Jun 04 02:53:58 PM PDT 24
Peak memory 330396 kb
Host smart-87d3992f-618b-4921-9fee-0fbb381fea13
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183624705 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.2183624705
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.393879075
Short name T135
Test name
Test status
Simulation time 46479700 ps
CPU time 13.7 seconds
Started Jun 04 02:52:25 PM PDT 24
Finished Jun 04 02:52:39 PM PDT 24
Peak memory 258840 kb
Host smart-8198b625-cff8-42f3-b42d-acf1764e32b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393879075 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.393879075
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.1620540487
Short name T848
Test name
Test status
Simulation time 14258452300 ps
CPU time 255.62 seconds
Started Jun 04 02:52:09 PM PDT 24
Finished Jun 04 02:56:25 PM PDT 24
Peak memory 262316 kb
Host smart-c86eea31-7fe5-4920-9ede-4f9e18c0db75
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620540487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.1620540487
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.3831810794
Short name T540
Test name
Test status
Simulation time 742526600 ps
CPU time 163.38 seconds
Started Jun 04 02:52:25 PM PDT 24
Finished Jun 04 02:55:09 PM PDT 24
Peak memory 289556 kb
Host smart-54449bca-2a8e-4e86-8d18-af09d3e8023b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831810794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.3831810794
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3027278193
Short name T742
Test name
Test status
Simulation time 24686010400 ps
CPU time 286.48 seconds
Started Jun 04 02:52:25 PM PDT 24
Finished Jun 04 02:57:12 PM PDT 24
Peak memory 292748 kb
Host smart-ec0fb194-a689-4bf4-b55c-d18b23d77e2d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027278193 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.3027278193
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.720666809
Short name T402
Test name
Test status
Simulation time 2023401300 ps
CPU time 87.21 seconds
Started Jun 04 02:52:16 PM PDT 24
Finished Jun 04 02:53:44 PM PDT 24
Peak memory 260432 kb
Host smart-3e505afb-9a3e-43db-99ed-0a2077c35096
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720666809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.720666809
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.954893321
Short name T509
Test name
Test status
Simulation time 27602200 ps
CPU time 13.23 seconds
Started Jun 04 02:52:24 PM PDT 24
Finished Jun 04 02:52:38 PM PDT 24
Peak memory 264816 kb
Host smart-57a42ce9-b03b-468c-9348-9db6d4860cff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954893321 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.954893321
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.1858096928
Short name T428
Test name
Test status
Simulation time 79784600 ps
CPU time 111.44 seconds
Started Jun 04 02:52:16 PM PDT 24
Finished Jun 04 02:54:08 PM PDT 24
Peak memory 259664 kb
Host smart-78b07b71-bd74-4e6c-80a4-72a7a57f74d1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858096928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.1858096928
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.3761809109
Short name T971
Test name
Test status
Simulation time 706548100 ps
CPU time 121.63 seconds
Started Jun 04 02:52:07 PM PDT 24
Finished Jun 04 02:54:09 PM PDT 24
Peak memory 262276 kb
Host smart-528b8c2b-e539-4ec7-8bf5-2f7814dd1e83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3761809109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.3761809109
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.2906945576
Short name T369
Test name
Test status
Simulation time 32210100 ps
CPU time 13.91 seconds
Started Jun 04 02:52:26 PM PDT 24
Finished Jun 04 02:52:41 PM PDT 24
Peak memory 264760 kb
Host smart-c97dae54-780c-4f66-b7f0-3f3943f50ef9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906945576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.2906945576
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.3247100988
Short name T108
Test name
Test status
Simulation time 178383700 ps
CPU time 210.18 seconds
Started Jun 04 02:52:07 PM PDT 24
Finished Jun 04 02:55:37 PM PDT 24
Peak memory 279332 kb
Host smart-1febee25-04ed-47d2-b356-e6a6cf8b628c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247100988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3247100988
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3036598362
Short name T4
Test name
Test status
Simulation time 89141000 ps
CPU time 33.68 seconds
Started Jun 04 02:52:24 PM PDT 24
Finished Jun 04 02:52:58 PM PDT 24
Peak memory 274160 kb
Host smart-74d4583f-69c6-43ad-8688-65afbbba808c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036598362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3036598362
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.1941580744
Short name T119
Test name
Test status
Simulation time 3183688400 ps
CPU time 550.81 seconds
Started Jun 04 02:52:25 PM PDT 24
Finished Jun 04 03:01:36 PM PDT 24
Peak memory 309164 kb
Host smart-52d8e5c5-03d4-424a-8de9-c17d26cb3bda
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941580744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.1941580744
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.12506735
Short name T333
Test name
Test status
Simulation time 82455700 ps
CPU time 32.66 seconds
Started Jun 04 02:52:25 PM PDT 24
Finished Jun 04 02:52:58 PM PDT 24
Peak memory 273148 kb
Host smart-b9743023-f3a9-44b2-9d41-428ea6b0eac5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12506735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flas
h_ctrl_rw_evict.12506735
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.3713179665
Short name T42
Test name
Test status
Simulation time 109598600 ps
CPU time 31.75 seconds
Started Jun 04 02:52:24 PM PDT 24
Finished Jun 04 02:52:57 PM PDT 24
Peak memory 275160 kb
Host smart-b84bee15-f1d2-49e3-8724-7861234ff08c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713179665 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.3713179665
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.1812249685
Short name T539
Test name
Test status
Simulation time 3284117400 ps
CPU time 67.9 seconds
Started Jun 04 02:52:24 PM PDT 24
Finished Jun 04 02:53:32 PM PDT 24
Peak memory 262844 kb
Host smart-97423068-dc0d-4983-98c0-2e14a9d27af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812249685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.1812249685
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.3145651279
Short name T456
Test name
Test status
Simulation time 23532000 ps
CPU time 99.52 seconds
Started Jun 04 02:51:58 PM PDT 24
Finished Jun 04 02:53:38 PM PDT 24
Peak memory 275092 kb
Host smart-4f06b9ce-b844-4d4a-afe1-d573813cba08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145651279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3145651279
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.2626948591
Short name T1046
Test name
Test status
Simulation time 2395011400 ps
CPU time 175.85 seconds
Started Jun 04 02:52:16 PM PDT 24
Finished Jun 04 02:55:13 PM PDT 24
Peak memory 259136 kb
Host smart-1971b82f-a61b-40f9-9a26-21491022d41f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626948591 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.2626948591
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.2025423936
Short name T1004
Test name
Test status
Simulation time 42450200 ps
CPU time 13.61 seconds
Started Jun 04 02:52:50 PM PDT 24
Finished Jun 04 02:53:04 PM PDT 24
Peak memory 264816 kb
Host smart-04c92d67-c7e7-4a40-9358-0dd49a1e554f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025423936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
2025423936
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.2013850509
Short name T893
Test name
Test status
Simulation time 14298600 ps
CPU time 15.46 seconds
Started Jun 04 02:52:51 PM PDT 24
Finished Jun 04 02:53:07 PM PDT 24
Peak memory 275876 kb
Host smart-ae2c7747-1939-4c50-a90c-1a33ec255425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013850509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.2013850509
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.2042628408
Short name T1045
Test name
Test status
Simulation time 27085600 ps
CPU time 23 seconds
Started Jun 04 02:52:42 PM PDT 24
Finished Jun 04 02:53:05 PM PDT 24
Peak memory 264820 kb
Host smart-62579425-e7e4-468d-a7e6-05ee90049a56
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042628408 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.2042628408
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.617099676
Short name T554
Test name
Test status
Simulation time 10019283300 ps
CPU time 83.71 seconds
Started Jun 04 02:52:55 PM PDT 24
Finished Jun 04 02:54:19 PM PDT 24
Peak memory 291448 kb
Host smart-5c50daaa-c0fb-4b6a-a35e-cbcf5295a8e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617099676 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.617099676
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.1122512783
Short name T1076
Test name
Test status
Simulation time 21447800 ps
CPU time 13.44 seconds
Started Jun 04 02:52:54 PM PDT 24
Finished Jun 04 02:53:08 PM PDT 24
Peak memory 257988 kb
Host smart-0cfd8a00-c772-481e-9efe-28d0c5ba2094
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122512783 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.1122512783
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.1516781410
Short name T607
Test name
Test status
Simulation time 140177862500 ps
CPU time 945.13 seconds
Started Jun 04 02:52:32 PM PDT 24
Finished Jun 04 03:08:18 PM PDT 24
Peak memory 263732 kb
Host smart-f15cade9-e471-493b-b3b3-03ec7742c6e1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516781410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.1516781410
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.1221641005
Short name T547
Test name
Test status
Simulation time 5039636400 ps
CPU time 90.89 seconds
Started Jun 04 02:52:33 PM PDT 24
Finished Jun 04 02:54:04 PM PDT 24
Peak memory 262372 kb
Host smart-cc70b6d2-cfe6-4c7d-a0d5-b35937e0511a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221641005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.1221641005
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.2011566560
Short name T805
Test name
Test status
Simulation time 2421709900 ps
CPU time 134.44 seconds
Started Jun 04 02:52:42 PM PDT 24
Finished Jun 04 02:54:57 PM PDT 24
Peak memory 289512 kb
Host smart-d713477a-6ebd-4b6e-9ac5-72848d0cd8c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011566560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.2011566560
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.2147084439
Short name T351
Test name
Test status
Simulation time 58150665400 ps
CPU time 300.21 seconds
Started Jun 04 02:52:41 PM PDT 24
Finished Jun 04 02:57:41 PM PDT 24
Peak memory 284028 kb
Host smart-a1c8c3ac-2dfc-47c6-99a5-3a6d376bae1f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147084439 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.2147084439
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.3052842921
Short name T1033
Test name
Test status
Simulation time 2647748100 ps
CPU time 71.97 seconds
Started Jun 04 02:52:33 PM PDT 24
Finished Jun 04 02:53:46 PM PDT 24
Peak memory 260500 kb
Host smart-fc01fdb9-20cd-4060-98f9-9920f0558573
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052842921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.3
052842921
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.3011147158
Short name T112
Test name
Test status
Simulation time 10936729900 ps
CPU time 270.18 seconds
Started Jun 04 02:52:32 PM PDT 24
Finished Jun 04 02:57:02 PM PDT 24
Peak memory 274064 kb
Host smart-3dc4609b-3381-4724-b281-fae68418c38e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011147158 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.3011147158
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.3929812053
Short name T550
Test name
Test status
Simulation time 37425200 ps
CPU time 129.55 seconds
Started Jun 04 02:52:34 PM PDT 24
Finished Jun 04 02:54:44 PM PDT 24
Peak memory 260736 kb
Host smart-570c4c7e-7aa6-4f7a-a703-b51af3019f44
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929812053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.3929812053
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.169867943
Short name T1003
Test name
Test status
Simulation time 175712100 ps
CPU time 187.7 seconds
Started Jun 04 02:52:34 PM PDT 24
Finished Jun 04 02:55:42 PM PDT 24
Peak memory 262224 kb
Host smart-b5092fa0-95c2-43f5-8871-d9f2f9cfd5ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169867943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.169867943
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.3624640285
Short name T511
Test name
Test status
Simulation time 2272606300 ps
CPU time 195.19 seconds
Started Jun 04 02:52:44 PM PDT 24
Finished Jun 04 02:56:00 PM PDT 24
Peak memory 258712 kb
Host smart-cc0d3cbf-4085-4d83-9224-becbe339203a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624640285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_re
set.3624640285
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.2013272802
Short name T82
Test name
Test status
Simulation time 3164120300 ps
CPU time 1190.42 seconds
Started Jun 04 02:52:26 PM PDT 24
Finished Jun 04 03:12:17 PM PDT 24
Peak memory 285604 kb
Host smart-14e0f2d8-4905-406d-b14e-afae3a43271c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013272802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.2013272802
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.890760902
Short name T419
Test name
Test status
Simulation time 50576500 ps
CPU time 33.45 seconds
Started Jun 04 02:52:44 PM PDT 24
Finished Jun 04 02:53:18 PM PDT 24
Peak memory 273112 kb
Host smart-ffa05136-e66a-43c1-9ee8-eaf1fb8271ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890760902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_re_evict.890760902
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.1002189925
Short name T457
Test name
Test status
Simulation time 1726468000 ps
CPU time 127.1 seconds
Started Jun 04 02:52:33 PM PDT 24
Finished Jun 04 02:54:40 PM PDT 24
Peak memory 281328 kb
Host smart-5967825f-a8ac-46dd-9b4b-be033c51dcae
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002189925 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_ro.1002189925
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.2782012509
Short name T1041
Test name
Test status
Simulation time 10556885600 ps
CPU time 747.59 seconds
Started Jun 04 02:52:43 PM PDT 24
Finished Jun 04 03:05:11 PM PDT 24
Peak memory 313596 kb
Host smart-f9e2c0fb-cdb2-41b1-8837-25112c4bc4bf
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782012509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_rw.2782012509
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.1030542338
Short name T491
Test name
Test status
Simulation time 43639800 ps
CPU time 31.34 seconds
Started Jun 04 02:52:45 PM PDT 24
Finished Jun 04 02:53:17 PM PDT 24
Peak memory 266900 kb
Host smart-7db8ba90-a416-46d9-b5d0-a851f4284704
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030542338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_rw_evict.1030542338
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.147642731
Short name T973
Test name
Test status
Simulation time 64083200 ps
CPU time 198.24 seconds
Started Jun 04 02:52:23 PM PDT 24
Finished Jun 04 02:55:42 PM PDT 24
Peak memory 281100 kb
Host smart-dd79b3cc-a237-4278-a136-aea524a85d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147642731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.147642731
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.1424753784
Short name T930
Test name
Test status
Simulation time 9563642900 ps
CPU time 181.8 seconds
Started Jun 04 02:52:36 PM PDT 24
Finished Jun 04 02:55:38 PM PDT 24
Peak memory 258732 kb
Host smart-f2db3b3d-6d57-4d11-a65c-741e672f600f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424753784 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.flash_ctrl_wo.1424753784
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.2620807152
Short name T520
Test name
Test status
Simulation time 41488400 ps
CPU time 13.7 seconds
Started Jun 04 02:53:18 PM PDT 24
Finished Jun 04 02:53:32 PM PDT 24
Peak memory 263920 kb
Host smart-d237c03f-6dec-47c7-a20e-9d3f060d78bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620807152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
2620807152
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.372814726
Short name T653
Test name
Test status
Simulation time 40475600 ps
CPU time 15.36 seconds
Started Jun 04 02:53:18 PM PDT 24
Finished Jun 04 02:53:34 PM PDT 24
Peak memory 275832 kb
Host smart-28b9d488-dbf6-4b8d-940c-835d6e028892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372814726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.372814726
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3335332548
Short name T809
Test name
Test status
Simulation time 10040432400 ps
CPU time 93.03 seconds
Started Jun 04 02:53:20 PM PDT 24
Finished Jun 04 02:54:53 PM PDT 24
Peak memory 269392 kb
Host smart-246c5126-6a79-44b8-8e36-f9ab86f28a1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335332548 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.3335332548
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.3590791974
Short name T353
Test name
Test status
Simulation time 15384700 ps
CPU time 13.55 seconds
Started Jun 04 02:53:17 PM PDT 24
Finished Jun 04 02:53:31 PM PDT 24
Peak memory 258916 kb
Host smart-805a4722-aec6-42f1-9502-bee40e24145a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590791974 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.3590791974
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.3090010801
Short name T681
Test name
Test status
Simulation time 60132352800 ps
CPU time 935.2 seconds
Started Jun 04 02:53:11 PM PDT 24
Finished Jun 04 03:08:46 PM PDT 24
Peak memory 262952 kb
Host smart-dba9d557-11bf-488c-9207-6d97302b9b04
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090010801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.3090010801
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.3631397712
Short name T812
Test name
Test status
Simulation time 9596005400 ps
CPU time 214.56 seconds
Started Jun 04 02:53:10 PM PDT 24
Finished Jun 04 02:56:45 PM PDT 24
Peak memory 261744 kb
Host smart-a8703513-8ed2-4f91-8e72-1fe125055277
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631397712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.3631397712
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.868463662
Short name T38
Test name
Test status
Simulation time 1837439700 ps
CPU time 218.14 seconds
Started Jun 04 02:53:18 PM PDT 24
Finished Jun 04 02:56:56 PM PDT 24
Peak memory 289472 kb
Host smart-fefa281d-5009-42e2-a019-1ef1eac2d529
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868463662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flas
h_ctrl_intr_rd.868463662
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3934887989
Short name T902
Test name
Test status
Simulation time 24922891800 ps
CPU time 143.21 seconds
Started Jun 04 02:53:21 PM PDT 24
Finished Jun 04 02:55:45 PM PDT 24
Peak memory 291800 kb
Host smart-12052dc6-d11f-4393-91c3-6f22a7abb1a3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934887989 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.3934887989
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.3306591394
Short name T920
Test name
Test status
Simulation time 8750244400 ps
CPU time 77.85 seconds
Started Jun 04 02:53:10 PM PDT 24
Finished Jun 04 02:54:28 PM PDT 24
Peak memory 259760 kb
Host smart-b8ed89d8-fafa-4287-ae7c-578a146dbfa0
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306591394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3
306591394
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.1705665332
Short name T683
Test name
Test status
Simulation time 15798000 ps
CPU time 13.47 seconds
Started Jun 04 02:53:21 PM PDT 24
Finished Jun 04 02:53:35 PM PDT 24
Peak memory 264804 kb
Host smart-3a36b47d-bcaf-47f3-9ac3-2910ea376d20
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705665332 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.1705665332
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.361113902
Short name T84
Test name
Test status
Simulation time 108191098400 ps
CPU time 411.78 seconds
Started Jun 04 02:53:09 PM PDT 24
Finished Jun 04 03:00:02 PM PDT 24
Peak memory 273536 kb
Host smart-7498bcf9-d744-4a9a-9cd2-6a9fe9223237
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361113902 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_mp_regions.361113902
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.1359595917
Short name T842
Test name
Test status
Simulation time 39033000 ps
CPU time 134.79 seconds
Started Jun 04 02:53:10 PM PDT 24
Finished Jun 04 02:55:25 PM PDT 24
Peak memory 264168 kb
Host smart-2a047b7b-a5e6-4d65-bb18-9225e8bb8796
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359595917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.1359595917
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.1552767016
Short name T867
Test name
Test status
Simulation time 66086800 ps
CPU time 134.69 seconds
Started Jun 04 02:52:59 PM PDT 24
Finished Jun 04 02:55:14 PM PDT 24
Peak memory 261500 kb
Host smart-c762e1c1-e72f-4b2f-8ece-166f5c11325f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552767016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.1552767016
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.122721114
Short name T469
Test name
Test status
Simulation time 5732889000 ps
CPU time 232.75 seconds
Started Jun 04 02:53:22 PM PDT 24
Finished Jun 04 02:57:15 PM PDT 24
Peak memory 259452 kb
Host smart-ae863c1f-9306-4aa0-9cf7-fc93bc3a9dd4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122721114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_res
et.122721114
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.1630265384
Short name T802
Test name
Test status
Simulation time 514733300 ps
CPU time 509.53 seconds
Started Jun 04 02:52:58 PM PDT 24
Finished Jun 04 03:01:28 PM PDT 24
Peak memory 281240 kb
Host smart-1e6eada1-f14b-4a5d-99e1-14c7cab889cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630265384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.1630265384
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.3930436363
Short name T407
Test name
Test status
Simulation time 215513400 ps
CPU time 36.78 seconds
Started Jun 04 02:53:21 PM PDT 24
Finished Jun 04 02:53:58 PM PDT 24
Peak memory 274180 kb
Host smart-a0e3e49a-bcf4-4df3-b350-986c867897df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930436363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.3930436363
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.3437870687
Short name T912
Test name
Test status
Simulation time 554718900 ps
CPU time 120.97 seconds
Started Jun 04 02:53:09 PM PDT 24
Finished Jun 04 02:55:10 PM PDT 24
Peak memory 280684 kb
Host smart-de429ae6-f9cd-4608-b961-ae8d4a511958
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437870687 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.3437870687
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.4255439420
Short name T570
Test name
Test status
Simulation time 7525311100 ps
CPU time 570.1 seconds
Started Jun 04 02:53:11 PM PDT 24
Finished Jun 04 03:02:42 PM PDT 24
Peak memory 313612 kb
Host smart-e7107ab1-0a65-4b78-92ac-4056c972201e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255439420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_rw.4255439420
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.2196206823
Short name T604
Test name
Test status
Simulation time 59091400 ps
CPU time 98.2 seconds
Started Jun 04 02:52:52 PM PDT 24
Finished Jun 04 02:54:30 PM PDT 24
Peak memory 275092 kb
Host smart-7fb5abad-2f5b-4c88-aa2b-ae03602f2711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196206823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.2196206823
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.2158688712
Short name T824
Test name
Test status
Simulation time 1975455200 ps
CPU time 149.09 seconds
Started Jun 04 02:53:10 PM PDT 24
Finished Jun 04 02:55:40 PM PDT 24
Peak memory 259124 kb
Host smart-c3622320-2842-41a8-a090-2c681b4c6899
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158688712 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.flash_ctrl_wo.2158688712
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.2997175747
Short name T590
Test name
Test status
Simulation time 211508000 ps
CPU time 14.41 seconds
Started Jun 04 02:53:44 PM PDT 24
Finished Jun 04 02:53:59 PM PDT 24
Peak memory 264812 kb
Host smart-b34c0900-0a69-4814-bffb-5d0c170fcb47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997175747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
2997175747
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.2158587295
Short name T487
Test name
Test status
Simulation time 14536500 ps
CPU time 15.98 seconds
Started Jun 04 02:53:42 PM PDT 24
Finished Jun 04 02:53:59 PM PDT 24
Peak memory 274800 kb
Host smart-379170a8-80a6-4699-adee-0c43f67aca7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158587295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2158587295
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3451444845
Short name T286
Test name
Test status
Simulation time 10034795000 ps
CPU time 100.96 seconds
Started Jun 04 02:53:47 PM PDT 24
Finished Jun 04 02:55:29 PM PDT 24
Peak memory 273656 kb
Host smart-d8cc8f72-cb26-4891-8722-2a22200b605a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451444845 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.3451444845
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.40680561
Short name T131
Test name
Test status
Simulation time 15111500 ps
CPU time 13.39 seconds
Started Jun 04 02:53:44 PM PDT 24
Finished Jun 04 02:53:58 PM PDT 24
Peak memory 257796 kb
Host smart-9e5394e1-410b-422d-b975-79cff0d46210
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40680561 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.40680561
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.3987452070
Short name T633
Test name
Test status
Simulation time 2367309000 ps
CPU time 77.13 seconds
Started Jun 04 02:53:18 PM PDT 24
Finished Jun 04 02:54:35 PM PDT 24
Peak memory 262276 kb
Host smart-583cd436-d6cb-49c3-9cc4-0c051733de59
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987452070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.3987452070
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.2153337183
Short name T274
Test name
Test status
Simulation time 641455600 ps
CPU time 167.25 seconds
Started Jun 04 02:53:36 PM PDT 24
Finished Jun 04 02:56:24 PM PDT 24
Peak memory 284400 kb
Host smart-6caa2780-44d1-4c3a-937c-9a863b6cac3a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153337183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.2153337183
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2213140467
Short name T956
Test name
Test status
Simulation time 49787772700 ps
CPU time 315.67 seconds
Started Jun 04 02:53:35 PM PDT 24
Finished Jun 04 02:58:51 PM PDT 24
Peak memory 292512 kb
Host smart-f806863b-be2d-4c13-8b8b-1da850e3e882
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213140467 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.2213140467
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1034803728
Short name T559
Test name
Test status
Simulation time 18381400 ps
CPU time 13.38 seconds
Started Jun 04 02:53:44 PM PDT 24
Finished Jun 04 02:53:58 PM PDT 24
Peak memory 260100 kb
Host smart-4e56e71c-6ac2-4553-a065-3281d6afc59a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034803728 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.1034803728
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.340216873
Short name T110
Test name
Test status
Simulation time 105595887400 ps
CPU time 305.04 seconds
Started Jun 04 02:53:19 PM PDT 24
Finished Jun 04 02:58:24 PM PDT 24
Peak memory 273284 kb
Host smart-77a7ed9b-01d8-46b4-afa8-5131a45056ec
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340216873 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_mp_regions.340216873
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.3729691268
Short name T561
Test name
Test status
Simulation time 73213200 ps
CPU time 108.35 seconds
Started Jun 04 02:53:19 PM PDT 24
Finished Jun 04 02:55:08 PM PDT 24
Peak memory 260772 kb
Host smart-a4f2ee01-a9ba-4801-9711-8d99ce90520d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729691268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.3729691268
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.4071134002
Short name T942
Test name
Test status
Simulation time 288592500 ps
CPU time 439.36 seconds
Started Jun 04 02:53:21 PM PDT 24
Finished Jun 04 03:00:41 PM PDT 24
Peak memory 262292 kb
Host smart-7b24c72c-4b32-4065-b508-b46b201a7346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4071134002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.4071134002
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.3382453092
Short name T462
Test name
Test status
Simulation time 1969924100 ps
CPU time 155.67 seconds
Started Jun 04 02:53:37 PM PDT 24
Finished Jun 04 02:56:13 PM PDT 24
Peak memory 259548 kb
Host smart-1a1eec2a-b142-4d60-8e3e-63e758e93174
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382453092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.3382453092
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.236585215
Short name T734
Test name
Test status
Simulation time 82008100 ps
CPU time 711.62 seconds
Started Jun 04 02:53:20 PM PDT 24
Finished Jun 04 03:05:12 PM PDT 24
Peak memory 283280 kb
Host smart-fb7d12a4-37cc-4320-926b-ef66b851a7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236585215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.236585215
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.2582468094
Short name T936
Test name
Test status
Simulation time 128155500 ps
CPU time 37.53 seconds
Started Jun 04 02:53:44 PM PDT 24
Finished Jun 04 02:54:23 PM PDT 24
Peak memory 269292 kb
Host smart-3e31f046-ed62-4f91-b1f8-258fda493f6d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582468094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.2582468094
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.3690195464
Short name T732
Test name
Test status
Simulation time 14716255600 ps
CPU time 515.98 seconds
Started Jun 04 02:53:35 PM PDT 24
Finished Jun 04 03:02:12 PM PDT 24
Peak memory 313348 kb
Host smart-f9e0482a-05b0-4559-8e28-4fe045456720
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690195464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.flash_ctrl_rw.3690195464
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.3668176583
Short name T29
Test name
Test status
Simulation time 47306600 ps
CPU time 31.73 seconds
Started Jun 04 02:53:48 PM PDT 24
Finished Jun 04 02:54:20 PM PDT 24
Peak memory 274056 kb
Host smart-19ed8298-d447-42d4-b062-4e81538b5e84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668176583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_rw_evict.3668176583
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.3304383623
Short name T628
Test name
Test status
Simulation time 59981100 ps
CPU time 31.66 seconds
Started Jun 04 02:53:45 PM PDT 24
Finished Jun 04 02:54:18 PM PDT 24
Peak memory 265960 kb
Host smart-6f431c5e-94c5-4a7d-83c3-ae533e6b29b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304383623 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.3304383623
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.1292854468
Short name T321
Test name
Test status
Simulation time 323793400 ps
CPU time 122.69 seconds
Started Jun 04 02:53:18 PM PDT 24
Finished Jun 04 02:55:22 PM PDT 24
Peak memory 276524 kb
Host smart-8303a572-76bb-4281-bd27-626867e4429f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292854468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.1292854468
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.4268928248
Short name T423
Test name
Test status
Simulation time 3266098100 ps
CPU time 162.73 seconds
Started Jun 04 02:53:26 PM PDT 24
Finished Jun 04 02:56:09 PM PDT 24
Peak memory 264848 kb
Host smart-2c26eefe-8dc6-492a-ad2f-02e3148b21db
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268928248 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.flash_ctrl_wo.4268928248
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.2208541408
Short name T594
Test name
Test status
Simulation time 27833100 ps
CPU time 13.44 seconds
Started Jun 04 02:54:17 PM PDT 24
Finished Jun 04 02:54:31 PM PDT 24
Peak memory 264812 kb
Host smart-730a0bb7-289f-4340-8d48-bdf642e655ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208541408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
2208541408
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.1726499184
Short name T966
Test name
Test status
Simulation time 15989500 ps
CPU time 13.54 seconds
Started Jun 04 02:54:06 PM PDT 24
Finished Jun 04 02:54:20 PM PDT 24
Peak memory 275828 kb
Host smart-decc63bb-b6cc-4bfb-b96e-0c4580ae5594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726499184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.1726499184
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.860987133
Short name T926
Test name
Test status
Simulation time 44689700 ps
CPU time 21.59 seconds
Started Jun 04 02:54:04 PM PDT 24
Finished Jun 04 02:54:26 PM PDT 24
Peak memory 273184 kb
Host smart-77d2c3b5-30e4-4f81-8152-2b73b3b48167
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860987133 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.860987133
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.616126279
Short name T535
Test name
Test status
Simulation time 10019999200 ps
CPU time 74.16 seconds
Started Jun 04 02:54:16 PM PDT 24
Finished Jun 04 02:55:30 PM PDT 24
Peak memory 284832 kb
Host smart-0e3757cd-f364-4bd3-8209-37c4c2c77462
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616126279 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.616126279
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.1588369319
Short name T1009
Test name
Test status
Simulation time 83417000 ps
CPU time 13.84 seconds
Started Jun 04 02:54:05 PM PDT 24
Finished Jun 04 02:54:19 PM PDT 24
Peak memory 258916 kb
Host smart-e5cda435-601f-40a8-a3df-220938e67abc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588369319 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.1588369319
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.934301301
Short name T917
Test name
Test status
Simulation time 160178697600 ps
CPU time 867.89 seconds
Started Jun 04 02:53:47 PM PDT 24
Finished Jun 04 03:08:16 PM PDT 24
Peak memory 263956 kb
Host smart-a9d5b9af-4066-425d-9f7b-032d58ba1658
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934301301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 18.flash_ctrl_hw_rma_reset.934301301
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.1202085658
Short name T931
Test name
Test status
Simulation time 10628326400 ps
CPU time 182.91 seconds
Started Jun 04 02:53:45 PM PDT 24
Finished Jun 04 02:56:48 PM PDT 24
Peak memory 262388 kb
Host smart-64126ac2-3172-46a0-81ce-387e9c602bc8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202085658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.1202085658
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.2254258010
Short name T345
Test name
Test status
Simulation time 11783119800 ps
CPU time 291.77 seconds
Started Jun 04 02:53:53 PM PDT 24
Finished Jun 04 02:58:46 PM PDT 24
Peak memory 283480 kb
Host smart-01a09beb-adb5-461b-bf33-a5648aa3929a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254258010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.2254258010
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.2341043779
Short name T602
Test name
Test status
Simulation time 11961950200 ps
CPU time 131.7 seconds
Started Jun 04 02:53:53 PM PDT 24
Finished Jun 04 02:56:06 PM PDT 24
Peak memory 293040 kb
Host smart-b1270cc0-ac0d-4ca4-975a-07e79c790566
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341043779 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.2341043779
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.359532775
Short name T467
Test name
Test status
Simulation time 2038221300 ps
CPU time 82.85 seconds
Started Jun 04 02:53:53 PM PDT 24
Finished Jun 04 02:55:16 PM PDT 24
Peak memory 260520 kb
Host smart-6c0eab46-2f62-483f-bc0d-651bae0e0658
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359532775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.359532775
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.4146787093
Short name T1
Test name
Test status
Simulation time 45879200 ps
CPU time 13.69 seconds
Started Jun 04 02:54:04 PM PDT 24
Finished Jun 04 02:54:18 PM PDT 24
Peak memory 264764 kb
Host smart-1025b534-75f1-4aed-9415-c1d5941f08b8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146787093 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.4146787093
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.4035879041
Short name T534
Test name
Test status
Simulation time 3656699200 ps
CPU time 139.82 seconds
Started Jun 04 02:53:53 PM PDT 24
Finished Jun 04 02:56:13 PM PDT 24
Peak memory 262456 kb
Host smart-933ab9d8-af08-4c4a-80b5-1bcb2787abe7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035879041 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.4035879041
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.1165298422
Short name T371
Test name
Test status
Simulation time 77035900 ps
CPU time 110.52 seconds
Started Jun 04 02:53:54 PM PDT 24
Finished Jun 04 02:55:45 PM PDT 24
Peak memory 259552 kb
Host smart-029c8bbe-1d1c-4688-baaf-1e05b5baacc5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165298422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.1165298422
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.2490902901
Short name T218
Test name
Test status
Simulation time 1445294500 ps
CPU time 565.65 seconds
Started Jun 04 02:53:44 PM PDT 24
Finished Jun 04 03:03:10 PM PDT 24
Peak memory 262268 kb
Host smart-4a5a6963-e8b2-46e2-87c2-c061a4ebbba7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490902901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.2490902901
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.1907870757
Short name T941
Test name
Test status
Simulation time 12115312900 ps
CPU time 264.98 seconds
Started Jun 04 02:53:54 PM PDT 24
Finished Jun 04 02:58:19 PM PDT 24
Peak memory 259492 kb
Host smart-317af806-bdf3-4bfb-b7d8-57398d7b0579
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907870757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.1907870757
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.1545765321
Short name T918
Test name
Test status
Simulation time 2084463200 ps
CPU time 1253.4 seconds
Started Jun 04 02:53:44 PM PDT 24
Finished Jun 04 03:14:39 PM PDT 24
Peak memory 287120 kb
Host smart-117d1977-8e37-4e4a-8792-8a5e0e622885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545765321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1545765321
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.3204714782
Short name T30
Test name
Test status
Simulation time 79497800 ps
CPU time 34.87 seconds
Started Jun 04 02:54:05 PM PDT 24
Finished Jun 04 02:54:41 PM PDT 24
Peak memory 266972 kb
Host smart-40313e84-366d-4a3c-8a18-8f6b1f962d5c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204714782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.3204714782
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.1310278265
Short name T1028
Test name
Test status
Simulation time 3342896000 ps
CPU time 118.71 seconds
Started Jun 04 02:53:53 PM PDT 24
Finished Jun 04 02:55:52 PM PDT 24
Peak memory 296848 kb
Host smart-f00d47ee-3d5e-42bd-ac5a-38495a4761be
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310278265 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.1310278265
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.2360790718
Short name T43
Test name
Test status
Simulation time 68301000 ps
CPU time 30.98 seconds
Started Jun 04 02:53:53 PM PDT 24
Finished Jun 04 02:54:25 PM PDT 24
Peak memory 275136 kb
Host smart-5a343514-6a31-4942-8b28-2f904e947476
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360790718 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.2360790718
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.3107085742
Short name T1006
Test name
Test status
Simulation time 2178473200 ps
CPU time 65.43 seconds
Started Jun 04 02:54:06 PM PDT 24
Finished Jun 04 02:55:12 PM PDT 24
Peak memory 264312 kb
Host smart-75ea2b6a-0bea-41e2-a31c-3f894646b94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107085742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.3107085742
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.1353750987
Short name T945
Test name
Test status
Simulation time 93847900 ps
CPU time 195.13 seconds
Started Jun 04 02:53:46 PM PDT 24
Finished Jun 04 02:57:02 PM PDT 24
Peak memory 279268 kb
Host smart-57347a2b-f9f5-4601-bfca-a754eb89c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353750987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.1353750987
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.1700862585
Short name T593
Test name
Test status
Simulation time 5322910200 ps
CPU time 191.11 seconds
Started Jun 04 02:53:54 PM PDT 24
Finished Jun 04 02:57:06 PM PDT 24
Peak memory 258888 kb
Host smart-6c294d6d-3732-46e1-9a72-a18638ee5e32
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700862585 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.1700862585
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.3596586125
Short name T671
Test name
Test status
Simulation time 36469300 ps
CPU time 13.38 seconds
Started Jun 04 02:54:45 PM PDT 24
Finished Jun 04 02:54:59 PM PDT 24
Peak memory 264940 kb
Host smart-35c38faa-8e23-4108-9938-9661e8fe6320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596586125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
3596586125
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.3502664303
Short name T1042
Test name
Test status
Simulation time 17739600 ps
CPU time 15.66 seconds
Started Jun 04 02:54:24 PM PDT 24
Finished Jun 04 02:54:41 PM PDT 24
Peak memory 274788 kb
Host smart-3c4918b1-66db-41ae-afad-6d70f12a5387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502664303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.3502664303
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.1011277177
Short name T373
Test name
Test status
Simulation time 39405100 ps
CPU time 21.95 seconds
Started Jun 04 02:54:25 PM PDT 24
Finished Jun 04 02:54:48 PM PDT 24
Peak memory 273212 kb
Host smart-fcc22c12-4386-4981-9739-5ca5027c83df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011277177 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.1011277177
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.2431235456
Short name T162
Test name
Test status
Simulation time 10019663000 ps
CPU time 89.93 seconds
Started Jun 04 02:54:24 PM PDT 24
Finished Jun 04 02:55:55 PM PDT 24
Peak memory 322644 kb
Host smart-09ed0181-84aa-4f61-b307-f2f42de196f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431235456 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.2431235456
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.2416266750
Short name T183
Test name
Test status
Simulation time 15497300 ps
CPU time 13.29 seconds
Started Jun 04 02:54:25 PM PDT 24
Finished Jun 04 02:54:39 PM PDT 24
Peak memory 258880 kb
Host smart-f609c8e0-f056-4b12-8a20-011d9cf86e24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416266750 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.2416266750
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.2638291936
Short name T718
Test name
Test status
Simulation time 612924300 ps
CPU time 59.2 seconds
Started Jun 04 02:54:19 PM PDT 24
Finished Jun 04 02:55:18 PM PDT 24
Peak memory 262432 kb
Host smart-128c348a-1027-4fa0-9ad8-518962c617ae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638291936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.2638291936
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.3690183392
Short name T1027
Test name
Test status
Simulation time 5468559100 ps
CPU time 201.76 seconds
Started Jun 04 02:54:25 PM PDT 24
Finished Jun 04 02:57:48 PM PDT 24
Peak memory 283544 kb
Host smart-fbbe1698-2f53-4525-88d4-3fad1501dd08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690183392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.3690183392
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.1996490592
Short name T489
Test name
Test status
Simulation time 18006387900 ps
CPU time 262.53 seconds
Started Jun 04 02:54:23 PM PDT 24
Finished Jun 04 02:58:47 PM PDT 24
Peak memory 283876 kb
Host smart-cf753f17-0660-476d-9121-e49626b8ea0d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996490592 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.1996490592
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.1193703526
Short name T442
Test name
Test status
Simulation time 6763002300 ps
CPU time 65.64 seconds
Started Jun 04 02:54:16 PM PDT 24
Finished Jun 04 02:55:22 PM PDT 24
Peak memory 260296 kb
Host smart-58101e8b-6b10-4185-8613-0cf051faf62a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193703526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.1
193703526
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.1914640202
Short name T114
Test name
Test status
Simulation time 20056094900 ps
CPU time 333.1 seconds
Started Jun 04 02:54:19 PM PDT 24
Finished Jun 04 02:59:52 PM PDT 24
Peak memory 274592 kb
Host smart-a5eed15b-c303-4bcc-8cee-38e0814b6ba0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914640202 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.1914640202
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.1558279355
Short name T929
Test name
Test status
Simulation time 39354000 ps
CPU time 131.92 seconds
Started Jun 04 02:54:15 PM PDT 24
Finished Jun 04 02:56:28 PM PDT 24
Peak memory 259744 kb
Host smart-1debca11-9484-469f-8971-efb203628b12
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558279355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.1558279355
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.2415839390
Short name T219
Test name
Test status
Simulation time 735674600 ps
CPU time 341.95 seconds
Started Jun 04 02:54:16 PM PDT 24
Finished Jun 04 02:59:59 PM PDT 24
Peak memory 262160 kb
Host smart-a9056fb0-1458-4f44-9b48-e5f6afa19919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2415839390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.2415839390
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.2726256103
Short name T925
Test name
Test status
Simulation time 4854686300 ps
CPU time 203.69 seconds
Started Jun 04 02:54:24 PM PDT 24
Finished Jun 04 02:57:48 PM PDT 24
Peak memory 263952 kb
Host smart-3e15e10d-14de-498e-85ce-6d9c16b5434e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726256103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.2726256103
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.1897008476
Short name T90
Test name
Test status
Simulation time 1363829100 ps
CPU time 645.01 seconds
Started Jun 04 02:54:17 PM PDT 24
Finished Jun 04 03:05:03 PM PDT 24
Peak memory 284112 kb
Host smart-b75d3296-7733-4367-afb1-83a4de02bc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897008476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1897008476
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.1322119647
Short name T626
Test name
Test status
Simulation time 629257500 ps
CPU time 128.11 seconds
Started Jun 04 02:54:24 PM PDT 24
Finished Jun 04 02:56:33 PM PDT 24
Peak memory 296740 kb
Host smart-91e42078-91a0-4139-8ff3-917dfe0e94cb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322119647 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.flash_ctrl_ro.1322119647
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.3695472111
Short name T691
Test name
Test status
Simulation time 27129907800 ps
CPU time 547.91 seconds
Started Jun 04 02:54:24 PM PDT 24
Finished Jun 04 03:03:33 PM PDT 24
Peak memory 305356 kb
Host smart-563de3d5-5212-4640-b212-52e419017d87
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695472111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.3695472111
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.4252323910
Short name T969
Test name
Test status
Simulation time 33763300 ps
CPU time 28.67 seconds
Started Jun 04 02:54:25 PM PDT 24
Finished Jun 04 02:54:54 PM PDT 24
Peak memory 273172 kb
Host smart-7ab7bdae-ca05-41f3-a54e-bece1e2999a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252323910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.4252323910
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.234237575
Short name T906
Test name
Test status
Simulation time 38879500 ps
CPU time 30.41 seconds
Started Jun 04 02:54:23 PM PDT 24
Finished Jun 04 02:54:54 PM PDT 24
Peak memory 274448 kb
Host smart-fe1a3fbb-6067-4a99-bc9a-65c881c516a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234237575 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.234237575
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.2688044053
Short name T688
Test name
Test status
Simulation time 20033100100 ps
CPU time 95.41 seconds
Started Jun 04 02:54:23 PM PDT 24
Finished Jun 04 02:55:59 PM PDT 24
Peak memory 262372 kb
Host smart-36163ecb-5052-462b-8fdc-08760051982a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688044053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.2688044053
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.1778278902
Short name T370
Test name
Test status
Simulation time 97497600 ps
CPU time 121.36 seconds
Started Jun 04 02:54:17 PM PDT 24
Finished Jun 04 02:56:19 PM PDT 24
Peak memory 275476 kb
Host smart-6e601dc2-edd1-4467-830d-a2e875771c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778278902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1778278902
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.1753699202
Short name T409
Test name
Test status
Simulation time 2032836400 ps
CPU time 150.76 seconds
Started Jun 04 02:54:15 PM PDT 24
Finished Jun 04 02:56:46 PM PDT 24
Peak memory 259320 kb
Host smart-b9de69ee-ade3-4a0b-b69d-35f79509cf26
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753699202 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.flash_ctrl_wo.1753699202
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.413908717
Short name T46
Test name
Test status
Simulation time 38837000 ps
CPU time 13.66 seconds
Started Jun 04 02:43:46 PM PDT 24
Finished Jun 04 02:44:00 PM PDT 24
Peak memory 260872 kb
Host smart-c9ac48bc-7b9f-42b1-9647-9d039082ec54
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413908717 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.413908717
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.1922754638
Short name T478
Test name
Test status
Simulation time 139118100 ps
CPU time 14.28 seconds
Started Jun 04 02:44:00 PM PDT 24
Finished Jun 04 02:44:15 PM PDT 24
Peak memory 264820 kb
Host smart-c1b3697a-8237-4a16-aa37-91eecdf7c2c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922754638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.1
922754638
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.3552776186
Short name T244
Test name
Test status
Simulation time 41161700 ps
CPU time 14.07 seconds
Started Jun 04 02:43:53 PM PDT 24
Finished Jun 04 02:44:07 PM PDT 24
Peak memory 264824 kb
Host smart-eea86909-72b1-4825-9e93-cc100acc1b69
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552776186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.3552776186
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.32161411
Short name T654
Test name
Test status
Simulation time 17041100 ps
CPU time 15.97 seconds
Started Jun 04 02:43:47 PM PDT 24
Finished Jun 04 02:44:03 PM PDT 24
Peak memory 274776 kb
Host smart-8c23c7bb-e93b-4ab9-b78e-c77f9a8870ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32161411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.32161411
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.912265197
Short name T830
Test name
Test status
Simulation time 329137400 ps
CPU time 105.2 seconds
Started Jun 04 02:43:32 PM PDT 24
Finished Jun 04 02:45:17 PM PDT 24
Peak memory 272448 kb
Host smart-f61bb356-51cb-456e-b29d-ed05a2115286
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912265197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_derr_detect.912265197
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.457095780
Short name T532
Test name
Test status
Simulation time 18015900 ps
CPU time 21.8 seconds
Started Jun 04 02:43:40 PM PDT 24
Finished Jun 04 02:44:02 PM PDT 24
Peak memory 273016 kb
Host smart-d9078908-dfda-4dfa-86e3-9c6d2287f257
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457095780 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.457095780
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.823046929
Short name T48
Test name
Test status
Simulation time 9505757600 ps
CPU time 616.19 seconds
Started Jun 04 02:42:57 PM PDT 24
Finished Jun 04 02:53:14 PM PDT 24
Peak memory 261076 kb
Host smart-c59c54c0-c3b1-4c7b-b1e8-797d44bae633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=823046929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.823046929
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.2972319845
Short name T291
Test name
Test status
Simulation time 6133190200 ps
CPU time 2426.68 seconds
Started Jun 04 02:43:16 PM PDT 24
Finished Jun 04 03:23:43 PM PDT 24
Peak memory 264664 kb
Host smart-282197ef-e436-4d22-bc52-22ed1ac9d1de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972319845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.2972319845
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.1163083469
Short name T773
Test name
Test status
Simulation time 505932200 ps
CPU time 2256.26 seconds
Started Jun 04 02:43:10 PM PDT 24
Finished Jun 04 03:20:47 PM PDT 24
Peak memory 264688 kb
Host smart-5b5ca488-78d1-4f02-a458-a970b27b588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163083469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.1163083469
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.3321246016
Short name T525
Test name
Test status
Simulation time 661859000 ps
CPU time 838.56 seconds
Started Jun 04 02:43:10 PM PDT 24
Finished Jun 04 02:57:09 PM PDT 24
Peak memory 264828 kb
Host smart-9520c696-3121-4496-baa9-9c4855d536dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321246016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.3321246016
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.2259166157
Short name T52
Test name
Test status
Simulation time 782365400 ps
CPU time 26.8 seconds
Started Jun 04 02:43:03 PM PDT 24
Finished Jun 04 02:43:30 PM PDT 24
Peak memory 264880 kb
Host smart-75591867-3931-4622-9ba7-90f81a76745c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259166157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.2259166157
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.534388149
Short name T879
Test name
Test status
Simulation time 1216245400 ps
CPU time 42.18 seconds
Started Jun 04 02:43:44 PM PDT 24
Finished Jun 04 02:44:26 PM PDT 24
Peak memory 264824 kb
Host smart-4b9c55be-6978-4957-9c60-990c3670e6f1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534388149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_fs_sup.534388149
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.1316457830
Short name T203
Test name
Test status
Simulation time 81366020700 ps
CPU time 2828.51 seconds
Started Jun 04 02:43:02 PM PDT 24
Finished Jun 04 03:30:11 PM PDT 24
Peak memory 262860 kb
Host smart-73c77e92-3263-48e7-9eef-77e6082ea8c4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316457830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.1316457830
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.820864744
Short name T275
Test name
Test status
Simulation time 143825500 ps
CPU time 61.38 seconds
Started Jun 04 02:42:55 PM PDT 24
Finished Jun 04 02:43:57 PM PDT 24
Peak memory 262332 kb
Host smart-10e994fc-1a9c-490c-b7d8-b9807a56fb0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820864744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.820864744
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.385820012
Short name T937
Test name
Test status
Simulation time 10075574300 ps
CPU time 57.64 seconds
Started Jun 04 02:44:00 PM PDT 24
Finished Jun 04 02:44:58 PM PDT 24
Peak memory 264932 kb
Host smart-2eca2318-4529-4985-a903-514ea858f0c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385820012 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.385820012
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.3854202270
Short name T464
Test name
Test status
Simulation time 23693600 ps
CPU time 13.77 seconds
Started Jun 04 02:43:59 PM PDT 24
Finished Jun 04 02:44:14 PM PDT 24
Peak memory 258836 kb
Host smart-7ef4f5d3-e6e2-4ba8-98f4-c792604dcc68
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854202270 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.3854202270
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.1854342893
Short name T139
Test name
Test status
Simulation time 83711445800 ps
CPU time 1838.28 seconds
Started Jun 04 02:42:57 PM PDT 24
Finished Jun 04 03:13:36 PM PDT 24
Peak memory 263664 kb
Host smart-2fceb8c1-6d12-45a7-b3de-0c99ee4a7fa6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854342893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.1854342893
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.3795842255
Short name T804
Test name
Test status
Simulation time 40123793000 ps
CPU time 789.09 seconds
Started Jun 04 02:42:56 PM PDT 24
Finished Jun 04 02:56:06 PM PDT 24
Peak memory 264296 kb
Host smart-5b9774fc-4f1d-4dbb-a28b-926594e703c6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795842255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.3795842255
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.3279897998
Short name T236
Test name
Test status
Simulation time 3785753500 ps
CPU time 665.54 seconds
Started Jun 04 02:43:32 PM PDT 24
Finished Jun 04 02:54:38 PM PDT 24
Peak memory 327604 kb
Host smart-768f2d74-158c-489d-8a4c-7f3f23289a1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279897998 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.3279897998
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.3320257466
Short name T896
Test name
Test status
Simulation time 970789200 ps
CPU time 171.86 seconds
Started Jun 04 02:43:32 PM PDT 24
Finished Jun 04 02:46:24 PM PDT 24
Peak memory 292552 kb
Host smart-bb517921-a7d5-41b5-b41f-357b67c5f5fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320257466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.3320257466
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.1121916807
Short name T443
Test name
Test status
Simulation time 2096846800 ps
CPU time 76.81 seconds
Started Jun 04 02:43:31 PM PDT 24
Finished Jun 04 02:44:48 PM PDT 24
Peak memory 259464 kb
Host smart-fcb29698-55a4-4a6f-9e58-274fb5ea73a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121916807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.1121916807
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.464711602
Short name T1088
Test name
Test status
Simulation time 16228570400 ps
CPU time 141.88 seconds
Started Jun 04 02:43:38 PM PDT 24
Finished Jun 04 02:46:01 PM PDT 24
Peak memory 264832 kb
Host smart-8edf5fb1-25f1-4c31-a12c-bc67efd61e7f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464
711602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.464711602
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.3319638026
Short name T483
Test name
Test status
Simulation time 8907742300 ps
CPU time 94.08 seconds
Started Jun 04 02:43:16 PM PDT 24
Finished Jun 04 02:44:51 PM PDT 24
Peak memory 260340 kb
Host smart-b799649c-8acc-4a6f-9cef-30876401d81c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319638026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3319638026
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.1800971845
Short name T500
Test name
Test status
Simulation time 26031500 ps
CPU time 13.74 seconds
Started Jun 04 02:44:00 PM PDT 24
Finished Jun 04 02:44:15 PM PDT 24
Peak memory 264776 kb
Host smart-7b494fd0-e639-48e2-9eea-e3d1b5d72c41
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800971845 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.1800971845
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.4211323334
Short name T778
Test name
Test status
Simulation time 4202385000 ps
CPU time 173.51 seconds
Started Jun 04 02:43:01 PM PDT 24
Finished Jun 04 02:45:55 PM PDT 24
Peak memory 262668 kb
Host smart-aea4973e-a803-4aa2-8c20-48bef4ce673f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211323334 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.4211323334
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.1668037798
Short name T911
Test name
Test status
Simulation time 150358800 ps
CPU time 129.61 seconds
Started Jun 04 02:42:55 PM PDT 24
Finished Jun 04 02:45:05 PM PDT 24
Peak memory 263816 kb
Host smart-10f4eb1d-791d-463a-9dd8-bdc74bb06626
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668037798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.1668037798
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.463840294
Short name T45
Test name
Test status
Simulation time 78632800 ps
CPU time 330.11 seconds
Started Jun 04 02:42:54 PM PDT 24
Finished Jun 04 02:48:24 PM PDT 24
Peak memory 262236 kb
Host smart-6e6d6fa2-977a-4f66-b3ad-4c38f0f8b274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=463840294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.463840294
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.4034178061
Short name T704
Test name
Test status
Simulation time 95408100 ps
CPU time 13.56 seconds
Started Jun 04 02:43:38 PM PDT 24
Finished Jun 04 02:43:52 PM PDT 24
Peak memory 258420 kb
Host smart-008f7941-a428-48be-b138-8f5ce48db910
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034178061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.4034178061
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.1646190855
Short name T871
Test name
Test status
Simulation time 179319300 ps
CPU time 679.5 seconds
Started Jun 04 02:42:50 PM PDT 24
Finished Jun 04 02:54:10 PM PDT 24
Peak memory 284836 kb
Host smart-319fd3fd-a007-46ba-8bb1-6bf5c52a6422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646190855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1646190855
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.2642230829
Short name T1079
Test name
Test status
Simulation time 1440246700 ps
CPU time 141.93 seconds
Started Jun 04 02:42:54 PM PDT 24
Finished Jun 04 02:45:17 PM PDT 24
Peak memory 264984 kb
Host smart-f15f5e12-7a89-4f7d-94a9-52b55c6e0066
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2642230829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.2642230829
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.3619311523
Short name T273
Test name
Test status
Simulation time 116474700 ps
CPU time 31.49 seconds
Started Jun 04 02:43:44 PM PDT 24
Finished Jun 04 02:44:16 PM PDT 24
Peak memory 279364 kb
Host smart-548f9821-f493-419f-8cc1-4cbb8dcbe9b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619311523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.3619311523
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.2173546542
Short name T639
Test name
Test status
Simulation time 836815300 ps
CPU time 36.11 seconds
Started Jun 04 02:43:38 PM PDT 24
Finished Jun 04 02:44:15 PM PDT 24
Peak memory 273052 kb
Host smart-14bbc721-0735-4808-89e2-0021d04ea90f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173546542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.2173546542
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.2445023257
Short name T530
Test name
Test status
Simulation time 28927600 ps
CPU time 22.51 seconds
Started Jun 04 02:43:31 PM PDT 24
Finished Jun 04 02:43:55 PM PDT 24
Peak memory 264884 kb
Host smart-3623c98b-8e98-4161-a582-449e5f754fd7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445023257 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.2445023257
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.1107667216
Short name T986
Test name
Test status
Simulation time 30671700 ps
CPU time 22.25 seconds
Started Jun 04 02:43:24 PM PDT 24
Finished Jun 04 02:43:46 PM PDT 24
Peak memory 264764 kb
Host smart-038601b9-9b37-4632-ba46-fbd3dc2d3bd8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107667216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.1107667216
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.115930997
Short name T153
Test name
Test status
Simulation time 303040612400 ps
CPU time 1054.51 seconds
Started Jun 04 02:43:52 PM PDT 24
Finished Jun 04 03:01:27 PM PDT 24
Peak memory 259080 kb
Host smart-e7a4a45f-b06e-40f4-9839-92877128eee2
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115930997 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.115930997
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.1377524444
Short name T195
Test name
Test status
Simulation time 1116558900 ps
CPU time 125.13 seconds
Started Jun 04 02:43:16 PM PDT 24
Finished Jun 04 02:45:22 PM PDT 24
Peak memory 290740 kb
Host smart-1105388e-9acc-42cb-86ac-efa416c94836
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377524444 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_ro.1377524444
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.3258549163
Short name T981
Test name
Test status
Simulation time 2570212900 ps
CPU time 170.27 seconds
Started Jun 04 02:43:30 PM PDT 24
Finished Jun 04 02:46:21 PM PDT 24
Peak memory 281232 kb
Host smart-a7312199-f950-4dd4-92bb-e66c2e93b856
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3258549163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.3258549163
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.92874961
Short name T618
Test name
Test status
Simulation time 1499983300 ps
CPU time 125.3 seconds
Started Jun 04 02:43:21 PM PDT 24
Finished Jun 04 02:45:27 PM PDT 24
Peak memory 289432 kb
Host smart-ef6a943f-287b-43ea-85f2-2692aefc3628
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92874961 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.92874961
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.877807554
Short name T199
Test name
Test status
Simulation time 6712364000 ps
CPU time 634.45 seconds
Started Jun 04 02:43:25 PM PDT 24
Finished Jun 04 02:54:00 PM PDT 24
Peak memory 309148 kb
Host smart-79c65dd6-ce7b-4128-982d-a9600bd4834d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877807554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.flash_ctrl_rw.877807554
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.312354099
Short name T57
Test name
Test status
Simulation time 2988589500 ps
CPU time 619.22 seconds
Started Jun 04 02:43:32 PM PDT 24
Finished Jun 04 02:53:52 PM PDT 24
Peak memory 323104 kb
Host smart-bc3ad13e-1ee5-45f6-a961-44f8ae166860
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312354099 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.flash_ctrl_rw_derr.312354099
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.1426476953
Short name T403
Test name
Test status
Simulation time 3509991500 ps
CPU time 707.05 seconds
Started Jun 04 02:43:25 PM PDT 24
Finished Jun 04 02:55:13 PM PDT 24
Peak memory 311572 kb
Host smart-a31b6547-2e1b-4a99-a425-17921f24f9c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426476953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s
err.1426476953
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.1710444219
Short name T15
Test name
Test status
Simulation time 3813393700 ps
CPU time 4935.28 seconds
Started Jun 04 02:43:38 PM PDT 24
Finished Jun 04 04:05:54 PM PDT 24
Peak memory 283424 kb
Host smart-87a31b34-2981-4a42-aaf2-6fd75d77f65c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710444219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.1710444219
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.1915039527
Short name T501
Test name
Test status
Simulation time 2043204200 ps
CPU time 61.3 seconds
Started Jun 04 02:43:31 PM PDT 24
Finished Jun 04 02:44:33 PM PDT 24
Peak memory 273044 kb
Host smart-2deaa49e-2ff5-4aef-8c56-c79b0bb89ff9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915039527 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.1915039527
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.2730995334
Short name T465
Test name
Test status
Simulation time 1382248800 ps
CPU time 78.58 seconds
Started Jun 04 02:43:25 PM PDT 24
Finished Jun 04 02:44:44 PM PDT 24
Peak memory 273160 kb
Host smart-eea89dd7-fc5c-469b-ba0b-39a5c36e612d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730995334 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.2730995334
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.4202554363
Short name T706
Test name
Test status
Simulation time 63245000 ps
CPU time 77.49 seconds
Started Jun 04 02:42:48 PM PDT 24
Finished Jun 04 02:44:06 PM PDT 24
Peak memory 275796 kb
Host smart-ec50319b-e1d7-47d8-942a-b5506ca4160d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202554363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.4202554363
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.445173665
Short name T959
Test name
Test status
Simulation time 30029300 ps
CPU time 25.78 seconds
Started Jun 04 02:42:49 PM PDT 24
Finished Jun 04 02:43:15 PM PDT 24
Peak memory 258900 kb
Host smart-41e37e3c-0e4b-4121-bfca-3394fc285178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445173665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.445173665
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.2989278915
Short name T1074
Test name
Test status
Simulation time 610891200 ps
CPU time 1296.29 seconds
Started Jun 04 02:43:39 PM PDT 24
Finished Jun 04 03:05:16 PM PDT 24
Peak memory 289580 kb
Host smart-0e42954a-fb91-4b27-9d76-43d4f0004042
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989278915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.2989278915
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.3793664503
Short name T840
Test name
Test status
Simulation time 20281900 ps
CPU time 27.23 seconds
Started Jun 04 02:42:49 PM PDT 24
Finished Jun 04 02:43:17 PM PDT 24
Peak memory 261376 kb
Host smart-a19c98be-7979-4d53-990a-f29af2b041f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793664503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.3793664503
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.2121891883
Short name T414
Test name
Test status
Simulation time 5087289400 ps
CPU time 246.97 seconds
Started Jun 04 02:43:16 PM PDT 24
Finished Jun 04 02:47:24 PM PDT 24
Peak memory 264796 kb
Host smart-1d2b2823-f1c5-4cf9-b498-98f5b8b3652e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121891883 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_wo.2121891883
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.2561595615
Short name T700
Test name
Test status
Simulation time 32808300 ps
CPU time 13.84 seconds
Started Jun 04 02:54:41 PM PDT 24
Finished Jun 04 02:54:56 PM PDT 24
Peak memory 264164 kb
Host smart-9d6e9efd-97e5-4f04-a2bd-cebcb462948c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561595615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
2561595615
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.2937070335
Short name T747
Test name
Test status
Simulation time 49589000 ps
CPU time 16.43 seconds
Started Jun 04 02:54:41 PM PDT 24
Finished Jun 04 02:54:58 PM PDT 24
Peak memory 275560 kb
Host smart-ae6a52d6-8e03-4e4d-ac9d-bba65057607a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937070335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.2937070335
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.1929633745
Short name T714
Test name
Test status
Simulation time 25614800 ps
CPU time 22 seconds
Started Jun 04 02:54:35 PM PDT 24
Finished Jun 04 02:54:58 PM PDT 24
Peak memory 264932 kb
Host smart-a4ed20f9-53a1-4bc2-976f-b8a8be195166
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929633745 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.1929633745
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.672808224
Short name T574
Test name
Test status
Simulation time 2746465500 ps
CPU time 179.03 seconds
Started Jun 04 02:54:34 PM PDT 24
Finished Jun 04 02:57:34 PM PDT 24
Peak memory 261728 kb
Host smart-71c8fc2f-dcf8-4798-9b55-fb5ec3474450
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672808224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_h
w_sec_otp.672808224
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.2683723950
Short name T710
Test name
Test status
Simulation time 675888600 ps
CPU time 135.21 seconds
Started Jun 04 02:54:35 PM PDT 24
Finished Jun 04 02:56:51 PM PDT 24
Peak memory 292816 kb
Host smart-6245c02c-aae9-4c62-bb75-e727ed80de29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683723950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.2683723950
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.2481530475
Short name T757
Test name
Test status
Simulation time 12604924600 ps
CPU time 252.12 seconds
Started Jun 04 02:54:32 PM PDT 24
Finished Jun 04 02:58:44 PM PDT 24
Peak memory 283872 kb
Host smart-f7484152-e7e1-4392-85d1-18f39b9f8a18
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481530475 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.2481530475
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.710896642
Short name T624
Test name
Test status
Simulation time 37811000 ps
CPU time 130.88 seconds
Started Jun 04 02:54:32 PM PDT 24
Finished Jun 04 02:56:43 PM PDT 24
Peak memory 259804 kb
Host smart-b5fd3f96-de95-42bd-adde-130fb2a1762c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710896642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_ot
p_reset.710896642
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.508434210
Short name T648
Test name
Test status
Simulation time 34638700 ps
CPU time 13.56 seconds
Started Jun 04 02:54:31 PM PDT 24
Finished Jun 04 02:54:45 PM PDT 24
Peak memory 258428 kb
Host smart-b2497bcd-7f51-46dd-a430-2dda0dde3fdf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508434210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_res
et.508434210
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.2378446549
Short name T739
Test name
Test status
Simulation time 47198600 ps
CPU time 29.02 seconds
Started Jun 04 02:54:32 PM PDT 24
Finished Jun 04 02:55:01 PM PDT 24
Peak memory 274100 kb
Host smart-34485ebe-1c1d-4915-82bd-ea72426ad700
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378446549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl
ash_ctrl_rw_evict.2378446549
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.2738796239
Short name T332
Test name
Test status
Simulation time 73970100 ps
CPU time 27.89 seconds
Started Jun 04 02:54:32 PM PDT 24
Finished Jun 04 02:55:01 PM PDT 24
Peak memory 274448 kb
Host smart-c56bdc58-80e3-4906-8769-2deba8e4fc10
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738796239 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.2738796239
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.1178370245
Short name T876
Test name
Test status
Simulation time 7233561200 ps
CPU time 66.5 seconds
Started Jun 04 02:54:43 PM PDT 24
Finished Jun 04 02:55:50 PM PDT 24
Peak memory 263108 kb
Host smart-e3cdd6d8-9d38-4fc0-a81d-84f15957c123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178370245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.1178370245
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.2034157403
Short name T756
Test name
Test status
Simulation time 40922800 ps
CPU time 170.45 seconds
Started Jun 04 02:54:31 PM PDT 24
Finished Jun 04 02:57:22 PM PDT 24
Peak memory 276584 kb
Host smart-7d532d83-a731-42f2-b09a-83ccd63dacc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034157403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2034157403
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.3472690289
Short name T763
Test name
Test status
Simulation time 64043000 ps
CPU time 13.56 seconds
Started Jun 04 02:54:52 PM PDT 24
Finished Jun 04 02:55:06 PM PDT 24
Peak memory 264764 kb
Host smart-29805271-11e0-4517-86cb-a87617f6c0f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472690289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
3472690289
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.983542916
Short name T411
Test name
Test status
Simulation time 30352600 ps
CPU time 15.85 seconds
Started Jun 04 02:54:51 PM PDT 24
Finished Jun 04 02:55:07 PM PDT 24
Peak memory 275796 kb
Host smart-69257a73-25f7-45e7-85ae-78b25cc130fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983542916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.983542916
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.889970759
Short name T116
Test name
Test status
Simulation time 12973800 ps
CPU time 22.33 seconds
Started Jun 04 02:54:51 PM PDT 24
Finished Jun 04 02:55:14 PM PDT 24
Peak memory 273100 kb
Host smart-bb90f588-2df0-4713-9d1c-499292abfee2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889970759 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.889970759
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.781864659
Short name T584
Test name
Test status
Simulation time 4363857400 ps
CPU time 199.46 seconds
Started Jun 04 02:54:44 PM PDT 24
Finished Jun 04 02:58:04 PM PDT 24
Peak memory 262372 kb
Host smart-7f5d0d84-d372-44a4-be1c-d49699e54fdc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781864659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_h
w_sec_otp.781864659
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.2934698502
Short name T697
Test name
Test status
Simulation time 6983073700 ps
CPU time 220.62 seconds
Started Jun 04 02:54:43 PM PDT 24
Finished Jun 04 02:58:24 PM PDT 24
Peak memory 289472 kb
Host smart-09b63858-9ec9-41be-b516-8f2d32e79b92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934698502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.2934698502
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.1366257220
Short name T853
Test name
Test status
Simulation time 11635288000 ps
CPU time 153.64 seconds
Started Jun 04 02:54:42 PM PDT 24
Finished Jun 04 02:57:16 PM PDT 24
Peak memory 292572 kb
Host smart-250a3bed-97e2-4c18-bfb3-d300925aa313
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366257220 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.1366257220
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.776783579
Short name T372
Test name
Test status
Simulation time 40301600 ps
CPU time 133.43 seconds
Started Jun 04 02:54:43 PM PDT 24
Finished Jun 04 02:56:57 PM PDT 24
Peak memory 264272 kb
Host smart-b71e76de-ef7d-4442-a48f-9ed8302b982d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776783579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ot
p_reset.776783579
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.3588037938
Short name T448
Test name
Test status
Simulation time 58242000 ps
CPU time 13.71 seconds
Started Jun 04 02:54:43 PM PDT 24
Finished Jun 04 02:54:57 PM PDT 24
Peak memory 258328 kb
Host smart-95431746-4891-49f5-8acb-40c25c5070fe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588037938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_re
set.3588037938
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.334956172
Short name T1024
Test name
Test status
Simulation time 90546500 ps
CPU time 32.03 seconds
Started Jun 04 02:54:41 PM PDT 24
Finished Jun 04 02:55:14 PM PDT 24
Peak memory 273032 kb
Host smart-14fa9b2d-daea-4097-8eca-49074379132a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334956172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_rw_evict.334956172
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.2129504054
Short name T380
Test name
Test status
Simulation time 1742612400 ps
CPU time 65.63 seconds
Started Jun 04 02:54:50 PM PDT 24
Finished Jun 04 02:55:56 PM PDT 24
Peak memory 262848 kb
Host smart-0f3fc1ca-6de5-4006-9e0a-dd674018cf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129504054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.2129504054
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.1336902429
Short name T685
Test name
Test status
Simulation time 27635200 ps
CPU time 74.44 seconds
Started Jun 04 02:54:40 PM PDT 24
Finished Jun 04 02:55:55 PM PDT 24
Peak memory 275828 kb
Host smart-affc2753-fdd2-4497-933b-123b544ceb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336902429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.1336902429
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.1867740712
Short name T433
Test name
Test status
Simulation time 40089300 ps
CPU time 13.51 seconds
Started Jun 04 02:55:00 PM PDT 24
Finished Jun 04 02:55:14 PM PDT 24
Peak memory 257860 kb
Host smart-02215912-b856-41da-9044-8ff87f52e481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867740712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
1867740712
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.800670417
Short name T962
Test name
Test status
Simulation time 17019900 ps
CPU time 13.21 seconds
Started Jun 04 02:55:01 PM PDT 24
Finished Jun 04 02:55:14 PM PDT 24
Peak memory 275624 kb
Host smart-5319bd0a-1509-4791-bf5e-00241d5eb653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800670417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.800670417
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.2407285793
Short name T361
Test name
Test status
Simulation time 15073000 ps
CPU time 22.15 seconds
Started Jun 04 02:54:58 PM PDT 24
Finished Jun 04 02:55:20 PM PDT 24
Peak memory 273152 kb
Host smart-22be779f-b2a3-4f72-bfb6-d8b83afa0c29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407285793 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.2407285793
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.3181287258
Short name T276
Test name
Test status
Simulation time 3567868300 ps
CPU time 208.63 seconds
Started Jun 04 02:54:57 PM PDT 24
Finished Jun 04 02:58:26 PM PDT 24
Peak memory 289468 kb
Host smart-ba657c10-f377-47c0-9875-05b09c7e2430
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181287258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.3181287258
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.612851136
Short name T420
Test name
Test status
Simulation time 24020090800 ps
CPU time 144.97 seconds
Started Jun 04 02:55:00 PM PDT 24
Finished Jun 04 02:57:26 PM PDT 24
Peak memory 291572 kb
Host smart-b5106a86-5f54-4cb7-bf0c-7399f27a5929
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612851136 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.612851136
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.1351714189
Short name T693
Test name
Test status
Simulation time 45771300 ps
CPU time 129.59 seconds
Started Jun 04 02:55:02 PM PDT 24
Finished Jun 04 02:57:12 PM PDT 24
Peak memory 260948 kb
Host smart-e73afbae-5dea-4b9c-b2d5-a49cb72a409b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351714189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.1351714189
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.523714285
Short name T455
Test name
Test status
Simulation time 30800100 ps
CPU time 13.44 seconds
Started Jun 04 02:54:56 PM PDT 24
Finished Jun 04 02:55:10 PM PDT 24
Peak memory 258488 kb
Host smart-7791a18d-b546-49c9-b5ce-daa6c687da83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523714285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_res
et.523714285
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.2344615253
Short name T336
Test name
Test status
Simulation time 44731200 ps
CPU time 31.38 seconds
Started Jun 04 02:55:01 PM PDT 24
Finished Jun 04 02:55:33 PM PDT 24
Peak memory 274468 kb
Host smart-b811da72-db36-4648-8e73-583c09598495
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344615253 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.2344615253
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.799643726
Short name T997
Test name
Test status
Simulation time 3930903500 ps
CPU time 77.51 seconds
Started Jun 04 02:55:00 PM PDT 24
Finished Jun 04 02:56:18 PM PDT 24
Peak memory 263260 kb
Host smart-53095a6c-b4b2-4a68-82c3-573878490efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799643726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.799643726
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.3899584474
Short name T518
Test name
Test status
Simulation time 226918900 ps
CPU time 147.71 seconds
Started Jun 04 02:54:51 PM PDT 24
Finished Jun 04 02:57:19 PM PDT 24
Peak memory 276092 kb
Host smart-43af4eb3-d736-460b-ba99-a85183786f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899584474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.3899584474
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.395502185
Short name T859
Test name
Test status
Simulation time 82249500 ps
CPU time 13.93 seconds
Started Jun 04 02:55:17 PM PDT 24
Finished Jun 04 02:55:32 PM PDT 24
Peak memory 257884 kb
Host smart-1e85be70-e0bd-47c3-a949-47894a01479e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395502185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.395502185
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.2089669500
Short name T1016
Test name
Test status
Simulation time 23145200 ps
CPU time 15.6 seconds
Started Jun 04 02:55:10 PM PDT 24
Finished Jun 04 02:55:26 PM PDT 24
Peak memory 275472 kb
Host smart-eea9cd09-8f4d-44bb-aedd-c0a1f023f922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089669500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.2089669500
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.1177028079
Short name T943
Test name
Test status
Simulation time 29684800 ps
CPU time 20.3 seconds
Started Jun 04 02:55:08 PM PDT 24
Finished Jun 04 02:55:29 PM PDT 24
Peak memory 264940 kb
Host smart-14e036ed-6c19-41a5-8025-e64023dc923b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177028079 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.1177028079
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.3622304360
Short name T454
Test name
Test status
Simulation time 11611882300 ps
CPU time 99.74 seconds
Started Jun 04 02:55:08 PM PDT 24
Finished Jun 04 02:56:48 PM PDT 24
Peak memory 262424 kb
Host smart-de57cb38-15c5-4a10-b7b0-5da24b953a88
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622304360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.3622304360
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.3182063766
Short name T398
Test name
Test status
Simulation time 6968685900 ps
CPU time 213.58 seconds
Started Jun 04 02:55:10 PM PDT 24
Finished Jun 04 02:58:44 PM PDT 24
Peak memory 290500 kb
Host smart-50bb522d-c3d8-4119-8af6-1f777bf6929c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182063766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.3182063766
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.3059652837
Short name T835
Test name
Test status
Simulation time 56523982300 ps
CPU time 328.2 seconds
Started Jun 04 02:55:07 PM PDT 24
Finished Jun 04 03:00:35 PM PDT 24
Peak memory 292552 kb
Host smart-f52376e7-1e18-43ec-a313-53f35513df4d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059652837 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.3059652837
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.3970727259
Short name T136
Test name
Test status
Simulation time 73992900 ps
CPU time 133.75 seconds
Started Jun 04 02:55:10 PM PDT 24
Finished Jun 04 02:57:24 PM PDT 24
Peak memory 262164 kb
Host smart-f8014387-b0f8-4826-916a-c40f73b44d45
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970727259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.3970727259
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.2470191114
Short name T1051
Test name
Test status
Simulation time 4102004100 ps
CPU time 223.48 seconds
Started Jun 04 02:55:10 PM PDT 24
Finished Jun 04 02:58:54 PM PDT 24
Peak memory 264816 kb
Host smart-4583c5c6-b319-4139-981f-f8c1aacbc497
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470191114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.2470191114
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.1121471189
Short name T836
Test name
Test status
Simulation time 100335900 ps
CPU time 28.77 seconds
Started Jun 04 02:55:10 PM PDT 24
Finished Jun 04 02:55:40 PM PDT 24
Peak memory 274144 kb
Host smart-7a8e2b62-7c98-4e64-9895-e9f05300e603
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121471189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl
ash_ctrl_rw_evict.1121471189
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.3302124312
Short name T846
Test name
Test status
Simulation time 2586989100 ps
CPU time 69.91 seconds
Started Jun 04 02:55:10 PM PDT 24
Finished Jun 04 02:56:20 PM PDT 24
Peak memory 263200 kb
Host smart-560d10f0-8435-429d-be2e-46e0c6d379ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302124312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.3302124312
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.3912289841
Short name T717
Test name
Test status
Simulation time 89759500 ps
CPU time 99.39 seconds
Started Jun 04 02:55:08 PM PDT 24
Finished Jun 04 02:56:48 PM PDT 24
Peak memory 275112 kb
Host smart-cf7c90dc-09ed-4430-9588-f5796e59a2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912289841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.3912289841
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.653128666
Short name T928
Test name
Test status
Simulation time 111294800 ps
CPU time 14.43 seconds
Started Jun 04 02:55:27 PM PDT 24
Finished Jun 04 02:55:41 PM PDT 24
Peak memory 264776 kb
Host smart-0c2ef572-5bf7-428d-becb-af06c697c08a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653128666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.653128666
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.3694886050
Short name T767
Test name
Test status
Simulation time 22473700 ps
CPU time 13.41 seconds
Started Jun 04 02:55:21 PM PDT 24
Finished Jun 04 02:55:35 PM PDT 24
Peak memory 275520 kb
Host smart-7cb75592-b4aa-47ef-809c-cbb019b0294e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694886050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3694886050
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.3252667142
Short name T1015
Test name
Test status
Simulation time 10904800 ps
CPU time 21.69 seconds
Started Jun 04 02:55:17 PM PDT 24
Finished Jun 04 02:55:39 PM PDT 24
Peak memory 273172 kb
Host smart-a9f8f68a-5959-451a-b34d-7ebdb092da7d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252667142 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.3252667142
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.1485313432
Short name T869
Test name
Test status
Simulation time 5787693400 ps
CPU time 106.2 seconds
Started Jun 04 02:55:18 PM PDT 24
Finished Jun 04 02:57:05 PM PDT 24
Peak memory 262360 kb
Host smart-9de1355d-5092-4d1b-a94e-793f9cd96d02
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485313432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.1485313432
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.2773275493
Short name T348
Test name
Test status
Simulation time 2655372600 ps
CPU time 173.11 seconds
Started Jun 04 02:55:16 PM PDT 24
Finished Jun 04 02:58:10 PM PDT 24
Peak memory 292732 kb
Host smart-67df8a32-f0d7-4d78-b43c-5ce21b0ed3cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773275493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.2773275493
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3748659845
Short name T172
Test name
Test status
Simulation time 46145011800 ps
CPU time 251.04 seconds
Started Jun 04 02:55:20 PM PDT 24
Finished Jun 04 02:59:31 PM PDT 24
Peak memory 292128 kb
Host smart-04cae994-0ae0-4c13-b9f2-1bafab770032
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748659845 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.3748659845
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.166433064
Short name T960
Test name
Test status
Simulation time 35974200 ps
CPU time 109.6 seconds
Started Jun 04 02:55:18 PM PDT 24
Finished Jun 04 02:57:08 PM PDT 24
Peak memory 264108 kb
Host smart-8a125fbb-e9af-4e3a-a00e-427f65283b97
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166433064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ot
p_reset.166433064
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.4027010150
Short name T517
Test name
Test status
Simulation time 79279600 ps
CPU time 13.46 seconds
Started Jun 04 02:55:20 PM PDT 24
Finished Jun 04 02:55:34 PM PDT 24
Peak memory 258356 kb
Host smart-3e14fd4b-44b8-481d-b69e-b1e6fbc2c8cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027010150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.4027010150
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.442988944
Short name T334
Test name
Test status
Simulation time 29063600 ps
CPU time 28.44 seconds
Started Jun 04 02:55:18 PM PDT 24
Finished Jun 04 02:55:47 PM PDT 24
Peak memory 266924 kb
Host smart-d2fa2e9f-f06c-4a9a-b020-05a5e1604da8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442988944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_rw_evict.442988944
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.64023359
Short name T768
Test name
Test status
Simulation time 43770600 ps
CPU time 30.84 seconds
Started Jun 04 02:55:18 PM PDT 24
Finished Jun 04 02:55:49 PM PDT 24
Peak memory 274316 kb
Host smart-7e3008e9-76d3-494e-82f3-40e2b5efc95e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64023359 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.64023359
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.1012523585
Short name T913
Test name
Test status
Simulation time 6532240800 ps
CPU time 61.73 seconds
Started Jun 04 02:55:17 PM PDT 24
Finished Jun 04 02:56:19 PM PDT 24
Peak memory 262120 kb
Host smart-8941dbbf-1e94-488a-ad66-82e658fde4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012523585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.1012523585
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.1904213044
Short name T826
Test name
Test status
Simulation time 34497300 ps
CPU time 123.65 seconds
Started Jun 04 02:55:17 PM PDT 24
Finished Jun 04 02:57:21 PM PDT 24
Peak memory 276352 kb
Host smart-a0fa3644-0fcc-4e77-b0f6-2683b3a97e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904213044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.1904213044
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.1143745582
Short name T405
Test name
Test status
Simulation time 219794900 ps
CPU time 13.78 seconds
Started Jun 04 02:55:36 PM PDT 24
Finished Jun 04 02:55:50 PM PDT 24
Peak memory 264772 kb
Host smart-2706d9fe-7cba-46f8-b9c4-ba3a1e0e27be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143745582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
1143745582
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.4178047233
Short name T996
Test name
Test status
Simulation time 204186500 ps
CPU time 15.86 seconds
Started Jun 04 02:55:36 PM PDT 24
Finished Jun 04 02:55:52 PM PDT 24
Peak memory 275444 kb
Host smart-a0f8caae-110d-4c32-8337-bf70771209bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178047233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.4178047233
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.3990598065
Short name T156
Test name
Test status
Simulation time 11713300 ps
CPU time 21.68 seconds
Started Jun 04 02:55:25 PM PDT 24
Finished Jun 04 02:55:48 PM PDT 24
Peak memory 273236 kb
Host smart-72e1aff5-6261-4b22-a5d5-d9b2d29a1060
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990598065 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.3990598065
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.2526252566
Short name T817
Test name
Test status
Simulation time 9661705300 ps
CPU time 175.99 seconds
Started Jun 04 02:55:26 PM PDT 24
Finished Jun 04 02:58:23 PM PDT 24
Peak memory 262440 kb
Host smart-e4b58500-65a4-45b5-b99f-f82dd3f7c0ce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526252566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.2526252566
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.2807830244
Short name T549
Test name
Test status
Simulation time 1694169200 ps
CPU time 219.68 seconds
Started Jun 04 02:55:27 PM PDT 24
Finished Jun 04 02:59:07 PM PDT 24
Peak memory 289464 kb
Host smart-f50a3640-aa6c-4432-8828-bdbd8ab96301
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807830244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla
sh_ctrl_intr_rd.2807830244
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.2607420104
Short name T343
Test name
Test status
Simulation time 47625781700 ps
CPU time 407.37 seconds
Started Jun 04 02:55:27 PM PDT 24
Finished Jun 04 03:02:15 PM PDT 24
Peak memory 292472 kb
Host smart-567aedde-f581-4e94-ac71-2c86c04437ae
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607420104 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.2607420104
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.1058709849
Short name T588
Test name
Test status
Simulation time 139263800 ps
CPU time 111.59 seconds
Started Jun 04 02:55:31 PM PDT 24
Finished Jun 04 02:57:23 PM PDT 24
Peak memory 259896 kb
Host smart-4785d1b8-0c4f-4a3b-a649-409a6c0a9112
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058709849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.1058709849
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.3632192085
Short name T1010
Test name
Test status
Simulation time 70060000 ps
CPU time 13.36 seconds
Started Jun 04 02:55:27 PM PDT 24
Finished Jun 04 02:55:41 PM PDT 24
Peak memory 264756 kb
Host smart-0ce2c3ee-0f00-4230-b034-5a551fb476b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632192085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.3632192085
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.2420864953
Short name T28
Test name
Test status
Simulation time 246267500 ps
CPU time 31.19 seconds
Started Jun 04 02:55:26 PM PDT 24
Finished Jun 04 02:55:58 PM PDT 24
Peak memory 274468 kb
Host smart-fbd5268a-c5dc-42b7-ac11-a40019aae74b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420864953 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.2420864953
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.2161688368
Short name T395
Test name
Test status
Simulation time 3058174100 ps
CPU time 64.42 seconds
Started Jun 04 02:55:28 PM PDT 24
Finished Jun 04 02:56:33 PM PDT 24
Peak memory 262700 kb
Host smart-f3ce8e1f-e4db-447f-8fd0-eac32940fd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161688368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.2161688368
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.3661999791
Short name T435
Test name
Test status
Simulation time 29171600 ps
CPU time 122.39 seconds
Started Jun 04 02:55:27 PM PDT 24
Finished Jun 04 02:57:29 PM PDT 24
Peak memory 275448 kb
Host smart-c33fd75e-8a17-40be-9d76-68e98381f31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661999791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.3661999791
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.1545225973
Short name T175
Test name
Test status
Simulation time 138158900 ps
CPU time 14.23 seconds
Started Jun 04 02:55:46 PM PDT 24
Finished Jun 04 02:56:01 PM PDT 24
Peak memory 257928 kb
Host smart-30b98718-9bc1-4312-a36a-8f4c74456b74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545225973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
1545225973
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.140709149
Short name T884
Test name
Test status
Simulation time 14539600 ps
CPU time 13.67 seconds
Started Jun 04 02:55:44 PM PDT 24
Finished Jun 04 02:55:58 PM PDT 24
Peak memory 275760 kb
Host smart-067d5f59-ef27-42a8-8dcc-e6174bf4afda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140709149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.140709149
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.2886901921
Short name T890
Test name
Test status
Simulation time 9785480600 ps
CPU time 106.66 seconds
Started Jun 04 02:55:35 PM PDT 24
Finished Jun 04 02:57:22 PM PDT 24
Peak memory 262296 kb
Host smart-bae09ddb-7e28-4f45-a712-5f12dabb2c07
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886901921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.2886901921
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1775143644
Short name T882
Test name
Test status
Simulation time 34502030000 ps
CPU time 152.1 seconds
Started Jun 04 02:55:34 PM PDT 24
Finished Jun 04 02:58:07 PM PDT 24
Peak memory 292828 kb
Host smart-53569a90-917c-40af-be1b-ad228b6ed15a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775143644 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1775143644
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.173135025
Short name T140
Test name
Test status
Simulation time 128383800 ps
CPU time 112.64 seconds
Started Jun 04 02:55:35 PM PDT 24
Finished Jun 04 02:57:28 PM PDT 24
Peak memory 259740 kb
Host smart-a11eda45-cd08-4902-a603-8f08da7c5e03
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173135025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ot
p_reset.173135025
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.1301971727
Short name T184
Test name
Test status
Simulation time 194922400 ps
CPU time 13.94 seconds
Started Jun 04 02:55:35 PM PDT 24
Finished Jun 04 02:55:50 PM PDT 24
Peak memory 258328 kb
Host smart-ee08b7b2-ed18-492b-b16a-553533682309
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301971727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.1301971727
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.3890886408
Short name T552
Test name
Test status
Simulation time 83182500 ps
CPU time 30.69 seconds
Started Jun 04 02:55:35 PM PDT 24
Finished Jun 04 02:56:07 PM PDT 24
Peak memory 274216 kb
Host smart-57cca4f5-383f-4037-ae31-003ae84d9f2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890886408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.3890886408
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.983957298
Short name T335
Test name
Test status
Simulation time 38339600 ps
CPU time 30.63 seconds
Started Jun 04 02:55:39 PM PDT 24
Finished Jun 04 02:56:10 PM PDT 24
Peak memory 275748 kb
Host smart-70f5a51e-51e1-44ce-934c-aaf4be8fa706
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983957298 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.983957298
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.3026651537
Short name T595
Test name
Test status
Simulation time 26547400 ps
CPU time 121.89 seconds
Started Jun 04 02:55:35 PM PDT 24
Finished Jun 04 02:57:38 PM PDT 24
Peak memory 277596 kb
Host smart-2673ba52-6330-4c95-bf6c-99a51d79ad51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026651537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.3026651537
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.2722949786
Short name T888
Test name
Test status
Simulation time 46599800 ps
CPU time 14.07 seconds
Started Jun 04 02:55:52 PM PDT 24
Finished Jun 04 02:56:07 PM PDT 24
Peak memory 264776 kb
Host smart-5efcbe06-8bd6-431d-a262-ccd78030dcbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722949786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
2722949786
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.448374527
Short name T17
Test name
Test status
Simulation time 42390800 ps
CPU time 16.03 seconds
Started Jun 04 02:55:53 PM PDT 24
Finished Jun 04 02:56:09 PM PDT 24
Peak memory 275960 kb
Host smart-d8a3a02a-42b7-4696-88d2-5cfdb1c1c93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448374527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.448374527
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.2559251532
Short name T362
Test name
Test status
Simulation time 37794500 ps
CPU time 20.72 seconds
Started Jun 04 02:55:53 PM PDT 24
Finished Jun 04 02:56:14 PM PDT 24
Peak memory 273156 kb
Host smart-bde7ffd9-9e0a-4801-8eca-0c2e53281d21
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559251532 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.2559251532
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.1579861691
Short name T177
Test name
Test status
Simulation time 1521513400 ps
CPU time 59.69 seconds
Started Jun 04 02:55:44 PM PDT 24
Finished Jun 04 02:56:44 PM PDT 24
Peak memory 262392 kb
Host smart-fba53d3e-c659-4bdb-9de3-7811508f41f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579861691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.1579861691
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.2728663334
Short name T493
Test name
Test status
Simulation time 34790624500 ps
CPU time 260.08 seconds
Started Jun 04 02:55:46 PM PDT 24
Finished Jun 04 03:00:07 PM PDT 24
Peak memory 291360 kb
Host smart-155e4a05-4405-45b1-a35a-150d6f63028b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728663334 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.2728663334
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.1012125968
Short name T2
Test name
Test status
Simulation time 146891500 ps
CPU time 133.36 seconds
Started Jun 04 02:55:44 PM PDT 24
Finished Jun 04 02:57:58 PM PDT 24
Peak memory 259884 kb
Host smart-6c4ecbff-716d-456c-ac06-326ff29a4c9c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012125968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.1012125968
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.940841626
Short name T610
Test name
Test status
Simulation time 63456400 ps
CPU time 13.57 seconds
Started Jun 04 02:55:44 PM PDT 24
Finished Jun 04 02:55:58 PM PDT 24
Peak memory 258440 kb
Host smart-877899d0-3158-4708-9ea4-5a970de78ba4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940841626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_res
et.940841626
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.142969878
Short name T625
Test name
Test status
Simulation time 87411700 ps
CPU time 32.08 seconds
Started Jun 04 02:55:44 PM PDT 24
Finished Jun 04 02:56:17 PM PDT 24
Peak memory 274192 kb
Host smart-cf24732a-6bb1-4c16-b359-d4c00818a29f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142969878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_rw_evict.142969878
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.3368931632
Short name T325
Test name
Test status
Simulation time 125222200 ps
CPU time 30.69 seconds
Started Jun 04 02:55:52 PM PDT 24
Finished Jun 04 02:56:24 PM PDT 24
Peak memory 274368 kb
Host smart-452af370-25cf-463d-96b1-72f15faacd86
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368931632 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.3368931632
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.947603041
Short name T659
Test name
Test status
Simulation time 2189757700 ps
CPU time 60.06 seconds
Started Jun 04 02:55:50 PM PDT 24
Finished Jun 04 02:56:51 PM PDT 24
Peak memory 262448 kb
Host smart-72d2b4fa-1ab1-4d95-b5e0-5f97f0f3c31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947603041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.947603041
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.1842306193
Short name T974
Test name
Test status
Simulation time 31798300 ps
CPU time 171.45 seconds
Started Jun 04 02:55:43 PM PDT 24
Finished Jun 04 02:58:35 PM PDT 24
Peak memory 276320 kb
Host smart-c091c0ff-2e46-4428-a103-8b5a49009310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842306193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.1842306193
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.1789032758
Short name T558
Test name
Test status
Simulation time 82644100 ps
CPU time 14 seconds
Started Jun 04 02:55:53 PM PDT 24
Finished Jun 04 02:56:07 PM PDT 24
Peak memory 264788 kb
Host smart-2e9e5313-2be7-4f56-a975-1a15d196ffca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789032758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
1789032758
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.2543898665
Short name T596
Test name
Test status
Simulation time 73587900 ps
CPU time 15.99 seconds
Started Jun 04 02:55:51 PM PDT 24
Finished Jun 04 02:56:08 PM PDT 24
Peak memory 275588 kb
Host smart-b0a8069b-18ea-4b02-b145-a5ed519941be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543898665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.2543898665
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.2827506006
Short name T1012
Test name
Test status
Simulation time 13164400 ps
CPU time 22.32 seconds
Started Jun 04 02:55:52 PM PDT 24
Finished Jun 04 02:56:15 PM PDT 24
Peak memory 273308 kb
Host smart-583e94bc-632e-4252-a46d-67108c1c2fb6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827506006 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.2827506006
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.1533585242
Short name T308
Test name
Test status
Simulation time 1779184600 ps
CPU time 122.14 seconds
Started Jun 04 02:55:53 PM PDT 24
Finished Jun 04 02:57:56 PM PDT 24
Peak memory 262448 kb
Host smart-931cd5ac-db3b-442d-937e-0bda28e14b39
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533585242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.1533585242
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.1614358459
Short name T687
Test name
Test status
Simulation time 1971659100 ps
CPU time 322.76 seconds
Started Jun 04 02:55:52 PM PDT 24
Finished Jun 04 03:01:16 PM PDT 24
Peak memory 283588 kb
Host smart-3fe02b8a-04a3-42d9-8103-d65f3756106a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614358459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_intr_rd.1614358459
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.2311682328
Short name T545
Test name
Test status
Simulation time 16376470500 ps
CPU time 143.16 seconds
Started Jun 04 02:55:50 PM PDT 24
Finished Jun 04 02:58:14 PM PDT 24
Peak memory 292948 kb
Host smart-33ffc43e-ba28-4a36-a7bc-fd0bd11236e7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311682328 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.2311682328
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.2496200028
Short name T664
Test name
Test status
Simulation time 76088500 ps
CPU time 131.69 seconds
Started Jun 04 02:55:50 PM PDT 24
Finished Jun 04 02:58:03 PM PDT 24
Peak memory 259512 kb
Host smart-1acecad3-800a-4e17-b6e6-1d45e7c73f49
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496200028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.2496200028
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.3406378088
Short name T1072
Test name
Test status
Simulation time 2299446500 ps
CPU time 202.42 seconds
Started Jun 04 02:55:52 PM PDT 24
Finished Jun 04 02:59:15 PM PDT 24
Peak memory 264816 kb
Host smart-9958d712-ed82-4e57-8a5a-531e6a6baae4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406378088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.3406378088
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.4280789753
Short name T377
Test name
Test status
Simulation time 581608400 ps
CPU time 69.04 seconds
Started Jun 04 02:55:52 PM PDT 24
Finished Jun 04 02:57:02 PM PDT 24
Peak memory 262072 kb
Host smart-94dd4388-ac42-4886-9a3d-2a075d2db5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280789753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.4280789753
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.2933017613
Short name T221
Test name
Test status
Simulation time 43633900 ps
CPU time 124.33 seconds
Started Jun 04 02:55:52 PM PDT 24
Finished Jun 04 02:57:57 PM PDT 24
Peak memory 275392 kb
Host smart-3a9077ca-a289-41b1-848d-5e063eaa9509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933017613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.2933017613
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.3000707414
Short name T526
Test name
Test status
Simulation time 103214900 ps
CPU time 13.68 seconds
Started Jun 04 02:56:10 PM PDT 24
Finished Jun 04 02:56:24 PM PDT 24
Peak memory 264172 kb
Host smart-9443565d-5b47-4f7d-8664-6ab0ef153c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000707414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
3000707414
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.2831852308
Short name T670
Test name
Test status
Simulation time 25656000 ps
CPU time 13.21 seconds
Started Jun 04 02:56:11 PM PDT 24
Finished Jun 04 02:56:25 PM PDT 24
Peak memory 275868 kb
Host smart-c3387bf3-5893-4b98-ba9d-975ad302718b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831852308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.2831852308
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.3544479220
Short name T121
Test name
Test status
Simulation time 26073900 ps
CPU time 22 seconds
Started Jun 04 02:56:02 PM PDT 24
Finished Jun 04 02:56:24 PM PDT 24
Peak memory 265016 kb
Host smart-8b7bed3a-2520-4de9-b440-7d48885cf8d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544479220 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.3544479220
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.1475003217
Short name T470
Test name
Test status
Simulation time 17230591800 ps
CPU time 150.71 seconds
Started Jun 04 02:56:01 PM PDT 24
Finished Jun 04 02:58:32 PM PDT 24
Peak memory 262364 kb
Host smart-ecb2ff61-78ec-4cb8-bb4c-63f9f7693140
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475003217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.1475003217
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.1302224067
Short name T352
Test name
Test status
Simulation time 4848850700 ps
CPU time 192.56 seconds
Started Jun 04 02:56:03 PM PDT 24
Finished Jun 04 02:59:16 PM PDT 24
Peak memory 289496 kb
Host smart-872323a6-2ba8-43e3-bc4f-f44a27b0bbd2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302224067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.1302224067
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.3336941263
Short name T36
Test name
Test status
Simulation time 22750460400 ps
CPU time 155.77 seconds
Started Jun 04 02:56:02 PM PDT 24
Finished Jun 04 02:58:38 PM PDT 24
Peak memory 293120 kb
Host smart-ffb5f485-8260-4b7d-88de-945f40c00ddb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336941263 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.3336941263
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.1204115840
Short name T429
Test name
Test status
Simulation time 419531300 ps
CPU time 134.1 seconds
Started Jun 04 02:56:01 PM PDT 24
Finished Jun 04 02:58:16 PM PDT 24
Peak memory 259776 kb
Host smart-758d6bc1-8ff9-4777-8c57-61112e6ff47e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204115840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.1204115840
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.2444256797
Short name T9
Test name
Test status
Simulation time 76717800 ps
CPU time 14.29 seconds
Started Jun 04 02:56:03 PM PDT 24
Finished Jun 04 02:56:18 PM PDT 24
Peak memory 264788 kb
Host smart-9421525c-524b-49f0-a884-840e5571e80f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444256797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.2444256797
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.3316054931
Short name T44
Test name
Test status
Simulation time 31324900 ps
CPU time 30.42 seconds
Started Jun 04 02:56:01 PM PDT 24
Finished Jun 04 02:56:32 PM PDT 24
Peak memory 273112 kb
Host smart-8b6f6835-fc8a-4a2e-9ad9-4ae64e426fe3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316054931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.3316054931
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.3946437313
Short name T1026
Test name
Test status
Simulation time 49896300 ps
CPU time 28.42 seconds
Started Jun 04 02:56:02 PM PDT 24
Finished Jun 04 02:56:31 PM PDT 24
Peak memory 274356 kb
Host smart-e519d292-7721-42e2-adf6-162c3b81f973
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946437313 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.3946437313
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.1851845276
Short name T222
Test name
Test status
Simulation time 77051900 ps
CPU time 120.39 seconds
Started Jun 04 02:56:01 PM PDT 24
Finished Jun 04 02:58:02 PM PDT 24
Peak memory 276592 kb
Host smart-5a04db17-9354-40d5-963e-9d8564a45f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851845276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.1851845276
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.3838346210
Short name T503
Test name
Test status
Simulation time 21082700 ps
CPU time 13.54 seconds
Started Jun 04 02:45:15 PM PDT 24
Finished Jun 04 02:45:29 PM PDT 24
Peak memory 257912 kb
Host smart-7352328d-82d1-427f-8665-46c33ac1a8b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838346210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.3
838346210
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.181628335
Short name T690
Test name
Test status
Simulation time 28620500 ps
CPU time 15.51 seconds
Started Jun 04 02:44:55 PM PDT 24
Finished Jun 04 02:45:11 PM PDT 24
Peak memory 275828 kb
Host smart-b557faab-fa93-4a03-9887-6998dfe792d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181628335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.181628335
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.876114431
Short name T851
Test name
Test status
Simulation time 184766400 ps
CPU time 106.7 seconds
Started Jun 04 02:44:47 PM PDT 24
Finished Jun 04 02:46:34 PM PDT 24
Peak memory 272188 kb
Host smart-11b653fd-ed80-4c04-9f98-1076b2c2c6b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876114431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.flash_ctrl_derr_detect.876114431
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.764554029
Short name T374
Test name
Test status
Simulation time 45532700 ps
CPU time 21.9 seconds
Started Jun 04 02:44:55 PM PDT 24
Finished Jun 04 02:45:17 PM PDT 24
Peak memory 264964 kb
Host smart-28b3ec91-aae1-4d13-a488-af81029701a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764554029 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.764554029
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.316049591
Short name T787
Test name
Test status
Simulation time 6839058200 ps
CPU time 544.53 seconds
Started Jun 04 02:44:14 PM PDT 24
Finished Jun 04 02:53:19 PM PDT 24
Peak memory 262848 kb
Host smart-3b7bfbea-d750-4108-91d5-34b95b396bb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=316049591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.316049591
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.2756236123
Short name T938
Test name
Test status
Simulation time 5483346900 ps
CPU time 2552.52 seconds
Started Jun 04 02:44:28 PM PDT 24
Finished Jun 04 03:27:02 PM PDT 24
Peak memory 263448 kb
Host smart-d7becc3a-0b97-4329-8b16-3149a3746bc8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756236123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.2756236123
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.839046133
Short name T165
Test name
Test status
Simulation time 851930000 ps
CPU time 1024.34 seconds
Started Jun 04 02:44:29 PM PDT 24
Finished Jun 04 03:01:34 PM PDT 24
Peak memory 273032 kb
Host smart-81d886e8-046b-44de-8560-ed46a1c03f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839046133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.839046133
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.2680505731
Short name T581
Test name
Test status
Simulation time 1599975500 ps
CPU time 24.91 seconds
Started Jun 04 02:44:22 PM PDT 24
Finished Jun 04 02:44:47 PM PDT 24
Peak memory 264788 kb
Host smart-7811875c-80a2-4870-a637-2490a2ddbe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680505731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.2680505731
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.2398737559
Short name T746
Test name
Test status
Simulation time 82935542300 ps
CPU time 2691.12 seconds
Started Jun 04 02:44:25 PM PDT 24
Finished Jun 04 03:29:17 PM PDT 24
Peak memory 262236 kb
Host smart-a07786d2-5376-4489-9833-3fce7c013bc2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398737559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.2398737559
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.1982243991
Short name T743
Test name
Test status
Simulation time 559669939000 ps
CPU time 2230.34 seconds
Started Jun 04 02:44:30 PM PDT 24
Finished Jun 04 03:21:41 PM PDT 24
Peak memory 262280 kb
Host smart-84ccf0f5-14c6-43fe-bdbb-648355cf076c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982243991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.1982243991
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.3805572603
Short name T866
Test name
Test status
Simulation time 668320900 ps
CPU time 100.59 seconds
Started Jun 04 02:44:09 PM PDT 24
Finished Jun 04 02:45:50 PM PDT 24
Peak memory 262316 kb
Host smart-a46aa8b5-ff8f-4b41-afe9-73d21b285e5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3805572603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.3805572603
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1990393419
Short name T287
Test name
Test status
Simulation time 10023440500 ps
CPU time 140.62 seconds
Started Jun 04 02:45:09 PM PDT 24
Finished Jun 04 02:47:30 PM PDT 24
Peak memory 273888 kb
Host smart-abe759f0-85c4-4b7b-99a0-85e728899edf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990393419 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.1990393419
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.836890632
Short name T948
Test name
Test status
Simulation time 103542500 ps
CPU time 13.65 seconds
Started Jun 04 02:45:08 PM PDT 24
Finished Jun 04 02:45:22 PM PDT 24
Peak memory 258820 kb
Host smart-06134bf6-aec6-446a-b53a-6ae41d7f2eee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836890632 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.836890632
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.4049248131
Short name T161
Test name
Test status
Simulation time 320305992600 ps
CPU time 948.43 seconds
Started Jun 04 02:44:12 PM PDT 24
Finished Jun 04 03:00:01 PM PDT 24
Peak memory 263756 kb
Host smart-ece31061-4bce-4164-a2b7-b7442d9e7aa1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049248131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_hw_rma_reset.4049248131
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.1917926881
Short name T599
Test name
Test status
Simulation time 3222361500 ps
CPU time 73.37 seconds
Started Jun 04 02:44:15 PM PDT 24
Finished Jun 04 02:45:29 PM PDT 24
Peak memory 262264 kb
Host smart-5d29f55b-ce0f-4905-8df9-00f47d2bfcef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917926881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.1917926881
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.782069804
Short name T695
Test name
Test status
Simulation time 3484631100 ps
CPU time 155.05 seconds
Started Jun 04 02:44:54 PM PDT 24
Finished Jun 04 02:47:29 PM PDT 24
Peak memory 292852 kb
Host smart-663a1044-bb6a-42f3-89a4-e9de6867dfc4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782069804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_intr_rd.782069804
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.135088772
Short name T810
Test name
Test status
Simulation time 61810446800 ps
CPU time 300.95 seconds
Started Jun 04 02:44:54 PM PDT 24
Finished Jun 04 02:49:55 PM PDT 24
Peak memory 292924 kb
Host smart-3fcf42bb-c272-499d-bd46-bc2ebc7c1dfe
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135088772 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.135088772
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.2416329090
Short name T32
Test name
Test status
Simulation time 2890723500 ps
CPU time 88.27 seconds
Started Jun 04 02:44:52 PM PDT 24
Finished Jun 04 02:46:21 PM PDT 24
Peak memory 258952 kb
Host smart-0a61c9c2-a429-455d-93d3-d3ae9b7b769f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416329090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.2416329090
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3836958238
Short name T784
Test name
Test status
Simulation time 40694700500 ps
CPU time 197.24 seconds
Started Jun 04 02:44:53 PM PDT 24
Finished Jun 04 02:48:11 PM PDT 24
Peak memory 264860 kb
Host smart-852f3952-8533-46c1-b056-1130289a8f9e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383
6958238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.3836958238
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.2525024519
Short name T1031
Test name
Test status
Simulation time 1921995000 ps
CPU time 59.11 seconds
Started Jun 04 02:44:28 PM PDT 24
Finished Jun 04 02:45:27 PM PDT 24
Peak memory 260344 kb
Host smart-89396bae-7e96-4748-bda7-d0add44e6185
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525024519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.2525024519
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.2090207473
Short name T137
Test name
Test status
Simulation time 32210300 ps
CPU time 13.3 seconds
Started Jun 04 02:45:07 PM PDT 24
Finished Jun 04 02:45:22 PM PDT 24
Peak memory 264796 kb
Host smart-eb60650c-58d7-4f07-a763-a434414d598c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090207473 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.2090207473
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.335744147
Short name T122
Test name
Test status
Simulation time 8047569200 ps
CPU time 85.27 seconds
Started Jun 04 02:44:30 PM PDT 24
Finished Jun 04 02:45:55 PM PDT 24
Peak memory 259792 kb
Host smart-bfb4b243-e237-4f7a-b302-94114301b4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335744147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.335744147
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.1727770529
Short name T88
Test name
Test status
Simulation time 8903750300 ps
CPU time 301.56 seconds
Started Jun 04 02:44:21 PM PDT 24
Finished Jun 04 02:49:23 PM PDT 24
Peak memory 273652 kb
Host smart-ae5b0748-28ab-4124-9a2c-3c5716c007aa
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727770529 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.1727770529
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.252360524
Short name T900
Test name
Test status
Simulation time 43576800 ps
CPU time 132.25 seconds
Started Jun 04 02:44:15 PM PDT 24
Finished Jun 04 02:46:27 PM PDT 24
Peak memory 259676 kb
Host smart-cc686562-4682-47ac-a59e-16b0d0d8401c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252360524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp
_reset.252360524
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.1944493107
Short name T916
Test name
Test status
Simulation time 6025182100 ps
CPU time 212.57 seconds
Started Jun 04 02:44:47 PM PDT 24
Finished Jun 04 02:48:20 PM PDT 24
Peak memory 281268 kb
Host smart-79a1f7c9-d01b-48f6-8bc7-2a8c839629cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944493107 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.1944493107
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.2000608436
Short name T216
Test name
Test status
Simulation time 16482900 ps
CPU time 14.07 seconds
Started Jun 04 02:45:09 PM PDT 24
Finished Jun 04 02:45:23 PM PDT 24
Peak memory 260756 kb
Host smart-00230ed8-d5c6-40f5-8ada-fd9276dc85ac
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2000608436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.2000608436
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.1644224863
Short name T417
Test name
Test status
Simulation time 110247500 ps
CPU time 66.79 seconds
Started Jun 04 02:44:09 PM PDT 24
Finished Jun 04 02:45:16 PM PDT 24
Peak memory 262016 kb
Host smart-1c4f7e84-b9d1-4b3e-859e-eda790d34c5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1644224863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1644224863
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.153541269
Short name T217
Test name
Test status
Simulation time 930525100 ps
CPU time 20.9 seconds
Started Jun 04 02:44:54 PM PDT 24
Finished Jun 04 02:45:15 PM PDT 24
Peak memory 263228 kb
Host smart-223ee234-cb11-480a-bea2-ad2db8852280
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153541269 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.153541269
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.4243278768
Short name T129
Test name
Test status
Simulation time 47848600 ps
CPU time 14.15 seconds
Started Jun 04 02:44:59 PM PDT 24
Finished Jun 04 02:45:14 PM PDT 24
Peak memory 265004 kb
Host smart-7ff0175b-dd4f-4f65-98c5-4ccf8bf8f511
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243278768 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.4243278768
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.320739061
Short name T471
Test name
Test status
Simulation time 32635100 ps
CPU time 13.84 seconds
Started Jun 04 02:44:52 PM PDT 24
Finished Jun 04 02:45:06 PM PDT 24
Peak memory 264744 kb
Host smart-a915a491-24ee-42d9-a620-aaad7bd1bfa3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320739061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_rese
t.320739061
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.319497452
Short name T898
Test name
Test status
Simulation time 98741400 ps
CPU time 291.28 seconds
Started Jun 04 02:43:59 PM PDT 24
Finished Jun 04 02:48:51 PM PDT 24
Peak memory 281232 kb
Host smart-809c2e2c-474b-4ec7-9165-55e851b16335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319497452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.319497452
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.112410734
Short name T68
Test name
Test status
Simulation time 142957300 ps
CPU time 100.79 seconds
Started Jun 04 02:44:12 PM PDT 24
Finished Jun 04 02:45:53 PM PDT 24
Peak memory 264796 kb
Host smart-030f74a0-224b-495a-b269-9d926b29f891
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=112410734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.112410734
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.444888536
Short name T330
Test name
Test status
Simulation time 510084400 ps
CPU time 37.99 seconds
Started Jun 04 02:44:58 PM PDT 24
Finished Jun 04 02:45:36 PM PDT 24
Peak memory 270436 kb
Host smart-1218f63b-8545-4069-9956-eb9d6c8fe722
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444888536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_re_evict.444888536
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.1092278846
Short name T759
Test name
Test status
Simulation time 1794170300 ps
CPU time 148 seconds
Started Jun 04 02:44:34 PM PDT 24
Finished Jun 04 02:47:03 PM PDT 24
Peak memory 281288 kb
Host smart-d32ce09d-05cd-43b5-b5b8-55ddeb05e86b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092278846 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.1092278846
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.1687826386
Short name T197
Test name
Test status
Simulation time 641587500 ps
CPU time 166.18 seconds
Started Jun 04 02:44:45 PM PDT 24
Finished Jun 04 02:47:32 PM PDT 24
Peak memory 281748 kb
Host smart-f3f9b74d-1aa2-4ac9-b012-90eda1ac0d56
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1687826386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.1687826386
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.2986141953
Short name T1022
Test name
Test status
Simulation time 1043774500 ps
CPU time 129.81 seconds
Started Jun 04 02:44:45 PM PDT 24
Finished Jun 04 02:46:55 PM PDT 24
Peak memory 293932 kb
Host smart-cb87eaa1-768f-429d-b98c-19bbc9deed25
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986141953 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.2986141953
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.3577707976
Short name T98
Test name
Test status
Simulation time 15326557600 ps
CPU time 566.64 seconds
Started Jun 04 02:44:35 PM PDT 24
Finished Jun 04 02:54:02 PM PDT 24
Peak memory 314088 kb
Host smart-7c3dcc81-5ddd-4df4-96ab-eda185b7bc07
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577707976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_rw.3577707976
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.989749306
Short name T769
Test name
Test status
Simulation time 80598500 ps
CPU time 28.26 seconds
Started Jun 04 02:44:53 PM PDT 24
Finished Jun 04 02:45:21 PM PDT 24
Peak memory 273020 kb
Host smart-47af4e4b-fe36-461f-b126-3f442db2deb2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989749306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_rw_evict.989749306
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.695507880
Short name T868
Test name
Test status
Simulation time 100797000 ps
CPU time 31.92 seconds
Started Jun 04 02:44:52 PM PDT 24
Finished Jun 04 02:45:25 PM PDT 24
Peak memory 275096 kb
Host smart-5f1d24b1-eb1d-4f6e-86da-f31661b8a83b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695507880 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.695507880
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.4111066899
Short name T187
Test name
Test status
Simulation time 3962359900 ps
CPU time 4824.99 seconds
Started Jun 04 02:44:54 PM PDT 24
Finished Jun 04 04:05:20 PM PDT 24
Peak memory 284828 kb
Host smart-92b43fad-03f1-4b68-a5f3-56c1bcc380e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111066899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.4111066899
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.2236254879
Short name T870
Test name
Test status
Simulation time 2538108100 ps
CPU time 73.07 seconds
Started Jun 04 02:44:56 PM PDT 24
Finished Jun 04 02:46:09 PM PDT 24
Peak memory 261988 kb
Host smart-1ebe5e27-bb3c-4a99-a8fb-44efe0616f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236254879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.2236254879
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.1543395678
Short name T41
Test name
Test status
Simulation time 2986770500 ps
CPU time 84.72 seconds
Started Jun 04 02:44:47 PM PDT 24
Finished Jun 04 02:46:13 PM PDT 24
Peak memory 264876 kb
Host smart-dbc0c5a0-1b34-4df7-82c1-7f3b837a5a03
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543395678 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.1543395678
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.1388352035
Short name T998
Test name
Test status
Simulation time 744964900 ps
CPU time 76.16 seconds
Started Jun 04 02:44:47 PM PDT 24
Finished Jun 04 02:46:04 PM PDT 24
Peak memory 264964 kb
Host smart-da701e91-12a5-4222-a170-1838174b6698
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388352035 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.1388352035
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.2066232425
Short name T20
Test name
Test status
Simulation time 39009900 ps
CPU time 121.59 seconds
Started Jun 04 02:43:59 PM PDT 24
Finished Jun 04 02:46:01 PM PDT 24
Peak memory 277048 kb
Host smart-dc3e5149-dd38-4c59-89ee-8ba9b72f0156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066232425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.2066232425
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.1608087932
Short name T905
Test name
Test status
Simulation time 60408900 ps
CPU time 23.71 seconds
Started Jun 04 02:44:00 PM PDT 24
Finished Jun 04 02:44:24 PM PDT 24
Peak memory 258768 kb
Host smart-28cc7185-81bc-4df3-a67e-f914c0ad9f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608087932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1608087932
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.1641241203
Short name T67
Test name
Test status
Simulation time 1207156800 ps
CPU time 388.38 seconds
Started Jun 04 02:44:53 PM PDT 24
Finished Jun 04 02:51:21 PM PDT 24
Peak memory 289528 kb
Host smart-3e3272a1-68a7-4335-80f4-b8250ad1bd27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641241203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.1641241203
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.3306711852
Short name T852
Test name
Test status
Simulation time 23375400 ps
CPU time 26.44 seconds
Started Jun 04 02:44:03 PM PDT 24
Finished Jun 04 02:44:30 PM PDT 24
Peak memory 258664 kb
Host smart-379969a4-e149-4e35-b053-875953acf984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306711852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3306711852
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.1766687647
Short name T682
Test name
Test status
Simulation time 2309611600 ps
CPU time 200.5 seconds
Started Jun 04 02:44:35 PM PDT 24
Finished Jun 04 02:47:56 PM PDT 24
Peak memory 264772 kb
Host smart-33feffc1-d070-43d6-9187-fad3b4920ea2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766687647 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_wo.1766687647
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.2062593032
Short name T903
Test name
Test status
Simulation time 77013100 ps
CPU time 13.71 seconds
Started Jun 04 02:56:19 PM PDT 24
Finished Jun 04 02:56:33 PM PDT 24
Peak memory 264816 kb
Host smart-cabe896f-a7d4-423b-9c41-4c5be6335d80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062593032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
2062593032
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.2512537546
Short name T886
Test name
Test status
Simulation time 15982700 ps
CPU time 13.67 seconds
Started Jun 04 02:56:19 PM PDT 24
Finished Jun 04 02:56:33 PM PDT 24
Peak memory 275508 kb
Host smart-ca4b1e2f-e362-4496-8fe5-8c4089ded9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512537546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.2512537546
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.2845355470
Short name T375
Test name
Test status
Simulation time 35231500 ps
CPU time 20.53 seconds
Started Jun 04 02:56:12 PM PDT 24
Finished Jun 04 02:56:33 PM PDT 24
Peak memory 273164 kb
Host smart-31dfe33e-5034-4ace-a8f2-09c3e60142ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845355470 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.2845355470
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.3719680644
Short name T806
Test name
Test status
Simulation time 6981998400 ps
CPU time 145.83 seconds
Started Jun 04 02:56:12 PM PDT 24
Finished Jun 04 02:58:39 PM PDT 24
Peak memory 262156 kb
Host smart-db3e795c-b1cd-4b96-9b98-14f4afff3a29
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719680644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.3719680644
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.3852140506
Short name T967
Test name
Test status
Simulation time 6613051500 ps
CPU time 235.87 seconds
Started Jun 04 02:56:11 PM PDT 24
Finished Jun 04 03:00:08 PM PDT 24
Peak memory 283640 kb
Host smart-06013bbd-9b96-467b-a268-ae6388aae713
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852140506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.3852140506
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.2458009904
Short name T792
Test name
Test status
Simulation time 23672080600 ps
CPU time 247.65 seconds
Started Jun 04 02:56:12 PM PDT 24
Finished Jun 04 03:00:21 PM PDT 24
Peak memory 292932 kb
Host smart-74b19214-2f97-4cd5-a5ed-c9ec0abe7de6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458009904 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.2458009904
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.2767017484
Short name T147
Test name
Test status
Simulation time 96503400 ps
CPU time 108.95 seconds
Started Jun 04 02:56:11 PM PDT 24
Finished Jun 04 02:58:00 PM PDT 24
Peak memory 259568 kb
Host smart-ff705771-9e1a-40f2-827d-9597e4af64a3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767017484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.2767017484
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.555677137
Short name T699
Test name
Test status
Simulation time 28794800 ps
CPU time 30.88 seconds
Started Jun 04 02:56:11 PM PDT 24
Finished Jun 04 02:56:43 PM PDT 24
Peak memory 274372 kb
Host smart-65a2f634-dae1-4491-ace5-16cddc71561b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555677137 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.555677137
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.2649080529
Short name T1068
Test name
Test status
Simulation time 597730100 ps
CPU time 60.93 seconds
Started Jun 04 02:56:21 PM PDT 24
Finished Jun 04 02:57:23 PM PDT 24
Peak memory 263176 kb
Host smart-2fa1723f-11ea-4f72-bde5-a773a6ee227d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649080529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.2649080529
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.1251605160
Short name T1064
Test name
Test status
Simulation time 101202100 ps
CPU time 193.23 seconds
Started Jun 04 02:56:11 PM PDT 24
Finished Jun 04 02:59:25 PM PDT 24
Peak memory 279192 kb
Host smart-acf6b52e-4f05-4469-af57-16fbff329ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251605160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.1251605160
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.218971461
Short name T730
Test name
Test status
Simulation time 91200500 ps
CPU time 13.81 seconds
Started Jun 04 02:56:23 PM PDT 24
Finished Jun 04 02:56:37 PM PDT 24
Peak memory 263508 kb
Host smart-90febfff-c32a-40cf-8dec-7389e7a75641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218971461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.218971461
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.3840373953
Short name T934
Test name
Test status
Simulation time 46369700 ps
CPU time 15.63 seconds
Started Jun 04 02:56:19 PM PDT 24
Finished Jun 04 02:56:35 PM PDT 24
Peak memory 274796 kb
Host smart-2b9c4f97-8f83-481a-9065-e33b01404c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840373953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3840373953
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.562090087
Short name T1048
Test name
Test status
Simulation time 26067600 ps
CPU time 21.78 seconds
Started Jun 04 02:56:23 PM PDT 24
Finished Jun 04 02:56:45 PM PDT 24
Peak memory 272044 kb
Host smart-8703e49e-866b-4e93-ac02-59e04d19b590
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562090087 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.562090087
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3156289528
Short name T643
Test name
Test status
Simulation time 5915505600 ps
CPU time 68.24 seconds
Started Jun 04 02:56:19 PM PDT 24
Finished Jun 04 02:57:28 PM PDT 24
Peak memory 262416 kb
Host smart-923095ca-ad27-47b4-968c-53d5486a48b6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156289528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.3156289528
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.2528206792
Short name T504
Test name
Test status
Simulation time 1457392300 ps
CPU time 192.26 seconds
Started Jun 04 02:56:20 PM PDT 24
Finished Jun 04 02:59:33 PM PDT 24
Peak memory 289456 kb
Host smart-986abd93-c3c3-4d84-b1b8-032fffa4cc5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528206792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.2528206792
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3570856909
Short name T1057
Test name
Test status
Simulation time 23354788300 ps
CPU time 128 seconds
Started Jun 04 02:56:21 PM PDT 24
Finished Jun 04 02:58:30 PM PDT 24
Peak memory 292412 kb
Host smart-9dde4727-66cf-450c-8e80-69d2d2a681b6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570856909 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.3570856909
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.3460010370
Short name T150
Test name
Test status
Simulation time 136476200 ps
CPU time 112.67 seconds
Started Jun 04 02:56:19 PM PDT 24
Finished Jun 04 02:58:12 PM PDT 24
Peak memory 259536 kb
Host smart-2fb34262-2f96-4e70-9e72-25091ebc6e46
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460010370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.3460010370
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.793440366
Short name T972
Test name
Test status
Simulation time 49830500 ps
CPU time 28.1 seconds
Started Jun 04 02:56:19 PM PDT 24
Finished Jun 04 02:56:48 PM PDT 24
Peak memory 274100 kb
Host smart-2c32938d-53e8-4960-b7f5-f0b29f7a7bfb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793440366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_rw_evict.793440366
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.2570614141
Short name T556
Test name
Test status
Simulation time 30345500 ps
CPU time 30.72 seconds
Started Jun 04 02:56:20 PM PDT 24
Finished Jun 04 02:56:51 PM PDT 24
Peak memory 274460 kb
Host smart-af63c9d2-d48b-4c87-984a-c7e4c4f53f64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570614141 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.2570614141
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.3742314971
Short name T385
Test name
Test status
Simulation time 3341826000 ps
CPU time 64.79 seconds
Started Jun 04 02:56:18 PM PDT 24
Finished Jun 04 02:57:23 PM PDT 24
Peak memory 262756 kb
Host smart-35932082-f490-4680-ac40-ee14c8105ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742314971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3742314971
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.3860378273
Short name T772
Test name
Test status
Simulation time 94372700 ps
CPU time 125.11 seconds
Started Jun 04 02:56:18 PM PDT 24
Finished Jun 04 02:58:24 PM PDT 24
Peak memory 275524 kb
Host smart-ac20e48e-53bd-4da4-acdc-940ab41fbcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860378273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.3860378273
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.710300404
Short name T319
Test name
Test status
Simulation time 44163500 ps
CPU time 14.29 seconds
Started Jun 04 02:56:27 PM PDT 24
Finished Jun 04 02:56:42 PM PDT 24
Peak memory 257912 kb
Host smart-6fa2a633-1b51-4116-ae1f-1b299a98d4b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710300404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.710300404
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.285181286
Short name T115
Test name
Test status
Simulation time 39920700 ps
CPU time 15.88 seconds
Started Jun 04 02:56:31 PM PDT 24
Finished Jun 04 02:56:47 PM PDT 24
Peak memory 274900 kb
Host smart-69e6583f-992c-41f9-aa26-0322aeaf7375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285181286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.285181286
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.232649548
Short name T862
Test name
Test status
Simulation time 10660900 ps
CPU time 21.57 seconds
Started Jun 04 02:56:28 PM PDT 24
Finished Jun 04 02:56:50 PM PDT 24
Peak memory 273160 kb
Host smart-c6f84da6-e001-4658-a25f-d74c1cd5987a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232649548 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.232649548
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.1668594675
Short name T317
Test name
Test status
Simulation time 2315474800 ps
CPU time 77.24 seconds
Started Jun 04 02:56:28 PM PDT 24
Finished Jun 04 02:57:46 PM PDT 24
Peak memory 262240 kb
Host smart-df872b08-d489-41bc-afce-ae7cdb23a222
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668594675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.1668594675
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.1859627879
Short name T904
Test name
Test status
Simulation time 3101518100 ps
CPU time 233.08 seconds
Started Jun 04 02:56:28 PM PDT 24
Finished Jun 04 03:00:21 PM PDT 24
Peak memory 283644 kb
Host smart-456d511d-db54-48cc-beec-40335db560f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859627879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.1859627879
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2275335094
Short name T800
Test name
Test status
Simulation time 11682825900 ps
CPU time 123.07 seconds
Started Jun 04 02:56:26 PM PDT 24
Finished Jun 04 02:58:29 PM PDT 24
Peak memory 293048 kb
Host smart-009d3757-451e-43cf-92c4-0c44908dae10
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275335094 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.2275335094
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.860001780
Short name T146
Test name
Test status
Simulation time 153288700 ps
CPU time 135.19 seconds
Started Jun 04 02:56:28 PM PDT 24
Finished Jun 04 02:58:44 PM PDT 24
Peak memory 264256 kb
Host smart-a6c60012-8367-4014-95f6-1d77a47025cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860001780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ot
p_reset.860001780
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.3410525509
Short name T537
Test name
Test status
Simulation time 46577900 ps
CPU time 31.6 seconds
Started Jun 04 02:56:28 PM PDT 24
Finished Jun 04 02:57:01 PM PDT 24
Peak memory 274432 kb
Host smart-c507728e-a1ae-4d03-a470-ad9faa1b7dcd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410525509 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.3410525509
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.3627894538
Short name T394
Test name
Test status
Simulation time 2449287000 ps
CPU time 57.94 seconds
Started Jun 04 02:56:28 PM PDT 24
Finished Jun 04 02:57:26 PM PDT 24
Peak memory 262852 kb
Host smart-fe1d4fc2-612a-47fd-827c-cadc8f89544c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627894538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3627894538
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.3868682094
Short name T922
Test name
Test status
Simulation time 69421600 ps
CPU time 50.27 seconds
Started Jun 04 02:56:29 PM PDT 24
Finished Jun 04 02:57:19 PM PDT 24
Peak memory 270316 kb
Host smart-f4194034-616c-4f84-befc-c2dffd1fbce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868682094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.3868682094
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.3686686410
Short name T946
Test name
Test status
Simulation time 106947600 ps
CPU time 14.32 seconds
Started Jun 04 02:56:42 PM PDT 24
Finished Jun 04 02:56:57 PM PDT 24
Peak memory 257932 kb
Host smart-dd5278a5-1eaf-49ee-bf4b-592fa5f4f991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686686410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
3686686410
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.614602015
Short name T311
Test name
Test status
Simulation time 49997300 ps
CPU time 15.81 seconds
Started Jun 04 02:56:38 PM PDT 24
Finished Jun 04 02:56:54 PM PDT 24
Peak memory 275548 kb
Host smart-f5457500-3280-4577-9d1d-9b69feb7623c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614602015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.614602015
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.360617886
Short name T506
Test name
Test status
Simulation time 13726200 ps
CPU time 21.98 seconds
Started Jun 04 02:56:37 PM PDT 24
Finished Jun 04 02:56:59 PM PDT 24
Peak memory 280416 kb
Host smart-e4b8f426-a3fc-4c1f-b88f-4e6a723ae2cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360617886 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.360617886
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.1167400270
Short name T647
Test name
Test status
Simulation time 2784535500 ps
CPU time 60.86 seconds
Started Jun 04 02:56:40 PM PDT 24
Finished Jun 04 02:57:41 PM PDT 24
Peak memory 262268 kb
Host smart-2a83536a-1f07-4220-8434-bedfc6df9eeb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167400270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.1167400270
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.3513329339
Short name T355
Test name
Test status
Simulation time 3219476300 ps
CPU time 143.13 seconds
Started Jun 04 02:56:37 PM PDT 24
Finished Jun 04 02:59:01 PM PDT 24
Peak memory 291628 kb
Host smart-3c173f9e-bc15-4283-8f3c-0b50315b0631
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513329339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.3513329339
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3050905217
Short name T173
Test name
Test status
Simulation time 12419965300 ps
CPU time 346.57 seconds
Started Jun 04 02:56:37 PM PDT 24
Finished Jun 04 03:02:24 PM PDT 24
Peak memory 292784 kb
Host smart-8dfb0f56-d579-40e6-b8e2-e0e8eab01f2c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050905217 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.3050905217
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.590938240
Short name T640
Test name
Test status
Simulation time 65177400 ps
CPU time 132.46 seconds
Started Jun 04 02:56:39 PM PDT 24
Finished Jun 04 02:58:52 PM PDT 24
Peak memory 259692 kb
Host smart-0332fb6c-6d30-46e4-b7cf-36ddc8e0f8a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590938240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ot
p_reset.590938240
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.2684704827
Short name T541
Test name
Test status
Simulation time 173832900 ps
CPU time 31.12 seconds
Started Jun 04 02:56:38 PM PDT 24
Finished Jun 04 02:57:09 PM PDT 24
Peak memory 273056 kb
Host smart-c289d875-c0b7-44db-9f9f-b22151b573fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684704827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.2684704827
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.40987273
Short name T992
Test name
Test status
Simulation time 45416600 ps
CPU time 31.3 seconds
Started Jun 04 02:56:37 PM PDT 24
Finished Jun 04 02:57:09 PM PDT 24
Peak memory 275828 kb
Host smart-62a79a48-9982-4446-a972-b52a9353decf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40987273 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.40987273
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.4253668594
Short name T389
Test name
Test status
Simulation time 1681298900 ps
CPU time 76.27 seconds
Started Jun 04 02:56:38 PM PDT 24
Finished Jun 04 02:57:55 PM PDT 24
Peak memory 262348 kb
Host smart-eb90cdb5-6753-40a9-ab2b-680a24937026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253668594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.4253668594
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.2347078467
Short name T1038
Test name
Test status
Simulation time 35915800 ps
CPU time 144.67 seconds
Started Jun 04 02:56:32 PM PDT 24
Finished Jun 04 02:58:57 PM PDT 24
Peak memory 276236 kb
Host smart-933e62f0-efe6-4c64-a700-60d019adfcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347078467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.2347078467
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.2080534273
Short name T984
Test name
Test status
Simulation time 28293700 ps
CPU time 13.52 seconds
Started Jun 04 02:56:45 PM PDT 24
Finished Jun 04 02:56:59 PM PDT 24
Peak memory 257892 kb
Host smart-86f86983-0935-4453-a527-ed9740fa862b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080534273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
2080534273
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.2644433147
Short name T597
Test name
Test status
Simulation time 28275800 ps
CPU time 16.06 seconds
Started Jun 04 02:56:45 PM PDT 24
Finished Jun 04 02:57:01 PM PDT 24
Peak memory 275932 kb
Host smart-09773be3-678e-4834-8375-b6ed22797379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644433147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.2644433147
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.3961414565
Short name T755
Test name
Test status
Simulation time 27324755400 ps
CPU time 225.25 seconds
Started Jun 04 02:56:47 PM PDT 24
Finished Jun 04 03:00:33 PM PDT 24
Peak memory 262200 kb
Host smart-d59c312c-9fd9-41bd-a9e3-0e8eb8a9d552
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961414565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.3961414565
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.164572661
Short name T578
Test name
Test status
Simulation time 152153722000 ps
CPU time 299.02 seconds
Started Jun 04 02:56:51 PM PDT 24
Finished Jun 04 03:01:51 PM PDT 24
Peak memory 283992 kb
Host smart-f1f4dea3-46b7-4f39-9016-5d15d82884fb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164572661 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.164572661
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.2688990547
Short name T815
Test name
Test status
Simulation time 42137200 ps
CPU time 129.22 seconds
Started Jun 04 02:56:51 PM PDT 24
Finished Jun 04 02:59:01 PM PDT 24
Peak memory 259676 kb
Host smart-154622f4-1155-42ba-a033-2f7d529a20c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688990547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.2688990547
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.1907713793
Short name T629
Test name
Test status
Simulation time 89207200 ps
CPU time 31.22 seconds
Started Jun 04 02:56:47 PM PDT 24
Finished Jun 04 02:57:19 PM PDT 24
Peak memory 273124 kb
Host smart-4f5c2343-0ce9-4d11-9a7e-570e4ab4bc62
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907713793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.1907713793
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.4216011491
Short name T202
Test name
Test status
Simulation time 77854900 ps
CPU time 30.11 seconds
Started Jun 04 02:56:51 PM PDT 24
Finished Jun 04 02:57:22 PM PDT 24
Peak memory 274372 kb
Host smart-25520e0b-d525-42c2-ba5b-7073a9e5a357
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216011491 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.4216011491
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.4034103823
Short name T533
Test name
Test status
Simulation time 1554270800 ps
CPU time 57.37 seconds
Started Jun 04 02:56:47 PM PDT 24
Finished Jun 04 02:57:45 PM PDT 24
Peak memory 262812 kb
Host smart-2480aa0c-1b5f-4f44-ab43-16f3c6c0bfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034103823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.4034103823
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.667881550
Short name T585
Test name
Test status
Simulation time 56285200 ps
CPU time 75.3 seconds
Started Jun 04 02:56:45 PM PDT 24
Finished Jun 04 02:58:01 PM PDT 24
Peak memory 275844 kb
Host smart-68972264-c111-4408-92b4-8d350551d510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667881550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.667881550
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.2493015166
Short name T447
Test name
Test status
Simulation time 30005600 ps
CPU time 15.52 seconds
Started Jun 04 02:57:03 PM PDT 24
Finished Jun 04 02:57:19 PM PDT 24
Peak memory 275540 kb
Host smart-e5312dff-e75c-459e-aa95-e47b0693c0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493015166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2493015166
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.3503989757
Short name T968
Test name
Test status
Simulation time 36341900 ps
CPU time 22.19 seconds
Started Jun 04 02:56:54 PM PDT 24
Finished Jun 04 02:57:16 PM PDT 24
Peak memory 273048 kb
Host smart-f81db828-f87d-4000-a20d-c099cfb055e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503989757 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.3503989757
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.3077473647
Short name T601
Test name
Test status
Simulation time 12997439400 ps
CPU time 274.74 seconds
Started Jun 04 02:56:51 PM PDT 24
Finished Jun 04 03:01:26 PM PDT 24
Peak memory 262316 kb
Host smart-0d3a8226-855c-4f64-bd8d-277b4be78157
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077473647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.3077473647
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3856465458
Short name T615
Test name
Test status
Simulation time 12659227300 ps
CPU time 263.75 seconds
Started Jun 04 02:57:00 PM PDT 24
Finished Jun 04 03:01:24 PM PDT 24
Peak memory 284340 kb
Host smart-231a5ce1-a1a7-4870-8706-733402469db4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856465458 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.3856465458
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.761755774
Short name T473
Test name
Test status
Simulation time 46120200 ps
CPU time 31.19 seconds
Started Jun 04 02:56:55 PM PDT 24
Finished Jun 04 02:57:26 PM PDT 24
Peak memory 274176 kb
Host smart-f550c2aa-656e-49a6-9cd4-c4853df477ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761755774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_rw_evict.761755774
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.3711063397
Short name T749
Test name
Test status
Simulation time 37492700 ps
CPU time 31.54 seconds
Started Jun 04 02:56:55 PM PDT 24
Finished Jun 04 02:57:27 PM PDT 24
Peak memory 274328 kb
Host smart-d866e60a-6967-4b3c-b909-1562fb2ccd4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711063397 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.3711063397
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.3875331196
Short name T383
Test name
Test status
Simulation time 1856651000 ps
CPU time 69.13 seconds
Started Jun 04 02:56:56 PM PDT 24
Finished Jun 04 02:58:05 PM PDT 24
Peak memory 263044 kb
Host smart-f1b6de93-cb38-4687-954d-7315ef916a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875331196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.3875331196
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.46912560
Short name T988
Test name
Test status
Simulation time 18314600 ps
CPU time 75.73 seconds
Started Jun 04 02:56:45 PM PDT 24
Finished Jun 04 02:58:01 PM PDT 24
Peak memory 275884 kb
Host smart-2b9a5c24-2d7e-4831-a0f0-c2bf983c9cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46912560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.46912560
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.4068907154
Short name T873
Test name
Test status
Simulation time 61457700 ps
CPU time 13.7 seconds
Started Jun 04 02:57:04 PM PDT 24
Finished Jun 04 02:57:18 PM PDT 24
Peak memory 257896 kb
Host smart-1afe3473-274e-4022-8cf5-b961eca75499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068907154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
4068907154
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.403612305
Short name T458
Test name
Test status
Simulation time 26667800 ps
CPU time 15.63 seconds
Started Jun 04 02:57:03 PM PDT 24
Finished Jun 04 02:57:19 PM PDT 24
Peak memory 275896 kb
Host smart-afcdf624-41d6-47bc-860d-7deebc6d2751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403612305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.403612305
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.243118929
Short name T814
Test name
Test status
Simulation time 12095400 ps
CPU time 21.42 seconds
Started Jun 04 02:57:05 PM PDT 24
Finished Jun 04 02:57:27 PM PDT 24
Peak memory 264964 kb
Host smart-f62f7f2e-3b5b-46ce-8783-cee3a517ba1c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243118929 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.243118929
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.3137306032
Short name T1000
Test name
Test status
Simulation time 7457810300 ps
CPU time 116.33 seconds
Started Jun 04 02:57:05 PM PDT 24
Finished Jun 04 02:59:01 PM PDT 24
Peak memory 261792 kb
Host smart-aed6276a-0f8d-4689-8a7a-5867faf1972e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137306032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.3137306032
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.509507663
Short name T634
Test name
Test status
Simulation time 576834600 ps
CPU time 135.11 seconds
Started Jun 04 02:57:04 PM PDT 24
Finished Jun 04 02:59:20 PM PDT 24
Peak memory 289476 kb
Host smart-881fd6c7-6e47-42b0-b670-80ccac4df45f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509507663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flas
h_ctrl_intr_rd.509507663
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.622787562
Short name T350
Test name
Test status
Simulation time 12299018800 ps
CPU time 257.2 seconds
Started Jun 04 02:57:04 PM PDT 24
Finished Jun 04 03:01:22 PM PDT 24
Peak memory 284396 kb
Host smart-ccae39e4-a0c9-467a-b50c-776107b7ca27
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622787562 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.622787562
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.2355432492
Short name T148
Test name
Test status
Simulation time 36242600 ps
CPU time 108.47 seconds
Started Jun 04 02:57:04 PM PDT 24
Finished Jun 04 02:58:53 PM PDT 24
Peak memory 259772 kb
Host smart-d81e7737-69d1-44eb-a227-d395d6528478
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355432492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.2355432492
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.2987255165
Short name T1089
Test name
Test status
Simulation time 27005900 ps
CPU time 31.35 seconds
Started Jun 04 02:57:03 PM PDT 24
Finished Jun 04 02:57:34 PM PDT 24
Peak memory 273124 kb
Host smart-0cae1203-ed84-43d1-a3c0-a114b0883794
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987255165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.2987255165
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.3920230739
Short name T580
Test name
Test status
Simulation time 39589600 ps
CPU time 30.68 seconds
Started Jun 04 02:57:05 PM PDT 24
Finished Jun 04 02:57:36 PM PDT 24
Peak memory 268912 kb
Host smart-e41c70ec-347e-4b05-97e2-c682c08c2779
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920230739 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.3920230739
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.3011016349
Short name T388
Test name
Test status
Simulation time 5085895700 ps
CPU time 67.04 seconds
Started Jun 04 02:57:06 PM PDT 24
Finished Jun 04 02:58:14 PM PDT 24
Peak memory 262920 kb
Host smart-7ad7aab9-f109-4c3b-b4d1-8b376cf31e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011016349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.3011016349
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.3718889663
Short name T667
Test name
Test status
Simulation time 69821600 ps
CPU time 146.3 seconds
Started Jun 04 02:57:03 PM PDT 24
Finished Jun 04 02:59:30 PM PDT 24
Peak memory 276112 kb
Host smart-5df169d1-84c9-4bda-84ca-748df3eeed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718889663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.3718889663
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.1384508795
Short name T927
Test name
Test status
Simulation time 84658500 ps
CPU time 13.95 seconds
Started Jun 04 02:57:11 PM PDT 24
Finished Jun 04 02:57:26 PM PDT 24
Peak memory 258752 kb
Host smart-ff48a68e-30b5-4d72-bb36-2c1b9220909a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384508795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
1384508795
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.2007849
Short name T155
Test name
Test status
Simulation time 16441800 ps
CPU time 22.12 seconds
Started Jun 04 02:57:13 PM PDT 24
Finished Jun 04 02:57:35 PM PDT 24
Peak memory 273304 kb
Host smart-d326cb61-aa01-4ded-8e77-98e1ae980860
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007849 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 37.flash_ctrl_disable.2007849
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1327597077
Short name T728
Test name
Test status
Simulation time 12165141400 ps
CPU time 127.69 seconds
Started Jun 04 02:57:02 PM PDT 24
Finished Jun 04 02:59:11 PM PDT 24
Peak memory 262312 kb
Host smart-9cab0f27-5523-438a-beb3-b90bd90ada2a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327597077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.1327597077
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.2731995457
Short name T271
Test name
Test status
Simulation time 4861847800 ps
CPU time 129.6 seconds
Started Jun 04 02:57:11 PM PDT 24
Finished Jun 04 02:59:21 PM PDT 24
Peak memory 292696 kb
Host smart-f77d2a85-90ab-459d-9eeb-841adf53b7bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731995457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.2731995457
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.1236279142
Short name T347
Test name
Test status
Simulation time 232900726700 ps
CPU time 325.14 seconds
Started Jun 04 02:57:13 PM PDT 24
Finished Jun 04 03:02:38 PM PDT 24
Peak memory 292536 kb
Host smart-e29ababb-8663-44f1-8eae-e9e0341ed53b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236279142 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.1236279142
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.4030673713
Short name T1090
Test name
Test status
Simulation time 195255500 ps
CPU time 132.83 seconds
Started Jun 04 02:57:13 PM PDT 24
Finished Jun 04 02:59:26 PM PDT 24
Peak memory 260904 kb
Host smart-bfea2fca-3b21-4aec-b993-415c4eb83af3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030673713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.4030673713
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.2560672165
Short name T331
Test name
Test status
Simulation time 36989500 ps
CPU time 28.17 seconds
Started Jun 04 02:57:12 PM PDT 24
Finished Jun 04 02:57:41 PM PDT 24
Peak memory 273108 kb
Host smart-f95dca60-88ff-4d55-914c-04c1b3cda0a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560672165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.2560672165
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.776619888
Short name T106
Test name
Test status
Simulation time 107767500 ps
CPU time 31.83 seconds
Started Jun 04 02:57:11 PM PDT 24
Finished Jun 04 02:57:43 PM PDT 24
Peak memory 274408 kb
Host smart-94282585-11db-45f4-a0f9-1c02246bf291
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776619888 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.776619888
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.1626865891
Short name T382
Test name
Test status
Simulation time 8559680900 ps
CPU time 86.79 seconds
Started Jun 04 02:57:11 PM PDT 24
Finished Jun 04 02:58:38 PM PDT 24
Peak memory 261932 kb
Host smart-ada20305-2346-45f7-a168-9a306d029801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626865891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.1626865891
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.2391130231
Short name T883
Test name
Test status
Simulation time 52974700 ps
CPU time 170.94 seconds
Started Jun 04 02:57:04 PM PDT 24
Finished Jun 04 02:59:55 PM PDT 24
Peak memory 278952 kb
Host smart-7436727f-7f7f-46f8-8d70-ed6007bed377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391130231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.2391130231
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.304339242
Short name T1029
Test name
Test status
Simulation time 258635500 ps
CPU time 13.79 seconds
Started Jun 04 02:57:22 PM PDT 24
Finished Jun 04 02:57:36 PM PDT 24
Peak memory 264812 kb
Host smart-c0f4077c-41ac-42a7-b490-e1cfc2b5a9e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304339242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.304339242
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.1404271833
Short name T632
Test name
Test status
Simulation time 39182200 ps
CPU time 15.63 seconds
Started Jun 04 02:57:23 PM PDT 24
Finished Jun 04 02:57:39 PM PDT 24
Peak memory 275464 kb
Host smart-8551f0ec-0294-43d1-aa9e-6f695b015854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404271833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.1404271833
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.2662317692
Short name T837
Test name
Test status
Simulation time 159868200 ps
CPU time 21.86 seconds
Started Jun 04 02:57:24 PM PDT 24
Finished Jun 04 02:57:46 PM PDT 24
Peak memory 264876 kb
Host smart-ee8925c4-0ad3-4029-9a2c-58b2f5cf9a5c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662317692 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.2662317692
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.2562411812
Short name T678
Test name
Test status
Simulation time 21373744100 ps
CPU time 123.57 seconds
Started Jun 04 02:57:12 PM PDT 24
Finished Jun 04 02:59:16 PM PDT 24
Peak memory 262356 kb
Host smart-b9c89b45-6b33-44e7-a7dd-26187fabb558
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562411812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.2562411812
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.4291386804
Short name T885
Test name
Test status
Simulation time 1360228600 ps
CPU time 164.32 seconds
Started Jun 04 02:57:12 PM PDT 24
Finished Jun 04 02:59:57 PM PDT 24
Peak memory 292992 kb
Host smart-39a792d8-b2ae-45f1-9b56-7b24f689d798
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291386804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.4291386804
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.4180611976
Short name T1030
Test name
Test status
Simulation time 11110505800 ps
CPU time 173.26 seconds
Started Jun 04 02:57:12 PM PDT 24
Finished Jun 04 03:00:06 PM PDT 24
Peak memory 292952 kb
Host smart-bdad99de-ac5c-40ac-a02e-a54614798d77
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180611976 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.4180611976
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.3165323704
Short name T408
Test name
Test status
Simulation time 80455200 ps
CPU time 111.63 seconds
Started Jun 04 02:57:14 PM PDT 24
Finished Jun 04 02:59:06 PM PDT 24
Peak memory 259592 kb
Host smart-70099f94-c877-4361-9a8b-cef1a0407b75
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165323704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.3165323704
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.630741798
Short name T990
Test name
Test status
Simulation time 80330000 ps
CPU time 30.41 seconds
Started Jun 04 02:57:13 PM PDT 24
Finished Jun 04 02:57:44 PM PDT 24
Peak memory 273100 kb
Host smart-65e964e9-3c88-4734-8b8a-b9b32d07c7e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630741798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_rw_evict.630741798
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.1384504394
Short name T329
Test name
Test status
Simulation time 26724900 ps
CPU time 30.76 seconds
Started Jun 04 02:57:12 PM PDT 24
Finished Jun 04 02:57:43 PM PDT 24
Peak memory 268664 kb
Host smart-daf0b3d0-5603-4da9-8a95-88848c565e33
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384504394 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.1384504394
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.3197405302
Short name T662
Test name
Test status
Simulation time 11253345000 ps
CPU time 63.58 seconds
Started Jun 04 02:57:22 PM PDT 24
Finished Jun 04 02:58:26 PM PDT 24
Peak memory 264724 kb
Host smart-abc2da02-9b49-4d01-b6d4-517d6a0bd376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197405302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.3197405302
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.2971518560
Short name T795
Test name
Test status
Simulation time 35900700 ps
CPU time 145.17 seconds
Started Jun 04 02:57:10 PM PDT 24
Finished Jun 04 02:59:35 PM PDT 24
Peak memory 277272 kb
Host smart-9c31abda-4ce6-4a64-b10f-ff14f375f9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971518560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.2971518560
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.690213691
Short name T438
Test name
Test status
Simulation time 187463200 ps
CPU time 13.66 seconds
Started Jun 04 02:57:30 PM PDT 24
Finished Jun 04 02:57:44 PM PDT 24
Peak memory 264820 kb
Host smart-9188d1cc-101c-46c3-9c13-77555b77cb56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690213691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.690213691
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.2397185927
Short name T93
Test name
Test status
Simulation time 16754300 ps
CPU time 15.73 seconds
Started Jun 04 02:57:31 PM PDT 24
Finished Jun 04 02:57:47 PM PDT 24
Peak memory 275872 kb
Host smart-49bb2fab-1824-45b0-9e28-9d8c619cba4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397185927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2397185927
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.261815540
Short name T644
Test name
Test status
Simulation time 10811700 ps
CPU time 21.66 seconds
Started Jun 04 02:57:33 PM PDT 24
Finished Jun 04 02:57:55 PM PDT 24
Peak memory 264476 kb
Host smart-b88299c7-f3a8-4b5a-bebf-edd27624c242
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261815540 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.261815540
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.816928526
Short name T875
Test name
Test status
Simulation time 16742494700 ps
CPU time 121.71 seconds
Started Jun 04 02:57:22 PM PDT 24
Finished Jun 04 02:59:24 PM PDT 24
Peak memory 259828 kb
Host smart-bb906f24-c157-4d5f-9868-2cc0452e85d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816928526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_h
w_sec_otp.816928526
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.2544328057
Short name T860
Test name
Test status
Simulation time 612450600 ps
CPU time 153.01 seconds
Started Jun 04 02:57:22 PM PDT 24
Finished Jun 04 02:59:55 PM PDT 24
Peak memory 293024 kb
Host smart-096ecee3-9e72-4f8b-b882-7851a1b42805
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544328057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.2544328057
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2366700893
Short name T39
Test name
Test status
Simulation time 52211737900 ps
CPU time 319.13 seconds
Started Jun 04 02:57:22 PM PDT 24
Finished Jun 04 03:02:42 PM PDT 24
Peak memory 292932 kb
Host smart-ac3d5343-4a91-4118-b180-0399b2b51155
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366700893 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.2366700893
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.253980658
Short name T977
Test name
Test status
Simulation time 43321800 ps
CPU time 31.01 seconds
Started Jun 04 02:57:32 PM PDT 24
Finished Jun 04 02:58:03 PM PDT 24
Peak memory 273032 kb
Host smart-0d999149-3840-4d8a-844a-b43fb5c9cc75
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253980658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_rw_evict.253980658
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.3369147731
Short name T933
Test name
Test status
Simulation time 38009500 ps
CPU time 28.71 seconds
Started Jun 04 02:57:37 PM PDT 24
Finished Jun 04 02:58:06 PM PDT 24
Peak memory 274436 kb
Host smart-213f04f9-046b-43d7-9679-bb0488882bbb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369147731 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.3369147731
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.1885516629
Short name T838
Test name
Test status
Simulation time 1348176500 ps
CPU time 61.82 seconds
Started Jun 04 02:57:32 PM PDT 24
Finished Jun 04 02:58:34 PM PDT 24
Peak memory 263328 kb
Host smart-e4b580f1-6361-4508-9b19-90ef71323724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885516629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1885516629
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.1527633825
Short name T441
Test name
Test status
Simulation time 38239700 ps
CPU time 99.29 seconds
Started Jun 04 02:57:23 PM PDT 24
Finished Jun 04 02:59:02 PM PDT 24
Peak memory 275116 kb
Host smart-db1d2f76-1824-4ecf-9b6b-932d0e3ccf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527633825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1527633825
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.333386162
Short name T91
Test name
Test status
Simulation time 89680900 ps
CPU time 14.31 seconds
Started Jun 04 02:46:30 PM PDT 24
Finished Jun 04 02:46:45 PM PDT 24
Peak memory 264784 kb
Host smart-2873ab75-9e06-4df9-b058-0973f337748b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333386162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.333386162
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.2949040598
Short name T101
Test name
Test status
Simulation time 19600200 ps
CPU time 13.75 seconds
Started Jun 04 02:46:23 PM PDT 24
Finished Jun 04 02:46:37 PM PDT 24
Peak memory 261264 kb
Host smart-a7ad911d-7c4c-4569-9670-2fc966b76209
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949040598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.2949040598
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.4094612871
Short name T993
Test name
Test status
Simulation time 15785400 ps
CPU time 15.67 seconds
Started Jun 04 02:46:15 PM PDT 24
Finished Jun 04 02:46:31 PM PDT 24
Peak memory 274844 kb
Host smart-323b2199-96ab-40e6-81ff-6740ece194b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094612871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.4094612871
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.2325001760
Short name T864
Test name
Test status
Simulation time 125644500 ps
CPU time 104.55 seconds
Started Jun 04 02:45:58 PM PDT 24
Finished Jun 04 02:47:43 PM PDT 24
Peak memory 281132 kb
Host smart-4a282967-ed6c-4303-bab3-12e4c6b9f4ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325001760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.2325001760
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.2178515826
Short name T363
Test name
Test status
Simulation time 10612100 ps
CPU time 22.06 seconds
Started Jun 04 02:46:07 PM PDT 24
Finished Jun 04 02:46:29 PM PDT 24
Peak memory 273172 kb
Host smart-5a78c843-f7e2-4324-81da-1e7164d0c697
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178515826 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.2178515826
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.4205965553
Short name T608
Test name
Test status
Simulation time 3791976600 ps
CPU time 2503.07 seconds
Started Jun 04 02:45:37 PM PDT 24
Finished Jun 04 03:27:21 PM PDT 24
Peak memory 264856 kb
Host smart-0f76a53e-b3cb-42d6-a18a-568d482aeb48
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205965553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.4205965553
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.1069182611
Short name T163
Test name
Test status
Simulation time 5015734200 ps
CPU time 2867.01 seconds
Started Jun 04 02:45:37 PM PDT 24
Finished Jun 04 03:33:25 PM PDT 24
Peak memory 263720 kb
Host smart-74e5d64c-10b0-4ce9-ac54-0e23c9b24914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069182611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.1069182611
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.3749056393
Short name T1067
Test name
Test status
Simulation time 7664093700 ps
CPU time 932.96 seconds
Started Jun 04 02:45:37 PM PDT 24
Finished Jun 04 03:01:10 PM PDT 24
Peak memory 273028 kb
Host smart-8f8806dd-d4a9-4897-b705-b29c8dd28184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749056393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.3749056393
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.3237869844
Short name T53
Test name
Test status
Simulation time 178673100 ps
CPU time 27.29 seconds
Started Jun 04 02:45:36 PM PDT 24
Finished Jun 04 02:46:04 PM PDT 24
Peak memory 264868 kb
Host smart-d28800b7-e900-4e67-946b-1828a177c60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237869844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.3237869844
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.4168323192
Short name T168
Test name
Test status
Simulation time 6404918900 ps
CPU time 45.74 seconds
Started Jun 04 02:46:15 PM PDT 24
Finished Jun 04 02:47:01 PM PDT 24
Peak memory 261220 kb
Host smart-ae304835-265e-4204-acfb-2259c4ef918a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168323192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.4168323192
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.2539165030
Short name T1034
Test name
Test status
Simulation time 919491802200 ps
CPU time 2958.27 seconds
Started Jun 04 02:45:37 PM PDT 24
Finished Jun 04 03:34:56 PM PDT 24
Peak memory 264832 kb
Host smart-9d4def61-491d-4d4b-af9c-cde1f4de8450
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539165030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.2539165030
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.1761594617
Short name T151
Test name
Test status
Simulation time 681189207500 ps
CPU time 2179.99 seconds
Started Jun 04 02:45:29 PM PDT 24
Finished Jun 04 03:21:49 PM PDT 24
Peak memory 264672 kb
Host smart-b26b4030-6e7c-49a7-89b9-5e18ed0a1035
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761594617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.1761594617
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.2484908901
Short name T621
Test name
Test status
Simulation time 175478100 ps
CPU time 80.76 seconds
Started Jun 04 02:45:21 PM PDT 24
Finished Jun 04 02:46:43 PM PDT 24
Peak memory 262288 kb
Host smart-f1b7cebd-0559-44b5-809d-9ea18d287dd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2484908901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.2484908901
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.3485144568
Short name T735
Test name
Test status
Simulation time 10012728400 ps
CPU time 300.79 seconds
Started Jun 04 02:46:32 PM PDT 24
Finished Jun 04 02:51:33 PM PDT 24
Peak memory 323352 kb
Host smart-f3bdfd36-092f-4320-bc50-3ce9a1e09d13
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485144568 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.3485144568
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.2688582529
Short name T764
Test name
Test status
Simulation time 22841500 ps
CPU time 14.03 seconds
Started Jun 04 02:46:30 PM PDT 24
Finished Jun 04 02:46:44 PM PDT 24
Peak memory 264764 kb
Host smart-b89a3370-7d91-417d-a969-0d82c08fd1c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688582529 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.2688582529
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.3720686560
Short name T154
Test name
Test status
Simulation time 160193438100 ps
CPU time 854.93 seconds
Started Jun 04 02:45:28 PM PDT 24
Finished Jun 04 02:59:43 PM PDT 24
Peak memory 263000 kb
Host smart-559ff0e2-0e87-4a43-87ea-3568287fac8a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720686560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.3720686560
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.3696351186
Short name T985
Test name
Test status
Simulation time 20693375200 ps
CPU time 79.55 seconds
Started Jun 04 02:45:20 PM PDT 24
Finished Jun 04 02:46:40 PM PDT 24
Peak memory 262344 kb
Host smart-18f8867c-345f-467a-a813-2e0050f51d1a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696351186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.3696351186
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.3884871314
Short name T238
Test name
Test status
Simulation time 13388275000 ps
CPU time 716.19 seconds
Started Jun 04 02:46:01 PM PDT 24
Finished Jun 04 02:57:58 PM PDT 24
Peak memory 326492 kb
Host smart-099c699f-6155-4f73-8546-51684ce96a91
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884871314 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.3884871314
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.1784090533
Short name T463
Test name
Test status
Simulation time 747556900 ps
CPU time 140.16 seconds
Started Jun 04 02:46:01 PM PDT 24
Finished Jun 04 02:48:21 PM PDT 24
Peak memory 292856 kb
Host smart-1f601092-a768-4adc-8712-77e9b20c5475
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784090533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.1784090533
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.2306339022
Short name T1014
Test name
Test status
Simulation time 5894511400 ps
CPU time 134.06 seconds
Started Jun 04 02:46:00 PM PDT 24
Finished Jun 04 02:48:14 PM PDT 24
Peak memory 291636 kb
Host smart-c3d5d409-9758-4509-a314-f91d88e86472
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306339022 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.2306339022
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.230230410
Short name T694
Test name
Test status
Simulation time 2426439500 ps
CPU time 71.81 seconds
Started Jun 04 02:46:01 PM PDT 24
Finished Jun 04 02:47:13 PM PDT 24
Peak memory 259808 kb
Host smart-3e17986b-844c-4ec7-8bfe-b49648891388
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230230410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_intr_wr.230230410
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3194775069
Short name T437
Test name
Test status
Simulation time 237917369200 ps
CPU time 353.64 seconds
Started Jun 04 02:46:02 PM PDT 24
Finished Jun 04 02:51:56 PM PDT 24
Peak memory 259524 kb
Host smart-2eddfbcd-a662-4dae-8e6f-676dab1849ac
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319
4775069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3194775069
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.3463971364
Short name T425
Test name
Test status
Simulation time 6792851200 ps
CPU time 65.01 seconds
Started Jun 04 02:45:39 PM PDT 24
Finished Jun 04 02:46:44 PM PDT 24
Peak memory 260324 kb
Host smart-ffb77bd4-d105-4b7d-ad19-cc309cbd7e4a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463971364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.3463971364
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.3584538764
Short name T477
Test name
Test status
Simulation time 48435500 ps
CPU time 13.43 seconds
Started Jun 04 02:46:23 PM PDT 24
Finished Jun 04 02:46:37 PM PDT 24
Peak memory 260068 kb
Host smart-1144842e-8bb7-44fb-9bd3-d068be94388a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584538764 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.3584538764
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.3690464345
Short name T1058
Test name
Test status
Simulation time 40993500 ps
CPU time 109.14 seconds
Started Jun 04 02:45:29 PM PDT 24
Finished Jun 04 02:47:18 PM PDT 24
Peak memory 264240 kb
Host smart-cbbb2c28-9ec6-4e5a-9b2c-6e7e0fb6e7ad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690464345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.3690464345
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.1222273982
Short name T822
Test name
Test status
Simulation time 1901185100 ps
CPU time 214.61 seconds
Started Jun 04 02:45:59 PM PDT 24
Finished Jun 04 02:49:34 PM PDT 24
Peak memory 281208 kb
Host smart-951f0a28-5d84-4008-8dab-1af50c95b292
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222273982 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.1222273982
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.1774230498
Short name T166
Test name
Test status
Simulation time 46280100 ps
CPU time 200.48 seconds
Started Jun 04 02:45:20 PM PDT 24
Finished Jun 04 02:48:41 PM PDT 24
Peak memory 261504 kb
Host smart-c0a615e1-a134-46b6-a5b4-760aa65b706d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774230498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1774230498
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.990586819
Short name T8
Test name
Test status
Simulation time 15085600 ps
CPU time 13.86 seconds
Started Jun 04 02:46:14 PM PDT 24
Finished Jun 04 02:46:28 PM PDT 24
Peak memory 261888 kb
Host smart-8349b7a0-b3df-4769-9849-8865d99182a1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990586819 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.990586819
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.1266844666
Short name T564
Test name
Test status
Simulation time 90652800 ps
CPU time 14.56 seconds
Started Jun 04 02:46:07 PM PDT 24
Finished Jun 04 02:46:22 PM PDT 24
Peak memory 263948 kb
Host smart-39f15be9-6800-4e69-9481-54e690d42a86
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266844666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_res
et.1266844666
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.971684234
Short name T109
Test name
Test status
Simulation time 3026248600 ps
CPU time 378.27 seconds
Started Jun 04 02:45:21 PM PDT 24
Finished Jun 04 02:51:40 PM PDT 24
Peak memory 282360 kb
Host smart-33cb23be-c54c-47fc-a6ff-ffb99332b485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971684234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.971684234
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.3179303620
Short name T185
Test name
Test status
Simulation time 3688415900 ps
CPU time 150.46 seconds
Started Jun 04 02:45:25 PM PDT 24
Finished Jun 04 02:47:56 PM PDT 24
Peak memory 264164 kb
Host smart-5e10eae6-4286-4e6a-b59d-a7bf042147f4
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3179303620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.3179303620
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.4184733686
Short name T825
Test name
Test status
Simulation time 79990700 ps
CPU time 35.19 seconds
Started Jun 04 02:46:07 PM PDT 24
Finished Jun 04 02:46:43 PM PDT 24
Peak memory 273136 kb
Host smart-fa06e39d-5f67-40d0-9caa-eea4df0c87b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184733686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.4184733686
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.237168193
Short name T666
Test name
Test status
Simulation time 70633900 ps
CPU time 22.08 seconds
Started Jun 04 02:46:00 PM PDT 24
Finished Jun 04 02:46:22 PM PDT 24
Peak memory 264920 kb
Host smart-c97e9e74-88b8-432a-9e6d-b9ed2e2d911b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237168193 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.237168193
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.580999184
Short name T538
Test name
Test status
Simulation time 693643600 ps
CPU time 119.72 seconds
Started Jun 04 02:45:44 PM PDT 24
Finished Jun 04 02:47:44 PM PDT 24
Peak memory 280728 kb
Host smart-4eec2b1e-6427-4a08-9636-455caa53ad32
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580999184 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.flash_ctrl_ro.580999184
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.2740248544
Short name T894
Test name
Test status
Simulation time 1242395400 ps
CPU time 175.93 seconds
Started Jun 04 02:45:51 PM PDT 24
Finished Jun 04 02:48:47 PM PDT 24
Peak memory 293976 kb
Host smart-83c82274-414f-41c1-8dc9-c3c92a906959
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740248544 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.2740248544
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.702194825
Short name T562
Test name
Test status
Simulation time 9574981300 ps
CPU time 724.63 seconds
Started Jun 04 02:45:44 PM PDT 24
Finished Jun 04 02:57:49 PM PDT 24
Peak memory 309248 kb
Host smart-3a7ebffe-d1eb-44ca-88c8-fe2e21f00f55
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702194825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.flash_ctrl_rw.702194825
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_derr.3337414488
Short name T636
Test name
Test status
Simulation time 5044816900 ps
CPU time 712 seconds
Started Jun 04 02:46:00 PM PDT 24
Finished Jun 04 02:57:52 PM PDT 24
Peak memory 329736 kb
Host smart-5d0fa041-64cc-451c-bcde-420192d300a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337414488 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_rw_derr.3337414488
Directory /workspace/4.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.2731581984
Short name T446
Test name
Test status
Simulation time 32603800 ps
CPU time 31.01 seconds
Started Jun 04 02:46:10 PM PDT 24
Finished Jun 04 02:46:41 PM PDT 24
Peak memory 266960 kb
Host smart-3f1f22de-036f-4d17-b620-be5fea713459
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731581984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_rw_evict.2731581984
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.1685993796
Short name T952
Test name
Test status
Simulation time 16325357100 ps
CPU time 668.14 seconds
Started Jun 04 02:45:51 PM PDT 24
Finished Jun 04 02:56:59 PM PDT 24
Peak memory 312764 kb
Host smart-06ed8d1a-2ac1-4149-ab49-ed55a54ca363
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685993796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_s
err.1685993796
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.1736221008
Short name T707
Test name
Test status
Simulation time 2036712800 ps
CPU time 69.72 seconds
Started Jun 04 02:46:09 PM PDT 24
Finished Jun 04 02:47:19 PM PDT 24
Peak memory 262900 kb
Host smart-ddf9da79-0329-4861-99c3-37967f6943bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736221008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.1736221008
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.1916582021
Short name T567
Test name
Test status
Simulation time 2916957100 ps
CPU time 92.98 seconds
Started Jun 04 02:45:52 PM PDT 24
Finished Jun 04 02:47:26 PM PDT 24
Peak memory 264884 kb
Host smart-78845fe9-f64b-4a7e-a214-fdb99a0cb564
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916582021 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.1916582021
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.2146258038
Short name T1055
Test name
Test status
Simulation time 1663447000 ps
CPU time 97.77 seconds
Started Jun 04 02:45:52 PM PDT 24
Finished Jun 04 02:47:30 PM PDT 24
Peak memory 273120 kb
Host smart-d33dbfa8-c580-4fd5-823d-8641114155ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146258038 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_serr_counter.2146258038
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.1324613350
Short name T505
Test name
Test status
Simulation time 24680100 ps
CPU time 74.74 seconds
Started Jun 04 02:45:14 PM PDT 24
Finished Jun 04 02:46:29 PM PDT 24
Peak memory 274772 kb
Host smart-ff7277e5-fc2c-428d-b8cb-8850e8f6ae57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324613350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.1324613350
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.2086956172
Short name T725
Test name
Test status
Simulation time 15008700 ps
CPU time 25.05 seconds
Started Jun 04 02:45:12 PM PDT 24
Finished Jun 04 02:45:38 PM PDT 24
Peak memory 258760 kb
Host smart-c512e2ff-6a24-4706-a13e-c476e4423c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086956172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.2086956172
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.2514465629
Short name T855
Test name
Test status
Simulation time 1126616400 ps
CPU time 1282.96 seconds
Started Jun 04 02:46:09 PM PDT 24
Finished Jun 04 03:07:33 PM PDT 24
Peak memory 286308 kb
Host smart-f6981e44-4392-4160-a562-26bce1e27fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514465629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.2514465629
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.2678643977
Short name T1017
Test name
Test status
Simulation time 156097600 ps
CPU time 26.5 seconds
Started Jun 04 02:45:25 PM PDT 24
Finished Jun 04 02:45:52 PM PDT 24
Peak memory 257888 kb
Host smart-d1e14554-1561-48c8-95d9-09deb8fb5a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678643977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2678643977
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.2830634937
Short name T619
Test name
Test status
Simulation time 2772011100 ps
CPU time 207.3 seconds
Started Jun 04 02:45:43 PM PDT 24
Finished Jun 04 02:49:11 PM PDT 24
Peak memory 258712 kb
Host smart-4cabb486-c057-4697-b77c-5fa689b04537
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830634937 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_wo.2830634937
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.1152581165
Short name T675
Test name
Test status
Simulation time 155210200 ps
CPU time 13.64 seconds
Started Jun 04 02:57:33 PM PDT 24
Finished Jun 04 02:57:47 PM PDT 24
Peak memory 257836 kb
Host smart-892e9bc9-d662-431d-9203-c58124c4d1e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152581165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
1152581165
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.4173493949
Short name T744
Test name
Test status
Simulation time 24353100 ps
CPU time 15.99 seconds
Started Jun 04 02:57:33 PM PDT 24
Finished Jun 04 02:57:50 PM PDT 24
Peak memory 274872 kb
Host smart-94330b35-bcb2-4ffa-999b-75c833473343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173493949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.4173493949
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.1167523464
Short name T557
Test name
Test status
Simulation time 31842500 ps
CPU time 20.64 seconds
Started Jun 04 02:57:32 PM PDT 24
Finished Jun 04 02:57:53 PM PDT 24
Peak memory 273132 kb
Host smart-a7031014-be48-4e10-9e2c-431fa735034d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167523464 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.1167523464
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.1355301391
Short name T940
Test name
Test status
Simulation time 1433810900 ps
CPU time 49.75 seconds
Started Jun 04 02:57:30 PM PDT 24
Finished Jun 04 02:58:21 PM PDT 24
Peak memory 262288 kb
Host smart-b9a79801-6c0e-40c9-9c88-b8a2ed1b6040
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355301391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.1355301391
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.4212960960
Short name T758
Test name
Test status
Simulation time 39068600 ps
CPU time 110.48 seconds
Started Jun 04 02:57:34 PM PDT 24
Finished Jun 04 02:59:25 PM PDT 24
Peak memory 260660 kb
Host smart-7a900a4c-d665-42bf-ac4f-4dc258deb8fb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212960960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.4212960960
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.2065795043
Short name T978
Test name
Test status
Simulation time 28152900 ps
CPU time 215.02 seconds
Started Jun 04 02:57:31 PM PDT 24
Finished Jun 04 03:01:07 PM PDT 24
Peak memory 279568 kb
Host smart-b581e2dc-aeee-4842-8a12-24841ffa3c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065795043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2065795043
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.2563965085
Short name T727
Test name
Test status
Simulation time 62985200 ps
CPU time 14.06 seconds
Started Jun 04 02:57:36 PM PDT 24
Finished Jun 04 02:57:51 PM PDT 24
Peak memory 264768 kb
Host smart-74f6bf36-f359-4147-8749-5040f65958cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563965085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
2563965085
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.4132763886
Short name T480
Test name
Test status
Simulation time 31187200 ps
CPU time 15.61 seconds
Started Jun 04 02:57:31 PM PDT 24
Finished Jun 04 02:57:47 PM PDT 24
Peak memory 275940 kb
Host smart-1e36f9ea-58ff-4294-a8d0-280d12e00cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132763886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.4132763886
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.1240161537
Short name T74
Test name
Test status
Simulation time 12265300 ps
CPU time 21.88 seconds
Started Jun 04 02:57:33 PM PDT 24
Finished Jun 04 02:57:56 PM PDT 24
Peak memory 273136 kb
Host smart-9155570e-da75-445b-97b2-2b19a3a2e4db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240161537 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.1240161537
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3158166291
Short name T445
Test name
Test status
Simulation time 6742836300 ps
CPU time 77.24 seconds
Started Jun 04 02:57:31 PM PDT 24
Finished Jun 04 02:58:48 PM PDT 24
Peak memory 262340 kb
Host smart-c92520ed-37b7-40c4-a4ef-f8b4652d878e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158166291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.3158166291
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.3924223925
Short name T819
Test name
Test status
Simulation time 462335400 ps
CPU time 132.59 seconds
Started Jun 04 02:57:32 PM PDT 24
Finished Jun 04 02:59:45 PM PDT 24
Peak memory 259764 kb
Host smart-1164d385-6192-4bbb-92af-e23eed7da566
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924223925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.3924223925
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.3767185352
Short name T118
Test name
Test status
Simulation time 763238800 ps
CPU time 55.5 seconds
Started Jun 04 02:57:37 PM PDT 24
Finished Jun 04 02:58:33 PM PDT 24
Peak memory 262792 kb
Host smart-98395137-7e5e-45b3-8cfb-66aeb846878f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767185352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.3767185352
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.4112350008
Short name T686
Test name
Test status
Simulation time 162563600 ps
CPU time 97.63 seconds
Started Jun 04 02:57:33 PM PDT 24
Finished Jun 04 02:59:11 PM PDT 24
Peak memory 276572 kb
Host smart-a0e37ae4-642a-459e-9495-603ac16a5ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112350008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.4112350008
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.3307726869
Short name T849
Test name
Test status
Simulation time 90478300 ps
CPU time 13.92 seconds
Started Jun 04 02:57:42 PM PDT 24
Finished Jun 04 02:57:57 PM PDT 24
Peak memory 264764 kb
Host smart-f0c46496-9612-4cb1-92e2-59ab3a631d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307726869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
3307726869
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.3735663588
Short name T563
Test name
Test status
Simulation time 23841300 ps
CPU time 15.75 seconds
Started Jun 04 02:57:41 PM PDT 24
Finished Jun 04 02:57:58 PM PDT 24
Peak memory 275404 kb
Host smart-4664a513-5bf2-4442-9a0c-4eb722d16549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735663588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.3735663588
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.1940305334
Short name T364
Test name
Test status
Simulation time 46862400 ps
CPU time 21.27 seconds
Started Jun 04 02:57:40 PM PDT 24
Finished Jun 04 02:58:02 PM PDT 24
Peak memory 273212 kb
Host smart-a90c0e2a-b7c9-4f0e-8541-18a00b626f77
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940305334 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.1940305334
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.2287350748
Short name T976
Test name
Test status
Simulation time 15847250900 ps
CPU time 76.77 seconds
Started Jun 04 02:57:43 PM PDT 24
Finished Jun 04 02:59:00 PM PDT 24
Peak memory 262384 kb
Host smart-80a15794-8298-403c-9d07-cbbf6453a263
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287350748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.2287350748
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.1002596889
Short name T692
Test name
Test status
Simulation time 37475000 ps
CPU time 109.22 seconds
Started Jun 04 02:57:41 PM PDT 24
Finished Jun 04 02:59:31 PM PDT 24
Peak memory 264384 kb
Host smart-98bd956b-75fc-4985-87ff-e7002097015f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002596889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.1002596889
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.2076341276
Short name T832
Test name
Test status
Simulation time 2054344300 ps
CPU time 68.41 seconds
Started Jun 04 02:57:42 PM PDT 24
Finished Jun 04 02:58:51 PM PDT 24
Peak memory 262400 kb
Host smart-4d112488-2924-4580-b895-4d3b843b8db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076341276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.2076341276
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.3871012659
Short name T1077
Test name
Test status
Simulation time 34318600 ps
CPU time 145.45 seconds
Started Jun 04 02:57:42 PM PDT 24
Finished Jun 04 03:00:08 PM PDT 24
Peak memory 276148 kb
Host smart-f694d410-9e3e-48a3-84ac-f279a0132772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871012659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.3871012659
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.2060021765
Short name T582
Test name
Test status
Simulation time 28266700 ps
CPU time 13.93 seconds
Started Jun 04 02:57:42 PM PDT 24
Finished Jun 04 02:57:57 PM PDT 24
Peak memory 257856 kb
Host smart-b19b1620-df91-4828-b766-7627bf934271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060021765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
2060021765
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.1108599653
Short name T573
Test name
Test status
Simulation time 16578300 ps
CPU time 15.33 seconds
Started Jun 04 02:57:42 PM PDT 24
Finished Jun 04 02:57:58 PM PDT 24
Peak memory 275568 kb
Host smart-ccd369f4-ef99-4c9f-86e1-6714175b2819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108599653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.1108599653
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.3151962327
Short name T811
Test name
Test status
Simulation time 10323300 ps
CPU time 21.38 seconds
Started Jun 04 02:57:41 PM PDT 24
Finished Jun 04 02:58:03 PM PDT 24
Peak memory 273104 kb
Host smart-6e100139-985e-43cc-a405-b695ee4dda47
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151962327 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.3151962327
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.841196948
Short name T482
Test name
Test status
Simulation time 2458826200 ps
CPU time 95.81 seconds
Started Jun 04 02:57:41 PM PDT 24
Finished Jun 04 02:59:17 PM PDT 24
Peak memory 262200 kb
Host smart-edbd70c4-d674-416d-a401-8a3540f0a845
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841196948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_h
w_sec_otp.841196948
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.1985042703
Short name T144
Test name
Test status
Simulation time 190816000 ps
CPU time 111.87 seconds
Started Jun 04 02:57:40 PM PDT 24
Finished Jun 04 02:59:32 PM PDT 24
Peak memory 259716 kb
Host smart-4ef7715b-bc6c-4184-a121-8e6ab2d816d8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985042703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.1985042703
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.3675555978
Short name T953
Test name
Test status
Simulation time 2398064400 ps
CPU time 69.77 seconds
Started Jun 04 02:57:41 PM PDT 24
Finished Jun 04 02:58:52 PM PDT 24
Peak memory 262716 kb
Host smart-ddc0529b-a97a-4887-a450-b24cf770e113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675555978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.3675555978
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.547862425
Short name T660
Test name
Test status
Simulation time 26358500 ps
CPU time 52.67 seconds
Started Jun 04 02:57:40 PM PDT 24
Finished Jun 04 02:58:34 PM PDT 24
Peak memory 270472 kb
Host smart-96573ec1-91de-4bd7-8519-d06ae8a78ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547862425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.547862425
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.1370073392
Short name T791
Test name
Test status
Simulation time 335422800 ps
CPU time 13.82 seconds
Started Jun 04 02:57:47 PM PDT 24
Finished Jun 04 02:58:01 PM PDT 24
Peak memory 264836 kb
Host smart-548fc5de-7a45-4ca7-b48a-a8b7f577baf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370073392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
1370073392
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.1423405332
Short name T703
Test name
Test status
Simulation time 38770700 ps
CPU time 15.61 seconds
Started Jun 04 02:57:48 PM PDT 24
Finished Jun 04 02:58:04 PM PDT 24
Peak memory 275520 kb
Host smart-e5b4540b-0b60-4132-b892-0f10a77507ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423405332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.1423405332
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.1475429059
Short name T157
Test name
Test status
Simulation time 13833100 ps
CPU time 22.04 seconds
Started Jun 04 02:57:47 PM PDT 24
Finished Jun 04 02:58:10 PM PDT 24
Peak memory 280020 kb
Host smart-ea932552-b9b1-4b9f-ba4d-93cd518f19a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475429059 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.1475429059
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.1532278771
Short name T914
Test name
Test status
Simulation time 10954269100 ps
CPU time 94.03 seconds
Started Jun 04 02:57:47 PM PDT 24
Finished Jun 04 02:59:21 PM PDT 24
Peak memory 262232 kb
Host smart-8945211a-c613-4864-b7d1-7ad9f5adba4e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532278771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.1532278771
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.2332076199
Short name T880
Test name
Test status
Simulation time 112375800 ps
CPU time 110.36 seconds
Started Jun 04 02:57:50 PM PDT 24
Finished Jun 04 02:59:40 PM PDT 24
Peak memory 260944 kb
Host smart-5d5c35e0-18cd-44b8-8554-8b769338af6f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332076199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.2332076199
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.2568285066
Short name T752
Test name
Test status
Simulation time 773943100 ps
CPU time 76.07 seconds
Started Jun 04 02:57:48 PM PDT 24
Finished Jun 04 02:59:05 PM PDT 24
Peak memory 263380 kb
Host smart-54657590-cf84-42c4-b30c-87d566e64d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568285066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.2568285066
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.3006397089
Short name T650
Test name
Test status
Simulation time 51695900 ps
CPU time 122.04 seconds
Started Jun 04 02:57:48 PM PDT 24
Finished Jun 04 02:59:50 PM PDT 24
Peak memory 276868 kb
Host smart-bd6f2692-2c65-4d70-b9ef-2a5f1e6330b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006397089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.3006397089
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.678066649
Short name T887
Test name
Test status
Simulation time 46727900 ps
CPU time 13.58 seconds
Started Jun 04 02:57:57 PM PDT 24
Finished Jun 04 02:58:11 PM PDT 24
Peak memory 264784 kb
Host smart-45a3d927-29f9-44fc-bae0-fa131008d8a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678066649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.678066649
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.812243529
Short name T406
Test name
Test status
Simulation time 16686400 ps
CPU time 16 seconds
Started Jun 04 02:57:59 PM PDT 24
Finished Jun 04 02:58:16 PM PDT 24
Peak memory 276012 kb
Host smart-faa46e78-599a-4a14-b8f2-de689b6f8bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812243529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.812243529
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.1774035123
Short name T73
Test name
Test status
Simulation time 38357300 ps
CPU time 22.14 seconds
Started Jun 04 02:57:56 PM PDT 24
Finished Jun 04 02:58:19 PM PDT 24
Peak memory 264824 kb
Host smart-b1952403-d532-4e70-9fed-0bbdb3362083
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774035123 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.1774035123
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.2825436581
Short name T315
Test name
Test status
Simulation time 6159336000 ps
CPU time 56.24 seconds
Started Jun 04 02:57:49 PM PDT 24
Finished Jun 04 02:58:45 PM PDT 24
Peak memory 259780 kb
Host smart-dbc761ac-72be-40e3-b400-f69b5ccbb499
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825436581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.2825436581
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.3432205178
Short name T508
Test name
Test status
Simulation time 131332300 ps
CPU time 131.76 seconds
Started Jun 04 02:57:48 PM PDT 24
Finished Jun 04 03:00:00 PM PDT 24
Peak memory 259840 kb
Host smart-59dfe06f-76e0-4ace-abf3-a3b0708a7fc0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432205178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.3432205178
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.2288938431
Short name T932
Test name
Test status
Simulation time 3850118700 ps
CPU time 69.1 seconds
Started Jun 04 02:57:59 PM PDT 24
Finished Jun 04 02:59:08 PM PDT 24
Peak memory 263024 kb
Host smart-51e13e16-77d6-4707-8d85-083f8c37ae71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288938431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.2288938431
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.1957767456
Short name T858
Test name
Test status
Simulation time 25498400 ps
CPU time 147.39 seconds
Started Jun 04 02:57:48 PM PDT 24
Finished Jun 04 03:00:16 PM PDT 24
Peak memory 278012 kb
Host smart-e921e8d8-97f6-47a6-9a50-ca225d492805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957767456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1957767456
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.1460814546
Short name T396
Test name
Test status
Simulation time 85134900 ps
CPU time 14.04 seconds
Started Jun 04 02:57:56 PM PDT 24
Finished Jun 04 02:58:10 PM PDT 24
Peak memory 264724 kb
Host smart-7ea13724-0fe8-48bc-89dc-4b0d6f820867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460814546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
1460814546
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.2152513286
Short name T850
Test name
Test status
Simulation time 48676700 ps
CPU time 15.56 seconds
Started Jun 04 02:57:59 PM PDT 24
Finished Jun 04 02:58:16 PM PDT 24
Peak memory 275564 kb
Host smart-0c9f4343-521d-4ddd-b572-0a4994c2d83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152513286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.2152513286
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.3095803500
Short name T781
Test name
Test status
Simulation time 12950900 ps
CPU time 20.36 seconds
Started Jun 04 02:57:56 PM PDT 24
Finished Jun 04 02:58:17 PM PDT 24
Peak memory 264940 kb
Host smart-7530656a-eab9-4804-b717-329b056d9bab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095803500 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.3095803500
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.3351329978
Short name T318
Test name
Test status
Simulation time 37380689900 ps
CPU time 244.83 seconds
Started Jun 04 02:57:56 PM PDT 24
Finished Jun 04 03:02:01 PM PDT 24
Peak memory 262392 kb
Host smart-ba5c2d7f-aa10-4407-8d36-9d8583d6d044
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351329978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.3351329978
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.2509374535
Short name T854
Test name
Test status
Simulation time 74523100 ps
CPU time 110.07 seconds
Started Jun 04 02:58:00 PM PDT 24
Finished Jun 04 02:59:50 PM PDT 24
Peak memory 260960 kb
Host smart-eea471b1-a294-42fc-82bf-aef7c38f2bc2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509374535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.2509374535
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.320795245
Short name T390
Test name
Test status
Simulation time 1528692400 ps
CPU time 55.09 seconds
Started Jun 04 02:57:57 PM PDT 24
Finished Jun 04 02:58:53 PM PDT 24
Peak memory 262160 kb
Host smart-ed955e31-34c4-4a5c-9f30-553c3221f127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320795245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.320795245
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.2724261772
Short name T897
Test name
Test status
Simulation time 62569600 ps
CPU time 51.57 seconds
Started Jun 04 02:57:56 PM PDT 24
Finished Jun 04 02:58:48 PM PDT 24
Peak memory 270360 kb
Host smart-ba6922d2-9331-4440-8a43-2e73c0d0b57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724261772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.2724261772
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.2440832132
Short name T426
Test name
Test status
Simulation time 70298000 ps
CPU time 13.72 seconds
Started Jun 04 02:58:04 PM PDT 24
Finished Jun 04 02:58:19 PM PDT 24
Peak memory 264792 kb
Host smart-82ee5dad-bbb0-4203-91b8-a85db8b2a68e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440832132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
2440832132
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.4143557811
Short name T788
Test name
Test status
Simulation time 16428700 ps
CPU time 13.16 seconds
Started Jun 04 02:58:05 PM PDT 24
Finished Jun 04 02:58:18 PM PDT 24
Peak memory 275812 kb
Host smart-f3eaa716-0a80-4770-a67c-804de7a196a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143557811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.4143557811
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.3029853399
Short name T598
Test name
Test status
Simulation time 10421000 ps
CPU time 22.02 seconds
Started Jun 04 02:58:06 PM PDT 24
Finished Jun 04 02:58:28 PM PDT 24
Peak memory 273148 kb
Host smart-a3171af6-b89a-46b9-999b-12306cf120bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029853399 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.3029853399
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.1961072611
Short name T510
Test name
Test status
Simulation time 3901851000 ps
CPU time 78.45 seconds
Started Jun 04 02:57:58 PM PDT 24
Finished Jun 04 02:59:17 PM PDT 24
Peak memory 262404 kb
Host smart-2859e50e-b106-4bde-80f2-fdd9f5356db3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961072611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.1961072611
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.306784231
Short name T78
Test name
Test status
Simulation time 40165000 ps
CPU time 130.61 seconds
Started Jun 04 02:57:56 PM PDT 24
Finished Jun 04 03:00:07 PM PDT 24
Peak memory 260680 kb
Host smart-4f9bceaf-92c6-417b-884a-d70ee07ab7da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306784231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ot
p_reset.306784231
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.4059557198
Short name T750
Test name
Test status
Simulation time 9433831800 ps
CPU time 82.95 seconds
Started Jun 04 02:58:07 PM PDT 24
Finished Jun 04 02:59:31 PM PDT 24
Peak memory 261524 kb
Host smart-e5648b1d-17e1-4209-97ab-cbfd79dd9de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059557198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.4059557198
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.3918973010
Short name T616
Test name
Test status
Simulation time 29224900 ps
CPU time 76.78 seconds
Started Jun 04 02:57:57 PM PDT 24
Finished Jun 04 02:59:14 PM PDT 24
Peak memory 274672 kb
Host smart-627510f7-731a-4932-b7af-89e1eac7a381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918973010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3918973010
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.761696286
Short name T536
Test name
Test status
Simulation time 244691900 ps
CPU time 13.89 seconds
Started Jun 04 02:58:05 PM PDT 24
Finished Jun 04 02:58:20 PM PDT 24
Peak memory 264800 kb
Host smart-3db2c5ce-fff8-408d-b2ba-d21a47a4ded7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761696286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.761696286
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.1964355677
Short name T1061
Test name
Test status
Simulation time 53843300 ps
CPU time 15.51 seconds
Started Jun 04 02:58:06 PM PDT 24
Finished Jun 04 02:58:22 PM PDT 24
Peak memory 275868 kb
Host smart-ea5995d3-b0d7-4c93-a41a-f7ff64b6c86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964355677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.1964355677
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.2882018361
Short name T544
Test name
Test status
Simulation time 11413300 ps
CPU time 21.63 seconds
Started Jun 04 02:58:06 PM PDT 24
Finished Jun 04 02:58:29 PM PDT 24
Peak memory 273152 kb
Host smart-35da20f1-7ee2-47bb-92ea-1b09079c44c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882018361 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.2882018361
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.1031608733
Short name T1007
Test name
Test status
Simulation time 8203028100 ps
CPU time 149.42 seconds
Started Jun 04 02:58:05 PM PDT 24
Finished Jun 04 03:00:35 PM PDT 24
Peak memory 262420 kb
Host smart-e1c434c8-d817-4dc6-88f2-12ed3fc9f725
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031608733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.1031608733
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.3900985292
Short name T1081
Test name
Test status
Simulation time 37701300 ps
CPU time 112.36 seconds
Started Jun 04 02:58:07 PM PDT 24
Finished Jun 04 03:00:00 PM PDT 24
Peak memory 259632 kb
Host smart-f5c40807-1f62-45e1-ae1f-4c7794fac986
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900985292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.3900985292
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.2454960918
Short name T635
Test name
Test status
Simulation time 4475779700 ps
CPU time 55.14 seconds
Started Jun 04 02:58:07 PM PDT 24
Finished Jun 04 02:59:02 PM PDT 24
Peak memory 263592 kb
Host smart-7dbdd456-cb20-427b-9118-b06fa69ee298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454960918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.2454960918
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.960166749
Short name T576
Test name
Test status
Simulation time 39632500 ps
CPU time 193.39 seconds
Started Jun 04 02:58:05 PM PDT 24
Finished Jun 04 03:01:19 PM PDT 24
Peak memory 276496 kb
Host smart-aa03ef80-5aa8-49f8-b3a0-47204bf7d41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960166749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.960166749
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.932172447
Short name T416
Test name
Test status
Simulation time 129900400 ps
CPU time 13.73 seconds
Started Jun 04 02:58:06 PM PDT 24
Finished Jun 04 02:58:21 PM PDT 24
Peak memory 264820 kb
Host smart-74a90ad5-2523-4e06-9574-25cc1954ca14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932172447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.932172447
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.635722698
Short name T994
Test name
Test status
Simulation time 14038400 ps
CPU time 13.7 seconds
Started Jun 04 02:58:05 PM PDT 24
Finished Jun 04 02:58:19 PM PDT 24
Peak memory 275768 kb
Host smart-bea17dbb-646c-4d71-96f6-ff2ab2db2cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635722698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.635722698
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.2992305984
Short name T949
Test name
Test status
Simulation time 25128400 ps
CPU time 21.73 seconds
Started Jun 04 02:58:07 PM PDT 24
Finished Jun 04 02:58:29 PM PDT 24
Peak memory 273192 kb
Host smart-82dcfa99-be37-4036-9f87-62fc6cd8ac7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992305984 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.2992305984
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.2343937099
Short name T180
Test name
Test status
Simulation time 685019800 ps
CPU time 63.17 seconds
Started Jun 04 02:58:04 PM PDT 24
Finished Jun 04 02:59:07 PM PDT 24
Peak memory 262340 kb
Host smart-6cbda077-dc61-4b35-ac36-bbe209852f7a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343937099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.2343937099
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.1466797381
Short name T726
Test name
Test status
Simulation time 66831200 ps
CPU time 109.45 seconds
Started Jun 04 02:58:06 PM PDT 24
Finished Jun 04 02:59:56 PM PDT 24
Peak memory 259760 kb
Host smart-4820a16a-de18-4815-968c-11559e672860
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466797381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.1466797381
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.52656196
Short name T954
Test name
Test status
Simulation time 450064600 ps
CPU time 61.61 seconds
Started Jun 04 02:58:05 PM PDT 24
Finished Jun 04 02:59:07 PM PDT 24
Peak memory 264052 kb
Host smart-fea176fd-06b1-45d0-abf8-26deb4b9b58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52656196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.52656196
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.3999802319
Short name T789
Test name
Test status
Simulation time 50638200 ps
CPU time 75.66 seconds
Started Jun 04 02:58:06 PM PDT 24
Finished Jun 04 02:59:22 PM PDT 24
Peak memory 275076 kb
Host smart-a1c6e430-da18-44a8-9db7-6528d4c8f143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999802319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.3999802319
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.133108621
Short name T512
Test name
Test status
Simulation time 110076900 ps
CPU time 13.89 seconds
Started Jun 04 02:47:15 PM PDT 24
Finished Jun 04 02:47:29 PM PDT 24
Peak memory 264792 kb
Host smart-e6ba64ee-42ab-48ec-ac5e-1e2a42c6c034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133108621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.133108621
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.1602222229
Short name T843
Test name
Test status
Simulation time 41701600 ps
CPU time 13.14 seconds
Started Jun 04 02:47:08 PM PDT 24
Finished Jun 04 02:47:22 PM PDT 24
Peak memory 275528 kb
Host smart-04d1991f-b241-43a4-a236-64bbd5e5fd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602222229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1602222229
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.3546136590
Short name T72
Test name
Test status
Simulation time 22405700 ps
CPU time 21.4 seconds
Started Jun 04 02:47:04 PM PDT 24
Finished Jun 04 02:47:26 PM PDT 24
Peak memory 273152 kb
Host smart-b714476a-17f8-4edc-8e1f-40200f90dae9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546136590 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.3546136590
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.2553899996
Short name T290
Test name
Test status
Simulation time 25345477200 ps
CPU time 2670.16 seconds
Started Jun 04 02:46:39 PM PDT 24
Finished Jun 04 03:31:10 PM PDT 24
Peak memory 264656 kb
Host smart-4feb898c-8fce-46f6-9a34-7e85183aa176
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553899996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.2553899996
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.1707943688
Short name T684
Test name
Test status
Simulation time 730422500 ps
CPU time 806.06 seconds
Started Jun 04 02:46:38 PM PDT 24
Finished Jun 04 03:00:05 PM PDT 24
Peak memory 264848 kb
Host smart-19e77387-e163-4847-9199-970bbb009b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707943688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.1707943688
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2501946144
Short name T284
Test name
Test status
Simulation time 10018749700 ps
CPU time 74.32 seconds
Started Jun 04 02:47:05 PM PDT 24
Finished Jun 04 02:48:20 PM PDT 24
Peak memory 280340 kb
Host smart-8f33b409-5328-4663-85fe-13c2f0eb7163
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501946144 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.2501946144
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.340050288
Short name T434
Test name
Test status
Simulation time 25369800 ps
CPU time 13.49 seconds
Started Jun 04 02:47:09 PM PDT 24
Finished Jun 04 02:47:23 PM PDT 24
Peak memory 264712 kb
Host smart-effef604-394a-4487-b577-c0e05375788b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340050288 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.340050288
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.916062942
Short name T627
Test name
Test status
Simulation time 80155807300 ps
CPU time 900.27 seconds
Started Jun 04 02:46:30 PM PDT 24
Finished Jun 04 03:01:31 PM PDT 24
Peak memory 263924 kb
Host smart-4cbb05d3-5bc4-46e4-945d-e051d99f5c71
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916062942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.flash_ctrl_hw_rma_reset.916062942
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.3047210567
Short name T589
Test name
Test status
Simulation time 9722965000 ps
CPU time 174.11 seconds
Started Jun 04 02:46:30 PM PDT 24
Finished Jun 04 02:49:24 PM PDT 24
Peak memory 261736 kb
Host smart-81536cfe-1bd0-4c1f-b2ec-7a02e5f67d3c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047210567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.3047210567
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.1467821694
Short name T980
Test name
Test status
Simulation time 1932686600 ps
CPU time 212.08 seconds
Started Jun 04 02:46:58 PM PDT 24
Finished Jun 04 02:50:31 PM PDT 24
Peak memory 289488 kb
Host smart-07753c79-0496-4399-8fe6-c70e096e3307
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467821694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.1467821694
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.4012163783
Short name T439
Test name
Test status
Simulation time 23257175400 ps
CPU time 175.78 seconds
Started Jun 04 02:46:58 PM PDT 24
Finished Jun 04 02:49:54 PM PDT 24
Peak memory 292388 kb
Host smart-f267701c-5424-4fd7-a7a8-8959b1c3122e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012163783 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.4012163783
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.2374007434
Short name T970
Test name
Test status
Simulation time 10418341300 ps
CPU time 75.53 seconds
Started Jun 04 02:46:56 PM PDT 24
Finished Jun 04 02:48:12 PM PDT 24
Peak memory 259560 kb
Host smart-b27f699b-32e5-48c2-9473-8d6ada35bb2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374007434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.2374007434
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3786462581
Short name T413
Test name
Test status
Simulation time 20577223000 ps
CPU time 172.27 seconds
Started Jun 04 02:46:59 PM PDT 24
Finished Jun 04 02:49:51 PM PDT 24
Peak memory 259932 kb
Host smart-4c05f986-6e78-4c16-9443-779184cc6a9c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378
6462581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.3786462581
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.3835941214
Short name T404
Test name
Test status
Simulation time 15796000 ps
CPU time 13.19 seconds
Started Jun 04 02:47:09 PM PDT 24
Finished Jun 04 02:47:22 PM PDT 24
Peak memory 259140 kb
Host smart-fc79f706-fc40-497e-b23a-55a3f4d6908f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835941214 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.3835941214
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.2517292780
Short name T753
Test name
Test status
Simulation time 4430509000 ps
CPU time 111.3 seconds
Started Jun 04 02:46:39 PM PDT 24
Finished Jun 04 02:48:31 PM PDT 24
Peak memory 264868 kb
Host smart-12cf5628-371d-4c0c-acc6-ee1ec3db6665
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517292780 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.2517292780
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.2889836481
Short name T583
Test name
Test status
Simulation time 74740800 ps
CPU time 130.7 seconds
Started Jun 04 02:46:41 PM PDT 24
Finished Jun 04 02:48:52 PM PDT 24
Peak memory 260880 kb
Host smart-e03d84fe-5ad9-4a2c-bbc3-fdac8c5eb27b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889836481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.2889836481
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.411235213
Short name T529
Test name
Test status
Simulation time 1403434400 ps
CPU time 440.07 seconds
Started Jun 04 02:46:31 PM PDT 24
Finished Jun 04 02:53:51 PM PDT 24
Peak memory 262200 kb
Host smart-a0642302-5383-478e-8a72-cdc1a8b7dcfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=411235213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.411235213
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.437189397
Short name T495
Test name
Test status
Simulation time 38151400 ps
CPU time 13.51 seconds
Started Jun 04 02:46:59 PM PDT 24
Finished Jun 04 02:47:13 PM PDT 24
Peak memory 264744 kb
Host smart-b4a1fe05-5edd-4377-9137-7d5bdb5e56e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437189397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_rese
t.437189397
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.101231095
Short name T513
Test name
Test status
Simulation time 57824900 ps
CPU time 289.13 seconds
Started Jun 04 02:46:32 PM PDT 24
Finished Jun 04 02:51:22 PM PDT 24
Peak memory 276664 kb
Host smart-a13e46bd-7fde-4f06-9fff-383690cf3f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101231095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.101231095
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.1563939484
Short name T1083
Test name
Test status
Simulation time 147090700 ps
CPU time 36.99 seconds
Started Jun 04 02:47:05 PM PDT 24
Finished Jun 04 02:47:43 PM PDT 24
Peak memory 274112 kb
Host smart-67c4a9f8-4867-4cdb-a253-23d02a54df7d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563939484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.1563939484
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.1241912549
Short name T528
Test name
Test status
Simulation time 938452900 ps
CPU time 113.34 seconds
Started Jun 04 02:46:49 PM PDT 24
Finished Jun 04 02:48:43 PM PDT 24
Peak memory 281288 kb
Host smart-c57a469b-129f-4ec4-90dc-ac15ae3bbac4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241912549 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_ro.1241912549
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.3539400096
Short name T620
Test name
Test status
Simulation time 2788372600 ps
CPU time 157.54 seconds
Started Jun 04 02:46:57 PM PDT 24
Finished Jun 04 02:49:35 PM PDT 24
Peak memory 281652 kb
Host smart-8677ebd1-ef63-4138-9570-69722f2feb2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3539400096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.3539400096
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.1901650471
Short name T892
Test name
Test status
Simulation time 2595788900 ps
CPU time 121.53 seconds
Started Jun 04 02:46:48 PM PDT 24
Finished Jun 04 02:48:50 PM PDT 24
Peak memory 281228 kb
Host smart-87b8ba61-3107-4f34-ac68-b9e2bcd80d1a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901650471 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.1901650471
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.3146652772
Short name T1085
Test name
Test status
Simulation time 4116988700 ps
CPU time 692.28 seconds
Started Jun 04 02:46:49 PM PDT 24
Finished Jun 04 02:58:22 PM PDT 24
Peak memory 309144 kb
Host smart-4a6b1769-6ee0-478f-93c0-777ad4bb6d05
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146652772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.flash_ctrl_rw.3146652772
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.4026398067
Short name T502
Test name
Test status
Simulation time 16900021700 ps
CPU time 648.26 seconds
Started Jun 04 02:46:57 PM PDT 24
Finished Jun 04 02:57:46 PM PDT 24
Peak memory 335680 kb
Host smart-d7232f69-909e-4d69-b3f5-e9ec2b318a99
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026398067 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_rw_derr.4026398067
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.4031108789
Short name T999
Test name
Test status
Simulation time 49713200 ps
CPU time 28.02 seconds
Started Jun 04 02:47:09 PM PDT 24
Finished Jun 04 02:47:37 PM PDT 24
Peak memory 274372 kb
Host smart-fe6b2976-75bb-4886-826b-409a0f6423cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031108789 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.4031108789
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.3565518309
Short name T909
Test name
Test status
Simulation time 4881939900 ps
CPU time 83.51 seconds
Started Jun 04 02:47:05 PM PDT 24
Finished Jun 04 02:48:29 PM PDT 24
Peak memory 263392 kb
Host smart-2803963f-0839-4f3b-a892-63bb77eeab13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565518309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.3565518309
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.2800577937
Short name T891
Test name
Test status
Simulation time 24769100 ps
CPU time 97.99 seconds
Started Jun 04 02:46:29 PM PDT 24
Finished Jun 04 02:48:08 PM PDT 24
Peak memory 275076 kb
Host smart-ef2a6e33-893d-4044-989b-46542d83c9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800577937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2800577937
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.1264074609
Short name T881
Test name
Test status
Simulation time 2425055000 ps
CPU time 158.01 seconds
Started Jun 04 02:46:39 PM PDT 24
Finished Jun 04 02:49:17 PM PDT 24
Peak memory 259164 kb
Host smart-51edd003-b43b-47bc-bcb6-316242ccc947
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264074609 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.flash_ctrl_wo.1264074609
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.3834022831
Short name T910
Test name
Test status
Simulation time 15991000 ps
CPU time 15.96 seconds
Started Jun 04 02:58:15 PM PDT 24
Finished Jun 04 02:58:31 PM PDT 24
Peak memory 275852 kb
Host smart-30ad5f20-05e6-4adc-bea0-fc9a2cbd1507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834022831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.3834022831
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.3830657172
Short name T775
Test name
Test status
Simulation time 81678000 ps
CPU time 131.74 seconds
Started Jun 04 02:58:14 PM PDT 24
Finished Jun 04 03:00:26 PM PDT 24
Peak memory 260924 kb
Host smart-f801493d-51ce-42a9-a4fa-68441249eae7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830657172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.3830657172
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.3031799356
Short name T182
Test name
Test status
Simulation time 25292100 ps
CPU time 13.24 seconds
Started Jun 04 02:58:13 PM PDT 24
Finished Jun 04 02:58:27 PM PDT 24
Peak memory 275952 kb
Host smart-8fb166bd-3611-4299-a0fd-e9280c572f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031799356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.3031799356
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.58789992
Short name T127
Test name
Test status
Simulation time 51543300 ps
CPU time 109.62 seconds
Started Jun 04 02:58:15 PM PDT 24
Finished Jun 04 03:00:05 PM PDT 24
Peak memory 260784 kb
Host smart-5f467c88-4247-43de-88e5-6d0aaf02be32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58789992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp
_reset.58789992
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.1678246705
Short name T94
Test name
Test status
Simulation time 59617000 ps
CPU time 15.58 seconds
Started Jun 04 02:58:14 PM PDT 24
Finished Jun 04 02:58:30 PM PDT 24
Peak memory 275828 kb
Host smart-d0b557bc-a840-494a-94e8-8cee84faa9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678246705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1678246705
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.2405671968
Short name T1080
Test name
Test status
Simulation time 40397500 ps
CPU time 133.51 seconds
Started Jun 04 02:58:15 PM PDT 24
Finished Jun 04 03:00:29 PM PDT 24
Peak memory 264236 kb
Host smart-921e70dd-9da6-4a6a-82ca-14e11c4af5e5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405671968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.2405671968
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.2986823377
Short name T1023
Test name
Test status
Simulation time 24575100 ps
CPU time 14.01 seconds
Started Jun 04 02:58:13 PM PDT 24
Finished Jun 04 02:58:28 PM PDT 24
Peak memory 275848 kb
Host smart-84348c3a-5f1e-4226-9c40-538a2bf35405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986823377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.2986823377
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.1484474153
Short name T1047
Test name
Test status
Simulation time 147961000 ps
CPU time 129.79 seconds
Started Jun 04 02:58:14 PM PDT 24
Finished Jun 04 03:00:24 PM PDT 24
Peak memory 259552 kb
Host smart-c7ce5c08-06b9-442e-a945-8cf0cff5caec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484474153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.1484474153
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.2542255724
Short name T498
Test name
Test status
Simulation time 26432500 ps
CPU time 15.62 seconds
Started Jun 04 02:58:25 PM PDT 24
Finished Jun 04 02:58:41 PM PDT 24
Peak memory 275536 kb
Host smart-ddf209aa-651e-4c35-8907-8468d75e814f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542255724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.2542255724
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.3192765729
Short name T309
Test name
Test status
Simulation time 80354300 ps
CPU time 130.52 seconds
Started Jun 04 02:58:25 PM PDT 24
Finished Jun 04 03:00:36 PM PDT 24
Peak memory 260692 kb
Host smart-9af07355-2310-4416-bd0b-128969e8ddd9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192765729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.3192765729
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.3251533691
Short name T515
Test name
Test status
Simulation time 116936000 ps
CPU time 15.5 seconds
Started Jun 04 02:58:24 PM PDT 24
Finished Jun 04 02:58:40 PM PDT 24
Peak memory 274716 kb
Host smart-276918ce-a6b5-46c8-8dde-cd868f6f6e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251533691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.3251533691
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.2899025058
Short name T591
Test name
Test status
Simulation time 142595000 ps
CPU time 131.09 seconds
Started Jun 04 02:58:26 PM PDT 24
Finished Jun 04 03:00:38 PM PDT 24
Peak memory 259784 kb
Host smart-bddc8f31-cb4d-4a45-b909-b6ce166ebf6f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899025058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.2899025058
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.1240767024
Short name T459
Test name
Test status
Simulation time 27300800 ps
CPU time 13.8 seconds
Started Jun 04 02:58:23 PM PDT 24
Finished Jun 04 02:58:38 PM PDT 24
Peak memory 275616 kb
Host smart-398a8a79-30a1-40e2-b7b0-bc8ac1880d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240767024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.1240767024
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.3801280976
Short name T546
Test name
Test status
Simulation time 135478900 ps
CPU time 131.78 seconds
Started Jun 04 02:58:22 PM PDT 24
Finished Jun 04 03:00:34 PM PDT 24
Peak memory 259540 kb
Host smart-09dc696e-6cb2-445d-99a3-74bba2b3ae44
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801280976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.3801280976
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.2472318138
Short name T494
Test name
Test status
Simulation time 14367100 ps
CPU time 15.6 seconds
Started Jun 04 02:58:22 PM PDT 24
Finished Jun 04 02:58:39 PM PDT 24
Peak memory 275796 kb
Host smart-24093810-e886-4a9c-9933-3aecd1adc616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472318138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.2472318138
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.2377449648
Short name T568
Test name
Test status
Simulation time 137120500 ps
CPU time 131.46 seconds
Started Jun 04 02:58:22 PM PDT 24
Finished Jun 04 03:00:34 PM PDT 24
Peak memory 259716 kb
Host smart-ff58bac6-d29d-476f-9146-b28378af22eb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377449648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.2377449648
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.1238330980
Short name T1002
Test name
Test status
Simulation time 23481200 ps
CPU time 15.86 seconds
Started Jun 04 02:58:26 PM PDT 24
Finished Jun 04 02:58:43 PM PDT 24
Peak memory 274972 kb
Host smart-6c75b453-3e61-4b05-9d92-5b75578a28fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238330980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.1238330980
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.334368735
Short name T646
Test name
Test status
Simulation time 76208700 ps
CPU time 129.81 seconds
Started Jun 04 02:58:23 PM PDT 24
Finished Jun 04 03:00:33 PM PDT 24
Peak memory 264264 kb
Host smart-e0b8cd28-e2d1-46ed-a02f-b79d2afa36f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334368735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_ot
p_reset.334368735
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.4160819535
Short name T1049
Test name
Test status
Simulation time 43103700 ps
CPU time 13.27 seconds
Started Jun 04 02:58:24 PM PDT 24
Finished Jun 04 02:58:38 PM PDT 24
Peak memory 275812 kb
Host smart-5862985f-8c40-4fba-ac24-39d275fce065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160819535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.4160819535
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.2312871293
Short name T565
Test name
Test status
Simulation time 69432100 ps
CPU time 14.33 seconds
Started Jun 04 02:47:55 PM PDT 24
Finished Jun 04 02:48:10 PM PDT 24
Peak memory 257916 kb
Host smart-28ba9b25-f02f-49b7-bb04-72897227f03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312871293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.2
312871293
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.1195571711
Short name T991
Test name
Test status
Simulation time 14903900 ps
CPU time 13.5 seconds
Started Jun 04 02:47:46 PM PDT 24
Finished Jun 04 02:48:00 PM PDT 24
Peak memory 275880 kb
Host smart-93e743fc-a097-4c80-bb39-f3bccc9cfae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195571711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1195571711
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.3416955302
Short name T3
Test name
Test status
Simulation time 55883000 ps
CPU time 20.66 seconds
Started Jun 04 02:47:47 PM PDT 24
Finished Jun 04 02:48:08 PM PDT 24
Peak memory 273432 kb
Host smart-3512c8a6-e691-437d-879c-f658546ee081
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416955302 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.3416955302
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.1718738271
Short name T613
Test name
Test status
Simulation time 1005383900 ps
CPU time 1110.53 seconds
Started Jun 04 02:47:22 PM PDT 24
Finished Jun 04 03:05:53 PM PDT 24
Peak memory 273040 kb
Host smart-5e4bceef-f48b-4ea2-9506-4876c8ddc59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718738271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.1718738271
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.2862655121
Short name T51
Test name
Test status
Simulation time 373710400 ps
CPU time 23.4 seconds
Started Jun 04 02:47:26 PM PDT 24
Finished Jun 04 02:47:50 PM PDT 24
Peak memory 264864 kb
Host smart-9f35a295-50f2-4b2a-9b63-5eb6c5d6b248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862655121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.2862655121
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.1681277056
Short name T785
Test name
Test status
Simulation time 10081869400 ps
CPU time 36.45 seconds
Started Jun 04 02:47:55 PM PDT 24
Finished Jun 04 02:48:32 PM PDT 24
Peak memory 265024 kb
Host smart-c4b80437-16e9-4311-8e2f-8596e0947a16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681277056 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.1681277056
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.3345524357
Short name T130
Test name
Test status
Simulation time 20728600 ps
CPU time 13.53 seconds
Started Jun 04 02:47:55 PM PDT 24
Finished Jun 04 02:48:09 PM PDT 24
Peak memory 264828 kb
Host smart-d925a47f-2560-44c6-a2ca-d265911167be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345524357 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.3345524357
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.2624303487
Short name T771
Test name
Test status
Simulation time 160180064800 ps
CPU time 883.79 seconds
Started Jun 04 02:47:15 PM PDT 24
Finished Jun 04 03:01:59 PM PDT 24
Peak memory 263004 kb
Host smart-860646ba-c069-4bdd-913b-6c2ea7abb28d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624303487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.2624303487
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.1423109900
Short name T766
Test name
Test status
Simulation time 3276689500 ps
CPU time 204.38 seconds
Started Jun 04 02:47:13 PM PDT 24
Finished Jun 04 02:50:38 PM PDT 24
Peak memory 262308 kb
Host smart-d2ee102e-6512-4c3c-bb7e-b8976ce9e7c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423109900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.1423109900
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.4152507093
Short name T657
Test name
Test status
Simulation time 1082860900 ps
CPU time 137.89 seconds
Started Jun 04 02:47:24 PM PDT 24
Finished Jun 04 02:49:42 PM PDT 24
Peak memory 292792 kb
Host smart-51c765b9-e528-4623-9b1e-c62c6d51b130
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152507093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.4152507093
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3824755937
Short name T721
Test name
Test status
Simulation time 9443215200 ps
CPU time 349.84 seconds
Started Jun 04 02:47:30 PM PDT 24
Finished Jun 04 02:53:20 PM PDT 24
Peak memory 291768 kb
Host smart-6f9e4d04-d002-41e9-8239-a71057933f65
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824755937 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.3824755937
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.1082539218
Short name T676
Test name
Test status
Simulation time 8071255700 ps
CPU time 66.28 seconds
Started Jun 04 02:47:29 PM PDT 24
Finished Jun 04 02:48:35 PM PDT 24
Peak memory 259600 kb
Host smart-cb11e960-4d6c-444a-bee6-811f9235baad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082539218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.1082539218
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2910107309
Short name T765
Test name
Test status
Simulation time 21657133100 ps
CPU time 171.65 seconds
Started Jun 04 02:47:30 PM PDT 24
Finished Jun 04 02:50:22 PM PDT 24
Peak memory 264264 kb
Host smart-32bf258f-2855-4b66-bd36-eb270a802946
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291
0107309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.2910107309
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.3249578676
Short name T863
Test name
Test status
Simulation time 5073770900 ps
CPU time 69.05 seconds
Started Jun 04 02:47:23 PM PDT 24
Finished Jun 04 02:48:32 PM PDT 24
Peak memory 260320 kb
Host smart-9365e771-a225-4567-b2ce-84c2fd8ca1cd
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249578676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.3249578676
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.4216280484
Short name T524
Test name
Test status
Simulation time 106683200 ps
CPU time 13.35 seconds
Started Jun 04 02:47:47 PM PDT 24
Finished Jun 04 02:48:01 PM PDT 24
Peak memory 259156 kb
Host smart-66d6fedf-3d13-43bd-848c-7b968ecad99f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216280484 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.4216280484
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.366336672
Short name T86
Test name
Test status
Simulation time 14769023200 ps
CPU time 941.92 seconds
Started Jun 04 02:47:13 PM PDT 24
Finished Jun 04 03:02:56 PM PDT 24
Peak memory 273628 kb
Host smart-d276e6ed-7f50-4961-809d-95c3f0c381ef
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366336672 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_mp_regions.366336672
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.971579992
Short name T314
Test name
Test status
Simulation time 74851000 ps
CPU time 131.26 seconds
Started Jun 04 02:47:16 PM PDT 24
Finished Jun 04 02:49:27 PM PDT 24
Peak memory 259808 kb
Host smart-f09f5a41-8483-49dc-89f4-cba2edcf2b29
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971579992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp
_reset.971579992
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.1732876179
Short name T1054
Test name
Test status
Simulation time 315510200 ps
CPU time 426.48 seconds
Started Jun 04 02:47:14 PM PDT 24
Finished Jun 04 02:54:21 PM PDT 24
Peak memory 262200 kb
Host smart-5da801e4-2b41-46cc-9b79-901fbd3afc62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732876179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.1732876179
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.2200679964
Short name T641
Test name
Test status
Simulation time 18292700 ps
CPU time 13.24 seconds
Started Jun 04 02:47:37 PM PDT 24
Finished Jun 04 02:47:51 PM PDT 24
Peak memory 258476 kb
Host smart-c7170c95-77e6-426c-93d6-cb3ef9f91e57
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200679964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.2200679964
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.4214848022
Short name T989
Test name
Test status
Simulation time 811572500 ps
CPU time 688.64 seconds
Started Jun 04 02:47:15 PM PDT 24
Finished Jun 04 02:58:44 PM PDT 24
Peak memory 282536 kb
Host smart-d6ae75b3-7e8b-4737-92f1-b797ca48a45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214848022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.4214848022
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.267867944
Short name T324
Test name
Test status
Simulation time 99813400 ps
CPU time 35.76 seconds
Started Jun 04 02:47:38 PM PDT 24
Finished Jun 04 02:48:14 PM PDT 24
Peak memory 273112 kb
Host smart-d53ff6a9-5b2e-4760-ae31-ed6d555dee01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267867944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_re_evict.267867944
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.1740093424
Short name T877
Test name
Test status
Simulation time 6477732300 ps
CPU time 133.7 seconds
Started Jun 04 02:47:26 PM PDT 24
Finished Jun 04 02:49:40 PM PDT 24
Peak memory 281360 kb
Host smart-91b7b1fa-078c-4c2c-a0db-ee7aca92341a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740093424 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_ro.1740093424
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.3485104239
Short name T497
Test name
Test status
Simulation time 381974500 ps
CPU time 109.01 seconds
Started Jun 04 02:47:23 PM PDT 24
Finished Jun 04 02:49:13 PM PDT 24
Peak memory 281244 kb
Host smart-141cbc42-bcf7-433c-adb5-4a71c9533a6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3485104239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.3485104239
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.3964940623
Short name T711
Test name
Test status
Simulation time 680881100 ps
CPU time 148.79 seconds
Started Jun 04 02:47:23 PM PDT 24
Finished Jun 04 02:49:53 PM PDT 24
Peak memory 294144 kb
Host smart-7848c2d0-fdfd-4ba3-94c2-ccf5fd6b0f36
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964940623 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.3964940623
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.2104858438
Short name T100
Test name
Test status
Simulation time 4366243100 ps
CPU time 549.87 seconds
Started Jun 04 02:47:27 PM PDT 24
Finished Jun 04 02:56:38 PM PDT 24
Peak memory 313428 kb
Host smart-0c059faf-002f-4ec7-bc06-55fef1a14f49
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104858438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.flash_ctrl_rw.2104858438
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.1418000496
Short name T201
Test name
Test status
Simulation time 16116199400 ps
CPU time 822.11 seconds
Started Jun 04 02:47:24 PM PDT 24
Finished Jun 04 03:01:06 PM PDT 24
Peak memory 339032 kb
Host smart-634439f9-239f-4192-b15d-f399a6796507
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418000496 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_rw_derr.1418000496
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.1473253274
Short name T961
Test name
Test status
Simulation time 7402581400 ps
CPU time 567.6 seconds
Started Jun 04 02:47:26 PM PDT 24
Finished Jun 04 02:56:54 PM PDT 24
Peak memory 319900 kb
Host smart-8f5b6d54-20dd-4efd-af66-eb77b4d77714
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473253274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.1473253274
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.2471993136
Short name T453
Test name
Test status
Simulation time 3066479000 ps
CPU time 78.18 seconds
Started Jun 04 02:47:46 PM PDT 24
Finished Jun 04 02:49:04 PM PDT 24
Peak memory 262876 kb
Host smart-ba1729dc-ac31-42dc-9491-768bfa8a8fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471993136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.2471993136
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.2301781608
Short name T935
Test name
Test status
Simulation time 91742000 ps
CPU time 98.62 seconds
Started Jun 04 02:47:13 PM PDT 24
Finished Jun 04 02:48:52 PM PDT 24
Peak memory 275136 kb
Host smart-9f111cd6-aadb-4327-b1ab-22c85fb02ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301781608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.2301781608
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.3047580273
Short name T878
Test name
Test status
Simulation time 2133716700 ps
CPU time 150.3 seconds
Started Jun 04 02:47:27 PM PDT 24
Finished Jun 04 02:49:58 PM PDT 24
Peak memory 258916 kb
Host smart-79bddd2b-36f6-4f79-9cc7-902faa5abf2c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047580273 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.flash_ctrl_wo.3047580273
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.1248210070
Short name T741
Test name
Test status
Simulation time 80245700 ps
CPU time 13.17 seconds
Started Jun 04 02:58:33 PM PDT 24
Finished Jun 04 02:58:47 PM PDT 24
Peak memory 275832 kb
Host smart-ef3d45cc-0b3d-46e0-a3a1-688c614e8c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248210070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.1248210070
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.3777520236
Short name T440
Test name
Test status
Simulation time 70445300 ps
CPU time 130.66 seconds
Started Jun 04 02:58:22 PM PDT 24
Finished Jun 04 03:00:34 PM PDT 24
Peak memory 259820 kb
Host smart-63375438-1d70-44d4-92c8-6e8d3252bebc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777520236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.3777520236
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.580394210
Short name T872
Test name
Test status
Simulation time 47579700 ps
CPU time 15.55 seconds
Started Jun 04 02:58:33 PM PDT 24
Finished Jun 04 02:58:49 PM PDT 24
Peak memory 275512 kb
Host smart-922e9e7f-5873-4591-8be6-d4b05bf43e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580394210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.580394210
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.3881021265
Short name T92
Test name
Test status
Simulation time 39205100 ps
CPU time 135.28 seconds
Started Jun 04 02:58:38 PM PDT 24
Finished Jun 04 03:00:54 PM PDT 24
Peak memory 259700 kb
Host smart-b66132e4-9002-440b-a8ba-d7a8cae9efde
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881021265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.3881021265
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.3087756832
Short name T507
Test name
Test status
Simulation time 55190900 ps
CPU time 15.43 seconds
Started Jun 04 02:58:33 PM PDT 24
Finished Jun 04 02:58:49 PM PDT 24
Peak memory 275624 kb
Host smart-289d9ed6-a120-4439-b29c-d252d11cf6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087756832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3087756832
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.1687386293
Short name T622
Test name
Test status
Simulation time 120657600 ps
CPU time 134.51 seconds
Started Jun 04 02:58:48 PM PDT 24
Finished Jun 04 03:01:03 PM PDT 24
Peak memory 264388 kb
Host smart-f541e2ac-e622-48e9-bd27-660537161205
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687386293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.1687386293
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.1475571313
Short name T1032
Test name
Test status
Simulation time 22674700 ps
CPU time 15.35 seconds
Started Jun 04 02:58:32 PM PDT 24
Finished Jun 04 02:58:48 PM PDT 24
Peak memory 274948 kb
Host smart-0a57264a-352d-4739-8720-8f9d3f19c7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475571313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.1475571313
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.3283127945
Short name T668
Test name
Test status
Simulation time 41014300 ps
CPU time 108.88 seconds
Started Jun 04 02:58:33 PM PDT 24
Finished Jun 04 03:00:22 PM PDT 24
Peak memory 260572 kb
Host smart-5a24661f-8f2e-46f4-8f7d-efb235e851f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283127945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.3283127945
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.2997913324
Short name T427
Test name
Test status
Simulation time 13793400 ps
CPU time 15.35 seconds
Started Jun 04 02:58:31 PM PDT 24
Finished Jun 04 02:58:47 PM PDT 24
Peak memory 275496 kb
Host smart-d40a6fa5-a5fa-46e6-a1e5-06b3a53c0c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997913324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.2997913324
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.363988662
Short name T649
Test name
Test status
Simulation time 41660200 ps
CPU time 110.61 seconds
Started Jun 04 02:58:32 PM PDT 24
Finished Jun 04 03:00:23 PM PDT 24
Peak memory 263172 kb
Host smart-e2ce4ea8-79bd-4110-bb58-474ad16efd4e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363988662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_ot
p_reset.363988662
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.1134912348
Short name T652
Test name
Test status
Simulation time 64788200 ps
CPU time 13.56 seconds
Started Jun 04 02:58:34 PM PDT 24
Finished Jun 04 02:58:48 PM PDT 24
Peak memory 275576 kb
Host smart-173266c3-c748-49bc-af20-db5e65f45eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134912348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.1134912348
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.2701921910
Short name T605
Test name
Test status
Simulation time 39864500 ps
CPU time 112.3 seconds
Started Jun 04 02:58:33 PM PDT 24
Finished Jun 04 03:00:25 PM PDT 24
Peak memory 260940 kb
Host smart-04a174ac-56b5-4de1-9f26-43dc9fde7f48
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701921910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.2701921910
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.2249630364
Short name T955
Test name
Test status
Simulation time 85924700 ps
CPU time 13.56 seconds
Started Jun 04 02:58:33 PM PDT 24
Finished Jun 04 02:58:48 PM PDT 24
Peak memory 275748 kb
Host smart-4e7529dc-27f1-487b-887b-7bc35226cd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249630364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2249630364
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.114488443
Short name T701
Test name
Test status
Simulation time 22476800 ps
CPU time 15.83 seconds
Started Jun 04 02:58:32 PM PDT 24
Finished Jun 04 02:58:48 PM PDT 24
Peak memory 275520 kb
Host smart-db18743d-94ac-4133-b641-2408d7e71e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114488443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.114488443
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.288790895
Short name T964
Test name
Test status
Simulation time 355841700 ps
CPU time 132.69 seconds
Started Jun 04 02:58:33 PM PDT 24
Finished Jun 04 03:00:47 PM PDT 24
Peak memory 260684 kb
Host smart-84029c53-ba5a-413a-9a59-7eaa91c2fe37
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288790895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_ot
p_reset.288790895
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.4064359507
Short name T1044
Test name
Test status
Simulation time 14317300 ps
CPU time 13.21 seconds
Started Jun 04 02:58:43 PM PDT 24
Finished Jun 04 02:58:57 PM PDT 24
Peak memory 275744 kb
Host smart-8d3e0194-d6d0-4ff6-a038-24f723005c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064359507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.4064359507
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.2668228193
Short name T783
Test name
Test status
Simulation time 141587000 ps
CPU time 130.98 seconds
Started Jun 04 02:58:34 PM PDT 24
Finished Jun 04 03:00:45 PM PDT 24
Peak memory 259684 kb
Host smart-77fec3bf-18bc-42d6-a3a0-7575369a60cf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668228193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.2668228193
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.3501451380
Short name T1050
Test name
Test status
Simulation time 44372800 ps
CPU time 13.51 seconds
Started Jun 04 02:58:42 PM PDT 24
Finished Jun 04 02:58:56 PM PDT 24
Peak memory 275816 kb
Host smart-f556d526-394e-4986-b401-da580b845d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501451380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.3501451380
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.177610588
Short name T575
Test name
Test status
Simulation time 39391300 ps
CPU time 131.75 seconds
Started Jun 04 02:58:42 PM PDT 24
Finished Jun 04 03:00:54 PM PDT 24
Peak memory 260868 kb
Host smart-913b8ae9-fc22-49d3-8e62-3cb8b2ca5ef7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177610588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_ot
p_reset.177610588
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.1789736056
Short name T723
Test name
Test status
Simulation time 90337600 ps
CPU time 14.06 seconds
Started Jun 04 02:48:35 PM PDT 24
Finished Jun 04 02:48:50 PM PDT 24
Peak memory 264844 kb
Host smart-2ee4f6df-e01d-4dc6-b394-3279b7c3675b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789736056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1
789736056
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.4106600719
Short name T366
Test name
Test status
Simulation time 114927700 ps
CPU time 15.66 seconds
Started Jun 04 02:48:34 PM PDT 24
Finished Jun 04 02:48:50 PM PDT 24
Peak memory 275860 kb
Host smart-346f2217-e729-4c18-8af6-cc41128251b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106600719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.4106600719
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.1850132805
Short name T975
Test name
Test status
Simulation time 48591200 ps
CPU time 22.82 seconds
Started Jun 04 02:48:33 PM PDT 24
Finished Jun 04 02:48:57 PM PDT 24
Peak memory 264812 kb
Host smart-c09e66f7-4683-4c94-b710-5e4c84c68cfc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850132805 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.1850132805
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.3784945283
Short name T995
Test name
Test status
Simulation time 20794774600 ps
CPU time 2536.52 seconds
Started Jun 04 02:48:09 PM PDT 24
Finished Jun 04 03:30:26 PM PDT 24
Peak memory 264320 kb
Host smart-24ba794d-8a67-4a6c-b341-ca79e94a25b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784945283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.3784945283
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.2316638616
Short name T770
Test name
Test status
Simulation time 478272800 ps
CPU time 838.74 seconds
Started Jun 04 02:48:02 PM PDT 24
Finished Jun 04 03:02:01 PM PDT 24
Peak memory 264872 kb
Host smart-aa654fac-28d1-4d4f-8513-8cac87c00362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316638616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.2316638616
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.3796172385
Short name T630
Test name
Test status
Simulation time 108940400 ps
CPU time 22.2 seconds
Started Jun 04 02:48:02 PM PDT 24
Finished Jun 04 02:48:25 PM PDT 24
Peak memory 264888 kb
Host smart-58eaf6fd-6926-4361-81ec-7a377676c4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796172385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.3796172385
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3051394300
Short name T560
Test name
Test status
Simulation time 10125198100 ps
CPU time 34.02 seconds
Started Jun 04 02:48:34 PM PDT 24
Finished Jun 04 02:49:09 PM PDT 24
Peak memory 263976 kb
Host smart-ec064708-4926-4e1f-a6d8-d0a164cdae84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051394300 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.3051394300
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.2129138523
Short name T452
Test name
Test status
Simulation time 26649200 ps
CPU time 13.32 seconds
Started Jun 04 02:48:34 PM PDT 24
Finished Jun 04 02:48:47 PM PDT 24
Peak memory 258924 kb
Host smart-632e5919-a4a2-4708-8bd0-bd467b892905
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129138523 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.2129138523
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.2991232159
Short name T733
Test name
Test status
Simulation time 40130209100 ps
CPU time 835.63 seconds
Started Jun 04 02:48:03 PM PDT 24
Finished Jun 04 03:01:59 PM PDT 24
Peak memory 263064 kb
Host smart-5139aa5f-feb1-4966-9efb-ff74d2e1e15c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991232159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.2991232159
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.3436338019
Short name T181
Test name
Test status
Simulation time 6353469900 ps
CPU time 73.26 seconds
Started Jun 04 02:48:04 PM PDT 24
Finished Jun 04 02:49:18 PM PDT 24
Peak memory 262052 kb
Host smart-f52e0860-7275-4613-8d0b-d4a9f5b953b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436338019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.3436338019
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.405733945
Short name T776
Test name
Test status
Simulation time 10466224200 ps
CPU time 154.09 seconds
Started Jun 04 02:48:18 PM PDT 24
Finished Jun 04 02:50:53 PM PDT 24
Peak memory 289500 kb
Host smart-aa3a918c-9e40-4d89-a0d8-c934f702cd79
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405733945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash
_ctrl_intr_rd.405733945
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.4245342124
Short name T947
Test name
Test status
Simulation time 12157496400 ps
CPU time 124.68 seconds
Started Jun 04 02:48:25 PM PDT 24
Finished Jun 04 02:50:30 PM PDT 24
Peak memory 293624 kb
Host smart-60949897-8a18-43c3-86c6-0c93fc68a7ad
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245342124 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.4245342124
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.1015115459
Short name T856
Test name
Test status
Simulation time 2405262800 ps
CPU time 77.76 seconds
Started Jun 04 02:48:18 PM PDT 24
Finished Jun 04 02:49:36 PM PDT 24
Peak memory 264840 kb
Host smart-656830c5-ac49-4365-b62d-cc7791c1787a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015115459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.1015115459
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2818366513
Short name T31
Test name
Test status
Simulation time 252094191300 ps
CPU time 374.34 seconds
Started Jun 04 02:48:25 PM PDT 24
Finished Jun 04 02:54:40 PM PDT 24
Peak memory 260028 kb
Host smart-2beb6634-b792-4201-9785-fff521a21211
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281
8366513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.2818366513
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.1134534647
Short name T193
Test name
Test status
Simulation time 11543936600 ps
CPU time 81.01 seconds
Started Jun 04 02:48:10 PM PDT 24
Finished Jun 04 02:49:31 PM PDT 24
Peak memory 260288 kb
Host smart-957166fe-f714-4a6f-b556-8e7b8395317d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134534647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.1134534647
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.3687195152
Short name T289
Test name
Test status
Simulation time 28265300 ps
CPU time 13.5 seconds
Started Jun 04 02:48:34 PM PDT 24
Finished Jun 04 02:48:48 PM PDT 24
Peak memory 259224 kb
Host smart-7759bb59-b5a4-4fbc-9971-ab9cab971c51
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687195152 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.3687195152
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.2917550680
Short name T103
Test name
Test status
Simulation time 3908560400 ps
CPU time 219.32 seconds
Started Jun 04 02:48:04 PM PDT 24
Finished Jun 04 02:51:43 PM PDT 24
Peak memory 262528 kb
Host smart-ad3f4e9a-3cf9-4137-aeee-55bfab15c3dc
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917550680 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.2917550680
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.2237328258
Short name T677
Test name
Test status
Simulation time 71937100 ps
CPU time 131.68 seconds
Started Jun 04 02:48:02 PM PDT 24
Finished Jun 04 02:50:14 PM PDT 24
Peak memory 260880 kb
Host smart-0e97f603-3648-4160-929c-a78310091078
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237328258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.2237328258
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.1081664436
Short name T738
Test name
Test status
Simulation time 30410300 ps
CPU time 102.87 seconds
Started Jun 04 02:48:02 PM PDT 24
Finished Jun 04 02:49:45 PM PDT 24
Peak memory 261456 kb
Host smart-ca5ca88f-8057-47e7-aefc-74cdadc43098
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1081664436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1081664436
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.3112216098
Short name T737
Test name
Test status
Simulation time 23723900 ps
CPU time 13.52 seconds
Started Jun 04 02:48:24 PM PDT 24
Finished Jun 04 02:48:38 PM PDT 24
Peak memory 258232 kb
Host smart-3fb0cedd-83e1-476c-ae09-a045f964bc2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112216098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.3112216098
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.3602485808
Short name T609
Test name
Test status
Simulation time 1696330700 ps
CPU time 1356.77 seconds
Started Jun 04 02:48:02 PM PDT 24
Finished Jun 04 03:10:39 PM PDT 24
Peak memory 286804 kb
Host smart-b8d58d65-8aac-4db3-9ae7-91a086eb4822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602485808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.3602485808
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.4285613402
Short name T603
Test name
Test status
Simulation time 134032200 ps
CPU time 35.71 seconds
Started Jun 04 02:48:25 PM PDT 24
Finished Jun 04 02:49:01 PM PDT 24
Peak memory 266936 kb
Host smart-646a6c1c-935c-432d-9d00-e52792078d48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285613402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.4285613402
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.1931451847
Short name T198
Test name
Test status
Simulation time 586602300 ps
CPU time 137.62 seconds
Started Jun 04 02:48:11 PM PDT 24
Finished Jun 04 02:50:29 PM PDT 24
Peak memory 281256 kb
Host smart-42ade0f5-eff8-4657-8bd8-dc53203d704f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931451847 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.1931451847
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.917139950
Short name T204
Test name
Test status
Simulation time 815033200 ps
CPU time 143.85 seconds
Started Jun 04 02:48:11 PM PDT 24
Finished Jun 04 02:50:35 PM PDT 24
Peak memory 281736 kb
Host smart-f010ee16-34af-4c89-a1d0-93fe96ddc51b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
917139950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.917139950
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.425897066
Short name T780
Test name
Test status
Simulation time 4832875600 ps
CPU time 163.22 seconds
Started Jun 04 02:48:09 PM PDT 24
Finished Jun 04 02:50:53 PM PDT 24
Peak memory 281112 kb
Host smart-da55a412-d090-434a-8a23-ae177916de13
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425897066 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.425897066
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.794667925
Short name T958
Test name
Test status
Simulation time 18233092300 ps
CPU time 744.33 seconds
Started Jun 04 02:48:10 PM PDT 24
Finished Jun 04 03:00:35 PM PDT 24
Peak memory 313464 kb
Host smart-033c549f-d1d3-4010-83ad-27855e207ca7
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794667925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.flash_ctrl_rw.794667925
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.3962650447
Short name T831
Test name
Test status
Simulation time 78463300 ps
CPU time 31.34 seconds
Started Jun 04 02:48:25 PM PDT 24
Finished Jun 04 02:48:57 PM PDT 24
Peak memory 274132 kb
Host smart-388ddafe-bf6f-4846-a4ab-592baf9ea9af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962650447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.3962650447
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.501245774
Short name T623
Test name
Test status
Simulation time 52884600 ps
CPU time 32.89 seconds
Started Jun 04 02:48:24 PM PDT 24
Finished Jun 04 02:48:58 PM PDT 24
Peak memory 275140 kb
Host smart-c0b38ddc-3d29-4b56-83a4-ea597153ac76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501245774 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.501245774
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.3395773522
Short name T210
Test name
Test status
Simulation time 1626220400 ps
CPU time 56.17 seconds
Started Jun 04 02:48:33 PM PDT 24
Finished Jun 04 02:49:30 PM PDT 24
Peak memory 262472 kb
Host smart-40d22f9c-b259-4fec-b892-e6a3e054a778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395773522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.3395773522
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.3381771356
Short name T460
Test name
Test status
Simulation time 1478600200 ps
CPU time 232.97 seconds
Started Jun 04 02:47:54 PM PDT 24
Finished Jun 04 02:51:47 PM PDT 24
Peak memory 281220 kb
Host smart-5694ed76-f95d-4c3f-a1b5-89543098ee37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381771356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.3381771356
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.3157033675
Short name T476
Test name
Test status
Simulation time 10364825200 ps
CPU time 228.3 seconds
Started Jun 04 02:48:09 PM PDT 24
Finished Jun 04 02:51:58 PM PDT 24
Peak memory 258560 kb
Host smart-c8b8c821-7158-4efb-a198-82496e19ce30
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157033675 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.flash_ctrl_wo.3157033675
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.3304851058
Short name T412
Test name
Test status
Simulation time 16319700 ps
CPU time 15.66 seconds
Started Jun 04 02:58:42 PM PDT 24
Finished Jun 04 02:58:58 PM PDT 24
Peak memory 275800 kb
Host smart-0ccb0a5d-85a9-4372-81ee-59390061666e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304851058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.3304851058
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.4092188284
Short name T761
Test name
Test status
Simulation time 68290900 ps
CPU time 130.85 seconds
Started Jun 04 02:58:42 PM PDT 24
Finished Jun 04 03:00:53 PM PDT 24
Peak memory 260988 kb
Host smart-1e9bbf22-a43b-4b9b-aeb7-a2d3b3bddaa0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092188284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.4092188284
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.2166533822
Short name T367
Test name
Test status
Simulation time 95286000 ps
CPU time 15.95 seconds
Started Jun 04 02:58:41 PM PDT 24
Finished Jun 04 02:58:57 PM PDT 24
Peak memory 275476 kb
Host smart-7d8d3f4b-e282-4aba-aa6e-2e163e6f1e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166533822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.2166533822
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.682204355
Short name T857
Test name
Test status
Simulation time 125122600 ps
CPU time 135.48 seconds
Started Jun 04 02:58:42 PM PDT 24
Finished Jun 04 03:00:58 PM PDT 24
Peak memory 259776 kb
Host smart-c3a99239-39f6-458f-8eea-72e6efe89d75
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682204355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_ot
p_reset.682204355
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.180628195
Short name T415
Test name
Test status
Simulation time 15471600 ps
CPU time 13.28 seconds
Started Jun 04 02:58:43 PM PDT 24
Finished Jun 04 02:58:57 PM PDT 24
Peak memory 275844 kb
Host smart-4e9b0c61-6456-48f4-bf03-3f97f33e70b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180628195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.180628195
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.1531490337
Short name T572
Test name
Test status
Simulation time 73895800 ps
CPU time 111.25 seconds
Started Jun 04 02:58:41 PM PDT 24
Finished Jun 04 03:00:32 PM PDT 24
Peak memory 259692 kb
Host smart-bf5b0edd-70f1-47f2-9f08-457a2c6319e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531490337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.1531490337
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.2664447215
Short name T754
Test name
Test status
Simulation time 16979500 ps
CPU time 13.1 seconds
Started Jun 04 02:58:40 PM PDT 24
Finished Jun 04 02:58:54 PM PDT 24
Peak memory 274780 kb
Host smart-3a9c5c46-f3be-48ff-9fba-9283965ff445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664447215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.2664447215
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.2331116679
Short name T571
Test name
Test status
Simulation time 73433700 ps
CPU time 134.29 seconds
Started Jun 04 02:58:43 PM PDT 24
Finished Jun 04 03:00:58 PM PDT 24
Peak memory 260968 kb
Host smart-161e7bbc-9725-42a1-a769-911b1e4c53b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331116679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.2331116679
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.2197452951
Short name T661
Test name
Test status
Simulation time 43827600 ps
CPU time 13.01 seconds
Started Jun 04 02:58:40 PM PDT 24
Finished Jun 04 02:58:54 PM PDT 24
Peak memory 275600 kb
Host smart-b7429e2b-e36d-480d-a436-2df166109403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197452951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.2197452951
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.536226705
Short name T466
Test name
Test status
Simulation time 55309800 ps
CPU time 129.49 seconds
Started Jun 04 02:58:42 PM PDT 24
Finished Jun 04 03:00:52 PM PDT 24
Peak memory 261944 kb
Host smart-b14a19d1-2f55-44c3-9d0e-3085f52ae8fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536226705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_ot
p_reset.536226705
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.1921654452
Short name T708
Test name
Test status
Simulation time 23669800 ps
CPU time 15.74 seconds
Started Jun 04 02:58:40 PM PDT 24
Finished Jun 04 02:58:56 PM PDT 24
Peak memory 275548 kb
Host smart-b7d262e3-0380-42a8-9ad8-587edcfa486f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921654452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.1921654452
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.2998425241
Short name T901
Test name
Test status
Simulation time 132043200 ps
CPU time 134.34 seconds
Started Jun 04 02:58:43 PM PDT 24
Finished Jun 04 03:00:58 PM PDT 24
Peak memory 259768 kb
Host smart-1115e39c-d735-4a9f-b706-d8c567acd9ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998425241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.2998425241
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.2785670246
Short name T799
Test name
Test status
Simulation time 24459700 ps
CPU time 16 seconds
Started Jun 04 02:58:41 PM PDT 24
Finished Jun 04 02:58:58 PM PDT 24
Peak memory 274696 kb
Host smart-c779e6de-709d-4364-8f19-6e67380bc7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785670246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.2785670246
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.3277700200
Short name T76
Test name
Test status
Simulation time 40149900 ps
CPU time 114.47 seconds
Started Jun 04 02:58:40 PM PDT 24
Finished Jun 04 03:00:36 PM PDT 24
Peak memory 264048 kb
Host smart-8110c138-635d-4fb4-9218-6615d75b6546
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277700200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.3277700200
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.444689232
Short name T979
Test name
Test status
Simulation time 48201600 ps
CPU time 13.55 seconds
Started Jun 04 02:58:42 PM PDT 24
Finished Jun 04 02:58:56 PM PDT 24
Peak memory 275456 kb
Host smart-c94daf6d-8fb2-4520-aadc-71ae2aceabda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444689232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.444689232
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.2798728332
Short name T75
Test name
Test status
Simulation time 73769400 ps
CPU time 135.4 seconds
Started Jun 04 02:58:43 PM PDT 24
Finished Jun 04 03:00:59 PM PDT 24
Peak memory 259620 kb
Host smart-fe2c8e39-77e0-43f8-ab77-8157f6a485e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798728332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.2798728332
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.260897522
Short name T1053
Test name
Test status
Simulation time 120639900 ps
CPU time 15.48 seconds
Started Jun 04 02:58:41 PM PDT 24
Finished Jun 04 02:58:57 PM PDT 24
Peak memory 275812 kb
Host smart-d0b042b9-a147-4d6d-92f6-402c27a326af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260897522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.260897522
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.2721800972
Short name T674
Test name
Test status
Simulation time 22793900 ps
CPU time 15.63 seconds
Started Jun 04 02:58:41 PM PDT 24
Finished Jun 04 02:58:57 PM PDT 24
Peak memory 275432 kb
Host smart-dfde1225-56d9-4bd6-be50-e7307174b3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721800972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.2721800972
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.3112676219
Short name T965
Test name
Test status
Simulation time 38818300 ps
CPU time 131.24 seconds
Started Jun 04 02:58:40 PM PDT 24
Finished Jun 04 03:00:52 PM PDT 24
Peak memory 259888 kb
Host smart-74cb631d-7970-43e3-9ac7-eba446fcc8f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112676219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.3112676219
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.4140221277
Short name T828
Test name
Test status
Simulation time 66674200 ps
CPU time 14.04 seconds
Started Jun 04 02:49:17 PM PDT 24
Finished Jun 04 02:49:31 PM PDT 24
Peak memory 257792 kb
Host smart-4c5c8ce9-8b3d-46c9-9d2f-29ba5dfba86e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140221277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.4
140221277
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.3451805225
Short name T963
Test name
Test status
Simulation time 16955300 ps
CPU time 13.38 seconds
Started Jun 04 02:49:22 PM PDT 24
Finished Jun 04 02:49:36 PM PDT 24
Peak memory 275580 kb
Host smart-07aeaee7-3f16-49f0-abea-c3fcf7eaa066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451805225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.3451805225
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.3040175373
Short name T19
Test name
Test status
Simulation time 14138100 ps
CPU time 22.82 seconds
Started Jun 04 02:49:13 PM PDT 24
Finished Jun 04 02:49:37 PM PDT 24
Peak memory 280340 kb
Host smart-c05a22d4-05c8-4cf9-b0a6-cd46a5c85e31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040175373 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.3040175373
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.679104116
Short name T751
Test name
Test status
Simulation time 20715716400 ps
CPU time 2631.23 seconds
Started Jun 04 02:48:57 PM PDT 24
Finished Jun 04 03:32:49 PM PDT 24
Peak memory 264524 kb
Host smart-7a0e4ad2-9b2b-4a3f-ae59-abe9e6b66eb0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679104116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_erro
r_mp.679104116
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.3594151656
Short name T1082
Test name
Test status
Simulation time 356786800 ps
CPU time 783.72 seconds
Started Jun 04 02:48:49 PM PDT 24
Finished Jun 04 03:01:53 PM PDT 24
Peak memory 264808 kb
Host smart-2bda33c0-9b77-495e-938c-9afdca826aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594151656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3594151656
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.4050792371
Short name T449
Test name
Test status
Simulation time 146485800 ps
CPU time 22.73 seconds
Started Jun 04 02:48:50 PM PDT 24
Finished Jun 04 02:49:13 PM PDT 24
Peak memory 264816 kb
Host smart-11540b72-e819-43a8-8abb-3d88655d1739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050792371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.4050792371
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1796088048
Short name T760
Test name
Test status
Simulation time 10012933500 ps
CPU time 121.69 seconds
Started Jun 04 02:49:18 PM PDT 24
Finished Jun 04 02:51:20 PM PDT 24
Peak memory 315876 kb
Host smart-823ef212-6fe0-490d-9df9-b5618433860c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796088048 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.1796088048
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.3891081320
Short name T282
Test name
Test status
Simulation time 49810000 ps
CPU time 13.41 seconds
Started Jun 04 02:49:14 PM PDT 24
Finished Jun 04 02:49:28 PM PDT 24
Peak memory 264972 kb
Host smart-0e58d692-614f-44cc-a00b-e4ac33129df4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891081320 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.3891081320
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.1235514939
Short name T1086
Test name
Test status
Simulation time 80145216800 ps
CPU time 844.25 seconds
Started Jun 04 02:48:54 PM PDT 24
Finished Jun 04 03:02:59 PM PDT 24
Peak memory 263060 kb
Host smart-ddae73b9-e2a7-47e5-bffc-f4af2882d91f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235514939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.1235514939
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.2927529740
Short name T1059
Test name
Test status
Simulation time 2185901900 ps
CPU time 46.18 seconds
Started Jun 04 02:48:41 PM PDT 24
Finished Jun 04 02:49:28 PM PDT 24
Peak memory 262368 kb
Host smart-51a5a393-8696-4cf6-8954-29b6f260942c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927529740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.2927529740
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.1755270456
Short name T915
Test name
Test status
Simulation time 4988625500 ps
CPU time 231.55 seconds
Started Jun 04 02:49:09 PM PDT 24
Finished Jun 04 02:53:01 PM PDT 24
Peak memory 289464 kb
Host smart-4c4b6ec5-7282-4ed5-98a0-5bd6b5751e97
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755270456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.1755270456
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.4271904390
Short name T907
Test name
Test status
Simulation time 12419306400 ps
CPU time 284.55 seconds
Started Jun 04 02:49:11 PM PDT 24
Finished Jun 04 02:53:56 PM PDT 24
Peak memory 293000 kb
Host smart-fa942afd-0a94-4b72-a857-b1158ef92225
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271904390 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.4271904390
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.1376258312
Short name T631
Test name
Test status
Simulation time 4527001500 ps
CPU time 70.97 seconds
Started Jun 04 02:49:13 PM PDT 24
Finished Jun 04 02:50:25 PM PDT 24
Peak memory 264808 kb
Host smart-316692ca-fe55-454b-b1d1-d5e3cc47becc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376258312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.1376258312
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.369592691
Short name T96
Test name
Test status
Simulation time 37389732700 ps
CPU time 190.84 seconds
Started Jun 04 02:49:11 PM PDT 24
Finished Jun 04 02:52:22 PM PDT 24
Peak memory 264900 kb
Host smart-6539b20c-bf3a-4b49-862f-04dff969526b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369
592691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.369592691
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.2653056824
Short name T1060
Test name
Test status
Simulation time 6787673600 ps
CPU time 62.84 seconds
Started Jun 04 02:48:52 PM PDT 24
Finished Jun 04 02:49:55 PM PDT 24
Peak memory 260464 kb
Host smart-6054fb35-ffc7-4ab7-baaa-fc181922c759
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653056824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.2653056824
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.2188576965
Short name T1040
Test name
Test status
Simulation time 33871200 ps
CPU time 13.97 seconds
Started Jun 04 02:49:14 PM PDT 24
Finished Jun 04 02:49:29 PM PDT 24
Peak memory 264864 kb
Host smart-174659f9-4529-4dcb-8e7f-ede33e65b4e1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188576965 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.2188576965
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.3128017151
Short name T698
Test name
Test status
Simulation time 4144612400 ps
CPU time 166.25 seconds
Started Jun 04 02:48:51 PM PDT 24
Finished Jun 04 02:51:38 PM PDT 24
Peak memory 264888 kb
Host smart-87954513-1d8e-4a86-91aa-121d06044416
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128017151 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.3128017151
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.509645241
Short name T719
Test name
Test status
Simulation time 39627000 ps
CPU time 136.66 seconds
Started Jun 04 02:48:58 PM PDT 24
Finished Jun 04 02:51:15 PM PDT 24
Peak memory 262192 kb
Host smart-6f3c5706-1e35-468a-95bd-f1c68fb14430
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509645241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp
_reset.509645241
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.3157594666
Short name T614
Test name
Test status
Simulation time 727577000 ps
CPU time 256.77 seconds
Started Jun 04 02:48:40 PM PDT 24
Finished Jun 04 02:52:58 PM PDT 24
Peak memory 262092 kb
Host smart-865ae39c-bcac-4d78-b366-e5d95057d94f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3157594666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3157594666
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.422959438
Short name T492
Test name
Test status
Simulation time 218626600 ps
CPU time 13.86 seconds
Started Jun 04 02:49:15 PM PDT 24
Finished Jun 04 02:49:29 PM PDT 24
Peak memory 264772 kb
Host smart-6d5ce83b-8c0b-4080-bc8e-529c0230e2ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422959438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_rese
t.422959438
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.3002021706
Short name T923
Test name
Test status
Simulation time 2886298800 ps
CPU time 308 seconds
Started Jun 04 02:48:33 PM PDT 24
Finished Jun 04 02:53:41 PM PDT 24
Peak memory 279156 kb
Host smart-376a4c75-dfc4-4a4d-89a6-ba3ee64b3399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002021706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.3002021706
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.1006599838
Short name T327
Test name
Test status
Simulation time 372182100 ps
CPU time 34.8 seconds
Started Jun 04 02:49:16 PM PDT 24
Finished Jun 04 02:49:51 PM PDT 24
Peak memory 269184 kb
Host smart-0bb5de28-15f2-4368-8f93-0c05f6a79113
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006599838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.1006599838
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.918948026
Short name T1039
Test name
Test status
Simulation time 3165059400 ps
CPU time 135.97 seconds
Started Jun 04 02:48:54 PM PDT 24
Finished Jun 04 02:51:11 PM PDT 24
Peak memory 296756 kb
Host smart-97ba1153-966b-43d0-aab2-a82e9235d1e9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918948026 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.flash_ctrl_ro.918948026
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.1027663857
Short name T432
Test name
Test status
Simulation time 2527062700 ps
CPU time 158.94 seconds
Started Jun 04 02:48:59 PM PDT 24
Finished Jun 04 02:51:38 PM PDT 24
Peak memory 293512 kb
Host smart-5601960e-b836-48fa-a264-a80f00847b8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027663857 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.1027663857
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.1022114994
Short name T97
Test name
Test status
Simulation time 25614375200 ps
CPU time 617.2 seconds
Started Jun 04 02:48:58 PM PDT 24
Finished Jun 04 02:59:16 PM PDT 24
Peak memory 309116 kb
Host smart-93a84fae-0980-4d75-9998-93adeb8ab101
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022114994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.flash_ctrl_rw.1022114994
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.4102381064
Short name T794
Test name
Test status
Simulation time 28499100 ps
CPU time 30.66 seconds
Started Jun 04 02:49:14 PM PDT 24
Finished Jun 04 02:49:45 PM PDT 24
Peak memory 273076 kb
Host smart-b960253c-2756-4b7d-b5a4-0f8a4d604b5f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102381064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.4102381064
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.3691063299
Short name T328
Test name
Test status
Simulation time 43277900 ps
CPU time 28.18 seconds
Started Jun 04 02:49:19 PM PDT 24
Finished Jun 04 02:49:48 PM PDT 24
Peak memory 274340 kb
Host smart-61e32db8-42e7-4d4b-b096-f76ce4e3a495
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691063299 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.3691063299
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.1261813065
Short name T167
Test name
Test status
Simulation time 62666500100 ps
CPU time 810.34 seconds
Started Jun 04 02:49:06 PM PDT 24
Finished Jun 04 03:02:37 PM PDT 24
Peak memory 319872 kb
Host smart-10623225-ebe8-46aa-82d8-665cade03247
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261813065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s
err.1261813065
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.1761803679
Short name T680
Test name
Test status
Simulation time 3401268800 ps
CPU time 78.29 seconds
Started Jun 04 02:49:14 PM PDT 24
Finished Jun 04 02:50:32 PM PDT 24
Peak memory 264720 kb
Host smart-4c540352-76f2-45ef-92a8-9dcd80fc18dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761803679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1761803679
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.2813831998
Short name T521
Test name
Test status
Simulation time 27661700 ps
CPU time 119.15 seconds
Started Jun 04 02:48:33 PM PDT 24
Finished Jun 04 02:50:32 PM PDT 24
Peak memory 275532 kb
Host smart-328732cc-e9a8-4569-a62a-3c5536b597ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813831998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.2813831998
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.96048718
Short name T1087
Test name
Test status
Simulation time 3964646300 ps
CPU time 169.62 seconds
Started Jun 04 02:48:55 PM PDT 24
Finished Jun 04 02:51:45 PM PDT 24
Peak memory 258952 kb
Host smart-24820460-8420-4e94-8e48-39b5cd7d5607
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96048718 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_wo.96048718
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.4267591593
Short name T748
Test name
Test status
Simulation time 25216400 ps
CPU time 13.27 seconds
Started Jun 04 02:50:03 PM PDT 24
Finished Jun 04 02:50:17 PM PDT 24
Peak memory 258032 kb
Host smart-6b6fbd2f-cbf8-4ede-b779-620fea0539de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267591593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.4
267591593
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.3906831343
Short name T689
Test name
Test status
Simulation time 16453100 ps
CPU time 13.34 seconds
Started Jun 04 02:49:55 PM PDT 24
Finished Jun 04 02:50:09 PM PDT 24
Peak memory 275604 kb
Host smart-cd571613-f4cf-46bc-9f54-581b8445f3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906831343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.3906831343
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.4169766959
Short name T178
Test name
Test status
Simulation time 10746700 ps
CPU time 22.94 seconds
Started Jun 04 02:49:56 PM PDT 24
Finished Jun 04 02:50:20 PM PDT 24
Peak memory 273212 kb
Host smart-8f766e15-10fc-4ae6-a59e-97e6df31bff1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169766959 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.4169766959
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.746627308
Short name T220
Test name
Test status
Simulation time 2653043500 ps
CPU time 2247.12 seconds
Started Jun 04 02:49:32 PM PDT 24
Finished Jun 04 03:27:00 PM PDT 24
Peak memory 264564 kb
Host smart-5e6f2977-787d-4beb-aa21-9c0b466511a5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746627308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_erro
r_mp.746627308
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.3207574847
Short name T66
Test name
Test status
Simulation time 692855300 ps
CPU time 842.17 seconds
Started Jun 04 02:49:32 PM PDT 24
Finished Jun 04 03:03:35 PM PDT 24
Peak memory 273000 kb
Host smart-bfe283a6-33bf-4f67-8cb5-cfc3d69ec1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207574847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.3207574847
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.4147141575
Short name T488
Test name
Test status
Simulation time 156295900 ps
CPU time 24.06 seconds
Started Jun 04 02:49:31 PM PDT 24
Finished Jun 04 02:49:56 PM PDT 24
Peak memory 264896 kb
Host smart-d9298bcd-8587-4089-a33c-5e8555b8e03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147141575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.4147141575
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1553180672
Short name T285
Test name
Test status
Simulation time 10016231100 ps
CPU time 91.95 seconds
Started Jun 04 02:50:02 PM PDT 24
Finished Jun 04 02:51:35 PM PDT 24
Peak memory 287952 kb
Host smart-23505754-c878-4abf-8140-7f7cbb9ead99
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553180672 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.1553180672
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.1282290706
Short name T1075
Test name
Test status
Simulation time 34250300 ps
CPU time 13.21 seconds
Started Jun 04 02:50:05 PM PDT 24
Finished Jun 04 02:50:19 PM PDT 24
Peak memory 258000 kb
Host smart-0f855fd1-f10a-4d87-b912-0bd3dcb25c84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282290706 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.1282290706
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.246410806
Short name T159
Test name
Test status
Simulation time 40128154500 ps
CPU time 825.37 seconds
Started Jun 04 02:49:32 PM PDT 24
Finished Jun 04 03:03:18 PM PDT 24
Peak memory 262916 kb
Host smart-c2e7036a-6a4f-4816-8035-717c65e4d5ea
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246410806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.flash_ctrl_hw_rma_reset.246410806
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.539310335
Short name T313
Test name
Test status
Simulation time 1693066800 ps
CPU time 99.93 seconds
Started Jun 04 02:49:30 PM PDT 24
Finished Jun 04 02:51:11 PM PDT 24
Peak memory 262524 kb
Host smart-ae0edadb-a28b-4577-8d42-58d614cf8734
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539310335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw
_sec_otp.539310335
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.4148793258
Short name T37
Test name
Test status
Simulation time 23435057200 ps
CPU time 209.71 seconds
Started Jun 04 02:49:41 PM PDT 24
Finished Jun 04 02:53:11 PM PDT 24
Peak memory 289488 kb
Host smart-77b5f72f-09f3-41f0-8c71-c6822a475dac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148793258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.4148793258
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.268236135
Short name T346
Test name
Test status
Simulation time 13616080000 ps
CPU time 200.03 seconds
Started Jun 04 02:49:47 PM PDT 24
Finished Jun 04 02:53:08 PM PDT 24
Peak memory 292796 kb
Host smart-511d2942-b4e4-4818-8d36-e9b091601694
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268236135 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.268236135
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.1660469713
Short name T474
Test name
Test status
Simulation time 4148150000 ps
CPU time 68.23 seconds
Started Jun 04 02:49:40 PM PDT 24
Finished Jun 04 02:50:48 PM PDT 24
Peak memory 259568 kb
Host smart-95a5915c-7888-4561-a9fc-7ff6dc349bda
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660469713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.1660469713
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1045054785
Short name T820
Test name
Test status
Simulation time 31836344600 ps
CPU time 173.03 seconds
Started Jun 04 02:49:46 PM PDT 24
Finished Jun 04 02:52:39 PM PDT 24
Peak memory 259344 kb
Host smart-ead28231-11c3-46b9-a2ca-2c7e2c2e7036
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104
5054785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.1045054785
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.2221561869
Short name T401
Test name
Test status
Simulation time 4769760300 ps
CPU time 65.1 seconds
Started Jun 04 02:49:36 PM PDT 24
Finished Jun 04 02:50:41 PM PDT 24
Peak memory 260508 kb
Host smart-a0bf6ddc-a212-47f1-b125-eb1b47d0e36b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221561869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2221561869
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.557438780
Short name T944
Test name
Test status
Simulation time 27126100 ps
CPU time 13.49 seconds
Started Jun 04 02:49:55 PM PDT 24
Finished Jun 04 02:50:09 PM PDT 24
Peak memory 260080 kb
Host smart-0e408463-0ea6-45e5-8e84-f5f77c844296
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557438780 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.557438780
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.2085547260
Short name T87
Test name
Test status
Simulation time 14811593600 ps
CPU time 250.38 seconds
Started Jun 04 02:49:33 PM PDT 24
Finished Jun 04 02:53:44 PM PDT 24
Peak memory 273692 kb
Host smart-7bc1010d-767a-4e9a-b45b-92a18a59b9ef
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085547260 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.2085547260
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.1483038530
Short name T376
Test name
Test status
Simulation time 279719000 ps
CPU time 129.71 seconds
Started Jun 04 02:49:31 PM PDT 24
Finished Jun 04 02:51:41 PM PDT 24
Peak memory 263184 kb
Host smart-a1732045-e7b5-4bee-8012-9c6dd82020c6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483038530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.1483038530
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.3755380363
Short name T577
Test name
Test status
Simulation time 108628400 ps
CPU time 112.48 seconds
Started Jun 04 02:49:25 PM PDT 24
Finished Jun 04 02:51:18 PM PDT 24
Peak memory 264808 kb
Host smart-d644601f-a11b-49f0-bf32-89675ea44429
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3755380363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.3755380363
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.1047720269
Short name T987
Test name
Test status
Simulation time 4878881700 ps
CPU time 158.68 seconds
Started Jun 04 02:49:48 PM PDT 24
Finished Jun 04 02:52:27 PM PDT 24
Peak memory 258900 kb
Host smart-b376db0d-28aa-421f-ac84-d07a5179bade
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047720269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.1047720269
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.1127431675
Short name T6
Test name
Test status
Simulation time 95818400 ps
CPU time 248.9 seconds
Started Jun 04 02:49:26 PM PDT 24
Finished Jun 04 02:53:36 PM PDT 24
Peak memory 281112 kb
Host smart-8b42fea3-f3c1-42bd-8da0-a32d73382158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127431675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.1127431675
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.425065916
Short name T490
Test name
Test status
Simulation time 183355900 ps
CPU time 33.04 seconds
Started Jun 04 02:49:55 PM PDT 24
Finished Jun 04 02:50:28 PM PDT 24
Peak memory 273156 kb
Host smart-370e9b40-05e8-47de-99b1-47cf816a6f27
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425065916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_re_evict.425065916
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.726482735
Short name T205
Test name
Test status
Simulation time 449762100 ps
CPU time 102.35 seconds
Started Jun 04 02:49:30 PM PDT 24
Finished Jun 04 02:51:13 PM PDT 24
Peak memory 296692 kb
Host smart-ddecd030-f266-4f67-97e9-87da9100f20f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726482735 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.flash_ctrl_ro.726482735
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.2694319085
Short name T786
Test name
Test status
Simulation time 2080984800 ps
CPU time 137.56 seconds
Started Jun 04 02:49:39 PM PDT 24
Finished Jun 04 02:51:57 PM PDT 24
Peak memory 281188 kb
Host smart-7a851ad8-e72b-424a-ba4a-14cbcec37d73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2694319085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.2694319085
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.3837143334
Short name T638
Test name
Test status
Simulation time 1285582900 ps
CPU time 120.77 seconds
Started Jun 04 02:49:38 PM PDT 24
Finished Jun 04 02:51:39 PM PDT 24
Peak memory 293900 kb
Host smart-fb8e70c2-3f94-45ac-813b-4fc761203c59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837143334 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.3837143334
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.777423956
Short name T522
Test name
Test status
Simulation time 14740969200 ps
CPU time 544.85 seconds
Started Jun 04 02:49:36 PM PDT 24
Finished Jun 04 02:58:41 PM PDT 24
Peak memory 309108 kb
Host smart-4abe683e-2ec6-4a3f-a67b-907a42d933e8
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777423956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.flash_ctrl_rw.777423956
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.3244702836
Short name T645
Test name
Test status
Simulation time 29961000 ps
CPU time 31.41 seconds
Started Jun 04 02:49:48 PM PDT 24
Finished Jun 04 02:50:20 PM PDT 24
Peak memory 275112 kb
Host smart-2f4b2ef1-3531-4bd8-9850-5b3bac210a23
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244702836 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.3244702836
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.3352778810
Short name T796
Test name
Test status
Simulation time 4175446300 ps
CPU time 641.66 seconds
Started Jun 04 02:49:40 PM PDT 24
Finished Jun 04 03:00:22 PM PDT 24
Peak memory 311700 kb
Host smart-8bf8b8ba-ab0d-467b-b557-4af17c769b8e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352778810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s
err.3352778810
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.4259000157
Short name T386
Test name
Test status
Simulation time 434649800 ps
CPU time 59.1 seconds
Started Jun 04 02:49:56 PM PDT 24
Finished Jun 04 02:50:56 PM PDT 24
Peak memory 262940 kb
Host smart-3ee1f468-d0f9-4811-9160-55ef301cc76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259000157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.4259000157
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.425412684
Short name T579
Test name
Test status
Simulation time 57567200 ps
CPU time 122.62 seconds
Started Jun 04 02:49:17 PM PDT 24
Finished Jun 04 02:51:20 PM PDT 24
Peak memory 275612 kb
Host smart-8e824739-f580-47e2-b328-2449fdfaba6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425412684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.425412684
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.2229689952
Short name T951
Test name
Test status
Simulation time 2153446500 ps
CPU time 180.69 seconds
Started Jun 04 02:49:31 PM PDT 24
Finished Jun 04 02:52:32 PM PDT 24
Peak memory 264824 kb
Host smart-1134912e-401b-41bf-aaef-bb9a64fe001f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229689952 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.flash_ctrl_wo.2229689952
Directory /workspace/9.flash_ctrl_wo/latest
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