Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	369629	1		T1	2		T2	1		T3	2
all_values[1]	369629	1		T1	2		T2	1		T3	2
all_values[2]	369629	1		T1	2		T2	1		T3	2
all_values[3]	369629	1		T1	2		T2	1		T3	2
all_values[4]	369629	1		T1	2		T2	1		T3	2
all_values[5]	369629	1		T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	745544	1		T1	12		T2	6		T3	12
auto[1]	1472230	1		T28	4560		T35	12528		T37	1080

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1089364	1		T1	7		T2	4		T3	7
auto[1]	1128410	1		T1	5		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	369469	1		T1	2		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	160	1		T257	4		T258	2		T259	3
all_values[1]	auto[0]	auto[1]	369484	1		T1	2		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	145	1		T257	1		T258	1		T259	7
all_values[2]	auto[0]	auto[0]	1596	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	52	1		T257	1		T258	2		T259	1
all_values[2]	auto[1]	auto[0]	367921	1		T28	1140		T35	3132		T37	270
all_values[2]	auto[1]	auto[1]	60	1		T257	1		T258	2		T259	3
all_values[3]	auto[0]	auto[0]	1593	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	76	1		T257	2		T258	1		T259	1
all_values[3]	auto[1]	auto[0]	83991	1		T28	570		T35	1566		T37	88
all_values[3]	auto[1]	auto[1]	283969	1		T28	570		T35	1566		T37	182
all_values[4]	auto[0]	auto[0]	1114	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	521	1		T1	1		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	263720	1		T28	570		T35	1566		T37	179
all_values[4]	auto[1]	auto[1]	104274	1		T28	570		T35	1566		T37	91
all_values[5]	auto[0]	auto[0]	1507	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	132	1		T21	1		T38	1		T39	5
all_values[5]	auto[1]	auto[0]	367922	1		T28	1140		T35	3132		T37	270
all_values[5]	auto[1]	auto[1]	68	1		T257	1		T258	2		T314	2