Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	251291	1		T1	3		T2	1		T3	6
auto[FlashEraseBank]	278022	1		T1	2		T3	2		T21	153

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	264062	1		T1	1		T3	4		T4	7
auto[FlashOpProgram]	246131	1		T1	4		T2	1		T3	4
auto[FlashOpErase]	15120	1		T4	9		T42	1		T66	2
auto[FlashOpInvalid]	4000	1		T60	200		T90	200		T117	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	264062	1		T1	1		T3	4		T4	7
op[FlashOpProgram]	246131	1		T1	4		T2	1		T3	4
op[FlashOpErase]	15120	1		T4	9		T42	1		T66	2
read_erase_read	648	1		T25	14		T23	2		T34	2
read_prog_read	823	1		T3	3		T5	6		T23	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	388337	1		T1	5		T2	1		T3	8
auto[FlashPartInfo]	137231	1		T4	464		T21	125		T5	425
auto[FlashPartInfo1]	974	1		T5	2		T22	64		T6	1
auto[FlashPartInfo2]	2771	1		T5	18		T22	128		T6	4

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpInvalid]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	190941	1		T1	1		T3	4		T21	82
auto[FlashPartData]	auto[FlashOpProgram]	189721	1		T1	4		T2	1		T3	4
auto[FlashPartData]	auto[FlashOpErase]	3745	1		T42	1		T66	1		T60	98
auto[FlashPartData]	auto[FlashOpInvalid]	3930	1		T60	196		T90	196		T117	196
auto[FlashPartInfo]	auto[FlashOpRead]	70523	1		T4	7		T21	78		T5	217
auto[FlashPartInfo]	auto[FlashOpProgram]	55301	1		T4	448		T21	47		T5	208
auto[FlashPartInfo]	auto[FlashOpErase]	11345	1		T4	9		T66	1		T60	2
auto[FlashPartInfo]	auto[FlashOpInvalid]	62	1		T60	4		T90	4		T117	2
auto[FlashPartInfo1]	auto[FlashOpRead]	806	1		T5	2		T22	32		T6	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T22	32		T167	1		T287	1
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T97	1		T115	2		T103	1
auto[FlashPartInfo2]	auto[FlashOpRead]	1792	1		T5	11		T22	64		T6	4
auto[FlashPartInfo2]	auto[FlashOpProgram]	947	1		T5	7		T22	64		T67	6
auto[FlashPartInfo2]	auto[FlashOpErase]	24	1		T117	1		T160	1		T161	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T117	2		T119	2		T341	2