Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	7	25	78.12

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	7	25	78.12	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29023	1		T3	16		T42	4		T60	400
auto[1]	12	1		T21	1		T176	2		T211	1
auto[2]	27	1		T64	16		T40	1		T319	1
auto[3]	71	1		T5	1		T26	1		T27	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7283	1		T3	4		T21	1		T42	1
evic_idx[1]	7286	1		T3	4		T5	1		T42	1
evic_idx[2]	7282	1		T3	4		T42	1		T60	100
evic_idx[3]	7282	1		T3	4		T42	1		T60	100

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28200	1		T42	4		T60	400		T89	440
evic_op[2]	305	1		T3	16		T21	1		T5	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	7	25	78.12	7

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[2]]	*	[auto[2]]	--	--	2

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[1]]	[auto[1]]	0	1	1
[evic_idx[0]]	[evic_op[2]]	[auto[2]]	0	1	1
[evic_idx[1]]	[evic_op[1]]	[auto[2]]	0	1	1
[evic_idx[3]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7044	1		T42	1		T60	100		T89	110
evic_idx[0]	evic_op[1]	auto[2]	1	1		T320	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	4	1		T321	3		T322	1		-	-
evic_idx[0]	evic_op[2]	auto[0]	62	1		T3	4		T23	4		T45	1
evic_idx[0]	evic_op[2]	auto[1]	4	1		T21	1		T211	1		T323	1
evic_idx[0]	evic_op[2]	auto[3]	11	1		T207	1		T324	1		T199	1
evic_idx[1]	evic_op[1]	auto[0]	7045	1		T42	1		T60	100		T89	110
evic_idx[1]	evic_op[1]	auto[1]	1	1		T325	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	6	1		T326	1		T321	3		T327	1
evic_idx[1]	evic_op[2]	auto[0]	59	1		T3	4		T23	4		T45	1
evic_idx[1]	evic_op[2]	auto[1]	1	1		T323	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	1	1		T319	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	16	1		T5	1		T29	1		T41	1
evic_idx[2]	evic_op[1]	auto[0]	7044	1		T42	1		T60	100		T89	110
evic_idx[2]	evic_op[1]	auto[1]	1	1		T325	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	4	1		T321	3		T322	1		-	-
evic_idx[2]	evic_op[2]	auto[0]	59	1		T3	4		T23	4		T45	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T176	1		T328	1		T323	1
evic_idx[2]	evic_op[2]	auto[3]	14	1		T26	1		T27	1		T29	1
evic_idx[3]	evic_op[1]	auto[0]	7045	1		T42	1		T60	100		T89	110
evic_idx[3]	evic_op[1]	auto[3]	5	1		T326	1		T321	3		T322	1
evic_idx[3]	evic_op[2]	auto[0]	61	1		T3	4		T23	4		T61	1
evic_idx[3]	evic_op[2]	auto[1]	2	1		T176	1		T329	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	1	1		T40	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	11	1		T29	1		T199	1		T330	1