Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	39149	1		T243	2624		T331	15371		T332	2643
rd_lvl[2]	62794	1		T243	2305		T331	11189		T332	2289
rd_lvl[3]	16671	1		T243	1317		T332	1418		T333	328
rd_lvl[4]	31430	1		T243	1477		T332	1389		T334	5573
rd_lvl[5]	18365	1		T243	1391		T278	2221		T332	1287
rd_lvl[6]	12267	1		T243	9		T278	1204		T332	3
rd_lvl[7]	12672	1		T37	140		T243	1359		T332	1261
rd_lvl[8]	14822	1		T37	35		T243	1359		T335	872
rd_lvl[9]	6169	1		T37	4		T243	1741		T335	136
rd_lvl[10]	11956	1		T37	3		T125	1434		T243	977
rd_lvl[11]	5529	1		T125	304		T36	289		T335	118
rd_lvl[12]	6923	1		T223	1296		T36	111		T336	1
rd_lvl[13]	1253	1		T223	362		T336	19		T269	156
rd_lvl[14]	2340	1		T28	284		T36	113		T337	17
rd_lvl[15]	2546	1		T28	225		T35	452		T269	44