Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	369629	1		T1	2		T2	1		T3	2
all_pins[1]	369629	1		T1	2		T2	1		T3	2
all_pins[2]	369629	1		T1	2		T2	1		T3	2
all_pins[3]	369629	1		T1	2		T2	1		T3	2
all_pins[4]	369629	1		T1	2		T2	1		T3	2
all_pins[5]	369629	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1855297	1		T1	12		T2	6		T3	12
values[0x1]	362477	1		T28	1262		T35	5360		T37	274
transitions[0x0=>0x1]	331327	1		T28	1140		T35	3132		T37	270
transitions[0x1=>0x0]	331314	1		T28	1140		T35	3132		T37	270

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	369469	1		T1	2		T2	1		T3	2
all_pins[0]	values[0x1]	160	1		T257	4		T258	2		T259	3
all_pins[0]	transitions[0x0=>0x1]	88	1		T257	3		T258	2		T259	1
all_pins[0]	transitions[0x1=>0x0]	73	1		T258	1		T259	5		T314	3
all_pins[1]	values[0x0]	369484	1		T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	145	1		T257	1		T258	1		T259	7
all_pins[1]	transitions[0x0=>0x1]	118	1		T257	1		T258	1		T259	5
all_pins[1]	transitions[0x1=>0x0]	1913	1		T28	61		T35	1114		T342	2
all_pins[2]	values[0x0]	367689	1		T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	1940	1		T28	61		T35	1114		T342	2
all_pins[2]	transitions[0x0=>0x1]	45	1		T258	1		T259	3		T313	1
all_pins[2]	transitions[0x1=>0x0]	245111	1		T28	509		T35	452		T37	182
all_pins[3]	values[0x0]	122623	1		T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	247006	1		T28	570		T35	1566		T37	182
all_pins[3]	transitions[0x0=>0x1]	217893	1		T28	509		T35	452		T37	178
all_pins[3]	transitions[0x1=>0x0]	84045	1		T28	570		T35	1566		T37	88
all_pins[4]	values[0x0]	256471	1		T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	113158	1		T28	631		T35	2680		T37	92
all_pins[4]	transitions[0x0=>0x1]	113150	1		T28	631		T35	2680		T37	92
all_pins[4]	transitions[0x1=>0x0]	60	1		T257	1		T258	2		T314	2
all_pins[5]	values[0x0]	369561	1		T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	68	1		T257	1		T258	2		T314	2
all_pins[5]	transitions[0x0=>0x1]	33	1		T258	1		T314	1		T315	1
all_pins[5]	transitions[0x1=>0x0]	112	1		T257	3		T258	1		T259	3