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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.52 95.84 94.24 98.85 92.52 98.24 98.01 97.93


Total test records in report: 1248
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T1073 /workspace/coverage/default/6.flash_ctrl_phy_arb.3008794725 Jun 05 06:01:53 PM PDT 24 Jun 05 06:10:18 PM PDT 24 3893433000 ps
T1074 /workspace/coverage/default/7.flash_ctrl_rw_evict.2063448866 Jun 05 06:01:55 PM PDT 24 Jun 05 06:02:26 PM PDT 24 45057500 ps
T274 /workspace/coverage/default/1.flash_ctrl_host_dir_rd.745548940 Jun 05 06:01:16 PM PDT 24 Jun 05 06:02:26 PM PDT 24 455781100 ps
T1075 /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.1459699910 Jun 05 06:04:02 PM PDT 24 Jun 05 06:08:42 PM PDT 24 6568587700 ps
T1076 /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2448424785 Jun 05 06:02:20 PM PDT 24 Jun 05 06:04:46 PM PDT 24 10012034400 ps
T1077 /workspace/coverage/default/10.flash_ctrl_ro.354533593 Jun 05 06:02:23 PM PDT 24 Jun 05 06:04:11 PM PDT 24 653272200 ps
T146 /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.97206835 Jun 05 06:01:55 PM PDT 24 Jun 05 06:15:04 PM PDT 24 140168540300 ps
T1078 /workspace/coverage/default/41.flash_ctrl_connect.445276691 Jun 05 06:05:08 PM PDT 24 Jun 05 06:05:25 PM PDT 24 24210100 ps
T1079 /workspace/coverage/default/0.flash_ctrl_intr_wr.1516849979 Jun 05 06:00:47 PM PDT 24 Jun 05 06:01:53 PM PDT 24 4313398600 ps
T1080 /workspace/coverage/default/1.flash_ctrl_rd_intg.1574909624 Jun 05 06:01:11 PM PDT 24 Jun 05 06:01:44 PM PDT 24 996438100 ps
T1081 /workspace/coverage/default/39.flash_ctrl_smoke.2428480024 Jun 05 06:05:09 PM PDT 24 Jun 05 06:07:14 PM PDT 24 76368200 ps
T1082 /workspace/coverage/default/23.flash_ctrl_rw_evict.4184911276 Jun 05 06:04:02 PM PDT 24 Jun 05 06:04:32 PM PDT 24 46175600 ps
T1083 /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.3892194274 Jun 05 06:03:34 PM PDT 24 Jun 05 06:03:49 PM PDT 24 21352700 ps
T1084 /workspace/coverage/default/0.flash_ctrl_stress_all.3641760069 Jun 05 06:00:51 PM PDT 24 Jun 05 06:15:32 PM PDT 24 176421200 ps
T1085 /workspace/coverage/default/23.flash_ctrl_connect.2710769418 Jun 05 06:04:03 PM PDT 24 Jun 05 06:04:17 PM PDT 24 27618100 ps
T1086 /workspace/coverage/default/5.flash_ctrl_intr_wr.1305833133 Jun 05 06:01:56 PM PDT 24 Jun 05 06:03:02 PM PDT 24 2131596100 ps
T1087 /workspace/coverage/default/8.flash_ctrl_connect.3762902360 Jun 05 06:02:06 PM PDT 24 Jun 05 06:02:22 PM PDT 24 14695500 ps
T248 /workspace/coverage/default/1.flash_ctrl_integrity.3523594761 Jun 05 06:01:24 PM PDT 24 Jun 05 06:10:16 PM PDT 24 3572339800 ps
T1088 /workspace/coverage/default/21.flash_ctrl_smoke.170292245 Jun 05 06:03:47 PM PDT 24 Jun 05 06:05:01 PM PDT 24 48965600 ps
T1089 /workspace/coverage/default/22.flash_ctrl_disable.1259195255 Jun 05 06:03:56 PM PDT 24 Jun 05 06:04:18 PM PDT 24 65999800 ps
T1090 /workspace/coverage/default/21.flash_ctrl_rw_evict.1583976697 Jun 05 06:03:55 PM PDT 24 Jun 05 06:04:26 PM PDT 24 425790800 ps
T1091 /workspace/coverage/default/10.flash_ctrl_mp_regions.875405828 Jun 05 06:02:19 PM PDT 24 Jun 05 06:13:03 PM PDT 24 7808340800 ps
T1092 /workspace/coverage/default/33.flash_ctrl_otp_reset.1689553696 Jun 05 06:04:50 PM PDT 24 Jun 05 06:07:02 PM PDT 24 137917100 ps
T1093 /workspace/coverage/default/34.flash_ctrl_rw_evict.3426991535 Jun 05 06:04:54 PM PDT 24 Jun 05 06:05:26 PM PDT 24 34393100 ps
T1094 /workspace/coverage/default/29.flash_ctrl_connect.1227094025 Jun 05 06:04:32 PM PDT 24 Jun 05 06:04:48 PM PDT 24 27370300 ps
T1095 /workspace/coverage/default/43.flash_ctrl_alert_test.2025545747 Jun 05 06:05:15 PM PDT 24 Jun 05 06:05:30 PM PDT 24 133949600 ps
T1096 /workspace/coverage/default/34.flash_ctrl_alert_test.2385013846 Jun 05 06:04:53 PM PDT 24 Jun 05 06:05:07 PM PDT 24 40445900 ps
T1097 /workspace/coverage/default/44.flash_ctrl_disable.3805977532 Jun 05 06:05:15 PM PDT 24 Jun 05 06:05:38 PM PDT 24 16087500 ps
T1098 /workspace/coverage/default/14.flash_ctrl_rw_evict.3553593140 Jun 05 06:02:59 PM PDT 24 Jun 05 06:03:29 PM PDT 24 71037700 ps
T1099 /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.3419185688 Jun 05 06:02:03 PM PDT 24 Jun 05 06:16:26 PM PDT 24 80135052400 ps
T1100 /workspace/coverage/default/2.flash_ctrl_rand_ops.2895393986 Jun 05 06:01:25 PM PDT 24 Jun 05 06:19:10 PM PDT 24 3511940600 ps
T1101 /workspace/coverage/default/0.flash_ctrl_host_dir_rd.804408122 Jun 05 06:00:56 PM PDT 24 Jun 05 06:01:56 PM PDT 24 67534300 ps
T1102 /workspace/coverage/default/8.flash_ctrl_rand_ops.2562908400 Jun 05 06:02:02 PM PDT 24 Jun 05 06:04:35 PM PDT 24 152743800 ps
T257 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2080902760 Jun 05 06:00:54 PM PDT 24 Jun 05 06:01:08 PM PDT 24 102797900 ps
T70 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2335272808 Jun 05 06:00:37 PM PDT 24 Jun 05 06:15:56 PM PDT 24 1335985800 ps
T71 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2586262498 Jun 05 06:00:31 PM PDT 24 Jun 05 06:00:49 PM PDT 24 56207200 ps
T258 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2636999906 Jun 05 06:00:28 PM PDT 24 Jun 05 06:00:43 PM PDT 24 60860300 ps
T1103 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1256006509 Jun 05 06:00:23 PM PDT 24 Jun 05 06:00:37 PM PDT 24 51910600 ps
T72 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3748005146 Jun 05 06:00:42 PM PDT 24 Jun 05 06:01:19 PM PDT 24 1060914900 ps
T259 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.688725508 Jun 05 06:00:40 PM PDT 24 Jun 05 06:00:54 PM PDT 24 29253800 ps
T1104 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2326270937 Jun 05 06:00:46 PM PDT 24 Jun 05 06:01:02 PM PDT 24 24410700 ps
T249 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.917534577 Jun 05 06:00:34 PM PDT 24 Jun 05 06:01:04 PM PDT 24 235984000 ps
T313 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2846751033 Jun 05 06:01:09 PM PDT 24 Jun 05 06:01:24 PM PDT 24 15534700 ps
T185 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.510376738 Jun 05 06:00:35 PM PDT 24 Jun 05 06:01:02 PM PDT 24 41887900 ps
T1105 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1699810113 Jun 05 06:00:30 PM PDT 24 Jun 05 06:00:44 PM PDT 24 55758500 ps
T188 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1222951755 Jun 05 06:00:58 PM PDT 24 Jun 05 06:01:17 PM PDT 24 199811000 ps
T186 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2370294182 Jun 05 06:00:35 PM PDT 24 Jun 05 06:06:59 PM PDT 24 568598200 ps
T187 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.314977218 Jun 05 06:00:27 PM PDT 24 Jun 05 06:00:44 PM PDT 24 207804200 ps
T250 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.947161843 Jun 05 06:00:57 PM PDT 24 Jun 05 06:01:15 PM PDT 24 60082800 ps
T314 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.638702012 Jun 05 06:00:30 PM PDT 24 Jun 05 06:00:45 PM PDT 24 18913100 ps
T1106 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3084507632 Jun 05 06:00:34 PM PDT 24 Jun 05 06:00:50 PM PDT 24 13786800 ps
T219 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3514364271 Jun 05 06:00:26 PM PDT 24 Jun 05 06:15:27 PM PDT 24 6259444900 ps
T315 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.4249396086 Jun 05 06:00:58 PM PDT 24 Jun 05 06:01:12 PM PDT 24 18219200 ps
T1107 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3046506845 Jun 05 06:00:36 PM PDT 24 Jun 05 06:00:52 PM PDT 24 12584300 ps
T317 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1635808398 Jun 05 06:00:26 PM PDT 24 Jun 05 06:00:41 PM PDT 24 55210800 ps
T217 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.645772622 Jun 05 06:00:36 PM PDT 24 Jun 05 06:00:54 PM PDT 24 44601500 ps
T316 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2559694662 Jun 05 06:00:40 PM PDT 24 Jun 05 06:00:55 PM PDT 24 26327300 ps
T228 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.186622373 Jun 05 06:00:44 PM PDT 24 Jun 05 06:13:22 PM PDT 24 1822174000 ps
T1108 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.84593693 Jun 05 06:00:24 PM PDT 24 Jun 05 06:00:38 PM PDT 24 50284500 ps
T318 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3732135349 Jun 05 06:00:32 PM PDT 24 Jun 05 06:00:47 PM PDT 24 17368000 ps
T1109 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2957200160 Jun 05 06:00:57 PM PDT 24 Jun 05 06:01:11 PM PDT 24 23869100 ps
T1110 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2219909039 Jun 05 06:00:53 PM PDT 24 Jun 05 06:01:07 PM PDT 24 70540100 ps
T290 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.59549903 Jun 05 06:00:42 PM PDT 24 Jun 05 06:00:59 PM PDT 24 389182700 ps
T218 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1405555699 Jun 05 06:00:36 PM PDT 24 Jun 05 06:00:54 PM PDT 24 29330800 ps
T1111 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1466863773 Jun 05 06:00:55 PM PDT 24 Jun 05 06:01:09 PM PDT 24 40362200 ps
T291 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3827467400 Jun 05 06:00:33 PM PDT 24 Jun 05 06:01:11 PM PDT 24 953564900 ps
T229 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.101651018 Jun 05 06:00:35 PM PDT 24 Jun 05 06:08:16 PM PDT 24 356320700 ps
T1112 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2672471813 Jun 05 06:00:47 PM PDT 24 Jun 05 06:01:04 PM PDT 24 55474400 ps
T1113 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1824828977 Jun 05 06:00:42 PM PDT 24 Jun 05 06:00:57 PM PDT 24 53267000 ps
T1114 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1051682914 Jun 05 06:00:47 PM PDT 24 Jun 05 06:01:01 PM PDT 24 25331200 ps
T230 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2975796402 Jun 05 06:00:44 PM PDT 24 Jun 05 06:01:05 PM PDT 24 58941200 ps
T231 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1384706014 Jun 05 06:00:32 PM PDT 24 Jun 05 06:00:49 PM PDT 24 373666600 ps
T1115 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3954430504 Jun 05 06:00:30 PM PDT 24 Jun 05 06:01:03 PM PDT 24 26352900 ps
T297 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3498781946 Jun 05 06:01:05 PM PDT 24 Jun 05 06:01:22 PM PDT 24 99552000 ps
T1116 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1420805725 Jun 05 06:00:55 PM PDT 24 Jun 05 06:01:11 PM PDT 24 25619800 ps
T232 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2137727172 Jun 05 06:00:37 PM PDT 24 Jun 05 06:00:57 PM PDT 24 238011000 ps
T1117 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.4285920824 Jun 05 06:00:32 PM PDT 24 Jun 05 06:00:47 PM PDT 24 32513700 ps
T233 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.421280372 Jun 05 06:00:29 PM PDT 24 Jun 05 06:00:46 PM PDT 24 34402100 ps
T234 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3808883062 Jun 05 06:00:47 PM PDT 24 Jun 05 06:01:07 PM PDT 24 55605200 ps
T1118 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.344590241 Jun 05 06:00:39 PM PDT 24 Jun 05 06:01:10 PM PDT 24 434427400 ps
T254 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2208557653 Jun 05 06:00:48 PM PDT 24 Jun 05 06:01:09 PM PDT 24 61008700 ps
T1119 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3257876488 Jun 05 06:00:36 PM PDT 24 Jun 05 06:00:55 PM PDT 24 123263600 ps
T1120 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1061525606 Jun 05 06:00:42 PM PDT 24 Jun 05 06:00:57 PM PDT 24 88163900 ps
T1121 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1129299934 Jun 05 06:00:59 PM PDT 24 Jun 05 06:01:13 PM PDT 24 141028100 ps
T263 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1600144594 Jun 05 06:00:53 PM PDT 24 Jun 05 06:01:12 PM PDT 24 55906400 ps
T1122 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1890304043 Jun 05 06:00:33 PM PDT 24 Jun 05 06:00:50 PM PDT 24 48917600 ps
T1123 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.739502522 Jun 05 06:00:34 PM PDT 24 Jun 05 06:00:54 PM PDT 24 276458800 ps
T343 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1901857029 Jun 05 06:00:26 PM PDT 24 Jun 05 06:06:48 PM PDT 24 361533300 ps
T296 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.666070074 Jun 05 06:00:33 PM PDT 24 Jun 05 06:00:49 PM PDT 24 46241300 ps
T1124 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3019398149 Jun 05 06:00:54 PM PDT 24 Jun 05 06:01:13 PM PDT 24 53318800 ps
T1125 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1456571387 Jun 05 06:01:13 PM PDT 24 Jun 05 06:01:27 PM PDT 24 15528000 ps
T1126 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1331523129 Jun 05 06:00:39 PM PDT 24 Jun 05 06:00:54 PM PDT 24 161530800 ps
T1127 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.89739670 Jun 05 06:00:48 PM PDT 24 Jun 05 06:01:02 PM PDT 24 18422000 ps
T345 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2492999592 Jun 05 06:00:28 PM PDT 24 Jun 05 06:15:39 PM PDT 24 339188700 ps
T1128 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3927284296 Jun 05 06:00:25 PM PDT 24 Jun 05 06:01:00 PM PDT 24 1010969000 ps
T1129 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4101364558 Jun 05 06:00:33 PM PDT 24 Jun 05 06:01:31 PM PDT 24 662414600 ps
T1130 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1220033621 Jun 05 06:00:45 PM PDT 24 Jun 05 06:01:16 PM PDT 24 237807500 ps
T255 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3028796271 Jun 05 06:00:24 PM PDT 24 Jun 05 06:00:40 PM PDT 24 47136300 ps
T1131 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1821413362 Jun 05 06:01:06 PM PDT 24 Jun 05 06:01:21 PM PDT 24 49205500 ps
T1132 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1656463372 Jun 05 06:00:25 PM PDT 24 Jun 05 06:00:42 PM PDT 24 37044300 ps
T1133 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3116638175 Jun 05 06:00:40 PM PDT 24 Jun 05 06:00:57 PM PDT 24 34029400 ps
T1134 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3487475816 Jun 05 06:00:33 PM PDT 24 Jun 05 06:00:47 PM PDT 24 58417900 ps
T1135 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.107473707 Jun 05 06:00:55 PM PDT 24 Jun 05 06:01:09 PM PDT 24 28650800 ps
T260 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2177796717 Jun 05 06:00:34 PM PDT 24 Jun 05 06:00:51 PM PDT 24 32137900 ps
T312 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.868519975 Jun 05 06:00:44 PM PDT 24 Jun 05 06:01:02 PM PDT 24 84882000 ps
T1136 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3103308044 Jun 05 06:00:35 PM PDT 24 Jun 05 06:00:49 PM PDT 24 40926700 ps
T1137 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4126151821 Jun 05 06:00:23 PM PDT 24 Jun 05 06:00:37 PM PDT 24 29060700 ps
T1138 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.610527021 Jun 05 06:00:31 PM PDT 24 Jun 05 06:01:48 PM PDT 24 9511080800 ps
T1139 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.507460503 Jun 05 06:01:11 PM PDT 24 Jun 05 06:01:25 PM PDT 24 217591400 ps
T1140 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1790191628 Jun 05 06:00:32 PM PDT 24 Jun 05 06:00:49 PM PDT 24 39217600 ps
T344 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4184580852 Jun 05 06:01:01 PM PDT 24 Jun 05 06:07:33 PM PDT 24 701568400 ps
T1141 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3933402990 Jun 05 06:00:22 PM PDT 24 Jun 05 06:00:36 PM PDT 24 20934600 ps
T1142 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1207511715 Jun 05 06:00:41 PM PDT 24 Jun 05 06:00:58 PM PDT 24 35677700 ps
T1143 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2757423667 Jun 05 06:00:42 PM PDT 24 Jun 05 06:00:56 PM PDT 24 20678100 ps
T348 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.352468102 Jun 05 06:00:56 PM PDT 24 Jun 05 06:15:59 PM PDT 24 1429729200 ps
T1144 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1091696954 Jun 05 06:00:32 PM PDT 24 Jun 05 06:00:51 PM PDT 24 55128600 ps
T256 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1829449031 Jun 05 06:00:54 PM PDT 24 Jun 05 06:01:11 PM PDT 24 35280500 ps
T236 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2199173452 Jun 05 06:00:38 PM PDT 24 Jun 05 06:00:52 PM PDT 24 54472700 ps
T1145 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1025205763 Jun 05 06:00:26 PM PDT 24 Jun 05 06:01:08 PM PDT 24 3957925200 ps
T1146 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1173396262 Jun 05 06:00:59 PM PDT 24 Jun 05 06:01:13 PM PDT 24 66934300 ps
T1147 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2476183083 Jun 05 06:01:08 PM PDT 24 Jun 05 06:01:22 PM PDT 24 18291300 ps
T1148 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3698869864 Jun 05 06:00:54 PM PDT 24 Jun 05 06:01:08 PM PDT 24 23576000 ps
T262 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3667086441 Jun 05 06:00:31 PM PDT 24 Jun 05 06:00:52 PM PDT 24 329945400 ps
T1149 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2530154609 Jun 05 06:01:02 PM PDT 24 Jun 05 06:01:17 PM PDT 24 24711500 ps
T292 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1240208651 Jun 05 06:00:25 PM PDT 24 Jun 05 06:00:45 PM PDT 24 113525000 ps
T1150 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.894740112 Jun 05 06:01:01 PM PDT 24 Jun 05 06:01:18 PM PDT 24 47558000 ps
T1151 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3803526677 Jun 05 06:01:05 PM PDT 24 Jun 05 06:01:19 PM PDT 24 30222200 ps
T1152 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2006101522 Jun 05 06:01:11 PM PDT 24 Jun 05 06:01:26 PM PDT 24 79119900 ps
T1153 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1870635464 Jun 05 06:00:45 PM PDT 24 Jun 05 06:00:59 PM PDT 24 24518900 ps
T1154 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3742209477 Jun 05 06:00:38 PM PDT 24 Jun 05 06:01:24 PM PDT 24 27113600 ps
T1155 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1055051399 Jun 05 06:00:30 PM PDT 24 Jun 05 06:00:47 PM PDT 24 33082600 ps
T261 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2940332456 Jun 05 06:00:44 PM PDT 24 Jun 05 06:01:02 PM PDT 24 160089500 ps
T264 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1889266250 Jun 05 06:00:53 PM PDT 24 Jun 05 06:01:14 PM PDT 24 61352300 ps
T293 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1298088389 Jun 05 06:00:55 PM PDT 24 Jun 05 06:01:13 PM PDT 24 120348300 ps
T1156 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3683619818 Jun 05 06:00:40 PM PDT 24 Jun 05 06:01:01 PM PDT 24 165265900 ps
T1157 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.702044589 Jun 05 06:00:34 PM PDT 24 Jun 05 06:00:51 PM PDT 24 13048400 ps
T1158 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.509453159 Jun 05 06:00:26 PM PDT 24 Jun 05 06:00:40 PM PDT 24 142760600 ps
T294 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3609198134 Jun 05 06:00:31 PM PDT 24 Jun 05 06:15:42 PM PDT 24 5749169400 ps
T1159 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.205447 Jun 05 06:01:11 PM PDT 24 Jun 05 06:01:25 PM PDT 24 22774900 ps
T295 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3663569542 Jun 05 06:00:45 PM PDT 24 Jun 05 06:08:27 PM PDT 24 1805024900 ps
T349 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2297205026 Jun 05 06:00:53 PM PDT 24 Jun 05 06:08:39 PM PDT 24 3299392800 ps
T1160 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3233112473 Jun 05 06:00:23 PM PDT 24 Jun 05 06:00:39 PM PDT 24 15831000 ps
T298 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3276411612 Jun 05 06:00:31 PM PDT 24 Jun 05 06:00:51 PM PDT 24 68901100 ps
T299 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4126178948 Jun 05 06:00:44 PM PDT 24 Jun 05 06:13:41 PM PDT 24 1227121000 ps
T1161 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1598690580 Jun 05 06:00:53 PM PDT 24 Jun 05 06:01:28 PM PDT 24 167586600 ps
T300 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1448383744 Jun 05 06:00:18 PM PDT 24 Jun 05 06:00:49 PM PDT 24 54144800 ps
T1162 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.4220931119 Jun 05 06:00:51 PM PDT 24 Jun 05 06:01:05 PM PDT 24 18067900 ps
T1163 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2132558612 Jun 05 06:00:53 PM PDT 24 Jun 05 06:01:06 PM PDT 24 19762500 ps
T1164 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2886453859 Jun 05 06:00:29 PM PDT 24 Jun 05 06:00:47 PM PDT 24 27583900 ps
T1165 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2937019532 Jun 05 06:00:49 PM PDT 24 Jun 05 06:01:02 PM PDT 24 70625300 ps
T237 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.904649657 Jun 05 06:00:26 PM PDT 24 Jun 05 06:00:41 PM PDT 24 16365200 ps
T301 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.605522961 Jun 05 06:00:36 PM PDT 24 Jun 05 06:00:56 PM PDT 24 1105119700 ps
T1166 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.374922816 Jun 05 06:00:29 PM PDT 24 Jun 05 06:00:48 PM PDT 24 48408900 ps
T1167 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4148400791 Jun 05 06:00:35 PM PDT 24 Jun 05 06:00:55 PM PDT 24 119027300 ps
T1168 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.711555542 Jun 05 06:00:35 PM PDT 24 Jun 05 06:01:11 PM PDT 24 157234000 ps
T1169 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.685847177 Jun 05 06:00:45 PM PDT 24 Jun 05 06:01:03 PM PDT 24 45702900 ps
T1170 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3188304696 Jun 05 06:00:57 PM PDT 24 Jun 05 06:01:11 PM PDT 24 11572600 ps
T1171 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.81653417 Jun 05 06:01:02 PM PDT 24 Jun 05 06:01:22 PM PDT 24 1148911200 ps
T302 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.141202434 Jun 05 06:00:27 PM PDT 24 Jun 05 06:01:03 PM PDT 24 853784400 ps
T1172 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2192657484 Jun 05 06:00:29 PM PDT 24 Jun 05 06:00:43 PM PDT 24 124703800 ps
T1173 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1068713623 Jun 05 06:00:32 PM PDT 24 Jun 05 06:00:52 PM PDT 24 70999900 ps
T1174 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1602804687 Jun 05 06:00:24 PM PDT 24 Jun 05 06:00:38 PM PDT 24 15886100 ps
T1175 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.697517060 Jun 05 06:00:30 PM PDT 24 Jun 05 06:00:48 PM PDT 24 123454000 ps
T1176 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3364338777 Jun 05 06:00:33 PM PDT 24 Jun 05 06:00:50 PM PDT 24 84663300 ps
T1177 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3980578183 Jun 05 06:00:26 PM PDT 24 Jun 05 06:00:44 PM PDT 24 19502500 ps
T1178 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2955963792 Jun 05 06:00:38 PM PDT 24 Jun 05 06:00:52 PM PDT 24 22329000 ps
T351 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1501275542 Jun 05 06:00:36 PM PDT 24 Jun 05 06:08:08 PM PDT 24 1488376500 ps
T1179 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.4000070796 Jun 05 06:00:53 PM PDT 24 Jun 05 06:01:10 PM PDT 24 15021500 ps
T238 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.488507898 Jun 05 06:00:39 PM PDT 24 Jun 05 06:00:53 PM PDT 24 16384400 ps
T1180 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3874513677 Jun 05 06:00:46 PM PDT 24 Jun 05 06:00:59 PM PDT 24 31690500 ps
T303 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3978402664 Jun 05 06:00:31 PM PDT 24 Jun 05 06:00:48 PM PDT 24 112510600 ps
T347 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3605257439 Jun 05 06:00:39 PM PDT 24 Jun 05 06:07:06 PM PDT 24 333901800 ps
T1181 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.115114640 Jun 05 06:01:03 PM PDT 24 Jun 05 06:01:24 PM PDT 24 82604800 ps
T1182 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3042206102 Jun 05 06:00:33 PM PDT 24 Jun 05 06:08:13 PM PDT 24 347842500 ps
T1183 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2738077163 Jun 05 06:00:25 PM PDT 24 Jun 05 06:00:39 PM PDT 24 32071500 ps
T1184 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.99694916 Jun 05 06:00:24 PM PDT 24 Jun 05 06:00:41 PM PDT 24 99634300 ps
T1185 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4028871931 Jun 05 06:00:54 PM PDT 24 Jun 05 06:01:31 PM PDT 24 825351400 ps
T304 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1227602167 Jun 05 06:00:31 PM PDT 24 Jun 05 06:00:53 PM PDT 24 225647400 ps
T305 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.658516591 Jun 05 06:00:33 PM PDT 24 Jun 05 06:00:51 PM PDT 24 216330700 ps
T1186 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.297670839 Jun 05 06:00:54 PM PDT 24 Jun 05 06:01:11 PM PDT 24 40635000 ps
T1187 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.681037569 Jun 05 06:00:55 PM PDT 24 Jun 05 06:01:26 PM PDT 24 160706300 ps
T1188 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3112571819 Jun 05 06:00:47 PM PDT 24 Jun 05 06:08:29 PM PDT 24 429556000 ps
T1189 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2521419893 Jun 05 06:00:34 PM PDT 24 Jun 05 06:00:52 PM PDT 24 134320300 ps
T1190 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2148642500 Jun 05 06:00:33 PM PDT 24 Jun 05 06:00:51 PM PDT 24 85814200 ps
T1191 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.708790708 Jun 05 06:00:24 PM PDT 24 Jun 05 06:00:42 PM PDT 24 38132800 ps
T346 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3753240237 Jun 05 06:00:49 PM PDT 24 Jun 05 06:15:55 PM PDT 24 2738847300 ps
T1192 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.363052315 Jun 05 06:00:26 PM PDT 24 Jun 05 06:00:44 PM PDT 24 49804300 ps
T1193 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.177802022 Jun 05 06:01:04 PM PDT 24 Jun 05 06:01:19 PM PDT 24 89796500 ps
T1194 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.5761918 Jun 05 06:00:25 PM PDT 24 Jun 05 06:01:05 PM PDT 24 330829700 ps
T265 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1396243347 Jun 05 06:00:54 PM PDT 24 Jun 05 06:01:12 PM PDT 24 177166800 ps
T1195 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2531100244 Jun 05 06:00:57 PM PDT 24 Jun 05 06:01:14 PM PDT 24 31799300 ps
T1196 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.746228159 Jun 05 06:00:49 PM PDT 24 Jun 05 06:01:03 PM PDT 24 26163300 ps
T239 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3804644952 Jun 05 06:00:31 PM PDT 24 Jun 05 06:00:46 PM PDT 24 112705300 ps
T1197 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.596416501 Jun 05 06:01:09 PM PDT 24 Jun 05 06:01:23 PM PDT 24 17307600 ps
T1198 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2915738902 Jun 05 06:00:47 PM PDT 24 Jun 05 06:01:07 PM PDT 24 231538500 ps
T1199 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3629742663 Jun 05 06:00:38 PM PDT 24 Jun 05 06:00:57 PM PDT 24 193626600 ps
T1200 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3166467821 Jun 05 06:00:58 PM PDT 24 Jun 05 06:01:17 PM PDT 24 421618900 ps
T1201 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2783150607 Jun 05 06:00:38 PM PDT 24 Jun 05 06:00:54 PM PDT 24 21454000 ps
T1202 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1245912739 Jun 05 06:00:28 PM PDT 24 Jun 05 06:00:42 PM PDT 24 21444800 ps
T1203 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.437623920 Jun 05 06:00:44 PM PDT 24 Jun 05 06:01:03 PM PDT 24 59981500 ps
T1204 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.86489915 Jun 05 06:00:46 PM PDT 24 Jun 05 06:01:00 PM PDT 24 28407600 ps
T1205 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3076432056 Jun 05 06:00:21 PM PDT 24 Jun 05 06:00:40 PM PDT 24 50937300 ps
T1206 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3478702261 Jun 05 06:00:42 PM PDT 24 Jun 05 06:00:57 PM PDT 24 48994600 ps
T1207 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3362170941 Jun 05 06:00:42 PM PDT 24 Jun 05 06:00:56 PM PDT 24 15188600 ps
T1208 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1073796663 Jun 05 06:01:06 PM PDT 24 Jun 05 06:01:20 PM PDT 24 16361300 ps
T1209 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1346210165 Jun 05 06:00:32 PM PDT 24 Jun 05 06:00:50 PM PDT 24 65343900 ps
T1210 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1567650531 Jun 05 06:00:53 PM PDT 24 Jun 05 06:01:11 PM PDT 24 94906800 ps
T1211 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1917777881 Jun 05 06:00:57 PM PDT 24 Jun 05 06:01:11 PM PDT 24 30124600 ps
T1212 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2966650225 Jun 05 06:00:46 PM PDT 24 Jun 05 06:01:01 PM PDT 24 34069100 ps
T1213 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2210148032 Jun 05 06:00:43 PM PDT 24 Jun 05 06:01:03 PM PDT 24 2185886500 ps
T1214 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1784082370 Jun 05 06:00:37 PM PDT 24 Jun 05 06:00:53 PM PDT 24 34054000 ps
T1215 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3342170052 Jun 05 06:00:44 PM PDT 24 Jun 05 06:01:02 PM PDT 24 1305162100 ps
T1216 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1471960597 Jun 05 06:00:26 PM PDT 24 Jun 05 06:00:43 PM PDT 24 136824500 ps
T1217 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2201765644 Jun 05 06:00:53 PM PDT 24 Jun 05 06:01:10 PM PDT 24 11328500 ps
T1218 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3123435780 Jun 05 06:00:32 PM PDT 24 Jun 05 06:00:49 PM PDT 24 18046700 ps
T1219 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.230114384 Jun 05 06:00:50 PM PDT 24 Jun 05 06:01:08 PM PDT 24 114816400 ps
T1220 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3431439714 Jun 05 06:00:44 PM PDT 24 Jun 05 06:00:59 PM PDT 24 18835900 ps
T1221 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3721865866 Jun 05 06:00:59 PM PDT 24 Jun 05 06:01:16 PM PDT 24 12536800 ps
T1222 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2026517028 Jun 05 06:00:49 PM PDT 24 Jun 05 06:01:02 PM PDT 24 15502400 ps
T1223 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3713135622 Jun 05 06:00:47 PM PDT 24 Jun 05 06:01:52 PM PDT 24 660266700 ps
T1224 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3608228858 Jun 05 06:00:33 PM PDT 24 Jun 05 06:01:05 PM PDT 24 37099800 ps
T1225 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2591978710 Jun 05 06:00:53 PM PDT 24 Jun 05 06:01:10 PM PDT 24 30786000 ps
T1226 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.49372744 Jun 05 06:00:52 PM PDT 24 Jun 05 06:01:09 PM PDT 24 113168800 ps
T1227 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2083419675 Jun 05 06:00:30 PM PDT 24 Jun 05 06:00:50 PM PDT 24 324920500 ps
T1228 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2436712567 Jun 05 06:01:05 PM PDT 24 Jun 05 06:01:19 PM PDT 24 56835200 ps
T1229 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3072899637 Jun 05 06:00:43 PM PDT 24 Jun 05 06:00:59 PM PDT 24 21576900 ps
T1230 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1962572498 Jun 05 06:00:28 PM PDT 24 Jun 05 06:00:43 PM PDT 24 15046200 ps
T1231 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.301568108 Jun 05 06:01:13 PM PDT 24 Jun 05 06:01:27 PM PDT 24 200045400 ps
T1232 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1773707086 Jun 05 06:00:28 PM PDT 24 Jun 05 06:00:45 PM PDT 24 12518000 ps
T1233 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2308130114 Jun 05 06:00:31 PM PDT 24 Jun 05 06:00:48 PM PDT 24 57993600 ps
T1234 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.4286874524 Jun 05 06:00:34 PM PDT 24 Jun 05 06:00:50 PM PDT 24 44848300 ps
T1235 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1804702389 Jun 05 06:00:42 PM PDT 24 Jun 05 06:01:57 PM PDT 24 5489805100 ps
T1236 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1465527890 Jun 05 06:00:40 PM PDT 24 Jun 05 06:00:54 PM PDT 24 44692000 ps
T1237 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2643776125 Jun 05 06:00:30 PM PDT 24 Jun 05 06:01:34 PM PDT 24 1907155400 ps
T1238 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4189732691 Jun 05 06:00:23 PM PDT 24 Jun 05 06:00:40 PM PDT 24 65547400 ps
T1239 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3004014537 Jun 05 06:01:06 PM PDT 24 Jun 05 06:01:20 PM PDT 24 15780300 ps
T1240 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3799904481 Jun 05 06:01:08 PM PDT 24 Jun 05 06:01:23 PM PDT 24 17562000 ps
T1241 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3963478 Jun 05 06:00:43 PM PDT 24 Jun 05 06:01:01 PM PDT 24 130486400 ps
T350 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4237411422 Jun 05 06:01:04 PM PDT 24 Jun 05 06:08:33 PM PDT 24 530344800 ps
T266 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1824786604 Jun 05 06:00:47 PM PDT 24 Jun 05 06:08:39 PM PDT 24 1017149600 ps
T1242 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3131503731 Jun 05 06:01:00 PM PDT 24 Jun 05 06:01:18 PM PDT 24 185733700 ps
T1243 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3590866789 Jun 05 06:00:32 PM PDT 24 Jun 05 06:00:46 PM PDT 24 28095300 ps
T240 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2899685865 Jun 05 06:00:22 PM PDT 24 Jun 05 06:00:36 PM PDT 24 19141800 ps
T1244 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.442422459 Jun 05 06:00:41 PM PDT 24 Jun 05 06:00:55 PM PDT 24 43172200 ps
T1245 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.4126135025 Jun 05 06:00:24 PM PDT 24 Jun 05 06:00:41 PM PDT 24 35339800 ps
T1246 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2518024551 Jun 05 06:00:42 PM PDT 24 Jun 05 06:00:56 PM PDT 24 27173900 ps
T1247 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2585887963 Jun 05 06:00:32 PM PDT 24 Jun 05 06:00:48 PM PDT 24 151074700 ps
T1248 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2273288585 Jun 05 06:00:44 PM PDT 24 Jun 05 06:00:58 PM PDT 24 14526500 ps

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.353017923
Short name T21
Test name
Test status
Simulation time 542064800 ps
CPU time 42.32 seconds
Started Jun 05 06:01:00 PM PDT 24
Finished Jun 05 06:01:42 PM PDT 24
Peak memory 261904 kb
Host smart-cec1faf7-4830-45eb-8ccb-4cd2640dd86c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353017923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_fs_sup.353017923
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.3013175413
Short name T11
Test name
Test status
Simulation time 96675400 ps
CPU time 132.07 seconds
Started Jun 05 06:01:04 PM PDT 24
Finished Jun 05 06:03:17 PM PDT 24
Peak memory 264160 kb
Host smart-13432ce7-27ae-484d-a9e7-dae84db01699
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013175413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.3013175413
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.993912070
Short name T112
Test name
Test status
Simulation time 12528113100 ps
CPU time 155.51 seconds
Started Jun 05 06:01:48 PM PDT 24
Finished Jun 05 06:04:24 PM PDT 24
Peak memory 261520 kb
Host smart-95ba5fcd-6780-4058-bbfa-55aee9931669
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993912070 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_mp_regions.993912070
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3514364271
Short name T219
Test name
Test status
Simulation time 6259444900 ps
CPU time 899.86 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:15:27 PM PDT 24
Peak memory 264220 kb
Host smart-6a8c9019-df0f-4284-997a-073abab99300
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514364271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.3514364271
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.1183160058
Short name T12
Test name
Test status
Simulation time 5683858700 ps
CPU time 4786.84 seconds
Started Jun 05 06:01:03 PM PDT 24
Finished Jun 05 07:20:51 PM PDT 24
Peak memory 286060 kb
Host smart-364783d1-bbf3-453e-a59a-85ac24876d25
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183160058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.1183160058
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.3493638636
Short name T5
Test name
Test status
Simulation time 42639077300 ps
CPU time 612.96 seconds
Started Jun 05 06:01:09 PM PDT 24
Finished Jun 05 06:11:23 PM PDT 24
Peak memory 312296 kb
Host smart-c3926844-15ed-4b43-8e0a-0ebeffa6087d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493638636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_rw.3493638636
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.2986636005
Short name T120
Test name
Test status
Simulation time 40124266700 ps
CPU time 787.76 seconds
Started Jun 05 06:03:21 PM PDT 24
Finished Jun 05 06:16:30 PM PDT 24
Peak memory 264796 kb
Host smart-9956c255-dfca-47ca-a63d-a949135296da
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986636005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.2986636005
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.1694194052
Short name T64
Test name
Test status
Simulation time 3487031100 ps
CPU time 533.02 seconds
Started Jun 05 06:01:18 PM PDT 24
Finished Jun 05 06:10:11 PM PDT 24
Peak memory 262916 kb
Host smart-124acabc-7728-456c-b997-87ae43adf69d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1694194052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.1694194052
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.3764106820
Short name T90
Test name
Test status
Simulation time 6800642500 ps
CPU time 58.8 seconds
Started Jun 05 06:02:05 PM PDT 24
Finished Jun 05 06:03:04 PM PDT 24
Peak memory 259768 kb
Host smart-ca7f94c3-b29c-4882-a013-2edc828e87fd
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764106820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.3764106820
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.186622373
Short name T228
Test name
Test status
Simulation time 1822174000 ps
CPU time 757.43 seconds
Started Jun 05 06:00:44 PM PDT 24
Finished Jun 05 06:13:22 PM PDT 24
Peak memory 264256 kb
Host smart-37f8206a-f81a-456a-841c-82cb6bae1acc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186622373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_tl_intg_err.186622373
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.3271197546
Short name T126
Test name
Test status
Simulation time 1835209000 ps
CPU time 68.89 seconds
Started Jun 05 06:01:23 PM PDT 24
Finished Jun 05 06:02:33 PM PDT 24
Peak memory 259772 kb
Host smart-5cbbb845-ea60-404c-90dd-48a3095ae739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271197546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.3271197546
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.2877671149
Short name T9
Test name
Test status
Simulation time 56047200 ps
CPU time 13.97 seconds
Started Jun 05 06:00:55 PM PDT 24
Finished Jun 05 06:01:10 PM PDT 24
Peak memory 264984 kb
Host smart-a0f7c88e-fa4e-4b1f-a928-3b830b48409f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877671149 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.2877671149
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.753893298
Short name T35
Test name
Test status
Simulation time 11914951400 ps
CPU time 263.33 seconds
Started Jun 05 06:02:00 PM PDT 24
Finished Jun 05 06:06:24 PM PDT 24
Peak memory 290756 kb
Host smart-7bce703e-5031-4186-953c-9768658cdda8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753893298 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.753893298
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.4243480695
Short name T153
Test name
Test status
Simulation time 35504600 ps
CPU time 110.38 seconds
Started Jun 05 06:05:36 PM PDT 24
Finished Jun 05 06:07:27 PM PDT 24
Peak memory 260000 kb
Host smart-38bf7178-db9c-4e9a-85ca-f88868167b4e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243480695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.4243480695
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2975796402
Short name T230
Test name
Test status
Simulation time 58941200 ps
CPU time 19.82 seconds
Started Jun 05 06:00:44 PM PDT 24
Finished Jun 05 06:01:05 PM PDT 24
Peak memory 264272 kb
Host smart-43ae9205-c9c9-4057-8fce-76f6c3eed85b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975796402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
2975796402
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.1534593213
Short name T133
Test name
Test status
Simulation time 10014744400 ps
CPU time 216.3 seconds
Started Jun 05 06:01:26 PM PDT 24
Finished Jun 05 06:05:03 PM PDT 24
Peak memory 306548 kb
Host smart-6eac7d77-ca4f-4da6-8c93-d59d3d83892c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534593213 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.1534593213
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.4249396086
Short name T315
Test name
Test status
Simulation time 18219200 ps
CPU time 13.65 seconds
Started Jun 05 06:00:58 PM PDT 24
Finished Jun 05 06:01:12 PM PDT 24
Peak memory 262764 kb
Host smart-459c87e4-6697-4b0b-8ae0-cac6eea13d83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249396086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
4249396086
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.858547251
Short name T78
Test name
Test status
Simulation time 35394400 ps
CPU time 131.03 seconds
Started Jun 05 06:04:58 PM PDT 24
Finished Jun 05 06:07:09 PM PDT 24
Peak memory 259880 kb
Host smart-f2eb7295-4421-4399-a53b-32eee45c862f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858547251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ot
p_reset.858547251
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.1763623278
Short name T89
Test name
Test status
Simulation time 14522994600 ps
CPU time 161.11 seconds
Started Jun 05 06:02:54 PM PDT 24
Finished Jun 05 06:05:36 PM PDT 24
Peak memory 262308 kb
Host smart-61f90c60-2cc4-4c21-941b-37d33101a830
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763623278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.1763623278
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.1039744422
Short name T100
Test name
Test status
Simulation time 17039730300 ps
CPU time 509.41 seconds
Started Jun 05 06:03:25 PM PDT 24
Finished Jun 05 06:11:55 PM PDT 24
Peak memory 274444 kb
Host smart-c31dc2cd-8939-4a08-a68f-33bed2f14af3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039744422 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.1039744422
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.2276109366
Short name T57
Test name
Test status
Simulation time 2213102700 ps
CPU time 149.88 seconds
Started Jun 05 06:01:46 PM PDT 24
Finished Jun 05 06:04:16 PM PDT 24
Peak memory 281852 kb
Host smart-286203f1-d27f-4e1f-bc00-af87fc6ea7db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2276109366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.2276109366
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.636025040
Short name T7
Test name
Test status
Simulation time 86490200 ps
CPU time 15.08 seconds
Started Jun 05 06:01:28 PM PDT 24
Finished Jun 05 06:01:43 PM PDT 24
Peak memory 264752 kb
Host smart-4523b301-bea7-4c43-9394-716862241d1e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636025040 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.636025040
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3166211650
Short name T154
Test name
Test status
Simulation time 351848949000 ps
CPU time 2155.84 seconds
Started Jun 05 06:01:20 PM PDT 24
Finished Jun 05 06:37:16 PM PDT 24
Peak memory 264984 kb
Host smart-7924b9f2-f0e0-4ad2-ae15-c7963a418540
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166211650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.3166211650
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.1694421753
Short name T18
Test name
Test status
Simulation time 59942800 ps
CPU time 13.32 seconds
Started Jun 05 06:01:48 PM PDT 24
Finished Jun 05 06:02:01 PM PDT 24
Peak memory 264780 kb
Host smart-a0a7719b-1bb5-4bfc-bc5d-763c9aa60d6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694421753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.1
694421753
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.3659711900
Short name T150
Test name
Test status
Simulation time 65329100 ps
CPU time 131.83 seconds
Started Jun 05 06:05:45 PM PDT 24
Finished Jun 05 06:07:57 PM PDT 24
Peak memory 259616 kb
Host smart-0e018ac4-9cb8-4d65-a49d-4b282a1f9693
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659711900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.3659711900
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.154622753
Short name T4
Test name
Test status
Simulation time 8190793300 ps
CPU time 77.48 seconds
Started Jun 05 06:03:15 PM PDT 24
Finished Jun 05 06:04:33 PM PDT 24
Peak memory 263048 kb
Host smart-554a5d94-0ffc-4a78-9be1-7fc5725461db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154622753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.154622753
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.3312390242
Short name T96
Test name
Test status
Simulation time 40201111500 ps
CPU time 902.6 seconds
Started Jun 05 06:01:24 PM PDT 24
Finished Jun 05 06:16:27 PM PDT 24
Peak memory 259008 kb
Host smart-3ec48ebf-11cd-4c33-87bf-b57eeae36954
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312390242 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.3312390242
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.574442295
Short name T58
Test name
Test status
Simulation time 1392589600 ps
CPU time 25.6 seconds
Started Jun 05 06:01:58 PM PDT 24
Finished Jun 05 06:02:24 PM PDT 24
Peak memory 264908 kb
Host smart-afaac709-15a6-417b-b89a-50f654677778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574442295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.574442295
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.2554343451
Short name T130
Test name
Test status
Simulation time 1017956300 ps
CPU time 70.89 seconds
Started Jun 05 06:00:48 PM PDT 24
Finished Jun 05 06:01:59 PM PDT 24
Peak memory 259668 kb
Host smart-c9d1f212-427a-4179-81f9-4d4df8441053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554343451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2554343451
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.4278183296
Short name T157
Test name
Test status
Simulation time 42629100 ps
CPU time 132.62 seconds
Started Jun 05 06:05:50 PM PDT 24
Finished Jun 05 06:08:03 PM PDT 24
Peak memory 259512 kb
Host smart-dfb96f2d-1857-4e61-8e48-cc4f0db07b6a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278183296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.4278183296
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.3881650142
Short name T197
Test name
Test status
Simulation time 5218540000 ps
CPU time 569.07 seconds
Started Jun 05 06:01:13 PM PDT 24
Finished Jun 05 06:10:43 PM PDT 24
Peak memory 328584 kb
Host smart-e564591c-6565-4872-a6ec-4e96922350d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881650142 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.3881650142
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.1797770459
Short name T332
Test name
Test status
Simulation time 10170179700 ps
CPU time 281.5 seconds
Started Jun 05 06:02:50 PM PDT 24
Finished Jun 05 06:07:32 PM PDT 24
Peak memory 283556 kb
Host smart-25878744-5103-4c50-a847-e8ac83376a1d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797770459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.1797770459
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.2121664956
Short name T479
Test name
Test status
Simulation time 44096100 ps
CPU time 13.64 seconds
Started Jun 05 06:02:34 PM PDT 24
Finished Jun 05 06:02:48 PM PDT 24
Peak memory 259112 kb
Host smart-714b5716-c386-47c0-afee-aed22561ae4a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121664956 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.2121664956
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.904649657
Short name T237
Test name
Test status
Simulation time 16365200 ps
CPU time 13.53 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:00:41 PM PDT 24
Peak memory 263648 kb
Host smart-671644e5-107e-408a-9b0e-fabd74c5b44b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904649657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_mem_partial_access.904649657
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.1312268594
Short name T65
Test name
Test status
Simulation time 2204540000 ps
CPU time 2800.42 seconds
Started Jun 05 06:00:54 PM PDT 24
Finished Jun 05 06:47:35 PM PDT 24
Peak memory 264836 kb
Host smart-dcfe2c7f-c209-41ed-9cca-f485d9e619f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312268594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.1312268594
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.1589906472
Short name T993
Test name
Test status
Simulation time 10019189100 ps
CPU time 92.68 seconds
Started Jun 05 06:02:33 PM PDT 24
Finished Jun 05 06:04:07 PM PDT 24
Peak memory 332740 kb
Host smart-e5be52d7-852f-4466-add0-97782142e452
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589906472 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.1589906472
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3667086441
Short name T262
Test name
Test status
Simulation time 329945400 ps
CPU time 19.58 seconds
Started Jun 05 06:00:31 PM PDT 24
Finished Jun 05 06:00:52 PM PDT 24
Peak memory 264276 kb
Host smart-a1a50a9f-1eca-4a3a-92d9-2eaf6a2b780e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667086441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
3667086441
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.101651018
Short name T229
Test name
Test status
Simulation time 356320700 ps
CPU time 460.48 seconds
Started Jun 05 06:00:35 PM PDT 24
Finished Jun 05 06:08:16 PM PDT 24
Peak memory 261952 kb
Host smart-4a67468e-0e2b-426c-b749-56bbdb8bcb07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101651018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_
tl_intg_err.101651018
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict.2182089077
Short name T27
Test name
Test status
Simulation time 77997000 ps
CPU time 30.7 seconds
Started Jun 05 06:03:07 PM PDT 24
Finished Jun 05 06:03:38 PM PDT 24
Peak memory 266952 kb
Host smart-6dd32121-c1cb-457a-b238-1aa1d6572c31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182089077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_rw_evict.2182089077
Directory /workspace/15.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3732135349
Short name T318
Test name
Test status
Simulation time 17368000 ps
CPU time 13.42 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:47 PM PDT 24
Peak memory 262728 kb
Host smart-f3f64a7c-43cf-4aca-9ec7-3b6580b12b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732135349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
3732135349
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.4129187106
Short name T704
Test name
Test status
Simulation time 3227885800 ps
CPU time 486 seconds
Started Jun 05 06:01:43 PM PDT 24
Finished Jun 05 06:09:50 PM PDT 24
Peak memory 314080 kb
Host smart-85d0ac6c-d268-4289-8ed8-7db71075d572
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129187106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.flash_ctrl_rw.4129187106
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.3390364044
Short name T84
Test name
Test status
Simulation time 745758000 ps
CPU time 23.49 seconds
Started Jun 05 06:01:18 PM PDT 24
Finished Jun 05 06:01:42 PM PDT 24
Peak memory 264964 kb
Host smart-470c3796-c369-4e7f-8b02-04cc1f4a8e2e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390364044 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.3390364044
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.2380433046
Short name T134
Test name
Test status
Simulation time 6762788400 ps
CPU time 4760.32 seconds
Started Jun 05 06:00:51 PM PDT 24
Finished Jun 05 07:20:12 PM PDT 24
Peak memory 289208 kb
Host smart-93cdf2b4-49f7-4f51-85dc-2533846e53f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380433046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.2380433046
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.314977218
Short name T187
Test name
Test status
Simulation time 207804200 ps
CPU time 16.51 seconds
Started Jun 05 06:00:27 PM PDT 24
Finished Jun 05 06:00:44 PM PDT 24
Peak memory 271760 kb
Host smart-7ac68308-89a0-4954-bbbc-548c59552088
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314977218 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.314977218
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.946340906
Short name T321
Test name
Test status
Simulation time 604722200 ps
CPU time 34.59 seconds
Started Jun 05 06:02:53 PM PDT 24
Finished Jun 05 06:03:29 PM PDT 24
Peak memory 273128 kb
Host smart-959253ab-bb6f-4753-bd09-ef9e8d68bf7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946340906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_re_evict.946340906
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.924052914
Short name T36
Test name
Test status
Simulation time 639444700 ps
CPU time 134.74 seconds
Started Jun 05 06:04:54 PM PDT 24
Finished Jun 05 06:07:09 PM PDT 24
Peak memory 292728 kb
Host smart-ff489917-c57e-4464-9566-f53fbb7929b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924052914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flas
h_ctrl_intr_rd.924052914
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.1056835874
Short name T69
Test name
Test status
Simulation time 63172300 ps
CPU time 14.01 seconds
Started Jun 05 06:00:52 PM PDT 24
Finished Jun 05 06:01:07 PM PDT 24
Peak memory 276452 kb
Host smart-29155f01-1651-4600-9f6a-cce0f64b6a9d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1056835874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.1056835874
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.3746569326
Short name T282
Test name
Test status
Simulation time 15721000 ps
CPU time 13.41 seconds
Started Jun 05 06:01:19 PM PDT 24
Finished Jun 05 06:01:32 PM PDT 24
Peak memory 258912 kb
Host smart-46464388-69d1-4dba-986a-d563a9533bc8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746569326 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3746569326
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.3777950523
Short name T176
Test name
Test status
Simulation time 386988200 ps
CPU time 42.97 seconds
Started Jun 05 06:01:10 PM PDT 24
Finished Jun 05 06:01:54 PM PDT 24
Peak memory 264864 kb
Host smart-326394a4-70cd-4a05-9b4c-3c8c766611ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777950523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.3777950523
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.3719873392
Short name T135
Test name
Test status
Simulation time 23100900 ps
CPU time 22.4 seconds
Started Jun 05 06:04:04 PM PDT 24
Finished Jun 05 06:04:27 PM PDT 24
Peak memory 273216 kb
Host smart-46b3cd2e-79e0-402f-a843-bf7b9f5ee835
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719873392 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.3719873392
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3241740650
Short name T894
Test name
Test status
Simulation time 18210200 ps
CPU time 13.37 seconds
Started Jun 05 06:03:06 PM PDT 24
Finished Jun 05 06:03:20 PM PDT 24
Peak memory 259296 kb
Host smart-4e47c82b-2287-4394-8807-eff6615fb288
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241740650 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3241740650
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4184580852
Short name T344
Test name
Test status
Simulation time 701568400 ps
CPU time 391.2 seconds
Started Jun 05 06:01:01 PM PDT 24
Finished Jun 05 06:07:33 PM PDT 24
Peak memory 264248 kb
Host smart-9c95ed5b-5409-4713-8507-3834e1b4ac7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184580852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.4184580852
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.1510411506
Short name T325
Test name
Test status
Simulation time 97842900 ps
CPU time 30.96 seconds
Started Jun 05 06:01:19 PM PDT 24
Finished Jun 05 06:01:51 PM PDT 24
Peak memory 273112 kb
Host smart-5798107b-88e9-44a4-81cc-2230d095505f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510411506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.1510411506
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.2350822221
Short name T192
Test name
Test status
Simulation time 52242400 ps
CPU time 13.53 seconds
Started Jun 05 06:05:02 PM PDT 24
Finished Jun 05 06:05:16 PM PDT 24
Peak memory 275528 kb
Host smart-75910a42-cca2-40b0-86e9-996e2dbba91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350822221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.2350822221
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.4185646087
Short name T22
Test name
Test status
Simulation time 711780402700 ps
CPU time 3082.63 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:52:35 PM PDT 24
Peak memory 264952 kb
Host smart-662878f5-beb7-4bc6-949e-e5c9dae619ce
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185646087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.4185646087
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.2909801854
Short name T48
Test name
Test status
Simulation time 2030464000 ps
CPU time 91.22 seconds
Started Jun 05 06:04:53 PM PDT 24
Finished Jun 05 06:06:25 PM PDT 24
Peak memory 259252 kb
Host smart-5299ff2e-b48a-44ac-9e5c-70ddb457a509
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909801854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.2909801854
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.1158561659
Short name T289
Test name
Test status
Simulation time 4680863700 ps
CPU time 837.44 seconds
Started Jun 05 06:01:21 PM PDT 24
Finished Jun 05 06:15:19 PM PDT 24
Peak memory 273056 kb
Host smart-e17663ef-3647-4925-9de3-07bc394696f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158561659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.1158561659
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.3074364653
Short name T13
Test name
Test status
Simulation time 14847700 ps
CPU time 13.96 seconds
Started Jun 05 06:01:35 PM PDT 24
Finished Jun 05 06:01:50 PM PDT 24
Peak memory 264972 kb
Host smart-9d4778f0-94c2-4f82-bfe7-da0cab711a14
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074364653 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3074364653
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.1156816235
Short name T202
Test name
Test status
Simulation time 21480071500 ps
CPU time 647.93 seconds
Started Jun 05 06:00:46 PM PDT 24
Finished Jun 05 06:11:35 PM PDT 24
Peak memory 338212 kb
Host smart-bb0766b5-ea75-4204-bc6f-ea48e3dcaf44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156816235 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.1156816235
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3275623194
Short name T654
Test name
Test status
Simulation time 10012393800 ps
CPU time 107.69 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:02:59 PM PDT 24
Peak memory 297092 kb
Host smart-312900a4-e0e9-4bc9-a7a3-2de0a4c0090b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275623194 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.3275623194
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.261154687
Short name T279
Test name
Test status
Simulation time 66065100 ps
CPU time 13.32 seconds
Started Jun 05 06:02:51 PM PDT 24
Finished Jun 05 06:03:05 PM PDT 24
Peak memory 265000 kb
Host smart-32033f7d-15ca-4623-b620-2812427f6006
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261154687 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.261154687
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.1964554940
Short name T199
Test name
Test status
Simulation time 8274190100 ps
CPU time 614.11 seconds
Started Jun 05 06:02:19 PM PDT 24
Finished Jun 05 06:12:34 PM PDT 24
Peak memory 313644 kb
Host smart-f57e7a62-ce99-4714-9077-c261c757644d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964554940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.flash_ctrl_rw.1964554940
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.1983047351
Short name T905
Test name
Test status
Simulation time 7474772500 ps
CPU time 66.89 seconds
Started Jun 05 06:03:51 PM PDT 24
Finished Jun 05 06:04:59 PM PDT 24
Peak memory 264724 kb
Host smart-94062d36-a32c-4fa0-8454-709c8c21c74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983047351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.1983047351
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.164308430
Short name T379
Test name
Test status
Simulation time 2205527500 ps
CPU time 69.74 seconds
Started Jun 05 06:05:08 PM PDT 24
Finished Jun 05 06:06:18 PM PDT 24
Peak memory 262656 kb
Host smart-57d7152e-4e32-463f-aa7d-25cf200fafad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164308430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.164308430
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.1647201403
Short name T361
Test name
Test status
Simulation time 7973969300 ps
CPU time 73.02 seconds
Started Jun 05 06:05:31 PM PDT 24
Finished Jun 05 06:06:45 PM PDT 24
Peak memory 262148 kb
Host smart-4abba011-caf3-45d0-8917-642bde6db64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647201403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.1647201403
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.1907144418
Short name T142
Test name
Test status
Simulation time 160167081500 ps
CPU time 896.65 seconds
Started Jun 05 06:01:30 PM PDT 24
Finished Jun 05 06:16:27 PM PDT 24
Peak memory 263176 kb
Host smart-9a87a744-0809-4350-b42c-48979041d585
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907144418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.1907144418
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.3804826490
Short name T82
Test name
Test status
Simulation time 845737000 ps
CPU time 21.52 seconds
Started Jun 05 06:01:25 PM PDT 24
Finished Jun 05 06:01:47 PM PDT 24
Peak memory 264496 kb
Host smart-7c584628-f13b-4feb-b3cf-b674e2da7c8a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804826490 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.3804826490
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.2247569762
Short name T179
Test name
Test status
Simulation time 11952051800 ps
CPU time 183.13 seconds
Started Jun 05 06:03:55 PM PDT 24
Finished Jun 05 06:06:59 PM PDT 24
Peak memory 293000 kb
Host smart-a90958e3-da1e-4956-8e92-aa2ebca18937
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247569762 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.2247569762
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1889266250
Short name T264
Test name
Test status
Simulation time 61352300 ps
CPU time 20.11 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:01:14 PM PDT 24
Peak memory 264232 kb
Host smart-6590b066-80e8-413f-99d3-2843038276e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889266250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
1889266250
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.1145722351
Short name T47
Test name
Test status
Simulation time 20846700 ps
CPU time 13.63 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:01:08 PM PDT 24
Peak memory 265024 kb
Host smart-6ffb8926-ac6d-4885-9f4b-adb33d414c52
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145722351 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.1145722351
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.232718260
Short name T949
Test name
Test status
Simulation time 10895000 ps
CPU time 22.07 seconds
Started Jun 05 06:02:30 PM PDT 24
Finished Jun 05 06:02:53 PM PDT 24
Peak memory 264924 kb
Host smart-88deb76a-578b-4978-9d9e-3d689fcf6483
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232718260 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.232718260
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.1949478159
Short name T66
Test name
Test status
Simulation time 40311800 ps
CPU time 22.21 seconds
Started Jun 05 06:03:28 PM PDT 24
Finished Jun 05 06:03:51 PM PDT 24
Peak memory 279988 kb
Host smart-7cbdd20a-b9d0-44fd-accc-f5fad7e2edca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949478159 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.1949478159
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1824786604
Short name T266
Test name
Test status
Simulation time 1017149600 ps
CPU time 471.31 seconds
Started Jun 05 06:00:47 PM PDT 24
Finished Jun 05 06:08:39 PM PDT 24
Peak memory 264248 kb
Host smart-9b7d0fa6-7fe1-4090-b9aa-2aded00c10be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824786604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.1824786604
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.3527369144
Short name T83
Test name
Test status
Simulation time 776336700 ps
CPU time 20.08 seconds
Started Jun 05 06:00:54 PM PDT 24
Finished Jun 05 06:01:15 PM PDT 24
Peak memory 264960 kb
Host smart-df4d8815-f2c0-4e18-95f9-b48be2229474
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527369144 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.3527369144
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.3885053714
Short name T85
Test name
Test status
Simulation time 756056500 ps
CPU time 23.81 seconds
Started Jun 05 06:01:32 PM PDT 24
Finished Jun 05 06:01:57 PM PDT 24
Peak memory 263244 kb
Host smart-bdb84140-f16a-4eb8-92a8-ad2c7b438cba
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885053714 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.3885053714
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.4206088532
Short name T87
Test name
Test status
Simulation time 272275618000 ps
CPU time 2872.27 seconds
Started Jun 05 06:00:59 PM PDT 24
Finished Jun 05 06:48:52 PM PDT 24
Peak memory 264968 kb
Host smart-ae088d83-4fd9-4f0a-84c0-bf90aaa37345
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206088532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.4206088532
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4126178948
Short name T299
Test name
Test status
Simulation time 1227121000 ps
CPU time 776.28 seconds
Started Jun 05 06:00:44 PM PDT 24
Finished Jun 05 06:13:41 PM PDT 24
Peak memory 264228 kb
Host smart-30b6b4ab-4749-4110-a0ae-1e6fc2b8575a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126178948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.4126178948
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.658516591
Short name T305
Test name
Test status
Simulation time 216330700 ps
CPU time 17.09 seconds
Started Jun 05 06:00:33 PM PDT 24
Finished Jun 05 06:00:51 PM PDT 24
Peak memory 270788 kb
Host smart-5232c91a-52d3-4363-af12-cd14daaeddca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658516591 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.658516591
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.1100782724
Short name T119
Test name
Test status
Simulation time 1630857900 ps
CPU time 71.44 seconds
Started Jun 05 06:00:49 PM PDT 24
Finished Jun 05 06:02:01 PM PDT 24
Peak memory 260412 kb
Host smart-846ec297-8439-4016-be70-79a344e0331c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100782724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.1100782724
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.219931151
Short name T115
Test name
Test status
Simulation time 13938453800 ps
CPU time 569.08 seconds
Started Jun 05 06:01:02 PM PDT 24
Finished Jun 05 06:10:32 PM PDT 24
Peak memory 262752 kb
Host smart-54524258-ea62-4f85-a249-64d3b27baaaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=219931151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.219931151
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.769958904
Short name T887
Test name
Test status
Simulation time 10630800 ps
CPU time 21.64 seconds
Started Jun 05 06:02:34 PM PDT 24
Finished Jun 05 06:02:56 PM PDT 24
Peak memory 264980 kb
Host smart-4bd46742-1360-4542-8ffb-b31f424a90da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769958904 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.769958904
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.1069851907
Short name T1067
Test name
Test status
Simulation time 630479907400 ps
CPU time 1219.44 seconds
Started Jun 05 06:02:44 PM PDT 24
Finished Jun 05 06:23:04 PM PDT 24
Peak memory 264192 kb
Host smart-f16af4c8-1f85-4d60-b086-28d36f36250a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069851907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.1069851907
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.115683283
Short name T375
Test name
Test status
Simulation time 2815926200 ps
CPU time 66.54 seconds
Started Jun 05 06:02:50 PM PDT 24
Finished Jun 05 06:03:57 PM PDT 24
Peak memory 262908 kb
Host smart-ff293f38-f5d2-4894-9d27-808f5422ceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115683283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.115683283
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.4205757807
Short name T320
Test name
Test status
Simulation time 107366800 ps
CPU time 36.09 seconds
Started Jun 05 06:03:06 PM PDT 24
Finished Jun 05 06:03:43 PM PDT 24
Peak memory 274096 kb
Host smart-7a7f6cc8-9fa7-4339-9202-31812194d103
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205757807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.4205757807
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.3245680168
Short name T319
Test name
Test status
Simulation time 157389400 ps
CPU time 31.21 seconds
Started Jun 05 06:03:36 PM PDT 24
Finished Jun 05 06:04:08 PM PDT 24
Peak memory 274120 kb
Host smart-042d2d47-d53d-49fa-809c-791562ed60f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245680168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_rw_evict.3245680168
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.4057737948
Short name T323
Test name
Test status
Simulation time 1294812800 ps
CPU time 35.47 seconds
Started Jun 05 06:01:22 PM PDT 24
Finished Jun 05 06:01:58 PM PDT 24
Peak memory 261676 kb
Host smart-fa0d4885-0011-4c77-aa85-2bd5b90daf1a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057737948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.4057737948
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.1322964448
Short name T183
Test name
Test status
Simulation time 14067600 ps
CPU time 20.86 seconds
Started Jun 05 06:04:19 PM PDT 24
Finished Jun 05 06:04:41 PM PDT 24
Peak memory 273180 kb
Host smart-2612bcc7-fea9-48b7-93a7-c054fa620894
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322964448 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.1322964448
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.1501952789
Short name T364
Test name
Test status
Simulation time 810028400 ps
CPU time 75.89 seconds
Started Jun 05 06:04:11 PM PDT 24
Finished Jun 05 06:05:27 PM PDT 24
Peak memory 263084 kb
Host smart-05097f98-f36c-43db-b934-79986a84a566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501952789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1501952789
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.3590698035
Short name T356
Test name
Test status
Simulation time 10427400 ps
CPU time 21 seconds
Started Jun 05 06:04:15 PM PDT 24
Finished Jun 05 06:04:36 PM PDT 24
Peak memory 273160 kb
Host smart-cbcb482d-db99-4596-90ba-df249a8d6faa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590698035 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.3590698035
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.3953064200
Short name T253
Test name
Test status
Simulation time 40395500 ps
CPU time 13.91 seconds
Started Jun 05 06:01:32 PM PDT 24
Finished Jun 05 06:01:46 PM PDT 24
Peak memory 260968 kb
Host smart-ddf24b16-31ae-4a80-9ca6-85aaabb87b3b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953064200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.3953064200
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.3070670859
Short name T40
Test name
Test status
Simulation time 61443300 ps
CPU time 31.05 seconds
Started Jun 05 06:05:08 PM PDT 24
Finished Jun 05 06:05:39 PM PDT 24
Peak memory 275168 kb
Host smart-2a36a57b-4326-4948-88cd-94068aff6ce2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070670859 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.3070670859
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.2024232791
Short name T701
Test name
Test status
Simulation time 39310404800 ps
CPU time 168.93 seconds
Started Jun 05 06:01:15 PM PDT 24
Finished Jun 05 06:04:04 PM PDT 24
Peak memory 264864 kb
Host smart-a43f4f7d-ce45-4d86-8082-ca3750d5ae8d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202
4232791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.2024232791
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.2740893823
Short name T802
Test name
Test status
Simulation time 1967636000 ps
CPU time 154.14 seconds
Started Jun 05 06:03:07 PM PDT 24
Finished Jun 05 06:05:41 PM PDT 24
Peak memory 262340 kb
Host smart-0c27b0db-94c4-4efa-a2f6-f010462f80b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740893823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.2740893823
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.804408122
Short name T1101
Test name
Test status
Simulation time 67534300 ps
CPU time 59.83 seconds
Started Jun 05 06:00:56 PM PDT 24
Finished Jun 05 06:01:56 PM PDT 24
Peak memory 262312 kb
Host smart-4f1fdca9-b14b-4b52-96c7-de3916f97240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=804408122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.804408122
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.2165214233
Short name T273
Test name
Test status
Simulation time 12819323300 ps
CPU time 149.48 seconds
Started Jun 05 06:00:55 PM PDT 24
Finished Jun 05 06:03:25 PM PDT 24
Peak memory 281688 kb
Host smart-68ec4fb7-fa74-4bd1-ac11-f621d0496a99
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2165214233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.2165214233
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.3460400492
Short name T94
Test name
Test status
Simulation time 40692200 ps
CPU time 15.76 seconds
Started Jun 05 06:01:34 PM PDT 24
Finished Jun 05 06:01:50 PM PDT 24
Peak memory 261280 kb
Host smart-5b83dc84-8c81-4b43-8813-17b512d7eb3a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3460400492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.3460400492
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3076432056
Short name T1205
Test name
Test status
Simulation time 50937300 ps
CPU time 18 seconds
Started Jun 05 06:00:21 PM PDT 24
Finished Jun 05 06:00:40 PM PDT 24
Peak memory 264244 kb
Host smart-f5b43a13-85be-42e5-9567-61921660a00c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076432056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.3
076432056
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.914151389
Short name T918
Test name
Test status
Simulation time 23462891000 ps
CPU time 2295.63 seconds
Started Jun 05 06:00:56 PM PDT 24
Finished Jun 05 06:39:12 PM PDT 24
Peak memory 264544 kb
Host smart-b9511d40-72df-4ed5-9ba9-95c2cf53594b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914151389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erro
r_mp.914151389
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.3998975389
Short name T54
Test name
Test status
Simulation time 493302300 ps
CPU time 24.09 seconds
Started Jun 05 06:00:47 PM PDT 24
Finished Jun 05 06:01:12 PM PDT 24
Peak memory 264876 kb
Host smart-d756eb22-9369-493c-9866-01a69e84c56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998975389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.3998975389
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.2079626376
Short name T205
Test name
Test status
Simulation time 494898621400 ps
CPU time 1815.57 seconds
Started Jun 05 06:01:07 PM PDT 24
Finished Jun 05 06:31:23 PM PDT 24
Peak memory 264948 kb
Host smart-25c224de-fafe-4296-bbe3-48523753a410
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079626376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.2079626376
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.2295836968
Short name T367
Test name
Test status
Simulation time 14952255300 ps
CPU time 80.06 seconds
Started Jun 05 06:01:17 PM PDT 24
Finished Jun 05 06:02:38 PM PDT 24
Peak memory 262744 kb
Host smart-94545d9a-2c34-4d79-917f-7480fced8e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295836968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.2295836968
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.1057688228
Short name T124
Test name
Test status
Simulation time 736199300 ps
CPU time 66.26 seconds
Started Jun 05 06:01:04 PM PDT 24
Finished Jun 05 06:02:11 PM PDT 24
Peak memory 259784 kb
Host smart-e8298dfb-3bd1-42e2-8fc2-331e8ff44674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057688228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.1057688228
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.869076580
Short name T209
Test name
Test status
Simulation time 5363151300 ps
CPU time 131.02 seconds
Started Jun 05 06:01:10 PM PDT 24
Finished Jun 05 06:03:22 PM PDT 24
Peak memory 281252 kb
Host smart-a1e6924e-fb7a-4cbb-8089-08aef4bdcb45
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
869076580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.869076580
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.4032900063
Short name T155
Test name
Test status
Simulation time 315912093400 ps
CPU time 2910.44 seconds
Started Jun 05 06:01:32 PM PDT 24
Finished Jun 05 06:50:03 PM PDT 24
Peak memory 262124 kb
Host smart-ba38c3c2-41d6-466d-b17f-cc18d5aabaad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032900063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.4032900063
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.162097082
Short name T271
Test name
Test status
Simulation time 59558400 ps
CPU time 100.19 seconds
Started Jun 05 06:01:29 PM PDT 24
Finished Jun 05 06:03:09 PM PDT 24
Peak memory 262196 kb
Host smart-856fb4e7-1dfe-4958-b016-b466e2a7cf64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=162097082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.162097082
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.1392052325
Short name T86
Test name
Test status
Simulation time 909115100 ps
CPU time 16.63 seconds
Started Jun 05 06:01:38 PM PDT 24
Finished Jun 05 06:01:55 PM PDT 24
Peak memory 260928 kb
Host smart-54aa033c-5f6f-44cd-a000-af89332878e0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392052325 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.1392052325
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2643776125
Short name T1237
Test name
Test status
Simulation time 1907155400 ps
CPU time 58.48 seconds
Started Jun 05 06:00:30 PM PDT 24
Finished Jun 05 06:01:34 PM PDT 24
Peak memory 260576 kb
Host smart-c73883c5-afb2-43ea-bc1b-79c717305a78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643776125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.2643776125
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.610527021
Short name T1138
Test name
Test status
Simulation time 9511080800 ps
CPU time 76.47 seconds
Started Jun 05 06:00:31 PM PDT 24
Finished Jun 05 06:01:48 PM PDT 24
Peak memory 260616 kb
Host smart-c25545a6-7aa3-41eb-8ea7-913e34e196c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610527021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_bit_bash.610527021
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1448383744
Short name T300
Test name
Test status
Simulation time 54144800 ps
CPU time 30.33 seconds
Started Jun 05 06:00:18 PM PDT 24
Finished Jun 05 06:00:49 PM PDT 24
Peak memory 264160 kb
Host smart-f0409377-111b-4b53-b8a9-63d0f76174dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448383744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.1448383744
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1240208651
Short name T292
Test name
Test status
Simulation time 113525000 ps
CPU time 19.31 seconds
Started Jun 05 06:00:25 PM PDT 24
Finished Jun 05 06:00:45 PM PDT 24
Peak memory 270972 kb
Host smart-f74d22f3-363d-4c23-b6d0-520d10e73307
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240208651 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.1240208651
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2886453859
Short name T1164
Test name
Test status
Simulation time 27583900 ps
CPU time 16.92 seconds
Started Jun 05 06:00:29 PM PDT 24
Finished Jun 05 06:00:47 PM PDT 24
Peak memory 260652 kb
Host smart-894589f9-7782-4cdd-87ff-e8d8927e5ccc
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886453859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.2886453859
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.509453159
Short name T1158
Test name
Test status
Simulation time 142760600 ps
CPU time 13.44 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:00:40 PM PDT 24
Peak memory 262916 kb
Host smart-ae082a2f-dc37-4c4b-9cd1-841479978400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509453159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.509453159
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2899685865
Short name T240
Test name
Test status
Simulation time 19141800 ps
CPU time 13.54 seconds
Started Jun 05 06:00:22 PM PDT 24
Finished Jun 05 06:00:36 PM PDT 24
Peak memory 264108 kb
Host smart-187dad7e-9f32-465e-ac79-53e2ab7d6206
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899685865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.2899685865
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3933402990
Short name T1141
Test name
Test status
Simulation time 20934600 ps
CPU time 13.62 seconds
Started Jun 05 06:00:22 PM PDT 24
Finished Jun 05 06:00:36 PM PDT 24
Peak memory 262852 kb
Host smart-ba3df6a6-9701-4a40-8a1e-b2d4d8822814
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933402990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.3933402990
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3257876488
Short name T1119
Test name
Test status
Simulation time 123263600 ps
CPU time 18.51 seconds
Started Jun 05 06:00:36 PM PDT 24
Finished Jun 05 06:00:55 PM PDT 24
Peak memory 260640 kb
Host smart-d4f01398-8188-4c15-a69f-278784e5bca8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257876488 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.3257876488
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1790191628
Short name T1140
Test name
Test status
Simulation time 39217600 ps
CPU time 15.79 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:49 PM PDT 24
Peak memory 260580 kb
Host smart-63d471e4-8db9-4dd8-825f-5f2791733fa8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790191628 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.1790191628
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1773707086
Short name T1232
Test name
Test status
Simulation time 12518000 ps
CPU time 15.52 seconds
Started Jun 05 06:00:28 PM PDT 24
Finished Jun 05 06:00:45 PM PDT 24
Peak memory 260608 kb
Host smart-08bf86ed-9dd3-46c4-b2d7-a78db4acdf6c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773707086 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.1773707086
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3609198134
Short name T294
Test name
Test status
Simulation time 5749169400 ps
CPU time 909.63 seconds
Started Jun 05 06:00:31 PM PDT 24
Finished Jun 05 06:15:42 PM PDT 24
Peak memory 263344 kb
Host smart-1009597c-6c03-4c6b-9f18-2aa8a77afae6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609198134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.3609198134
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.344590241
Short name T1118
Test name
Test status
Simulation time 434427400 ps
CPU time 30.02 seconds
Started Jun 05 06:00:39 PM PDT 24
Finished Jun 05 06:01:10 PM PDT 24
Peak memory 260656 kb
Host smart-41be5d98-f5a1-4228-9822-78bea8bd2187
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344590241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_aliasing.344590241
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3713135622
Short name T1223
Test name
Test status
Simulation time 660266700 ps
CPU time 63.97 seconds
Started Jun 05 06:00:47 PM PDT 24
Finished Jun 05 06:01:52 PM PDT 24
Peak memory 260664 kb
Host smart-e45a0b13-48d4-4c8f-bf65-f74cbe911716
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713135622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.3713135622
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3742209477
Short name T1154
Test name
Test status
Simulation time 27113600 ps
CPU time 45.58 seconds
Started Jun 05 06:00:38 PM PDT 24
Finished Jun 05 06:01:24 PM PDT 24
Peak memory 260776 kb
Host smart-7d4ac816-65fd-4013-8c0d-cad564b81181
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742209477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.3742209477
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1405555699
Short name T218
Test name
Test status
Simulation time 29330800 ps
CPU time 17.81 seconds
Started Jun 05 06:00:36 PM PDT 24
Finished Jun 05 06:00:54 PM PDT 24
Peak memory 277592 kb
Host smart-22bcbdd2-7a5f-48f7-b7db-5c90f14b9c67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405555699 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.1405555699
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1331523129
Short name T1126
Test name
Test status
Simulation time 161530800 ps
CPU time 14.84 seconds
Started Jun 05 06:00:39 PM PDT 24
Finished Jun 05 06:00:54 PM PDT 24
Peak memory 260612 kb
Host smart-af1dfe3d-96b5-4745-a239-a47e50564f22
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331523129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.1331523129
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.638702012
Short name T314
Test name
Test status
Simulation time 18913100 ps
CPU time 13.52 seconds
Started Jun 05 06:00:30 PM PDT 24
Finished Jun 05 06:00:45 PM PDT 24
Peak memory 262788 kb
Host smart-06a2904c-8e1e-4770-b377-febc6d2f3035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638702012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.638702012
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3698869864
Short name T1148
Test name
Test status
Simulation time 23576000 ps
CPU time 13.53 seconds
Started Jun 05 06:00:54 PM PDT 24
Finished Jun 05 06:01:08 PM PDT 24
Peak memory 262832 kb
Host smart-0b2628cf-e991-4144-855c-6037277ece88
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698869864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.3698869864
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1227602167
Short name T304
Test name
Test status
Simulation time 225647400 ps
CPU time 21.63 seconds
Started Jun 05 06:00:31 PM PDT 24
Finished Jun 05 06:00:53 PM PDT 24
Peak memory 262488 kb
Host smart-4c9218ac-ca81-45da-9169-a169ba3744a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227602167 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.1227602167
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2308130114
Short name T1233
Test name
Test status
Simulation time 57993600 ps
CPU time 15.77 seconds
Started Jun 05 06:00:31 PM PDT 24
Finished Jun 05 06:00:48 PM PDT 24
Peak memory 260640 kb
Host smart-3e3d1094-ed76-4b93-8f9b-6f18b4c6e972
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308130114 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.2308130114
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.4286874524
Short name T1234
Test name
Test status
Simulation time 44848300 ps
CPU time 15.66 seconds
Started Jun 05 06:00:34 PM PDT 24
Finished Jun 05 06:00:50 PM PDT 24
Peak memory 260628 kb
Host smart-858d58f5-2d6b-45ca-ae90-a08c3e10c599
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286874524 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.4286874524
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3629742663
Short name T1199
Test name
Test status
Simulation time 193626600 ps
CPU time 18.41 seconds
Started Jun 05 06:00:38 PM PDT 24
Finished Jun 05 06:00:57 PM PDT 24
Peak memory 264276 kb
Host smart-c16b74be-ee56-42ed-9a1f-8937bf99b450
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629742663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3
629742663
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2335272808
Short name T70
Test name
Test status
Simulation time 1335985800 ps
CPU time 917.92 seconds
Started Jun 05 06:00:37 PM PDT 24
Finished Jun 05 06:15:56 PM PDT 24
Peak memory 264208 kb
Host smart-f79f2712-aa7d-4ca9-963a-7ea3ea200699
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335272808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.2335272808
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3019398149
Short name T1124
Test name
Test status
Simulation time 53318800 ps
CPU time 18.02 seconds
Started Jun 05 06:00:54 PM PDT 24
Finished Jun 05 06:01:13 PM PDT 24
Peak memory 264216 kb
Host smart-b29830c2-3250-4f04-b80a-d6597f9e70bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019398149 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3019398149
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.666070074
Short name T296
Test name
Test status
Simulation time 46241300 ps
CPU time 14.11 seconds
Started Jun 05 06:00:33 PM PDT 24
Finished Jun 05 06:00:49 PM PDT 24
Peak memory 260572 kb
Host smart-4f002777-6cf1-4cb2-a324-dc8491212edf
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666070074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.flash_ctrl_csr_rw.666070074
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.4220931119
Short name T1162
Test name
Test status
Simulation time 18067900 ps
CPU time 13.68 seconds
Started Jun 05 06:00:51 PM PDT 24
Finished Jun 05 06:01:05 PM PDT 24
Peak memory 262704 kb
Host smart-875786df-fb5f-4f51-bda9-78a4ff04d8f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220931119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
4220931119
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1598690580
Short name T1161
Test name
Test status
Simulation time 167586600 ps
CPU time 34.94 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:01:28 PM PDT 24
Peak memory 262168 kb
Host smart-9e8c59dc-2f8a-41c2-ab52-4da76e85bd88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598690580 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.1598690580
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1466863773
Short name T1111
Test name
Test status
Simulation time 40362200 ps
CPU time 13.47 seconds
Started Jun 05 06:00:55 PM PDT 24
Finished Jun 05 06:01:09 PM PDT 24
Peak memory 260332 kb
Host smart-66d70a25-8265-4f43-87d1-48de8eded3e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466863773 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.1466863773
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3123435780
Short name T1218
Test name
Test status
Simulation time 18046700 ps
CPU time 15.8 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:49 PM PDT 24
Peak memory 260644 kb
Host smart-85886673-8b1f-4922-8e6a-07e504bad307
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123435780 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.3123435780
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2177796717
Short name T260
Test name
Test status
Simulation time 32137900 ps
CPU time 15.99 seconds
Started Jun 05 06:00:34 PM PDT 24
Finished Jun 05 06:00:51 PM PDT 24
Peak memory 264236 kb
Host smart-9ecc2824-5792-4c7c-be90-53230c7a6975
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177796717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
2177796717
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3605257439
Short name T347
Test name
Test status
Simulation time 333901800 ps
CPU time 385.84 seconds
Started Jun 05 06:00:39 PM PDT 24
Finished Jun 05 06:07:06 PM PDT 24
Peak memory 260732 kb
Host smart-594ee4ff-f854-4e21-8da5-d5f3e4e81ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605257439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.3605257439
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1384706014
Short name T231
Test name
Test status
Simulation time 373666600 ps
CPU time 16.33 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:49 PM PDT 24
Peak memory 278252 kb
Host smart-91903775-73f5-49c0-aad4-9852ae18b918
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384706014 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.1384706014
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1091696954
Short name T1144
Test name
Test status
Simulation time 55128600 ps
CPU time 17.44 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:51 PM PDT 24
Peak memory 261880 kb
Host smart-aef8dc2b-d7d9-434e-a434-b268c39a0a45
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091696954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.1091696954
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2559694662
Short name T316
Test name
Test status
Simulation time 26327300 ps
CPU time 13.83 seconds
Started Jun 05 06:00:40 PM PDT 24
Finished Jun 05 06:00:55 PM PDT 24
Peak memory 262744 kb
Host smart-5f33d7a6-1c91-4a0f-abc2-21f094e30bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559694662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
2559694662
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.681037569
Short name T1187
Test name
Test status
Simulation time 160706300 ps
CPU time 30.72 seconds
Started Jun 05 06:00:55 PM PDT 24
Finished Jun 05 06:01:26 PM PDT 24
Peak memory 260680 kb
Host smart-52dadbee-950a-4edb-832d-0e9ddfee61ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681037569 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.681037569
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3116638175
Short name T1133
Test name
Test status
Simulation time 34029400 ps
CPU time 15.3 seconds
Started Jun 05 06:00:40 PM PDT 24
Finished Jun 05 06:00:57 PM PDT 24
Peak memory 260656 kb
Host smart-d59dfc5d-b215-400b-ac0e-8e817b2037ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116638175 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.3116638175
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2219909039
Short name T1110
Test name
Test status
Simulation time 70540100 ps
CPU time 13.41 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:01:07 PM PDT 24
Peak memory 260644 kb
Host smart-61fb62a8-e470-4cf8-ac28-9bad88f1d84d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219909039 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.2219909039
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1396243347
Short name T265
Test name
Test status
Simulation time 177166800 ps
CPU time 17.19 seconds
Started Jun 05 06:00:54 PM PDT 24
Finished Jun 05 06:01:12 PM PDT 24
Peak memory 264240 kb
Host smart-cb3c92c8-1770-4f9f-89cd-18cc5545e647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396243347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
1396243347
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2137727172
Short name T232
Test name
Test status
Simulation time 238011000 ps
CPU time 19.7 seconds
Started Jun 05 06:00:37 PM PDT 24
Finished Jun 05 06:00:57 PM PDT 24
Peak memory 272416 kb
Host smart-079dc22a-614b-4f1d-9bdb-a08d28c5f95f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137727172 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.2137727172
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.947161843
Short name T250
Test name
Test status
Simulation time 60082800 ps
CPU time 17.44 seconds
Started Jun 05 06:00:57 PM PDT 24
Finished Jun 05 06:01:15 PM PDT 24
Peak memory 261660 kb
Host smart-ee640f8a-e36d-42c9-a891-74553c7d2a70
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947161843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.flash_ctrl_csr_rw.947161843
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2915738902
Short name T1198
Test name
Test status
Simulation time 231538500 ps
CPU time 19.13 seconds
Started Jun 05 06:00:47 PM PDT 24
Finished Jun 05 06:01:07 PM PDT 24
Peak memory 260688 kb
Host smart-dae501a6-9fcc-402f-bfc0-bffd43eee42b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915738902 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.2915738902
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1051682914
Short name T1114
Test name
Test status
Simulation time 25331200 ps
CPU time 13.56 seconds
Started Jun 05 06:00:47 PM PDT 24
Finished Jun 05 06:01:01 PM PDT 24
Peak memory 260580 kb
Host smart-7e6fd8b1-ad6a-4ab2-8105-8b15e57bef88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051682914 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.1051682914
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1784082370
Short name T1214
Test name
Test status
Simulation time 34054000 ps
CPU time 15.82 seconds
Started Jun 05 06:00:37 PM PDT 24
Finished Jun 05 06:00:53 PM PDT 24
Peak memory 260848 kb
Host smart-ff50ef87-60eb-4b42-8551-82266a4b8ac3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784082370 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.1784082370
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4148400791
Short name T1167
Test name
Test status
Simulation time 119027300 ps
CPU time 19.09 seconds
Started Jun 05 06:00:35 PM PDT 24
Finished Jun 05 06:00:55 PM PDT 24
Peak memory 264248 kb
Host smart-1cff4e9b-8947-42a4-a774-6c6acb2bdc5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148400791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
4148400791
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1068713623
Short name T1173
Test name
Test status
Simulation time 70999900 ps
CPU time 19.02 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:52 PM PDT 24
Peak memory 272376 kb
Host smart-5a78c46a-9282-4262-8aec-f30527f3c965
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068713623 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.1068713623
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1567650531
Short name T1210
Test name
Test status
Simulation time 94906800 ps
CPU time 17.03 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:01:11 PM PDT 24
Peak memory 260564 kb
Host smart-8c48c96e-f042-4968-8935-a6a4586dbbc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567650531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.1567650531
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2436712567
Short name T1228
Test name
Test status
Simulation time 56835200 ps
CPU time 13.46 seconds
Started Jun 05 06:01:05 PM PDT 24
Finished Jun 05 06:01:19 PM PDT 24
Peak memory 262968 kb
Host smart-f4137fc8-b09e-4eb7-bccb-28df82a22937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436712567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
2436712567
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3166467821
Short name T1200
Test name
Test status
Simulation time 421618900 ps
CPU time 18.48 seconds
Started Jun 05 06:00:58 PM PDT 24
Finished Jun 05 06:01:17 PM PDT 24
Peak memory 260708 kb
Host smart-51a7d003-6007-4564-8904-bfbea7996813
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166467821 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.3166467821
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3721865866
Short name T1221
Test name
Test status
Simulation time 12536800 ps
CPU time 15.93 seconds
Started Jun 05 06:00:59 PM PDT 24
Finished Jun 05 06:01:16 PM PDT 24
Peak memory 260556 kb
Host smart-5dab82c1-6633-4579-b80f-2ada7464b94c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721865866 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.3721865866
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.4000070796
Short name T1179
Test name
Test status
Simulation time 15021500 ps
CPU time 15.78 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:01:10 PM PDT 24
Peak memory 260636 kb
Host smart-9b077219-7398-497d-bd6b-3ee9ce1d29f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000070796 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.4000070796
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3112571819
Short name T1188
Test name
Test status
Simulation time 429556000 ps
CPU time 461.12 seconds
Started Jun 05 06:00:47 PM PDT 24
Finished Jun 05 06:08:29 PM PDT 24
Peak memory 261752 kb
Host smart-2e6870a0-8261-4333-b5b6-ced874b14553
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112571819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.3112571819
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.605522961
Short name T301
Test name
Test status
Simulation time 1105119700 ps
CPU time 19.47 seconds
Started Jun 05 06:00:36 PM PDT 24
Finished Jun 05 06:00:56 PM PDT 24
Peak memory 279456 kb
Host smart-0285b0f8-b0d8-4d66-a7e9-2f82c9cf3043
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605522961 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.605522961
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3276411612
Short name T298
Test name
Test status
Simulation time 68901100 ps
CPU time 18.08 seconds
Started Jun 05 06:00:31 PM PDT 24
Finished Jun 05 06:00:51 PM PDT 24
Peak memory 260576 kb
Host smart-e18e5b4d-681f-4bb0-a8b0-ccd9760e8617
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276411612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.3276411612
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3590866789
Short name T1243
Test name
Test status
Simulation time 28095300 ps
CPU time 13.46 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:46 PM PDT 24
Peak memory 262960 kb
Host smart-1cbad5a5-51c4-446a-a296-23eb6c11b7a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590866789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
3590866789
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1220033621
Short name T1130
Test name
Test status
Simulation time 237807500 ps
CPU time 30.09 seconds
Started Jun 05 06:00:45 PM PDT 24
Finished Jun 05 06:01:16 PM PDT 24
Peak memory 262968 kb
Host smart-77afaa52-6992-4d06-bcce-1083d0238ed0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220033621 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.1220033621
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3084507632
Short name T1106
Test name
Test status
Simulation time 13786800 ps
CPU time 15.66 seconds
Started Jun 05 06:00:34 PM PDT 24
Finished Jun 05 06:00:50 PM PDT 24
Peak memory 260632 kb
Host smart-764acc94-bd7d-46bc-a9d0-b9e7ddc84348
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084507632 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.3084507632
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.894740112
Short name T1150
Test name
Test status
Simulation time 47558000 ps
CPU time 15.72 seconds
Started Jun 05 06:01:01 PM PDT 24
Finished Jun 05 06:01:18 PM PDT 24
Peak memory 260584 kb
Host smart-fc69fdee-88b0-4701-89e1-f178cbb4f58f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894740112 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.894740112
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3683619818
Short name T1156
Test name
Test status
Simulation time 165265900 ps
CPU time 19.54 seconds
Started Jun 05 06:00:40 PM PDT 24
Finished Jun 05 06:01:01 PM PDT 24
Peak memory 272400 kb
Host smart-517ecc92-b525-4f57-960c-5807a8403768
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683619818 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3683619818
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.81653417
Short name T1171
Test name
Test status
Simulation time 1148911200 ps
CPU time 18.18 seconds
Started Jun 05 06:01:02 PM PDT 24
Finished Jun 05 06:01:22 PM PDT 24
Peak memory 260636 kb
Host smart-4c1cd725-7f85-462d-8c34-b6459fe465b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81653417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 15.flash_ctrl_csr_rw.81653417
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1821413362
Short name T1131
Test name
Test status
Simulation time 49205500 ps
CPU time 13.36 seconds
Started Jun 05 06:01:06 PM PDT 24
Finished Jun 05 06:01:21 PM PDT 24
Peak memory 263012 kb
Host smart-7fdfaa15-8311-4d2d-a6fc-b253a0550a92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821413362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
1821413362
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.711555542
Short name T1168
Test name
Test status
Simulation time 157234000 ps
CPU time 35.16 seconds
Started Jun 05 06:00:35 PM PDT 24
Finished Jun 05 06:01:11 PM PDT 24
Peak memory 260572 kb
Host smart-0166b1fb-4fbb-406b-8dac-957e84687217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711555542 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.711555542
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.442422459
Short name T1244
Test name
Test status
Simulation time 43172200 ps
CPU time 13.14 seconds
Started Jun 05 06:00:41 PM PDT 24
Finished Jun 05 06:00:55 PM PDT 24
Peak memory 260632 kb
Host smart-65b7ab90-694f-4e87-a1c0-af9770b7e87f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442422459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.442422459
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1055051399
Short name T1155
Test name
Test status
Simulation time 33082600 ps
CPU time 15.44 seconds
Started Jun 05 06:00:30 PM PDT 24
Finished Jun 05 06:00:47 PM PDT 24
Peak memory 260532 kb
Host smart-be6bab1c-6355-4825-ac57-b172b08358b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055051399 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.1055051399
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1600144594
Short name T263
Test name
Test status
Simulation time 55906400 ps
CPU time 18.58 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:01:12 PM PDT 24
Peak memory 264248 kb
Host smart-7b2df9d4-81d9-4b3e-a249-f3af368910ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600144594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
1600144594
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3663569542
Short name T295
Test name
Test status
Simulation time 1805024900 ps
CPU time 461.27 seconds
Started Jun 05 06:00:45 PM PDT 24
Finished Jun 05 06:08:27 PM PDT 24
Peak memory 263244 kb
Host smart-e6588c5c-37d8-4bc7-a3b0-912d3ca1d19c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663569542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.3663569542
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3963478
Short name T1241
Test name
Test status
Simulation time 130486400 ps
CPU time 17.44 seconds
Started Jun 05 06:00:43 PM PDT 24
Finished Jun 05 06:01:01 PM PDT 24
Peak memory 271648 kb
Host smart-eee7b1d9-36a8-454a-a93a-0778564cc017
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963478 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.3963478
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1298088389
Short name T293
Test name
Test status
Simulation time 120348300 ps
CPU time 16.97 seconds
Started Jun 05 06:00:55 PM PDT 24
Finished Jun 05 06:01:13 PM PDT 24
Peak memory 260636 kb
Host smart-65f4465d-8317-43c4-8fc1-37ad44bc956e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298088389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.1298088389
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.4285920824
Short name T1117
Test name
Test status
Simulation time 32513700 ps
CPU time 13.44 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:47 PM PDT 24
Peak memory 262644 kb
Host smart-05e701d2-263f-4496-8868-4d6fb3158c7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285920824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
4285920824
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3498781946
Short name T297
Test name
Test status
Simulation time 99552000 ps
CPU time 15.49 seconds
Started Jun 05 06:01:05 PM PDT 24
Finished Jun 05 06:01:22 PM PDT 24
Peak memory 260644 kb
Host smart-054163fd-b2bb-48e6-b7e6-84686b1abe91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498781946 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.3498781946
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3364338777
Short name T1176
Test name
Test status
Simulation time 84663300 ps
CPU time 15.71 seconds
Started Jun 05 06:00:33 PM PDT 24
Finished Jun 05 06:00:50 PM PDT 24
Peak memory 260672 kb
Host smart-90c8dbdb-009d-4c3e-8cd6-da8e978accb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364338777 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.3364338777
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2591978710
Short name T1225
Test name
Test status
Simulation time 30786000 ps
CPU time 15.72 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:01:10 PM PDT 24
Peak memory 260564 kb
Host smart-c9f2f3d6-ad90-41ef-8818-36d075af0b89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591978710 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.2591978710
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1890304043
Short name T1122
Test name
Test status
Simulation time 48917600 ps
CPU time 15.65 seconds
Started Jun 05 06:00:33 PM PDT 24
Finished Jun 05 06:00:50 PM PDT 24
Peak memory 264244 kb
Host smart-12b69ddb-ff81-486c-a420-8978a039c47c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890304043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
1890304043
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4237411422
Short name T350
Test name
Test status
Simulation time 530344800 ps
CPU time 448.77 seconds
Started Jun 05 06:01:04 PM PDT 24
Finished Jun 05 06:08:33 PM PDT 24
Peak memory 260688 kb
Host smart-02c47cf3-cc51-4a6e-999f-1a75d7e89a27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237411422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.4237411422
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.437623920
Short name T1203
Test name
Test status
Simulation time 59981500 ps
CPU time 17.92 seconds
Started Jun 05 06:00:44 PM PDT 24
Finished Jun 05 06:01:03 PM PDT 24
Peak memory 272568 kb
Host smart-9998961f-1093-4af1-bb54-a27e55239d62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437623920 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.437623920
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1420805725
Short name T1116
Test name
Test status
Simulation time 25619800 ps
CPU time 14.78 seconds
Started Jun 05 06:00:55 PM PDT 24
Finished Jun 05 06:01:11 PM PDT 24
Peak memory 264172 kb
Host smart-8ab881dd-71e4-4b95-ab09-b40b192267a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420805725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.1420805725
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2937019532
Short name T1165
Test name
Test status
Simulation time 70625300 ps
CPU time 13.3 seconds
Started Jun 05 06:00:49 PM PDT 24
Finished Jun 05 06:01:02 PM PDT 24
Peak memory 262564 kb
Host smart-605d2fa3-d43d-43b4-89e6-dd4937c68074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937019532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
2937019532
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.115114640
Short name T1181
Test name
Test status
Simulation time 82604800 ps
CPU time 19.94 seconds
Started Jun 05 06:01:03 PM PDT 24
Finished Jun 05 06:01:24 PM PDT 24
Peak memory 262312 kb
Host smart-50332157-9c50-40ae-a8ba-4a6137dee772
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115114640 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.115114640
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2132558612
Short name T1163
Test name
Test status
Simulation time 19762500 ps
CPU time 13.18 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:01:06 PM PDT 24
Peak memory 260616 kb
Host smart-6fe61e06-c819-453d-b337-d94acb7f794a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132558612 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.2132558612
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2757423667
Short name T1143
Test name
Test status
Simulation time 20678100 ps
CPU time 13.21 seconds
Started Jun 05 06:00:42 PM PDT 24
Finished Jun 05 06:00:56 PM PDT 24
Peak memory 260676 kb
Host smart-6cc8cb57-9089-4af8-80a0-69892cf5fc38
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757423667 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.2757423667
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2940332456
Short name T261
Test name
Test status
Simulation time 160089500 ps
CPU time 17.78 seconds
Started Jun 05 06:00:44 PM PDT 24
Finished Jun 05 06:01:02 PM PDT 24
Peak memory 264408 kb
Host smart-490e05d2-2c7d-4186-8588-0cf61c5feff8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940332456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
2940332456
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.868519975
Short name T312
Test name
Test status
Simulation time 84882000 ps
CPU time 16.99 seconds
Started Jun 05 06:00:44 PM PDT 24
Finished Jun 05 06:01:02 PM PDT 24
Peak memory 272364 kb
Host smart-a10b5c90-28bf-46f9-9144-bbd4fb54a291
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868519975 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.868519975
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.59549903
Short name T290
Test name
Test status
Simulation time 389182700 ps
CPU time 16.41 seconds
Started Jun 05 06:00:42 PM PDT 24
Finished Jun 05 06:00:59 PM PDT 24
Peak memory 264120 kb
Host smart-ee653c25-c729-4106-a214-0a90a0b98089
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59549903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 18.flash_ctrl_csr_rw.59549903
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2957200160
Short name T1109
Test name
Test status
Simulation time 23869100 ps
CPU time 13.42 seconds
Started Jun 05 06:00:57 PM PDT 24
Finished Jun 05 06:01:11 PM PDT 24
Peak memory 262964 kb
Host smart-8885da36-e49b-4594-b106-67bdd8b32d81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957200160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
2957200160
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3748005146
Short name T72
Test name
Test status
Simulation time 1060914900 ps
CPU time 36.2 seconds
Started Jun 05 06:00:42 PM PDT 24
Finished Jun 05 06:01:19 PM PDT 24
Peak memory 260912 kb
Host smart-da416b36-43e7-498e-a443-9109de05ab01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748005146 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.3748005146
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2326270937
Short name T1104
Test name
Test status
Simulation time 24410700 ps
CPU time 15.5 seconds
Started Jun 05 06:00:46 PM PDT 24
Finished Jun 05 06:01:02 PM PDT 24
Peak memory 260608 kb
Host smart-0a8ba315-9afa-4b2a-b2d8-86ec7ecd8ccd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326270937 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.2326270937
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3188304696
Short name T1170
Test name
Test status
Simulation time 11572600 ps
CPU time 13.15 seconds
Started Jun 05 06:00:57 PM PDT 24
Finished Jun 05 06:01:11 PM PDT 24
Peak memory 260564 kb
Host smart-5099bc50-1f63-43d1-af8c-b9e5728300e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188304696 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.3188304696
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2297205026
Short name T349
Test name
Test status
Simulation time 3299392800 ps
CPU time 465.97 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:08:39 PM PDT 24
Peak memory 264416 kb
Host smart-c4b91a90-e714-492f-bb2a-4a22a8ab8344
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297205026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.2297205026
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.685847177
Short name T1169
Test name
Test status
Simulation time 45702900 ps
CPU time 17.06 seconds
Started Jun 05 06:00:45 PM PDT 24
Finished Jun 05 06:01:03 PM PDT 24
Peak memory 264208 kb
Host smart-c836353a-0e46-466d-bad6-064d7eb3d6ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685847177 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.685847177
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1222951755
Short name T188
Test name
Test status
Simulation time 199811000 ps
CPU time 17.72 seconds
Started Jun 05 06:00:58 PM PDT 24
Finished Jun 05 06:01:17 PM PDT 24
Peak memory 260696 kb
Host smart-15e296ca-a920-44a8-acfe-6cf57cd6893d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222951755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.1222951755
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1173396262
Short name T1146
Test name
Test status
Simulation time 66934300 ps
CPU time 13.74 seconds
Started Jun 05 06:00:59 PM PDT 24
Finished Jun 05 06:01:13 PM PDT 24
Peak memory 262800 kb
Host smart-2958fdc3-5196-4e1b-bded-ae46a3a871f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173396262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
1173396262
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3342170052
Short name T1215
Test name
Test status
Simulation time 1305162100 ps
CPU time 16.86 seconds
Started Jun 05 06:00:44 PM PDT 24
Finished Jun 05 06:01:02 PM PDT 24
Peak memory 262076 kb
Host smart-4de2552b-84ba-42cd-a4e9-4054cae61715
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342170052 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.3342170052
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1465527890
Short name T1236
Test name
Test status
Simulation time 44692000 ps
CPU time 13.07 seconds
Started Jun 05 06:00:40 PM PDT 24
Finished Jun 05 06:00:54 PM PDT 24
Peak memory 260620 kb
Host smart-3c7c104b-60c3-44c2-9941-fe0920f823b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465527890 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.1465527890
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1456571387
Short name T1125
Test name
Test status
Simulation time 15528000 ps
CPU time 13.43 seconds
Started Jun 05 06:01:13 PM PDT 24
Finished Jun 05 06:01:27 PM PDT 24
Peak memory 260564 kb
Host smart-26e1b607-4a88-41b6-aaf4-5005c77b972a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456571387 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.1456571387
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3131503731
Short name T1242
Test name
Test status
Simulation time 185733700 ps
CPU time 18.21 seconds
Started Jun 05 06:01:00 PM PDT 24
Finished Jun 05 06:01:18 PM PDT 24
Peak memory 264248 kb
Host smart-2109b1c1-7041-4a5f-b844-219d9914b659
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131503731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
3131503731
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.352468102
Short name T348
Test name
Test status
Simulation time 1429729200 ps
CPU time 902.89 seconds
Started Jun 05 06:00:56 PM PDT 24
Finished Jun 05 06:15:59 PM PDT 24
Peak memory 264224 kb
Host smart-cac56699-e5e2-492c-9d09-694b404f7da7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352468102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl
_tl_intg_err.352468102
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4028871931
Short name T1185
Test name
Test status
Simulation time 825351400 ps
CPU time 36.4 seconds
Started Jun 05 06:00:54 PM PDT 24
Finished Jun 05 06:01:31 PM PDT 24
Peak memory 260644 kb
Host smart-504b6412-a834-4873-a077-6966f8f6cb9b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028871931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.4028871931
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4101364558
Short name T1129
Test name
Test status
Simulation time 662414600 ps
CPU time 57.03 seconds
Started Jun 05 06:00:33 PM PDT 24
Finished Jun 05 06:01:31 PM PDT 24
Peak memory 260624 kb
Host smart-920a5f9b-5d94-4d8c-9c76-d18232160ded
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101364558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.4101364558
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.510376738
Short name T185
Test name
Test status
Simulation time 41887900 ps
CPU time 26.2 seconds
Started Jun 05 06:00:35 PM PDT 24
Finished Jun 05 06:01:02 PM PDT 24
Peak memory 260604 kb
Host smart-77504975-8cfc-4479-b022-2be7157e5eb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510376738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_hw_reset.510376738
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2585887963
Short name T1247
Test name
Test status
Simulation time 151074700 ps
CPU time 14.61 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:48 PM PDT 24
Peak memory 263220 kb
Host smart-e1a7aff0-8524-48dd-b3ab-195d75d45dcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585887963 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.2585887963
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.697517060
Short name T1175
Test name
Test status
Simulation time 123454000 ps
CPU time 16.79 seconds
Started Jun 05 06:00:30 PM PDT 24
Finished Jun 05 06:00:48 PM PDT 24
Peak memory 264120 kb
Host smart-12c72a79-22bc-4bc9-85e3-7f795687c684
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697517060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_csr_rw.697517060
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2955963792
Short name T1178
Test name
Test status
Simulation time 22329000 ps
CPU time 13.5 seconds
Started Jun 05 06:00:38 PM PDT 24
Finished Jun 05 06:00:52 PM PDT 24
Peak memory 262840 kb
Host smart-6a54141a-c9d9-484e-b158-f5030bc7a9f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955963792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.2
955963792
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2199173452
Short name T236
Test name
Test status
Simulation time 54472700 ps
CPU time 13.65 seconds
Started Jun 05 06:00:38 PM PDT 24
Finished Jun 05 06:00:52 PM PDT 24
Peak memory 264128 kb
Host smart-576564cb-fa8a-4511-b3aa-0901a443fa18
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199173452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.2199173452
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1256006509
Short name T1103
Test name
Test status
Simulation time 51910600 ps
CPU time 14 seconds
Started Jun 05 06:00:23 PM PDT 24
Finished Jun 05 06:00:37 PM PDT 24
Peak memory 262792 kb
Host smart-2f682e66-df4a-4c17-99b2-5be9eca7b680
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256006509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.1256006509
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3827467400
Short name T291
Test name
Test status
Simulation time 953564900 ps
CPU time 36.25 seconds
Started Jun 05 06:00:33 PM PDT 24
Finished Jun 05 06:01:11 PM PDT 24
Peak memory 260656 kb
Host smart-90c788fc-4a60-4d4c-afa8-b01376975c95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827467400 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.3827467400
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2192657484
Short name T1172
Test name
Test status
Simulation time 124703800 ps
CPU time 13.26 seconds
Started Jun 05 06:00:29 PM PDT 24
Finished Jun 05 06:00:43 PM PDT 24
Peak memory 260688 kb
Host smart-65d1325e-5222-4252-a594-76ff09147c2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192657484 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2192657484
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.702044589
Short name T1157
Test name
Test status
Simulation time 13048400 ps
CPU time 16.18 seconds
Started Jun 05 06:00:34 PM PDT 24
Finished Jun 05 06:00:51 PM PDT 24
Peak memory 260584 kb
Host smart-7fa1ae67-d723-4b56-b190-3251064709b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702044589 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.702044589
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.421280372
Short name T233
Test name
Test status
Simulation time 34402100 ps
CPU time 16.09 seconds
Started Jun 05 06:00:29 PM PDT 24
Finished Jun 05 06:00:46 PM PDT 24
Peak memory 264244 kb
Host smart-64b2cb75-f635-4520-82f9-1cd8735f0cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421280372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.421280372
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3753240237
Short name T346
Test name
Test status
Simulation time 2738847300 ps
CPU time 905.02 seconds
Started Jun 05 06:00:49 PM PDT 24
Finished Jun 05 06:15:55 PM PDT 24
Peak memory 264228 kb
Host smart-be9f7557-811a-4b6c-97b4-99bda3953eef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753240237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.3753240237
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3004014537
Short name T1239
Test name
Test status
Simulation time 15780300 ps
CPU time 13.42 seconds
Started Jun 05 06:01:06 PM PDT 24
Finished Jun 05 06:01:20 PM PDT 24
Peak memory 262656 kb
Host smart-1f7b1674-1449-48c7-be99-1c1de68cfeef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004014537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
3004014537
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1824828977
Short name T1113
Test name
Test status
Simulation time 53267000 ps
CPU time 13.88 seconds
Started Jun 05 06:00:42 PM PDT 24
Finished Jun 05 06:00:57 PM PDT 24
Peak memory 262868 kb
Host smart-52538e34-a673-4de1-ad7c-f337fffaa634
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824828977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
1824828977
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3362170941
Short name T1207
Test name
Test status
Simulation time 15188600 ps
CPU time 13.47 seconds
Started Jun 05 06:00:42 PM PDT 24
Finished Jun 05 06:00:56 PM PDT 24
Peak memory 262836 kb
Host smart-6d409867-063a-4bbe-9da3-23b3da17bc88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362170941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
3362170941
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2026517028
Short name T1222
Test name
Test status
Simulation time 15502400 ps
CPU time 13.3 seconds
Started Jun 05 06:00:49 PM PDT 24
Finished Jun 05 06:01:02 PM PDT 24
Peak memory 262740 kb
Host smart-ac4fe4d2-9038-44e9-a810-f6d0864cc98a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026517028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
2026517028
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.86489915
Short name T1204
Test name
Test status
Simulation time 28407600 ps
CPU time 13.63 seconds
Started Jun 05 06:00:46 PM PDT 24
Finished Jun 05 06:01:00 PM PDT 24
Peak memory 262780 kb
Host smart-39cf5d3e-99a3-414d-8b43-736c783e102d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86489915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.86489915
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3478702261
Short name T1206
Test name
Test status
Simulation time 48994600 ps
CPU time 13.49 seconds
Started Jun 05 06:00:42 PM PDT 24
Finished Jun 05 06:00:57 PM PDT 24
Peak memory 262760 kb
Host smart-f9e5f4ab-d670-4f26-9f8d-377d51df4d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478702261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
3478702261
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2080902760
Short name T257
Test name
Test status
Simulation time 102797900 ps
CPU time 13.59 seconds
Started Jun 05 06:00:54 PM PDT 24
Finished Jun 05 06:01:08 PM PDT 24
Peak memory 262740 kb
Host smart-c18749ec-6cc0-427c-bdac-32dd62e3dd8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080902760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
2080902760
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3803526677
Short name T1151
Test name
Test status
Simulation time 30222200 ps
CPU time 13.72 seconds
Started Jun 05 06:01:05 PM PDT 24
Finished Jun 05 06:01:19 PM PDT 24
Peak memory 262924 kb
Host smart-d6a9193d-4552-4fdc-b2ff-8ffd1132ce03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803526677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
3803526677
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1073796663
Short name T1208
Test name
Test status
Simulation time 16361300 ps
CPU time 13.42 seconds
Started Jun 05 06:01:06 PM PDT 24
Finished Jun 05 06:01:20 PM PDT 24
Peak memory 262932 kb
Host smart-0968865a-697a-422d-915f-1c0aa5192ef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073796663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
1073796663
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2966650225
Short name T1212
Test name
Test status
Simulation time 34069100 ps
CPU time 14.15 seconds
Started Jun 05 06:00:46 PM PDT 24
Finished Jun 05 06:01:01 PM PDT 24
Peak memory 262740 kb
Host smart-a6f03a63-1ae5-4c79-981c-a52c925296e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966650225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
2966650225
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3927284296
Short name T1128
Test name
Test status
Simulation time 1010969000 ps
CPU time 34.32 seconds
Started Jun 05 06:00:25 PM PDT 24
Finished Jun 05 06:01:00 PM PDT 24
Peak memory 260636 kb
Host smart-5ffda44d-5cf0-4d75-8f3d-f689c88e620f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927284296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.3927284296
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.5761918
Short name T1194
Test name
Test status
Simulation time 330829700 ps
CPU time 39.49 seconds
Started Jun 05 06:00:25 PM PDT 24
Finished Jun 05 06:01:05 PM PDT 24
Peak memory 263380 kb
Host smart-60f81ca3-e18f-4a84-856c-2fdcacc09686
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5761918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.flash_ctrl_csr_bit_bash.5761918
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3608228858
Short name T1224
Test name
Test status
Simulation time 37099800 ps
CPU time 31.07 seconds
Started Jun 05 06:00:33 PM PDT 24
Finished Jun 05 06:01:05 PM PDT 24
Peak memory 260644 kb
Host smart-81013eed-6ad7-4898-91da-2d36d1d04b18
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608228858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.3608228858
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.99694916
Short name T1184
Test name
Test status
Simulation time 99634300 ps
CPU time 16.9 seconds
Started Jun 05 06:00:24 PM PDT 24
Finished Jun 05 06:00:41 PM PDT 24
Peak memory 260528 kb
Host smart-58884223-c8ea-4bc5-b451-b675b7e38e4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99694916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_csr_rw.99694916
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1602804687
Short name T1174
Test name
Test status
Simulation time 15886100 ps
CPU time 13.62 seconds
Started Jun 05 06:00:24 PM PDT 24
Finished Jun 05 06:00:38 PM PDT 24
Peak memory 262660 kb
Host smart-981b1978-d960-4004-a50b-f0a43e7a4f3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602804687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.1
602804687
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3804644952
Short name T239
Test name
Test status
Simulation time 112705300 ps
CPU time 13.67 seconds
Started Jun 05 06:00:31 PM PDT 24
Finished Jun 05 06:00:46 PM PDT 24
Peak memory 264120 kb
Host smart-553a059c-e040-490a-acdc-b57dece2696a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804644952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.3804644952
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4126151821
Short name T1137
Test name
Test status
Simulation time 29060700 ps
CPU time 13.69 seconds
Started Jun 05 06:00:23 PM PDT 24
Finished Jun 05 06:00:37 PM PDT 24
Peak memory 262916 kb
Host smart-8e2736f4-5a26-4b32-84c9-ce342d67dc89
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126151821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.4126151821
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.708790708
Short name T1191
Test name
Test status
Simulation time 38132800 ps
CPU time 17.55 seconds
Started Jun 05 06:00:24 PM PDT 24
Finished Jun 05 06:00:42 PM PDT 24
Peak memory 260736 kb
Host smart-a7470714-db32-4ef9-bb6b-10832a0b489f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708790708 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.708790708
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3233112473
Short name T1160
Test name
Test status
Simulation time 15831000 ps
CPU time 16.11 seconds
Started Jun 05 06:00:23 PM PDT 24
Finished Jun 05 06:00:39 PM PDT 24
Peak memory 260568 kb
Host smart-244114ef-2119-4dcd-844e-abc366e12ac0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233112473 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.3233112473
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2738077163
Short name T1183
Test name
Test status
Simulation time 32071500 ps
CPU time 13 seconds
Started Jun 05 06:00:25 PM PDT 24
Finished Jun 05 06:00:39 PM PDT 24
Peak memory 260616 kb
Host smart-62a0ae09-6469-4a73-9ddc-0db0ef66cbdd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738077163 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.2738077163
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1471960597
Short name T1216
Test name
Test status
Simulation time 136824500 ps
CPU time 16.93 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:00:43 PM PDT 24
Peak memory 264244 kb
Host smart-f24f1472-3e73-49f8-a83b-8bb51e48e182
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471960597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1
471960597
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1901857029
Short name T343
Test name
Test status
Simulation time 361533300 ps
CPU time 381.98 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:06:48 PM PDT 24
Peak memory 260616 kb
Host smart-2293f468-db05-448f-afa7-b088b6bc85bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901857029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.1901857029
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.205447
Short name T1159
Test name
Test status
Simulation time 22774900 ps
CPU time 13.58 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:01:25 PM PDT 24
Peak memory 262788 kb
Host smart-41d0e371-7c83-4347-a6bd-defaa6900b84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.205447
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2530154609
Short name T1149
Test name
Test status
Simulation time 24711500 ps
CPU time 13.44 seconds
Started Jun 05 06:01:02 PM PDT 24
Finished Jun 05 06:01:17 PM PDT 24
Peak memory 262968 kb
Host smart-d3d54d31-e237-4381-be95-0d5de11cb1d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530154609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
2530154609
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2518024551
Short name T1246
Test name
Test status
Simulation time 27173900 ps
CPU time 13.53 seconds
Started Jun 05 06:00:42 PM PDT 24
Finished Jun 05 06:00:56 PM PDT 24
Peak memory 262692 kb
Host smart-c171d5fe-a193-4183-9b8d-ee8082da93fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518024551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
2518024551
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1061525606
Short name T1120
Test name
Test status
Simulation time 88163900 ps
CPU time 13.24 seconds
Started Jun 05 06:00:42 PM PDT 24
Finished Jun 05 06:00:57 PM PDT 24
Peak memory 262772 kb
Host smart-dac4773e-db28-4745-856c-eac44ca761b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061525606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
1061525606
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1870635464
Short name T1153
Test name
Test status
Simulation time 24518900 ps
CPU time 13.68 seconds
Started Jun 05 06:00:45 PM PDT 24
Finished Jun 05 06:00:59 PM PDT 24
Peak memory 262684 kb
Host smart-e2c30daf-3cdc-4bdc-9373-c094463b2405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870635464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
1870635464
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.177802022
Short name T1193
Test name
Test status
Simulation time 89796500 ps
CPU time 13.99 seconds
Started Jun 05 06:01:04 PM PDT 24
Finished Jun 05 06:01:19 PM PDT 24
Peak memory 262436 kb
Host smart-f36b668e-b7d8-42d1-a813-81acfc0a463d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177802022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.177802022
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1917777881
Short name T1211
Test name
Test status
Simulation time 30124600 ps
CPU time 13.9 seconds
Started Jun 05 06:00:57 PM PDT 24
Finished Jun 05 06:01:11 PM PDT 24
Peak memory 262800 kb
Host smart-7c46bcb0-7c5d-4ec8-84e2-aecd83fae3a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917777881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
1917777881
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3431439714
Short name T1220
Test name
Test status
Simulation time 18835900 ps
CPU time 13.81 seconds
Started Jun 05 06:00:44 PM PDT 24
Finished Jun 05 06:00:59 PM PDT 24
Peak memory 261944 kb
Host smart-b782f4f1-a437-47be-bfa8-bc2930ca4d85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431439714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
3431439714
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.507460503
Short name T1139
Test name
Test status
Simulation time 217591400 ps
CPU time 13.58 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:01:25 PM PDT 24
Peak memory 262808 kb
Host smart-ffdc0518-5f4f-4bef-adf8-8b076df0f85f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507460503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.507460503
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3799904481
Short name T1240
Test name
Test status
Simulation time 17562000 ps
CPU time 13.82 seconds
Started Jun 05 06:01:08 PM PDT 24
Finished Jun 05 06:01:23 PM PDT 24
Peak memory 262908 kb
Host smart-b7ce2f8a-dc95-4d7e-abb7-5816aab5f924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799904481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
3799904481
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1025205763
Short name T1145
Test name
Test status
Simulation time 3957925200 ps
CPU time 41.19 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:01:08 PM PDT 24
Peak memory 260664 kb
Host smart-2581d2bc-45ce-4781-9c9f-a48ca63ff841
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025205763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.1025205763
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1804702389
Short name T1235
Test name
Test status
Simulation time 5489805100 ps
CPU time 74.42 seconds
Started Jun 05 06:00:42 PM PDT 24
Finished Jun 05 06:01:57 PM PDT 24
Peak memory 260524 kb
Host smart-f2a0b25a-adaf-4aca-af70-9b64f29c6ab4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804702389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.1804702389
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3954430504
Short name T1115
Test name
Test status
Simulation time 26352900 ps
CPU time 31.56 seconds
Started Jun 05 06:00:30 PM PDT 24
Finished Jun 05 06:01:03 PM PDT 24
Peak memory 260560 kb
Host smart-ddaabb15-6af7-42a1-bddc-c50e439cefd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954430504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.3954430504
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.374922816
Short name T1166
Test name
Test status
Simulation time 48408900 ps
CPU time 17.51 seconds
Started Jun 05 06:00:29 PM PDT 24
Finished Jun 05 06:00:48 PM PDT 24
Peak memory 270956 kb
Host smart-8958c028-0a1e-4905-a16a-f1e8ba805685
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374922816 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.374922816
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4189732691
Short name T1238
Test name
Test status
Simulation time 65547400 ps
CPU time 16.51 seconds
Started Jun 05 06:00:23 PM PDT 24
Finished Jun 05 06:00:40 PM PDT 24
Peak memory 264160 kb
Host smart-051842f5-4f97-4eee-a41c-aa3e0e940690
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189732691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.4189732691
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1635808398
Short name T317
Test name
Test status
Simulation time 55210800 ps
CPU time 13.91 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:00:41 PM PDT 24
Peak memory 262960 kb
Host smart-ed49ec13-b63b-4ef3-8817-f0f3cbb39e16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635808398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.1
635808398
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.488507898
Short name T238
Test name
Test status
Simulation time 16384400 ps
CPU time 13.51 seconds
Started Jun 05 06:00:39 PM PDT 24
Finished Jun 05 06:00:53 PM PDT 24
Peak memory 263908 kb
Host smart-3f63cc18-6b7f-4a39-89e4-f4f449ceabd9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488507898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_mem_partial_access.488507898
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.84593693
Short name T1108
Test name
Test status
Simulation time 50284500 ps
CPU time 13.31 seconds
Started Jun 05 06:00:24 PM PDT 24
Finished Jun 05 06:00:38 PM PDT 24
Peak memory 262976 kb
Host smart-ddee74ee-dea3-4fad-8064-71e605f4ef36
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84593693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_
walk.84593693
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.917534577
Short name T249
Test name
Test status
Simulation time 235984000 ps
CPU time 28.77 seconds
Started Jun 05 06:00:34 PM PDT 24
Finished Jun 05 06:01:04 PM PDT 24
Peak memory 260632 kb
Host smart-129f0c98-3da7-4e30-9138-66fd160e01c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917534577 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.917534577
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.4126135025
Short name T1245
Test name
Test status
Simulation time 35339800 ps
CPU time 15.88 seconds
Started Jun 05 06:00:24 PM PDT 24
Finished Jun 05 06:00:41 PM PDT 24
Peak memory 260792 kb
Host smart-a27d8c90-e89e-4b77-a32a-4c59a83bab0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126135025 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.4126135025
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1245912739
Short name T1202
Test name
Test status
Simulation time 21444800 ps
CPU time 13.29 seconds
Started Jun 05 06:00:28 PM PDT 24
Finished Jun 05 06:00:42 PM PDT 24
Peak memory 260552 kb
Host smart-353ed954-6513-4949-91b7-872189d94557
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245912739 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.1245912739
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.645772622
Short name T217
Test name
Test status
Simulation time 44601500 ps
CPU time 17.07 seconds
Started Jun 05 06:00:36 PM PDT 24
Finished Jun 05 06:00:54 PM PDT 24
Peak memory 264268 kb
Host smart-aebf7068-4c7c-4536-a02c-a82ac49332af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645772622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.645772622
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.2370294182
Short name T186
Test name
Test status
Simulation time 568598200 ps
CPU time 383.89 seconds
Started Jun 05 06:00:35 PM PDT 24
Finished Jun 05 06:06:59 PM PDT 24
Peak memory 261816 kb
Host smart-35db511e-80fd-4d0a-a168-69a15dc700ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370294182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.2370294182
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2846751033
Short name T313
Test name
Test status
Simulation time 15534700 ps
CPU time 13.48 seconds
Started Jun 05 06:01:09 PM PDT 24
Finished Jun 05 06:01:24 PM PDT 24
Peak memory 263000 kb
Host smart-8024e835-ad35-4559-9d5f-0cfbb8768932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846751033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
2846751033
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2476183083
Short name T1147
Test name
Test status
Simulation time 18291300 ps
CPU time 13.28 seconds
Started Jun 05 06:01:08 PM PDT 24
Finished Jun 05 06:01:22 PM PDT 24
Peak memory 263008 kb
Host smart-e0862da8-0798-4681-9c28-b7164ae4bf23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476183083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
2476183083
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3874513677
Short name T1180
Test name
Test status
Simulation time 31690500 ps
CPU time 13.23 seconds
Started Jun 05 06:00:46 PM PDT 24
Finished Jun 05 06:00:59 PM PDT 24
Peak memory 262888 kb
Host smart-c8c87f1a-b394-4002-ac14-395d0a41c263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874513677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
3874513677
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.2006101522
Short name T1152
Test name
Test status
Simulation time 79119900 ps
CPU time 13.68 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:01:26 PM PDT 24
Peak memory 262776 kb
Host smart-a096d5cb-14e6-43c7-995e-1fea1d4b031f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006101522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
2006101522
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.89739670
Short name T1127
Test name
Test status
Simulation time 18422000 ps
CPU time 13.51 seconds
Started Jun 05 06:00:48 PM PDT 24
Finished Jun 05 06:01:02 PM PDT 24
Peak memory 262780 kb
Host smart-42a5b5af-ae9f-4cde-a98a-c38d1a1f8a30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89739670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.89739670
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.746228159
Short name T1196
Test name
Test status
Simulation time 26163300 ps
CPU time 13.44 seconds
Started Jun 05 06:00:49 PM PDT 24
Finished Jun 05 06:01:03 PM PDT 24
Peak memory 262912 kb
Host smart-776610c9-51f3-4384-9494-589adb249229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746228159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.746228159
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.596416501
Short name T1197
Test name
Test status
Simulation time 17307600 ps
CPU time 13.58 seconds
Started Jun 05 06:01:09 PM PDT 24
Finished Jun 05 06:01:23 PM PDT 24
Peak memory 262672 kb
Host smart-e0dd3195-d6be-4d23-9013-6f7b3a7fdb3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596416501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.596416501
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1129299934
Short name T1121
Test name
Test status
Simulation time 141028100 ps
CPU time 13.7 seconds
Started Jun 05 06:00:59 PM PDT 24
Finished Jun 05 06:01:13 PM PDT 24
Peak memory 262616 kb
Host smart-16a605b1-ced6-492e-8d37-309c0b7715ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129299934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
1129299934
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.301568108
Short name T1231
Test name
Test status
Simulation time 200045400 ps
CPU time 13.64 seconds
Started Jun 05 06:01:13 PM PDT 24
Finished Jun 05 06:01:27 PM PDT 24
Peak memory 262832 kb
Host smart-e856e71d-d8c0-42ad-98f5-c556bf20c02a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301568108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.301568108
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.363052315
Short name T1192
Test name
Test status
Simulation time 49804300 ps
CPU time 17.22 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:00:44 PM PDT 24
Peak memory 264248 kb
Host smart-b8ed0e11-1613-4e0f-b0c8-cd97bb93ae30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363052315 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.363052315
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3980578183
Short name T1177
Test name
Test status
Simulation time 19502500 ps
CPU time 16.53 seconds
Started Jun 05 06:00:26 PM PDT 24
Finished Jun 05 06:00:44 PM PDT 24
Peak memory 260632 kb
Host smart-1f0c3095-736e-4810-b107-d1296f8c0c24
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980578183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.3980578183
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.107473707
Short name T1135
Test name
Test status
Simulation time 28650800 ps
CPU time 13.76 seconds
Started Jun 05 06:00:55 PM PDT 24
Finished Jun 05 06:01:09 PM PDT 24
Peak memory 262384 kb
Host smart-550f5836-d97f-48d0-b6f9-a5b5e3955b99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107473707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.107473707
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3978402664
Short name T303
Test name
Test status
Simulation time 112510600 ps
CPU time 16.3 seconds
Started Jun 05 06:00:31 PM PDT 24
Finished Jun 05 06:00:48 PM PDT 24
Peak memory 260736 kb
Host smart-b731c868-d21d-4b6f-b444-215c31d6c3c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978402664 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.3978402664
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3046506845
Short name T1107
Test name
Test status
Simulation time 12584300 ps
CPU time 15.6 seconds
Started Jun 05 06:00:36 PM PDT 24
Finished Jun 05 06:00:52 PM PDT 24
Peak memory 260648 kb
Host smart-843c41ac-012d-455f-916b-177c1a8070c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046506845 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.3046506845
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1699810113
Short name T1105
Test name
Test status
Simulation time 55758500 ps
CPU time 13.25 seconds
Started Jun 05 06:00:30 PM PDT 24
Finished Jun 05 06:00:44 PM PDT 24
Peak memory 260620 kb
Host smart-3aaede1a-2252-4036-a135-35b77c6ab082
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699810113 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.1699810113
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3028796271
Short name T255
Test name
Test status
Simulation time 47136300 ps
CPU time 15.23 seconds
Started Jun 05 06:00:24 PM PDT 24
Finished Jun 05 06:00:40 PM PDT 24
Peak memory 264144 kb
Host smart-fee91ae2-915b-4de6-9420-1e28ec936478
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028796271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.3
028796271
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2492999592
Short name T345
Test name
Test status
Simulation time 339188700 ps
CPU time 909.73 seconds
Started Jun 05 06:00:28 PM PDT 24
Finished Jun 05 06:15:39 PM PDT 24
Peak memory 260980 kb
Host smart-7f8fc74b-13ef-44f8-9330-06a35f5361d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492999592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.2492999592
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.297670839
Short name T1186
Test name
Test status
Simulation time 40635000 ps
CPU time 16.57 seconds
Started Jun 05 06:00:54 PM PDT 24
Finished Jun 05 06:01:11 PM PDT 24
Peak memory 272376 kb
Host smart-06faf83b-0807-4a14-8c32-560556ed974a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297670839 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.297670839
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2586262498
Short name T71
Test name
Test status
Simulation time 56207200 ps
CPU time 17.31 seconds
Started Jun 05 06:00:31 PM PDT 24
Finished Jun 05 06:00:49 PM PDT 24
Peak memory 260500 kb
Host smart-f830a68b-b8f3-4e2f-9fc2-a1402ed9a9ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586262498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.2586262498
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1962572498
Short name T1230
Test name
Test status
Simulation time 15046200 ps
CPU time 13.53 seconds
Started Jun 05 06:00:28 PM PDT 24
Finished Jun 05 06:00:43 PM PDT 24
Peak memory 262948 kb
Host smart-5bf70483-311d-418c-a38d-7fd25df767a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962572498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.1
962572498
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.141202434
Short name T302
Test name
Test status
Simulation time 853784400 ps
CPU time 35.61 seconds
Started Jun 05 06:00:27 PM PDT 24
Finished Jun 05 06:01:03 PM PDT 24
Peak memory 260736 kb
Host smart-d0c26feb-9adc-4181-b90e-ddcb04c70f4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141202434 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.141202434
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3487475816
Short name T1134
Test name
Test status
Simulation time 58417900 ps
CPU time 13.14 seconds
Started Jun 05 06:00:33 PM PDT 24
Finished Jun 05 06:00:47 PM PDT 24
Peak memory 260676 kb
Host smart-f89eef9a-8434-4614-8cc1-a1f61e9c2e37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487475816 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.3487475816
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2783150607
Short name T1201
Test name
Test status
Simulation time 21454000 ps
CPU time 15.83 seconds
Started Jun 05 06:00:38 PM PDT 24
Finished Jun 05 06:00:54 PM PDT 24
Peak memory 260648 kb
Host smart-d59aff73-8ff4-42a6-95f5-890fecbda0fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783150607 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.2783150607
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2208557653
Short name T254
Test name
Test status
Simulation time 61008700 ps
CPU time 19.47 seconds
Started Jun 05 06:00:48 PM PDT 24
Finished Jun 05 06:01:09 PM PDT 24
Peak memory 264248 kb
Host smart-31e58de3-9978-46f9-b96e-4b35cf8678e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208557653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.2
208557653
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2148642500
Short name T1190
Test name
Test status
Simulation time 85814200 ps
CPU time 16.63 seconds
Started Jun 05 06:00:33 PM PDT 24
Finished Jun 05 06:00:51 PM PDT 24
Peak memory 271084 kb
Host smart-167429bc-e722-4581-8d88-e9db51f7a418
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148642500 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.2148642500
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1656463372
Short name T1132
Test name
Test status
Simulation time 37044300 ps
CPU time 16.04 seconds
Started Jun 05 06:00:25 PM PDT 24
Finished Jun 05 06:00:42 PM PDT 24
Peak memory 260792 kb
Host smart-f4ece7dd-5335-4b99-9288-46b1f0e82d2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656463372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.1656463372
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2636999906
Short name T258
Test name
Test status
Simulation time 60860300 ps
CPU time 13.67 seconds
Started Jun 05 06:00:28 PM PDT 24
Finished Jun 05 06:00:43 PM PDT 24
Peak memory 262748 kb
Host smart-b87a6889-3fc0-4313-9926-22403b5344b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636999906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.2
636999906
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2210148032
Short name T1213
Test name
Test status
Simulation time 2185886500 ps
CPU time 19.28 seconds
Started Jun 05 06:00:43 PM PDT 24
Finished Jun 05 06:01:03 PM PDT 24
Peak memory 262896 kb
Host smart-fbd2c7a5-ef67-4b76-84ce-0d0ed20143f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210148032 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.2210148032
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2672471813
Short name T1112
Test name
Test status
Simulation time 55474400 ps
CPU time 15.74 seconds
Started Jun 05 06:00:47 PM PDT 24
Finished Jun 05 06:01:04 PM PDT 24
Peak memory 260688 kb
Host smart-54c1dea5-dfaf-4485-a191-9bc1d04a46ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672471813 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.2672471813
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2273288585
Short name T1248
Test name
Test status
Simulation time 14526500 ps
CPU time 13.22 seconds
Started Jun 05 06:00:44 PM PDT 24
Finished Jun 05 06:00:58 PM PDT 24
Peak memory 260636 kb
Host smart-25825c47-8920-40bb-a6f0-b375d5b8f2e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273288585 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.2273288585
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3808883062
Short name T234
Test name
Test status
Simulation time 55605200 ps
CPU time 19.11 seconds
Started Jun 05 06:00:47 PM PDT 24
Finished Jun 05 06:01:07 PM PDT 24
Peak memory 264228 kb
Host smart-a4b668e5-211a-43b0-a6e8-8776fb48c440
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808883062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.3
808883062
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.739502522
Short name T1123
Test name
Test status
Simulation time 276458800 ps
CPU time 19.25 seconds
Started Jun 05 06:00:34 PM PDT 24
Finished Jun 05 06:00:54 PM PDT 24
Peak memory 272384 kb
Host smart-acddcb2d-87d7-4f12-baf0-5d9f91542868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739502522 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.739502522
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2521419893
Short name T1189
Test name
Test status
Simulation time 134320300 ps
CPU time 17.78 seconds
Started Jun 05 06:00:34 PM PDT 24
Finished Jun 05 06:00:52 PM PDT 24
Peak memory 260572 kb
Host smart-9aa803c6-fc1d-4b8a-9369-29c6df4df1b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521419893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.2521419893
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3103308044
Short name T1136
Test name
Test status
Simulation time 40926700 ps
CPU time 13.64 seconds
Started Jun 05 06:00:35 PM PDT 24
Finished Jun 05 06:00:49 PM PDT 24
Peak memory 262868 kb
Host smart-141db857-31db-4a0d-91a1-85a10b143227
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103308044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.3
103308044
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.230114384
Short name T1219
Test name
Test status
Simulation time 114816400 ps
CPU time 17.1 seconds
Started Jun 05 06:00:50 PM PDT 24
Finished Jun 05 06:01:08 PM PDT 24
Peak memory 260716 kb
Host smart-3cdc3e29-5ea2-47a3-bb50-5e67d24e22b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230114384 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.230114384
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2201765644
Short name T1217
Test name
Test status
Simulation time 11328500 ps
CPU time 15.92 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:01:10 PM PDT 24
Peak memory 260512 kb
Host smart-e22c6aca-b97e-441a-a269-e7a895472f28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201765644 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.2201765644
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1207511715
Short name T1142
Test name
Test status
Simulation time 35677700 ps
CPU time 16.03 seconds
Started Jun 05 06:00:41 PM PDT 24
Finished Jun 05 06:00:58 PM PDT 24
Peak memory 260648 kb
Host smart-b6c5f2d1-0d43-4d02-a49c-d46f6474b50a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207511715 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.1207511715
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1829449031
Short name T256
Test name
Test status
Simulation time 35280500 ps
CPU time 16.67 seconds
Started Jun 05 06:00:54 PM PDT 24
Finished Jun 05 06:01:11 PM PDT 24
Peak memory 264264 kb
Host smart-41a7406e-0693-4d1a-a94b-2b08032c730f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829449031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.1
829449031
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1501275542
Short name T351
Test name
Test status
Simulation time 1488376500 ps
CPU time 451.4 seconds
Started Jun 05 06:00:36 PM PDT 24
Finished Jun 05 06:08:08 PM PDT 24
Peak memory 264188 kb
Host smart-9114b234-431f-4d2e-9d85-01bf4f5bd80f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501275542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.1501275542
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1346210165
Short name T1209
Test name
Test status
Simulation time 65343900 ps
CPU time 17.44 seconds
Started Jun 05 06:00:32 PM PDT 24
Finished Jun 05 06:00:50 PM PDT 24
Peak memory 260600 kb
Host smart-2ab2229a-b2f3-4c92-b8b8-9e430cea0f1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346210165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.1346210165
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.688725508
Short name T259
Test name
Test status
Simulation time 29253800 ps
CPU time 13.46 seconds
Started Jun 05 06:00:40 PM PDT 24
Finished Jun 05 06:00:54 PM PDT 24
Peak memory 262784 kb
Host smart-994955fa-5a93-42f8-88b4-7d07fcd79ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688725508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.688725508
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2083419675
Short name T1227
Test name
Test status
Simulation time 324920500 ps
CPU time 18.01 seconds
Started Jun 05 06:00:30 PM PDT 24
Finished Jun 05 06:00:50 PM PDT 24
Peak memory 260692 kb
Host smart-8a27ca92-4f54-4d4d-986a-b56a726a3d5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083419675 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.2083419675
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3072899637
Short name T1229
Test name
Test status
Simulation time 21576900 ps
CPU time 15.47 seconds
Started Jun 05 06:00:43 PM PDT 24
Finished Jun 05 06:00:59 PM PDT 24
Peak memory 260640 kb
Host smart-00ea2a95-fb03-4c99-9b0f-efa8b94fa8ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072899637 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.3072899637
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2531100244
Short name T1195
Test name
Test status
Simulation time 31799300 ps
CPU time 16.06 seconds
Started Jun 05 06:00:57 PM PDT 24
Finished Jun 05 06:01:14 PM PDT 24
Peak memory 260548 kb
Host smart-1b67faaf-df09-45d1-a96b-babab8fe2e92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531100244 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.2531100244
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.49372744
Short name T1226
Test name
Test status
Simulation time 113168800 ps
CPU time 16.64 seconds
Started Jun 05 06:00:52 PM PDT 24
Finished Jun 05 06:01:09 PM PDT 24
Peak memory 264224 kb
Host smart-f8ba7d8d-1727-4ce6-8fe1-4e3508a446e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49372744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.49372744
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3042206102
Short name T1182
Test name
Test status
Simulation time 347842500 ps
CPU time 458.69 seconds
Started Jun 05 06:00:33 PM PDT 24
Finished Jun 05 06:08:13 PM PDT 24
Peak memory 260584 kb
Host smart-0ce96679-4c43-4392-b6b4-34482e167a92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042206102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.3042206102
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.3247153844
Short name T865
Test name
Test status
Simulation time 205212600 ps
CPU time 13.92 seconds
Started Jun 05 06:00:52 PM PDT 24
Finished Jun 05 06:01:07 PM PDT 24
Peak memory 257856 kb
Host smart-66cbae1b-76c0-4e10-9f01-769f4b1acac9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247153844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.3
247153844
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.1211141402
Short name T601
Test name
Test status
Simulation time 31680200 ps
CPU time 15.29 seconds
Started Jun 05 06:01:12 PM PDT 24
Finished Jun 05 06:01:28 PM PDT 24
Peak memory 275544 kb
Host smart-20049840-0408-4d6f-8a2d-49a1453a9119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211141402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.1211141402
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.1670967573
Short name T1053
Test name
Test status
Simulation time 123646500 ps
CPU time 104.67 seconds
Started Jun 05 06:01:04 PM PDT 24
Finished Jun 05 06:02:50 PM PDT 24
Peak memory 280412 kb
Host smart-62268a07-6b14-4f1f-a69b-14b5aa33e8cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670967573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.1670967573
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.808256193
Short name T44
Test name
Test status
Simulation time 32518600 ps
CPU time 22.09 seconds
Started Jun 05 06:00:51 PM PDT 24
Finished Jun 05 06:01:14 PM PDT 24
Peak memory 273184 kb
Host smart-6402203b-e4ee-4f29-a9b3-b837b2d47158
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808256193 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.808256193
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.3471678661
Short name T127
Test name
Test status
Simulation time 90548400 ps
CPU time 235.9 seconds
Started Jun 05 06:01:10 PM PDT 24
Finished Jun 05 06:05:07 PM PDT 24
Peak memory 262844 kb
Host smart-63200342-0230-4df0-92d5-c6e0ebcd4ed1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471678661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.3471678661
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.1606488532
Short name T946
Test name
Test status
Simulation time 912773700 ps
CPU time 2201.12 seconds
Started Jun 05 06:00:48 PM PDT 24
Finished Jun 05 06:37:30 PM PDT 24
Peak memory 264744 kb
Host smart-16a26264-eec7-475a-ae21-face1944dae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606488532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.1606488532
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.1925143149
Short name T1047
Test name
Test status
Simulation time 2756239800 ps
CPU time 789.3 seconds
Started Jun 05 06:01:12 PM PDT 24
Finished Jun 05 06:14:22 PM PDT 24
Peak memory 273040 kb
Host smart-3a7cd817-842c-462a-a362-d654010c190d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925143149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.1925143149
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.3556981305
Short name T1000
Test name
Test status
Simulation time 271939419900 ps
CPU time 3708.39 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 07:02:42 PM PDT 24
Peak memory 264892 kb
Host smart-638136c3-a7ab-4c45-b31a-bb1163229771
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556981305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.3556981305
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.1786174259
Short name T1024
Test name
Test status
Simulation time 15675700 ps
CPU time 14.04 seconds
Started Jun 05 06:01:12 PM PDT 24
Finished Jun 05 06:01:27 PM PDT 24
Peak memory 257888 kb
Host smart-bfa870d6-82ad-4911-bb04-b74bc920d650
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786174259 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.1786174259
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.279495255
Short name T1043
Test name
Test status
Simulation time 1023845795700 ps
CPU time 2531.16 seconds
Started Jun 05 06:00:47 PM PDT 24
Finished Jun 05 06:42:59 PM PDT 24
Peak memory 264120 kb
Host smart-04248515-5805-475c-a550-a5feab258c76
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279495255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_hw_rma.279495255
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.3265956589
Short name T801
Test name
Test status
Simulation time 320278669700 ps
CPU time 1078.16 seconds
Started Jun 05 06:01:05 PM PDT 24
Finished Jun 05 06:19:04 PM PDT 24
Peak memory 263176 kb
Host smart-708708b2-8726-414f-9116-4831e830269e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265956589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.3265956589
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.2855391368
Short name T633
Test name
Test status
Simulation time 4810122300 ps
CPU time 40.66 seconds
Started Jun 05 06:01:06 PM PDT 24
Finished Jun 05 06:01:48 PM PDT 24
Peak memory 261772 kb
Host smart-5b5e8856-fe18-4ec4-991b-4fd9cd67b574
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855391368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.2855391368
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.3234341676
Short name T737
Test name
Test status
Simulation time 4681885300 ps
CPU time 605.21 seconds
Started Jun 05 06:01:06 PM PDT 24
Finished Jun 05 06:11:12 PM PDT 24
Peak memory 314048 kb
Host smart-df52fc3a-82b1-46fb-a20a-55a705480bc4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234341676 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_integrity.3234341676
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.3793149004
Short name T869
Test name
Test status
Simulation time 3228171500 ps
CPU time 215.7 seconds
Started Jun 05 06:01:05 PM PDT 24
Finished Jun 05 06:04:42 PM PDT 24
Peak memory 283552 kb
Host smart-d7c3de03-f75d-4258-a3ba-481c2cb9ce38
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793149004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_intr_rd.3793149004
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.3468067382
Short name T694
Test name
Test status
Simulation time 22554077500 ps
CPU time 325.22 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:06:37 PM PDT 24
Peak memory 292960 kb
Host smart-deb2acc1-8b63-458f-b057-7b636b21e82e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468067382 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.3468067382
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.1516849979
Short name T1079
Test name
Test status
Simulation time 4313398600 ps
CPU time 65.26 seconds
Started Jun 05 06:00:47 PM PDT 24
Finished Jun 05 06:01:53 PM PDT 24
Peak memory 259748 kb
Host smart-ab7542bc-e0c6-440e-979f-44379a9849de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516849979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.1516849979
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.3306259335
Short name T891
Test name
Test status
Simulation time 23912046800 ps
CPU time 203.65 seconds
Started Jun 05 06:01:03 PM PDT 24
Finished Jun 05 06:04:28 PM PDT 24
Peak memory 260072 kb
Host smart-be9de74f-393b-4a02-8521-a9187b6419fb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330
6259335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.3306259335
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.2092469841
Short name T902
Test name
Test status
Simulation time 45400100 ps
CPU time 13.33 seconds
Started Jun 05 06:00:56 PM PDT 24
Finished Jun 05 06:01:10 PM PDT 24
Peak memory 259244 kb
Host smart-8730b637-b6d7-4cd8-8953-5e939fe2cebb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092469841 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.2092469841
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.627577278
Short name T554
Test name
Test status
Simulation time 20728124300 ps
CPU time 142.46 seconds
Started Jun 05 06:00:51 PM PDT 24
Finished Jun 05 06:03:14 PM PDT 24
Peak memory 264908 kb
Host smart-a02d1a55-3e5e-45fb-85de-d69bed6d1b26
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627577278 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_mp_regions.627577278
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.4201652674
Short name T463
Test name
Test status
Simulation time 977909000 ps
CPU time 160.66 seconds
Started Jun 05 06:01:06 PM PDT 24
Finished Jun 05 06:03:48 PM PDT 24
Peak memory 281244 kb
Host smart-aab990b0-d1c6-4f89-a6f8-e05a6a264ad9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201652674 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.4201652674
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.188926661
Short name T501
Test name
Test status
Simulation time 78030300 ps
CPU time 287.83 seconds
Started Jun 05 06:01:05 PM PDT 24
Finished Jun 05 06:05:53 PM PDT 24
Peak memory 262200 kb
Host smart-7e73b011-e101-4e27-b924-6c33dad6738e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188926661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.188926661
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.3642740440
Short name T639
Test name
Test status
Simulation time 33316500 ps
CPU time 14.06 seconds
Started Jun 05 06:00:57 PM PDT 24
Finished Jun 05 06:01:11 PM PDT 24
Peak memory 264824 kb
Host smart-c4d3e770-0adb-4113-8721-58b723aa22f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642740440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.3642740440
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.3364342419
Short name T687
Test name
Test status
Simulation time 2957063600 ps
CPU time 449.57 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:08:23 PM PDT 24
Peak memory 282588 kb
Host smart-fbb6e111-c9c3-4616-8dd7-605966c3e282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364342419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3364342419
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.795529951
Short name T708
Test name
Test status
Simulation time 9188806100 ps
CPU time 123.79 seconds
Started Jun 05 06:00:52 PM PDT 24
Finished Jun 05 06:02:56 PM PDT 24
Peak memory 264964 kb
Host smart-77df5ac7-7e2e-4a29-944d-be175f9a4ffa
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=795529951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.795529951
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.4210687582
Short name T866
Test name
Test status
Simulation time 79360500 ps
CPU time 31.75 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:01:44 PM PDT 24
Peak memory 279116 kb
Host smart-45797baa-64f4-48a2-825e-e63398f64c96
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210687582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.4210687582
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.2721945000
Short name T466
Test name
Test status
Simulation time 153584400 ps
CPU time 45.99 seconds
Started Jun 05 06:01:02 PM PDT 24
Finished Jun 05 06:01:49 PM PDT 24
Peak memory 274140 kb
Host smart-c6698a2f-7464-4b88-9aea-5f2999a2455e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721945000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.2721945000
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.808621116
Short name T795
Test name
Test status
Simulation time 441654100 ps
CPU time 34.11 seconds
Started Jun 05 06:01:20 PM PDT 24
Finished Jun 05 06:01:54 PM PDT 24
Peak memory 273112 kb
Host smart-977425c4-ded4-4f94-a63c-447b95461b8b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808621116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_re_evict.808621116
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.4274567546
Short name T506
Test name
Test status
Simulation time 36681800 ps
CPU time 13.45 seconds
Started Jun 05 06:01:07 PM PDT 24
Finished Jun 05 06:01:21 PM PDT 24
Peak memory 257752 kb
Host smart-62ae4171-9a83-47e2-b5ad-b424aa093be8
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=4274567546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.4274567546
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.2726204832
Short name T165
Test name
Test status
Simulation time 200082200 ps
CPU time 21.42 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:01:16 PM PDT 24
Peak memory 264888 kb
Host smart-824df13c-7299-45c6-b245-755551bfb565
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726204832 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.2726204832
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.2577083392
Short name T159
Test name
Test status
Simulation time 84167636000 ps
CPU time 899.85 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:15:54 PM PDT 24
Peak memory 259092 kb
Host smart-0538aacf-d831-471d-b07b-3f4a5f8ababf
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577083392 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.2577083392
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.3390950182
Short name T410
Test name
Test status
Simulation time 545224900 ps
CPU time 111.64 seconds
Started Jun 05 06:01:10 PM PDT 24
Finished Jun 05 06:03:02 PM PDT 24
Peak memory 281276 kb
Host smart-22e5ff2b-3dde-40bc-ac5a-61a481d8e66e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390950182 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.3390950182
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.2414095923
Short name T806
Test name
Test status
Simulation time 1348506700 ps
CPU time 128.68 seconds
Started Jun 05 06:00:58 PM PDT 24
Finished Jun 05 06:03:07 PM PDT 24
Peak memory 294040 kb
Host smart-557b864f-b5b0-4ac6-a125-e2a16d301a21
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414095923 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.2414095923
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.2883466360
Short name T998
Test name
Test status
Simulation time 40977245600 ps
CPU time 595.24 seconds
Started Jun 05 06:00:49 PM PDT 24
Finished Jun 05 06:10:45 PM PDT 24
Peak memory 309080 kb
Host smart-9db9234f-fb26-4ef5-8c6a-7708e4e001df
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883466360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.2883466360
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.46828131
Short name T41
Test name
Test status
Simulation time 79226400 ps
CPU time 31.87 seconds
Started Jun 05 06:00:48 PM PDT 24
Finished Jun 05 06:01:21 PM PDT 24
Peak memory 274432 kb
Host smart-40446e40-2940-401e-9d00-83eb1b9f7bb0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46828131 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.46828131
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.3521206368
Short name T200
Test name
Test status
Simulation time 36318171100 ps
CPU time 658.61 seconds
Started Jun 05 06:00:52 PM PDT 24
Finished Jun 05 06:11:51 PM PDT 24
Peak memory 312172 kb
Host smart-3adb3d63-e9bb-4197-bda5-87ddf72cb528
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521206368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_s
err.3521206368
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.64333679
Short name T473
Test name
Test status
Simulation time 3405086400 ps
CPU time 79.36 seconds
Started Jun 05 06:00:53 PM PDT 24
Finished Jun 05 06:02:12 PM PDT 24
Peak memory 273032 kb
Host smart-97c61067-875b-44ba-a928-15257442bfac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64333679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_serr_address.64333679
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.2562110883
Short name T648
Test name
Test status
Simulation time 514940600 ps
CPU time 55.92 seconds
Started Jun 05 06:01:05 PM PDT 24
Finished Jun 05 06:02:01 PM PDT 24
Peak memory 273208 kb
Host smart-ce0930fa-f025-4acb-adb0-64fccb5ff82f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562110883 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.2562110883
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.2692353427
Short name T621
Test name
Test status
Simulation time 37664900 ps
CPU time 99.13 seconds
Started Jun 05 06:01:08 PM PDT 24
Finished Jun 05 06:02:48 PM PDT 24
Peak memory 275436 kb
Host smart-0a688801-0f8e-4eb0-a709-f88ee331e1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692353427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2692353427
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.2175987622
Short name T417
Test name
Test status
Simulation time 58554900 ps
CPU time 23.94 seconds
Started Jun 05 06:00:44 PM PDT 24
Finished Jun 05 06:01:09 PM PDT 24
Peak memory 258868 kb
Host smart-668f7b91-522e-4767-8d69-aa9dbba49d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175987622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.2175987622
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.3641760069
Short name T1084
Test name
Test status
Simulation time 176421200 ps
CPU time 880.42 seconds
Started Jun 05 06:00:51 PM PDT 24
Finished Jun 05 06:15:32 PM PDT 24
Peak memory 289584 kb
Host smart-1642787b-33b9-44a5-82b0-8bbe41b25856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641760069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.3641760069
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.4122236535
Short name T42
Test name
Test status
Simulation time 54765100 ps
CPU time 26.42 seconds
Started Jun 05 06:00:58 PM PDT 24
Finished Jun 05 06:01:25 PM PDT 24
Peak memory 261428 kb
Host smart-cf100cef-fbfa-47a8-9a37-ac43bee6d83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122236535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.4122236535
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.1747985203
Short name T705
Test name
Test status
Simulation time 3854010100 ps
CPU time 142.43 seconds
Started Jun 05 06:00:51 PM PDT 24
Finished Jun 05 06:03:14 PM PDT 24
Peak memory 259180 kb
Host smart-db18a78e-d6b4-48ac-a6ea-459b7959daa0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747985203 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_wo.1747985203
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.1178566972
Short name T8
Test name
Test status
Simulation time 45403900 ps
CPU time 14.97 seconds
Started Jun 05 06:01:10 PM PDT 24
Finished Jun 05 06:01:26 PM PDT 24
Peak memory 259420 kb
Host smart-fad022cc-a315-4cda-9e22-c5f423fbe5a3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178566972 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.1178566972
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.3722438505
Short name T472
Test name
Test status
Simulation time 62135100 ps
CPU time 15.55 seconds
Started Jun 05 06:00:48 PM PDT 24
Finished Jun 05 06:01:04 PM PDT 24
Peak memory 264664 kb
Host smart-881bd7b1-5349-4869-8059-3dcb6b9c09e4
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3722438505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.3722438505
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.3653346694
Short name T24
Test name
Test status
Simulation time 15229400 ps
CPU time 14.01 seconds
Started Jun 05 06:01:08 PM PDT 24
Finished Jun 05 06:01:23 PM PDT 24
Peak memory 264812 kb
Host smart-78d6bf44-1466-474d-98eb-66bc90a36f32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653346694 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.3653346694
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.3974455153
Short name T716
Test name
Test status
Simulation time 28347300 ps
CPU time 13.95 seconds
Started Jun 05 06:01:09 PM PDT 24
Finished Jun 05 06:01:24 PM PDT 24
Peak memory 257944 kb
Host smart-a4f87f8f-e04e-4c4a-a80d-11619c1b6e04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974455153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.3
974455153
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.3779879994
Short name T406
Test name
Test status
Simulation time 40612700 ps
CPU time 13.31 seconds
Started Jun 05 06:01:23 PM PDT 24
Finished Jun 05 06:01:37 PM PDT 24
Peak memory 275840 kb
Host smart-75f355c4-b35c-4c4c-971f-9fd0cdfbcfaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779879994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.3779879994
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.3906265173
Short name T39
Test name
Test status
Simulation time 178754300 ps
CPU time 102.14 seconds
Started Jun 05 06:01:01 PM PDT 24
Finished Jun 05 06:02:45 PM PDT 24
Peak memory 280324 kb
Host smart-d5769749-cd33-443d-bc1d-3b60f936e6c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906265173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.3906265173
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.3307003257
Short name T98
Test name
Test status
Simulation time 10167900 ps
CPU time 21.39 seconds
Started Jun 05 06:01:12 PM PDT 24
Finished Jun 05 06:01:34 PM PDT 24
Peak memory 273228 kb
Host smart-29176efb-a0af-400f-b9a3-b385ef0a2f86
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307003257 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.3307003257
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.707104734
Short name T950
Test name
Test status
Simulation time 4924305000 ps
CPU time 2271.76 seconds
Started Jun 05 06:01:00 PM PDT 24
Finished Jun 05 06:38:52 PM PDT 24
Peak memory 264760 kb
Host smart-9721ea0e-93cf-4e3f-9d01-344bab947b23
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707104734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erro
r_mp.707104734
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.1909151879
Short name T838
Test name
Test status
Simulation time 371642500 ps
CPU time 939.77 seconds
Started Jun 05 06:00:56 PM PDT 24
Finished Jun 05 06:16:37 PM PDT 24
Peak memory 273048 kb
Host smart-e267c6de-9f42-436a-aa78-448e25cf3c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909151879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.1909151879
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.1858314170
Short name T994
Test name
Test status
Simulation time 113771200 ps
CPU time 20.68 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:01:33 PM PDT 24
Peak memory 264884 kb
Host smart-4dd035d8-d142-474f-83c6-5a8ba2dfb06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858314170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.1858314170
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.745548940
Short name T274
Test name
Test status
Simulation time 455781100 ps
CPU time 69.98 seconds
Started Jun 05 06:01:16 PM PDT 24
Finished Jun 05 06:02:26 PM PDT 24
Peak memory 262320 kb
Host smart-c2f22d88-9f6e-4b12-ad45-dfa42c0caf80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745548940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.745548940
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2045907989
Short name T805
Test name
Test status
Simulation time 10059659700 ps
CPU time 63.42 seconds
Started Jun 05 06:01:09 PM PDT 24
Finished Jun 05 06:02:14 PM PDT 24
Peak memory 264916 kb
Host smart-d497dee8-6cf5-4325-a182-09145f8ce221
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045907989 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.2045907989
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.2849504916
Short name T95
Test name
Test status
Simulation time 101691862600 ps
CPU time 1907.13 seconds
Started Jun 05 06:00:59 PM PDT 24
Finished Jun 05 06:32:47 PM PDT 24
Peak memory 261788 kb
Host smart-cff68cdb-0404-4896-9543-3fe8c018c967
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849504916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.2849504916
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.688871836
Short name T936
Test name
Test status
Simulation time 40120429900 ps
CPU time 815.5 seconds
Started Jun 05 06:00:59 PM PDT 24
Finished Jun 05 06:14:35 PM PDT 24
Peak memory 264364 kb
Host smart-778d44df-3b6c-4040-ba43-6b167fe89434
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688871836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_hw_rma_reset.688871836
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.289371886
Short name T486
Test name
Test status
Simulation time 2673485900 ps
CPU time 113.83 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:03:06 PM PDT 24
Peak memory 262336 kb
Host smart-d8b488eb-1039-4f84-a24a-024639cfef9d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289371886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw
_sec_otp.289371886
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.3523594761
Short name T248
Test name
Test status
Simulation time 3572339800 ps
CPU time 531.05 seconds
Started Jun 05 06:01:24 PM PDT 24
Finished Jun 05 06:10:16 PM PDT 24
Peak memory 314040 kb
Host smart-fbdee311-4b59-4d86-913a-84c4169c666f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523594761 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.3523594761
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.2475695190
Short name T906
Test name
Test status
Simulation time 1163647200 ps
CPU time 171.32 seconds
Started Jun 05 06:01:14 PM PDT 24
Finished Jun 05 06:04:05 PM PDT 24
Peak memory 292820 kb
Host smart-8631a543-f597-4d0e-b477-b6eee567b9f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475695190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.2475695190
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.1483315106
Short name T433
Test name
Test status
Simulation time 23740827200 ps
CPU time 152.03 seconds
Started Jun 05 06:01:00 PM PDT 24
Finished Jun 05 06:03:33 PM PDT 24
Peak memory 291548 kb
Host smart-4eaf9e2c-6387-457e-98d8-926f6af091e8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483315106 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.1483315106
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.1171345549
Short name T796
Test name
Test status
Simulation time 9531286300 ps
CPU time 73.78 seconds
Started Jun 05 06:01:09 PM PDT 24
Finished Jun 05 06:02:24 PM PDT 24
Peak memory 259524 kb
Host smart-dc2d8f52-d02f-4c9a-b28f-3f1c84e07835
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171345549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.1171345549
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.1593247702
Short name T1063
Test name
Test status
Simulation time 1634221000 ps
CPU time 66.84 seconds
Started Jun 05 06:01:00 PM PDT 24
Finished Jun 05 06:02:07 PM PDT 24
Peak memory 259768 kb
Host smart-bef0e02d-6f7c-408b-9089-94a2bb38405c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593247702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1593247702
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.2654824754
Short name T710
Test name
Test status
Simulation time 83575100 ps
CPU time 13.84 seconds
Started Jun 05 06:01:26 PM PDT 24
Finished Jun 05 06:01:41 PM PDT 24
Peak memory 259228 kb
Host smart-d0c2408a-f9e8-43e5-b672-7db9027f0c93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654824754 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.2654824754
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.2730941534
Short name T99
Test name
Test status
Simulation time 40007831200 ps
CPU time 737.51 seconds
Started Jun 05 06:01:00 PM PDT 24
Finished Jun 05 06:13:18 PM PDT 24
Peak memory 273676 kb
Host smart-cdd11ac9-cdc1-43d3-8214-43d73ab1ddf2
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730941534 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.2730941534
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.3363410846
Short name T414
Test name
Test status
Simulation time 76455900 ps
CPU time 109.02 seconds
Started Jun 05 06:00:56 PM PDT 24
Finished Jun 05 06:02:46 PM PDT 24
Peak memory 259656 kb
Host smart-89d30407-37a3-4d65-9546-9d5e2051fcd5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363410846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.3363410846
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.4288224120
Short name T709
Test name
Test status
Simulation time 5226399900 ps
CPU time 181.5 seconds
Started Jun 05 06:01:18 PM PDT 24
Finished Jun 05 06:04:20 PM PDT 24
Peak memory 281340 kb
Host smart-0e69be14-7a86-42c5-94f0-247276511f2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288224120 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.4288224120
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.2161534978
Short name T62
Test name
Test status
Simulation time 44627000 ps
CPU time 14.32 seconds
Started Jun 05 06:01:09 PM PDT 24
Finished Jun 05 06:01:24 PM PDT 24
Peak memory 276332 kb
Host smart-3f80e54d-0a3d-45ce-bed3-5ca52f16051c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2161534978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.2161534978
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.3886475782
Short name T430
Test name
Test status
Simulation time 101552800 ps
CPU time 68.42 seconds
Started Jun 05 06:01:05 PM PDT 24
Finished Jun 05 06:02:14 PM PDT 24
Peak memory 262100 kb
Host smart-32679b61-a888-4a21-b4bc-7edbc306d321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886475782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.3886475782
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.1830096281
Short name T904
Test name
Test status
Simulation time 15628900 ps
CPU time 13.9 seconds
Started Jun 05 06:01:26 PM PDT 24
Finished Jun 05 06:01:40 PM PDT 24
Peak memory 264432 kb
Host smart-ebb31bdb-413d-4ab1-987f-406e8e1e08f3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830096281 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.1830096281
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.4042434624
Short name T931
Test name
Test status
Simulation time 4085257000 ps
CPU time 143.49 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:03:35 PM PDT 24
Peak memory 258724 kb
Host smart-f9c4d802-fcd7-4ba2-bd18-6fdd8201e687
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042434624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.4042434624
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.1258230640
Short name T170
Test name
Test status
Simulation time 160019800 ps
CPU time 324.47 seconds
Started Jun 05 06:00:55 PM PDT 24
Finished Jun 05 06:06:20 PM PDT 24
Peak memory 281260 kb
Host smart-28b27076-8784-4019-9e4c-6f10e565df81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258230640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.1258230640
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.1126483378
Short name T23
Test name
Test status
Simulation time 5531392900 ps
CPU time 129.99 seconds
Started Jun 05 06:01:25 PM PDT 24
Finished Jun 05 06:03:35 PM PDT 24
Peak memory 264968 kb
Host smart-802c5e29-3022-427b-8fa3-962300fa85ba
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1126483378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.1126483378
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.1574909624
Short name T1080
Test name
Test status
Simulation time 996438100 ps
CPU time 32.1 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:01:44 PM PDT 24
Peak memory 278924 kb
Host smart-58baaf66-84d1-4ae9-9dd4-531c6029ec7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574909624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.1574909624
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.3305155542
Short name T396
Test name
Test status
Simulation time 1037986600 ps
CPU time 33.01 seconds
Started Jun 05 06:01:00 PM PDT 24
Finished Jun 05 06:01:33 PM PDT 24
Peak memory 273088 kb
Host smart-49f69d6d-caf2-41db-84e4-274efdd90140
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305155542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.3305155542
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.459406348
Short name T421
Test name
Test status
Simulation time 19142000 ps
CPU time 22.53 seconds
Started Jun 05 06:01:03 PM PDT 24
Finished Jun 05 06:01:27 PM PDT 24
Peak memory 264884 kb
Host smart-a9a24dce-2e0f-4a25-b34d-3683b8cc50c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459406348 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.459406348
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.667816292
Short name T38
Test name
Test status
Simulation time 22563500 ps
CPU time 22.29 seconds
Started Jun 05 06:01:03 PM PDT 24
Finished Jun 05 06:01:26 PM PDT 24
Peak memory 264316 kb
Host smart-3502cce2-b22e-4059-92e6-66d1b838621a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667816292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_read_word_sweep_serr.667816292
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.380479645
Short name T158
Test name
Test status
Simulation time 66164788500 ps
CPU time 871.7 seconds
Started Jun 05 06:01:10 PM PDT 24
Finished Jun 05 06:15:42 PM PDT 24
Peak memory 259160 kb
Host smart-17b2fc2a-faea-4190-b529-8bca008097ff
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380479645 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.380479645
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.3523678253
Short name T615
Test name
Test status
Simulation time 575701700 ps
CPU time 126.35 seconds
Started Jun 05 06:00:59 PM PDT 24
Finished Jun 05 06:03:06 PM PDT 24
Peak memory 280468 kb
Host smart-4559ca37-0244-42b4-91ed-07beb529f65e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523678253 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_ro.3523678253
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.56438068
Short name T397
Test name
Test status
Simulation time 2888868400 ps
CPU time 138.94 seconds
Started Jun 05 06:01:00 PM PDT 24
Finished Jun 05 06:03:20 PM PDT 24
Peak memory 281276 kb
Host smart-b48bd4f3-f2f2-4e22-88a9-00c0c27ff032
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56438068 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.56438068
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.2684058745
Short name T941
Test name
Test status
Simulation time 3724753100 ps
CPU time 462.23 seconds
Started Jun 05 06:01:04 PM PDT 24
Finished Jun 05 06:08:47 PM PDT 24
Peak memory 314088 kb
Host smart-089fe52f-003c-4fcf-904c-f62cbcccad96
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684058745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.flash_ctrl_rw.2684058745
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_derr.476010497
Short name T1065
Test name
Test status
Simulation time 27726268100 ps
CPU time 681.12 seconds
Started Jun 05 06:01:12 PM PDT 24
Finished Jun 05 06:12:34 PM PDT 24
Peak memory 338100 kb
Host smart-94a2ec04-97bf-4b68-bb6a-ed6452df0cd9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476010497 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.flash_ctrl_rw_derr.476010497
Directory /workspace/1.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.2816787295
Short name T494
Test name
Test status
Simulation time 300848000 ps
CPU time 30.58 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:01:42 PM PDT 24
Peak memory 273148 kb
Host smart-914cc800-6524-4370-868c-a333f094e57a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816787295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.2816787295
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.799076613
Short name T665
Test name
Test status
Simulation time 66449400 ps
CPU time 30.5 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:01:42 PM PDT 24
Peak memory 275920 kb
Host smart-ae3ab36c-6a08-4d26-a505-0d9046826023
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799076613 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.799076613
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.1140347732
Short name T556
Test name
Test status
Simulation time 15937033400 ps
CPU time 571.59 seconds
Started Jun 05 06:01:25 PM PDT 24
Finished Jun 05 06:10:57 PM PDT 24
Peak memory 311612 kb
Host smart-1fed9cec-4cf9-409a-80f1-04ba9f3b26c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140347732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.1140347732
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.3522227146
Short name T996
Test name
Test status
Simulation time 9820270200 ps
CPU time 78.11 seconds
Started Jun 05 06:01:12 PM PDT 24
Finished Jun 05 06:02:30 PM PDT 24
Peak memory 264296 kb
Host smart-c5a58f38-5039-479e-8a18-7327c5c9eb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522227146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.3522227146
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.3037420718
Short name T520
Test name
Test status
Simulation time 2109304300 ps
CPU time 80.25 seconds
Started Jun 05 06:01:02 PM PDT 24
Finished Jun 05 06:02:23 PM PDT 24
Peak memory 264932 kb
Host smart-bad88b7f-677e-4ce4-8d8e-0365b9f99755
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037420718 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.3037420718
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.1025876097
Short name T663
Test name
Test status
Simulation time 4219692900 ps
CPU time 97.33 seconds
Started Jun 05 06:01:15 PM PDT 24
Finished Jun 05 06:02:52 PM PDT 24
Peak memory 274052 kb
Host smart-375514a7-3bff-42ea-8f45-15217bb7177c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025876097 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.1025876097
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.3708906634
Short name T461
Test name
Test status
Simulation time 29868800 ps
CPU time 122.92 seconds
Started Jun 05 06:00:55 PM PDT 24
Finished Jun 05 06:02:58 PM PDT 24
Peak memory 275536 kb
Host smart-820acfaf-4e15-4288-9b47-0d9d99230e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708906634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3708906634
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.3526624265
Short name T934
Test name
Test status
Simulation time 16090200 ps
CPU time 23.78 seconds
Started Jun 05 06:01:01 PM PDT 24
Finished Jun 05 06:01:25 PM PDT 24
Peak memory 258684 kb
Host smart-eba0655e-c478-4e43-a313-edc7f8c375ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526624265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.3526624265
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.342565533
Short name T637
Test name
Test status
Simulation time 1126720400 ps
CPU time 1152.09 seconds
Started Jun 05 06:01:06 PM PDT 24
Finished Jun 05 06:20:19 PM PDT 24
Peak memory 284704 kb
Host smart-65e9f114-e943-4b6e-85b3-bf8f8921d7a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342565533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress
_all.342565533
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.2973484333
Short name T718
Test name
Test status
Simulation time 68313300 ps
CPU time 26.72 seconds
Started Jun 05 06:01:06 PM PDT 24
Finished Jun 05 06:01:34 PM PDT 24
Peak memory 261232 kb
Host smart-d80f0e3d-4f74-4a2e-b6ad-3ced452f7c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973484333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.2973484333
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.2509293558
Short name T67
Test name
Test status
Simulation time 5000315200 ps
CPU time 201.48 seconds
Started Jun 05 06:00:58 PM PDT 24
Finished Jun 05 06:04:20 PM PDT 24
Peak memory 260020 kb
Host smart-8d4d08ac-b6b3-48d0-a2ff-8cb5412dc7f5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509293558 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_wo.2509293558
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.982165460
Short name T225
Test name
Test status
Simulation time 78053400 ps
CPU time 14.89 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:01:27 PM PDT 24
Peak memory 264936 kb
Host smart-cd7328b6-08e5-40df-a1e2-35c53d7c4da4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982165460 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.982165460
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.3949748384
Short name T719
Test name
Test status
Simulation time 302951100 ps
CPU time 13.66 seconds
Started Jun 05 06:02:25 PM PDT 24
Finished Jun 05 06:02:40 PM PDT 24
Peak memory 264808 kb
Host smart-fd96e9bc-8c10-4f06-9d76-5ec604a4c3c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949748384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
3949748384
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.4132709247
Short name T499
Test name
Test status
Simulation time 43440900 ps
CPU time 15.78 seconds
Started Jun 05 06:02:28 PM PDT 24
Finished Jun 05 06:02:44 PM PDT 24
Peak memory 275592 kb
Host smart-09c6eb09-6008-4c2c-b210-5b35deca0ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132709247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.4132709247
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.801714933
Short name T598
Test name
Test status
Simulation time 10018417600 ps
CPU time 175.03 seconds
Started Jun 05 06:02:27 PM PDT 24
Finished Jun 05 06:05:22 PM PDT 24
Peak memory 295304 kb
Host smart-d59a8faf-afd0-47dc-9363-79028ed4b21e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801714933 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.801714933
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.1064989929
Short name T340
Test name
Test status
Simulation time 15744500 ps
CPU time 13.53 seconds
Started Jun 05 06:02:29 PM PDT 24
Finished Jun 05 06:02:43 PM PDT 24
Peak memory 258828 kb
Host smart-3f2d8de5-878d-4774-a571-a8993a4f1ef2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064989929 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.1064989929
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.2939766431
Short name T144
Test name
Test status
Simulation time 100152737000 ps
CPU time 889.21 seconds
Started Jun 05 06:02:19 PM PDT 24
Finished Jun 05 06:17:09 PM PDT 24
Peak memory 263304 kb
Host smart-1a92d4a5-030f-4283-88f0-8bb570a7e493
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939766431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.2939766431
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.1537113138
Short name T310
Test name
Test status
Simulation time 3993755900 ps
CPU time 138.85 seconds
Started Jun 05 06:02:20 PM PDT 24
Finished Jun 05 06:04:40 PM PDT 24
Peak memory 259832 kb
Host smart-947dddca-e33e-4323-b6c5-ab77dc6a43b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537113138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.1537113138
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.4054758931
Short name T277
Test name
Test status
Simulation time 1732007900 ps
CPU time 180.5 seconds
Started Jun 05 06:02:19 PM PDT 24
Finished Jun 05 06:05:20 PM PDT 24
Peak memory 283736 kb
Host smart-a1bd9ef6-0bf2-4cf7-a67a-cfa7e13013d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054758931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.4054758931
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.444517134
Short name T178
Test name
Test status
Simulation time 95592413600 ps
CPU time 346.91 seconds
Started Jun 05 06:02:24 PM PDT 24
Finished Jun 05 06:08:12 PM PDT 24
Peak memory 292844 kb
Host smart-a6d228eb-ce42-415b-a8fc-50d9bab1734e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444517134 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.444517134
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.91285604
Short name T117
Test name
Test status
Simulation time 2031495300 ps
CPU time 65.19 seconds
Started Jun 05 06:02:20 PM PDT 24
Finished Jun 05 06:03:26 PM PDT 24
Peak memory 260344 kb
Host smart-ddcbaee7-1442-4495-abf3-6c2ccf052955
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91285604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.91285604
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.2563376379
Short name T285
Test name
Test status
Simulation time 138028900 ps
CPU time 13.52 seconds
Started Jun 05 06:02:27 PM PDT 24
Finished Jun 05 06:02:41 PM PDT 24
Peak memory 260044 kb
Host smart-c58bf507-074a-4f43-afbc-a9de293fd4c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563376379 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.2563376379
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.875405828
Short name T1091
Test name
Test status
Simulation time 7808340800 ps
CPU time 643.16 seconds
Started Jun 05 06:02:19 PM PDT 24
Finished Jun 05 06:13:03 PM PDT 24
Peak memory 273796 kb
Host smart-8df44647-604d-4f23-bf97-fbab9ca0eba5
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875405828 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_mp_regions.875405828
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.698590071
Short name T975
Test name
Test status
Simulation time 40191200 ps
CPU time 131.28 seconds
Started Jun 05 06:02:19 PM PDT 24
Finished Jun 05 06:04:31 PM PDT 24
Peak memory 260992 kb
Host smart-1222f27f-d944-4496-9d14-7a53e93b435d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698590071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ot
p_reset.698590071
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.3431861529
Short name T1049
Test name
Test status
Simulation time 6299841800 ps
CPU time 548.52 seconds
Started Jun 05 06:02:19 PM PDT 24
Finished Jun 05 06:11:28 PM PDT 24
Peak memory 262108 kb
Host smart-2c8e1fe3-f570-4579-bf2a-37c7a9816a7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3431861529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3431861529
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.1350531823
Short name T409
Test name
Test status
Simulation time 26477600 ps
CPU time 14.37 seconds
Started Jun 05 06:02:25 PM PDT 24
Finished Jun 05 06:02:40 PM PDT 24
Peak memory 264812 kb
Host smart-1a37f749-3d7e-4157-a138-d578696e18da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350531823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.1350531823
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.4012953421
Short name T879
Test name
Test status
Simulation time 921715600 ps
CPU time 908.23 seconds
Started Jun 05 06:02:20 PM PDT 24
Finished Jun 05 06:17:28 PM PDT 24
Peak memory 287760 kb
Host smart-d49786b0-91ed-41b4-8ab4-6b196d039f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012953421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.4012953421
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.1412977805
Short name T326
Test name
Test status
Simulation time 421858600 ps
CPU time 39.42 seconds
Started Jun 05 06:02:26 PM PDT 24
Finished Jun 05 06:03:06 PM PDT 24
Peak memory 273280 kb
Host smart-1a6ea806-90e4-4280-8b38-087b412cb4cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412977805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.1412977805
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.354533593
Short name T1077
Test name
Test status
Simulation time 653272200 ps
CPU time 108.13 seconds
Started Jun 05 06:02:23 PM PDT 24
Finished Jun 05 06:04:11 PM PDT 24
Peak memory 289468 kb
Host smart-76b538d7-130d-4c12-93bf-6a14cac17790
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354533593 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.flash_ctrl_ro.354533593
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.3864980174
Short name T914
Test name
Test status
Simulation time 32822000 ps
CPU time 32.01 seconds
Started Jun 05 06:02:26 PM PDT 24
Finished Jun 05 06:02:58 PM PDT 24
Peak memory 273120 kb
Host smart-b38493d9-64b0-43e3-9751-007ff0b7a967
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864980174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_rw_evict.3864980174
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.1285926270
Short name T641
Test name
Test status
Simulation time 80387100 ps
CPU time 31.36 seconds
Started Jun 05 06:02:29 PM PDT 24
Finished Jun 05 06:03:00 PM PDT 24
Peak memory 274436 kb
Host smart-10df54be-14e9-4e1c-bd0d-2445806d01bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285926270 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.1285926270
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.2431395848
Short name T794
Test name
Test status
Simulation time 5757872300 ps
CPU time 75.55 seconds
Started Jun 05 06:02:30 PM PDT 24
Finished Jun 05 06:03:46 PM PDT 24
Peak memory 262784 kb
Host smart-98c76f06-fddf-488f-a1c6-70b5bc2d26fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431395848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.2431395848
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.1885227143
Short name T206
Test name
Test status
Simulation time 25132800 ps
CPU time 98.22 seconds
Started Jun 05 06:02:19 PM PDT 24
Finished Jun 05 06:03:58 PM PDT 24
Peak memory 276796 kb
Host smart-2995aeee-9790-4946-9854-25663675b5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885227143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.1885227143
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.4118096046
Short name T970
Test name
Test status
Simulation time 1955710300 ps
CPU time 173.78 seconds
Started Jun 05 06:02:19 PM PDT 24
Finished Jun 05 06:05:13 PM PDT 24
Peak memory 259252 kb
Host smart-b8596bdc-c2fc-4ae9-92d4-ca5e9308a20b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118096046 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.flash_ctrl_wo.4118096046
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.3167872287
Short name T979
Test name
Test status
Simulation time 41825500 ps
CPU time 13.68 seconds
Started Jun 05 06:02:35 PM PDT 24
Finished Jun 05 06:02:49 PM PDT 24
Peak memory 263960 kb
Host smart-98f357c7-43b3-44cd-996f-05d4983aafba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167872287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
3167872287
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.1587711901
Short name T1058
Test name
Test status
Simulation time 15006000 ps
CPU time 13.38 seconds
Started Jun 05 06:02:33 PM PDT 24
Finished Jun 05 06:02:47 PM PDT 24
Peak memory 275916 kb
Host smart-daa8cb45-8a4b-4c33-adf1-a64cc10a6c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587711901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.1587711901
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3366297342
Short name T338
Test name
Test status
Simulation time 46899200 ps
CPU time 13.28 seconds
Started Jun 05 06:02:31 PM PDT 24
Finished Jun 05 06:02:45 PM PDT 24
Peak memory 257860 kb
Host smart-476081de-4e70-4cbd-a554-55963538939b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366297342 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.3366297342
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.1352262758
Short name T1069
Test name
Test status
Simulation time 160190666000 ps
CPU time 880.48 seconds
Started Jun 05 06:02:33 PM PDT 24
Finished Jun 05 06:17:14 PM PDT 24
Peak memory 264072 kb
Host smart-e5c5ba71-926b-4839-8e4b-07cf1a01f7b0
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352262758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.1352262758
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.4041953995
Short name T672
Test name
Test status
Simulation time 7143858300 ps
CPU time 121.11 seconds
Started Jun 05 06:02:27 PM PDT 24
Finished Jun 05 06:04:28 PM PDT 24
Peak memory 262380 kb
Host smart-4395ce15-6b22-4689-b552-6a5498c56ed0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041953995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.4041953995
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.3753093979
Short name T988
Test name
Test status
Simulation time 1884777600 ps
CPU time 228.2 seconds
Started Jun 05 06:02:30 PM PDT 24
Finished Jun 05 06:06:18 PM PDT 24
Peak memory 290508 kb
Host smart-10ab2f37-051a-4c3f-bea4-7b63408afae1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753093979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.3753093979
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.1918886099
Short name T530
Test name
Test status
Simulation time 24382985500 ps
CPU time 148.17 seconds
Started Jun 05 06:02:30 PM PDT 24
Finished Jun 05 06:04:58 PM PDT 24
Peak memory 293072 kb
Host smart-c5904d60-8d61-413f-ba20-1a8292121501
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918886099 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.1918886099
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.2225937561
Short name T738
Test name
Test status
Simulation time 3277165200 ps
CPU time 66.47 seconds
Started Jun 05 06:02:28 PM PDT 24
Finished Jun 05 06:03:35 PM PDT 24
Peak memory 263328 kb
Host smart-d7475dfe-063b-4636-b03d-360d8ccbae06
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225937561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.2
225937561
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.935425535
Short name T785
Test name
Test status
Simulation time 50270541300 ps
CPU time 271.96 seconds
Started Jun 05 06:02:25 PM PDT 24
Finished Jun 05 06:06:58 PM PDT 24
Peak memory 273772 kb
Host smart-7783bf00-4738-45fe-8e8d-538e0164497e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935425535 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_mp_regions.935425535
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.3421002103
Short name T645
Test name
Test status
Simulation time 36295600 ps
CPU time 110.09 seconds
Started Jun 05 06:02:27 PM PDT 24
Finished Jun 05 06:04:18 PM PDT 24
Peak memory 264480 kb
Host smart-6bd34603-5e7e-42aa-96c9-634f843b016f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421002103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.3421002103
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.740486670
Short name T985
Test name
Test status
Simulation time 9046090900 ps
CPU time 388.88 seconds
Started Jun 05 06:02:28 PM PDT 24
Finished Jun 05 06:08:57 PM PDT 24
Peak memory 261656 kb
Host smart-6caf17ac-9eee-41ef-a6bc-b57c4816a3d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=740486670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.740486670
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.3701148624
Short name T926
Test name
Test status
Simulation time 33978300 ps
CPU time 13.76 seconds
Started Jun 05 06:02:33 PM PDT 24
Finished Jun 05 06:02:47 PM PDT 24
Peak memory 264796 kb
Host smart-54b41c63-7c4f-430a-8a60-b6d56865b048
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701148624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.3701148624
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.3629399007
Short name T845
Test name
Test status
Simulation time 91346900 ps
CPU time 208.42 seconds
Started Jun 05 06:02:33 PM PDT 24
Finished Jun 05 06:06:02 PM PDT 24
Peak memory 280244 kb
Host smart-00ac7183-3765-480b-840f-bab9b40ab7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629399007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.3629399007
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.133966673
Short name T787
Test name
Test status
Simulation time 77795800 ps
CPU time 31.65 seconds
Started Jun 05 06:02:36 PM PDT 24
Finished Jun 05 06:03:08 PM PDT 24
Peak memory 269816 kb
Host smart-bf0d020e-7c61-49a9-bb01-897a597f8dcf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133966673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_re_evict.133966673
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.3235960957
Short name T210
Test name
Test status
Simulation time 1073067500 ps
CPU time 115.09 seconds
Started Jun 05 06:02:26 PM PDT 24
Finished Jun 05 06:04:22 PM PDT 24
Peak memory 288860 kb
Host smart-538f17ac-d4ad-4615-a15e-23ac292599e9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235960957 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.flash_ctrl_ro.3235960957
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.3361918371
Short name T1038
Test name
Test status
Simulation time 64840954600 ps
CPU time 539.99 seconds
Started Jun 05 06:02:28 PM PDT 24
Finished Jun 05 06:11:28 PM PDT 24
Peak memory 309364 kb
Host smart-8d228eb2-bf0e-452e-a73b-d08cadbc8903
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361918371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_rw.3361918371
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.512764769
Short name T555
Test name
Test status
Simulation time 33003700 ps
CPU time 31.19 seconds
Started Jun 05 06:02:36 PM PDT 24
Finished Jun 05 06:03:07 PM PDT 24
Peak memory 272220 kb
Host smart-4eec1911-df29-488e-a15a-0b56c629de35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512764769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_rw_evict.512764769
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.2489495046
Short name T922
Test name
Test status
Simulation time 69613900 ps
CPU time 30.94 seconds
Started Jun 05 06:02:35 PM PDT 24
Finished Jun 05 06:03:07 PM PDT 24
Peak memory 275168 kb
Host smart-bf934e7b-5277-47e5-a13b-705d42f00766
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489495046 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.2489495046
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.3583962665
Short name T662
Test name
Test status
Simulation time 3597115500 ps
CPU time 64.36 seconds
Started Jun 05 06:02:34 PM PDT 24
Finished Jun 05 06:03:39 PM PDT 24
Peak memory 264276 kb
Host smart-ec1e7d63-74dd-475e-9e6e-ffa356e6efc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583962665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.3583962665
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.3278011470
Short name T1044
Test name
Test status
Simulation time 37014200 ps
CPU time 145.54 seconds
Started Jun 05 06:02:33 PM PDT 24
Finished Jun 05 06:05:00 PM PDT 24
Peak memory 277212 kb
Host smart-9dc49d03-2386-41a3-9c1e-fe05f20b73cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278011470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.3278011470
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.150595422
Short name T948
Test name
Test status
Simulation time 2026455500 ps
CPU time 154.24 seconds
Started Jun 05 06:02:26 PM PDT 24
Finished Jun 05 06:05:00 PM PDT 24
Peak memory 259204 kb
Host smart-2811642a-bc4d-4f3a-99bc-5b340e147fa0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150595422 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.flash_ctrl_wo.150595422
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.3373277054
Short name T452
Test name
Test status
Simulation time 175394200 ps
CPU time 13.63 seconds
Started Jun 05 06:02:45 PM PDT 24
Finished Jun 05 06:02:59 PM PDT 24
Peak memory 264852 kb
Host smart-58567e45-63ca-49dc-a9fd-af0c97cf9a2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373277054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
3373277054
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.1267757343
Short name T647
Test name
Test status
Simulation time 14024500 ps
CPU time 15.37 seconds
Started Jun 05 06:02:42 PM PDT 24
Finished Jun 05 06:02:58 PM PDT 24
Peak memory 275980 kb
Host smart-42d791e1-40b1-49bd-8978-d72494b54a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267757343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.1267757343
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.257605448
Short name T1003
Test name
Test status
Simulation time 15293100 ps
CPU time 21.64 seconds
Started Jun 05 06:02:46 PM PDT 24
Finished Jun 05 06:03:08 PM PDT 24
Peak memory 273168 kb
Host smart-6b3d458b-6685-4646-92c0-c4ee6ab627d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257605448 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.257605448
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2470394637
Short name T145
Test name
Test status
Simulation time 10020738300 ps
CPU time 74.27 seconds
Started Jun 05 06:02:43 PM PDT 24
Finished Jun 05 06:03:58 PM PDT 24
Peak memory 286192 kb
Host smart-77de2e2e-4c70-4d66-9028-6839972ac0c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470394637 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2470394637
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.1448597041
Short name T339
Test name
Test status
Simulation time 46595200 ps
CPU time 13.5 seconds
Started Jun 05 06:02:43 PM PDT 24
Finished Jun 05 06:02:57 PM PDT 24
Peak memory 258920 kb
Host smart-82c1d545-7340-469d-8454-bd69796f194d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448597041 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1448597041
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.409374148
Short name T977
Test name
Test status
Simulation time 40121339600 ps
CPU time 834.08 seconds
Started Jun 05 06:02:36 PM PDT 24
Finished Jun 05 06:16:30 PM PDT 24
Peak memory 259088 kb
Host smart-6722b3c3-5fad-4a36-ae7a-447a9da19839
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409374148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 12.flash_ctrl_hw_rma_reset.409374148
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.2400896298
Short name T858
Test name
Test status
Simulation time 5465557100 ps
CPU time 175.95 seconds
Started Jun 05 06:02:32 PM PDT 24
Finished Jun 05 06:05:29 PM PDT 24
Peak memory 261892 kb
Host smart-2ee859cb-08c6-4365-a770-e5efe4baa616
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400896298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.2400896298
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.3123483628
Short name T336
Test name
Test status
Simulation time 2275410700 ps
CPU time 160.33 seconds
Started Jun 05 06:02:34 PM PDT 24
Finished Jun 05 06:05:15 PM PDT 24
Peak memory 292856 kb
Host smart-6aa67433-415e-4bdf-8a07-308f00a7ff42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123483628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.3123483628
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.4177515506
Short name T813
Test name
Test status
Simulation time 11400030800 ps
CPU time 138.43 seconds
Started Jun 05 06:02:35 PM PDT 24
Finished Jun 05 06:04:54 PM PDT 24
Peak memory 291872 kb
Host smart-d80991c5-5118-485d-9ecd-f670cd229c3b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177515506 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.4177515506
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.3659473302
Short name T60
Test name
Test status
Simulation time 1633155200 ps
CPU time 63.68 seconds
Started Jun 05 06:02:32 PM PDT 24
Finished Jun 05 06:03:36 PM PDT 24
Peak memory 260496 kb
Host smart-83735d71-be9a-4057-b8b7-2a195039e833
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659473302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.3
659473302
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.765846709
Short name T139
Test name
Test status
Simulation time 15925500 ps
CPU time 13.7 seconds
Started Jun 05 06:02:45 PM PDT 24
Finished Jun 05 06:02:59 PM PDT 24
Peak memory 260160 kb
Host smart-99e6d924-b003-41a6-b9a5-66c2762f0197
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765846709 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.765846709
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.3514212069
Short name T1010
Test name
Test status
Simulation time 29313481400 ps
CPU time 330.88 seconds
Started Jun 05 06:02:34 PM PDT 24
Finished Jun 05 06:08:05 PM PDT 24
Peak memory 274116 kb
Host smart-c0fe798e-edcd-41db-be94-465ab54f0d1a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514212069 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.3514212069
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.1260039994
Short name T371
Test name
Test status
Simulation time 69914200 ps
CPU time 110.21 seconds
Started Jun 05 06:02:35 PM PDT 24
Finished Jun 05 06:04:26 PM PDT 24
Peak memory 263224 kb
Host smart-5cf9597b-a022-4667-97ac-3d15322ed1c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260039994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.1260039994
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.2798750018
Short name T812
Test name
Test status
Simulation time 2792305900 ps
CPU time 443.99 seconds
Started Jun 05 06:02:34 PM PDT 24
Finished Jun 05 06:09:59 PM PDT 24
Peak memory 261536 kb
Host smart-614576ad-faa6-45af-b24b-2d86ec2e65d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2798750018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.2798750018
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.3082995241
Short name T386
Test name
Test status
Simulation time 25945600 ps
CPU time 13.65 seconds
Started Jun 05 06:02:35 PM PDT 24
Finished Jun 05 06:02:49 PM PDT 24
Peak memory 258456 kb
Host smart-dce76771-f5c2-41c6-b244-59224459aa93
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082995241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.3082995241
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.956491466
Short name T743
Test name
Test status
Simulation time 698299800 ps
CPU time 748.71 seconds
Started Jun 05 06:02:32 PM PDT 24
Finished Jun 05 06:15:02 PM PDT 24
Peak memory 282292 kb
Host smart-003f6271-16bd-4767-88ea-750beb590ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956491466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.956491466
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.420404586
Short name T25
Test name
Test status
Simulation time 98388700 ps
CPU time 35.81 seconds
Started Jun 05 06:02:45 PM PDT 24
Finished Jun 05 06:03:21 PM PDT 24
Peak memory 269432 kb
Host smart-8468b753-fbf1-4e3a-84f4-be93f3b96881
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420404586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_re_evict.420404586
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.1770695265
Short name T927
Test name
Test status
Simulation time 588482700 ps
CPU time 107.66 seconds
Started Jun 05 06:02:49 PM PDT 24
Finished Jun 05 06:04:37 PM PDT 24
Peak memory 297096 kb
Host smart-b138b341-6233-4b58-a6ea-e8f713583ad7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770695265 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_ro.1770695265
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.3534523324
Short name T769
Test name
Test status
Simulation time 12853958000 ps
CPU time 515.38 seconds
Started Jun 05 06:02:34 PM PDT 24
Finished Jun 05 06:11:10 PM PDT 24
Peak memory 313444 kb
Host smart-15cacff8-a674-42c5-85fa-1f3d28476bba
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534523324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.3534523324
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.2766891009
Short name T407
Test name
Test status
Simulation time 29984700 ps
CPU time 31 seconds
Started Jun 05 06:02:45 PM PDT 24
Finished Jun 05 06:03:16 PM PDT 24
Peak memory 272788 kb
Host smart-29baee2d-6618-498c-90fb-580992b4ce07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766891009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_rw_evict.2766891009
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.31237339
Short name T211
Test name
Test status
Simulation time 73582100 ps
CPU time 30.48 seconds
Started Jun 05 06:02:45 PM PDT 24
Finished Jun 05 06:03:16 PM PDT 24
Peak memory 268524 kb
Host smart-c048f686-2e2b-4a79-a8d0-c6493a892b7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31237339 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.31237339
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.2992972144
Short name T526
Test name
Test status
Simulation time 5359828800 ps
CPU time 83.01 seconds
Started Jun 05 06:02:44 PM PDT 24
Finished Jun 05 06:04:07 PM PDT 24
Peak memory 264768 kb
Host smart-e487ef66-3a2f-457a-9297-4cde2c3b597e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992972144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.2992972144
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.2660207251
Short name T843
Test name
Test status
Simulation time 45012700 ps
CPU time 193.22 seconds
Started Jun 05 06:02:32 PM PDT 24
Finished Jun 05 06:05:45 PM PDT 24
Peak memory 277876 kb
Host smart-5563ed79-d741-4fc5-99e0-cf219a3d8a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660207251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.2660207251
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.3696777925
Short name T939
Test name
Test status
Simulation time 4411301600 ps
CPU time 189.83 seconds
Started Jun 05 06:02:33 PM PDT 24
Finished Jun 05 06:05:44 PM PDT 24
Peak memory 264728 kb
Host smart-1532b6c0-51f6-4b28-baab-e32d9e60c303
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696777925 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.flash_ctrl_wo.3696777925
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.2904144249
Short name T17
Test name
Test status
Simulation time 273708500 ps
CPU time 14.4 seconds
Started Jun 05 06:02:50 PM PDT 24
Finished Jun 05 06:03:05 PM PDT 24
Peak memory 258776 kb
Host smart-ada9522e-d7a4-44a3-81c3-868a120f6910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904144249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
2904144249
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.172145394
Short name T907
Test name
Test status
Simulation time 16975300 ps
CPU time 13.39 seconds
Started Jun 05 06:02:51 PM PDT 24
Finished Jun 05 06:03:04 PM PDT 24
Peak memory 275816 kb
Host smart-617e570b-1e78-41b6-ba50-909c1e0467a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172145394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.172145394
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.2782831762
Short name T644
Test name
Test status
Simulation time 44656100 ps
CPU time 21.21 seconds
Started Jun 05 06:02:50 PM PDT 24
Finished Jun 05 06:03:12 PM PDT 24
Peak memory 273116 kb
Host smart-cd74be28-f110-45dc-8f97-1e3fca918b14
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782831762 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.2782831762
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2932968585
Short name T850
Test name
Test status
Simulation time 10017074100 ps
CPU time 85.07 seconds
Started Jun 05 06:02:49 PM PDT 24
Finished Jun 05 06:04:15 PM PDT 24
Peak memory 285932 kb
Host smart-b0edbe04-f0ab-4efb-947a-98e86fa089a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932968585 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.2932968585
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3712856261
Short name T960
Test name
Test status
Simulation time 7660637400 ps
CPU time 117.52 seconds
Started Jun 05 06:02:44 PM PDT 24
Finished Jun 05 06:04:42 PM PDT 24
Peak memory 261780 kb
Host smart-c573cb54-a354-4990-a99c-d47dd0a0e3ce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712856261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.3712856261
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2258210058
Short name T884
Test name
Test status
Simulation time 126995127500 ps
CPU time 296.75 seconds
Started Jun 05 06:02:50 PM PDT 24
Finished Jun 05 06:07:47 PM PDT 24
Peak memory 283812 kb
Host smart-51ae8349-3e4e-48fa-9d9b-b40ea30d435d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258210058 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.2258210058
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.789174201
Short name T897
Test name
Test status
Simulation time 5368885100 ps
CPU time 86.46 seconds
Started Jun 05 06:02:44 PM PDT 24
Finished Jun 05 06:04:11 PM PDT 24
Peak memory 260552 kb
Host smart-7b88836c-36b4-4408-b410-17bc67d55f63
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789174201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.789174201
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2136740121
Short name T885
Test name
Test status
Simulation time 59303900 ps
CPU time 13.48 seconds
Started Jun 05 06:02:52 PM PDT 24
Finished Jun 05 06:03:06 PM PDT 24
Peak memory 264836 kb
Host smart-63a5fbee-54e6-4012-8da4-3f943e12eb9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136740121 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2136740121
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.1447511593
Short name T962
Test name
Test status
Simulation time 20423333000 ps
CPU time 287.34 seconds
Started Jun 05 06:02:45 PM PDT 24
Finished Jun 05 06:07:33 PM PDT 24
Peak memory 273700 kb
Host smart-fbb31d44-95c0-4b70-90e3-e88d1bdb151e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447511593 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_mp_regions.1447511593
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.2496997752
Short name T190
Test name
Test status
Simulation time 40657900 ps
CPU time 131.78 seconds
Started Jun 05 06:02:44 PM PDT 24
Finished Jun 05 06:04:56 PM PDT 24
Peak memory 260756 kb
Host smart-f5f522ca-06f0-41d3-973c-3776cd19ee48
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496997752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.2496997752
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.2109110762
Short name T760
Test name
Test status
Simulation time 3862520300 ps
CPU time 256.7 seconds
Started Jun 05 06:02:43 PM PDT 24
Finished Jun 05 06:07:00 PM PDT 24
Peak memory 262252 kb
Host smart-24addfb0-d04e-4266-93ad-50a51f61db06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2109110762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.2109110762
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.435867300
Short name T128
Test name
Test status
Simulation time 18455300 ps
CPU time 13.69 seconds
Started Jun 05 06:02:50 PM PDT 24
Finished Jun 05 06:03:04 PM PDT 24
Peak memory 258476 kb
Host smart-02b8a78c-5e85-421b-9b15-ab673977170c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435867300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_res
et.435867300
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.883676458
Short name T449
Test name
Test status
Simulation time 420934900 ps
CPU time 646.17 seconds
Started Jun 05 06:02:45 PM PDT 24
Finished Jun 05 06:13:32 PM PDT 24
Peak memory 283932 kb
Host smart-a7e001a9-f198-41d5-b3b5-130515493fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883676458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.883676458
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.283400362
Short name T474
Test name
Test status
Simulation time 2070420400 ps
CPU time 109.26 seconds
Started Jun 05 06:02:49 PM PDT 24
Finished Jun 05 06:04:38 PM PDT 24
Peak memory 281316 kb
Host smart-e9e3ec50-e826-485f-8c79-d8622d01b3f7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283400362 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.flash_ctrl_ro.283400362
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.43486430
Short name T535
Test name
Test status
Simulation time 7551698000 ps
CPU time 580.45 seconds
Started Jun 05 06:02:53 PM PDT 24
Finished Jun 05 06:12:34 PM PDT 24
Peak memory 313208 kb
Host smart-07c5dd79-8973-4d4b-a180-4633ccaa3584
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43486430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.flash_ctrl_rw.43486430
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.4045277029
Short name T742
Test name
Test status
Simulation time 76420700 ps
CPU time 30.76 seconds
Started Jun 05 06:02:54 PM PDT 24
Finished Jun 05 06:03:25 PM PDT 24
Peak memory 268328 kb
Host smart-4270a474-22c9-41aa-83b0-20b08abb1c41
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045277029 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.4045277029
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.10877363
Short name T867
Test name
Test status
Simulation time 65601400 ps
CPU time 148.15 seconds
Started Jun 05 06:02:44 PM PDT 24
Finished Jun 05 06:05:13 PM PDT 24
Peak memory 277448 kb
Host smart-a7bdcdd9-4b4b-474c-96ba-9b59d4b75908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10877363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.10877363
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.167671807
Short name T481
Test name
Test status
Simulation time 6109428900 ps
CPU time 224.08 seconds
Started Jun 05 06:02:46 PM PDT 24
Finished Jun 05 06:06:30 PM PDT 24
Peak memory 258612 kb
Host smart-da05b123-0c45-4d60-93f3-2edc61d84893
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167671807 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.flash_ctrl_wo.167671807
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.2382758156
Short name T959
Test name
Test status
Simulation time 67734200 ps
CPU time 14 seconds
Started Jun 05 06:02:59 PM PDT 24
Finished Jun 05 06:03:14 PM PDT 24
Peak memory 257956 kb
Host smart-145b03b9-5445-4d1d-b530-5edaf3b8e696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382758156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
2382758156
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.3649426277
Short name T611
Test name
Test status
Simulation time 26248900 ps
CPU time 13.54 seconds
Started Jun 05 06:03:01 PM PDT 24
Finished Jun 05 06:03:15 PM PDT 24
Peak memory 275556 kb
Host smart-7e76d915-1089-4a19-832f-7a19f2372e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649426277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.3649426277
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.3337045245
Short name T991
Test name
Test status
Simulation time 37290300 ps
CPU time 21.84 seconds
Started Jun 05 06:03:02 PM PDT 24
Finished Jun 05 06:03:24 PM PDT 24
Peak memory 264848 kb
Host smart-82e1b96f-11f2-4923-b886-bcf417c9cf28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337045245 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.3337045245
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1382753276
Short name T541
Test name
Test status
Simulation time 10012181300 ps
CPU time 325.54 seconds
Started Jun 05 06:03:01 PM PDT 24
Finished Jun 05 06:08:27 PM PDT 24
Peak memory 326952 kb
Host smart-450836e3-972c-4dfa-904c-757ff25c819d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382753276 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1382753276
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.2125263319
Short name T280
Test name
Test status
Simulation time 47214300 ps
CPU time 13.51 seconds
Started Jun 05 06:02:59 PM PDT 24
Finished Jun 05 06:03:13 PM PDT 24
Peak memory 258128 kb
Host smart-7ae23199-a90e-48be-bd9f-e39ce7c0207c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125263319 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.2125263319
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.918148519
Short name T830
Test name
Test status
Simulation time 40123485300 ps
CPU time 780.53 seconds
Started Jun 05 06:02:51 PM PDT 24
Finished Jun 05 06:15:53 PM PDT 24
Peak memory 264232 kb
Host smart-3dd17bfe-8252-4792-abd2-a196bae2b886
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918148519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.flash_ctrl_hw_rma_reset.918148519
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.320559759
Short name T585
Test name
Test status
Simulation time 2939223000 ps
CPU time 141.58 seconds
Started Jun 05 06:02:51 PM PDT 24
Finished Jun 05 06:05:14 PM PDT 24
Peak memory 292804 kb
Host smart-9d81eb1d-b0a8-44b6-a4c7-d59c032859f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320559759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flas
h_ctrl_intr_rd.320559759
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3511164712
Short name T697
Test name
Test status
Simulation time 32371409600 ps
CPU time 272.21 seconds
Started Jun 05 06:02:52 PM PDT 24
Finished Jun 05 06:07:25 PM PDT 24
Peak memory 292860 kb
Host smart-84bea90a-e00c-4a59-b69d-c89ebf2f312a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511164712 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.3511164712
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.990103215
Short name T591
Test name
Test status
Simulation time 7844812200 ps
CPU time 60.38 seconds
Started Jun 05 06:02:53 PM PDT 24
Finished Jun 05 06:03:55 PM PDT 24
Peak memory 260424 kb
Host smart-8fbaa3cd-9cef-4c01-b99d-36707a235e48
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990103215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.990103215
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.616486292
Short name T823
Test name
Test status
Simulation time 25978300 ps
CPU time 13.56 seconds
Started Jun 05 06:03:00 PM PDT 24
Finished Jun 05 06:03:14 PM PDT 24
Peak memory 264812 kb
Host smart-250d66e4-9e82-4e2d-b060-b6f439b62700
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616486292 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.616486292
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.3733366927
Short name T114
Test name
Test status
Simulation time 22697296300 ps
CPU time 311.87 seconds
Started Jun 05 06:02:56 PM PDT 24
Finished Jun 05 06:08:08 PM PDT 24
Peak memory 273848 kb
Host smart-52039c96-1de7-4fb0-b24d-ea60544a810d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733366927 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.3733366927
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.3372340352
Short name T493
Test name
Test status
Simulation time 136403600 ps
CPU time 132.4 seconds
Started Jun 05 06:02:51 PM PDT 24
Finished Jun 05 06:05:04 PM PDT 24
Peak memory 261052 kb
Host smart-dc6f0549-5b7a-4c45-9e9a-0815eb22fd45
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372340352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.3372340352
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.1501515720
Short name T1005
Test name
Test status
Simulation time 41707700 ps
CPU time 155.63 seconds
Started Jun 05 06:02:56 PM PDT 24
Finished Jun 05 06:05:33 PM PDT 24
Peak memory 261460 kb
Host smart-21b52d7e-97bb-41b8-b690-9f9fd12174a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501515720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.1501515720
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.1649439948
Short name T853
Test name
Test status
Simulation time 7448364500 ps
CPU time 212.67 seconds
Started Jun 05 06:02:52 PM PDT 24
Finished Jun 05 06:06:25 PM PDT 24
Peak memory 259540 kb
Host smart-59f1192a-cef9-408e-9bc5-d07709eb78e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649439948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.1649439948
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.3780653675
Short name T504
Test name
Test status
Simulation time 122298600 ps
CPU time 989.38 seconds
Started Jun 05 06:02:54 PM PDT 24
Finished Jun 05 06:19:24 PM PDT 24
Peak memory 286996 kb
Host smart-42335659-1f49-4847-ba79-7360fa7ae247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780653675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3780653675
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.2111773653
Short name T683
Test name
Test status
Simulation time 216865200 ps
CPU time 38.69 seconds
Started Jun 05 06:03:00 PM PDT 24
Finished Jun 05 06:03:40 PM PDT 24
Peak memory 277196 kb
Host smart-501ccf70-8c9a-4141-bd41-da30d9d3861a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111773653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.2111773653
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.42639353
Short name T714
Test name
Test status
Simulation time 9211505600 ps
CPU time 121.56 seconds
Started Jun 05 06:02:52 PM PDT 24
Finished Jun 05 06:04:54 PM PDT 24
Peak memory 280512 kb
Host smart-29be8502-3a23-451b-ac9f-6bde33335dd8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42639353 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 14.flash_ctrl_ro.42639353
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.1183887476
Short name T548
Test name
Test status
Simulation time 13126576900 ps
CPU time 610.81 seconds
Started Jun 05 06:02:52 PM PDT 24
Finished Jun 05 06:13:03 PM PDT 24
Peak memory 309092 kb
Host smart-f0d6386b-9259-4b36-bc11-6da391d3707f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183887476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.1183887476
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.3553593140
Short name T1098
Test name
Test status
Simulation time 71037700 ps
CPU time 28.76 seconds
Started Jun 05 06:02:59 PM PDT 24
Finished Jun 05 06:03:29 PM PDT 24
Peak memory 273124 kb
Host smart-d3380d21-d3ff-4ae5-99e8-97d8792409c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553593140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.3553593140
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.680278209
Short name T835
Test name
Test status
Simulation time 29682800 ps
CPU time 31.34 seconds
Started Jun 05 06:02:59 PM PDT 24
Finished Jun 05 06:03:31 PM PDT 24
Peak memory 271960 kb
Host smart-82b2911b-2cc3-4217-8e78-08aee7f2b922
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680278209 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.680278209
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.976919022
Short name T365
Test name
Test status
Simulation time 2540438500 ps
CPU time 86.26 seconds
Started Jun 05 06:03:00 PM PDT 24
Finished Jun 05 06:04:26 PM PDT 24
Peak memory 262500 kb
Host smart-b3305718-7137-4f52-9504-6955d3185a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976919022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.976919022
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.272869072
Short name T488
Test name
Test status
Simulation time 58926700 ps
CPU time 119.19 seconds
Started Jun 05 06:02:52 PM PDT 24
Finished Jun 05 06:04:51 PM PDT 24
Peak memory 275660 kb
Host smart-89c1b244-a4b4-48eb-942b-09854daa8998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272869072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.272869072
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.3596188855
Short name T111
Test name
Test status
Simulation time 2235967900 ps
CPU time 165.46 seconds
Started Jun 05 06:02:50 PM PDT 24
Finished Jun 05 06:05:36 PM PDT 24
Peak memory 259912 kb
Host smart-dcbfd4e9-8ffb-4930-8f90-def02cea1290
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596188855 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.3596188855
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.1540250622
Short name T411
Test name
Test status
Simulation time 50095700 ps
CPU time 13.97 seconds
Started Jun 05 06:03:07 PM PDT 24
Finished Jun 05 06:03:21 PM PDT 24
Peak memory 264776 kb
Host smart-e7f00c04-0d12-45b9-acfd-e5348df4839d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540250622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
1540250622
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.2184587783
Short name T1070
Test name
Test status
Simulation time 45512600 ps
CPU time 15.63 seconds
Started Jun 05 06:03:05 PM PDT 24
Finished Jun 05 06:03:21 PM PDT 24
Peak memory 275576 kb
Host smart-fca0309f-6495-4972-b8d6-cb35a0662cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184587783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.2184587783
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.625373909
Short name T357
Test name
Test status
Simulation time 11211400 ps
CPU time 20.78 seconds
Started Jun 05 06:03:05 PM PDT 24
Finished Jun 05 06:03:26 PM PDT 24
Peak memory 273288 kb
Host smart-4df6ae6d-e140-43a2-ad2c-9b6b85c6c685
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625373909 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.625373909
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2806534833
Short name T587
Test name
Test status
Simulation time 10012633500 ps
CPU time 308.38 seconds
Started Jun 05 06:03:08 PM PDT 24
Finished Jun 05 06:08:17 PM PDT 24
Peak memory 318976 kb
Host smart-aa73d647-a30c-4309-91d7-4e3c57be984a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806534833 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.2806534833
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.3087137100
Short name T129
Test name
Test status
Simulation time 15717800 ps
CPU time 13.93 seconds
Started Jun 05 06:03:09 PM PDT 24
Finished Jun 05 06:03:23 PM PDT 24
Peak memory 257828 kb
Host smart-87f90fe6-bfae-4de4-a946-e808774f0a87
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087137100 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.3087137100
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.2276189827
Short name T121
Test name
Test status
Simulation time 40125686900 ps
CPU time 906.63 seconds
Started Jun 05 06:03:04 PM PDT 24
Finished Jun 05 06:18:12 PM PDT 24
Peak memory 264068 kb
Host smart-ec46bc38-da1a-47d8-9e11-49178b28f891
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276189827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.2276189827
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.861275238
Short name T168
Test name
Test status
Simulation time 9935887200 ps
CPU time 98.98 seconds
Started Jun 05 06:03:03 PM PDT 24
Finished Jun 05 06:04:42 PM PDT 24
Peak memory 262272 kb
Host smart-284bb49b-dba4-441f-b992-f10b28be36df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861275238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_h
w_sec_otp.861275238
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.1204523809
Short name T28
Test name
Test status
Simulation time 1591599900 ps
CPU time 127.62 seconds
Started Jun 05 06:03:07 PM PDT 24
Finished Jun 05 06:05:16 PM PDT 24
Peak memory 292960 kb
Host smart-fff1080c-744d-4bb8-bfd9-e909889c4048
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204523809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.1204523809
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.66220661
Short name T834
Test name
Test status
Simulation time 17379435900 ps
CPU time 274.13 seconds
Started Jun 05 06:03:05 PM PDT 24
Finished Jun 05 06:07:40 PM PDT 24
Peak memory 283988 kb
Host smart-85ffa889-214b-41ab-b2c3-e3a34b8d9ab0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66220661 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.66220661
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.3459412058
Short name T640
Test name
Test status
Simulation time 997280300 ps
CPU time 86.62 seconds
Started Jun 05 06:03:06 PM PDT 24
Finished Jun 05 06:04:33 PM PDT 24
Peak memory 259788 kb
Host smart-8d9c9a0a-0618-40a0-b065-e94ffce3c095
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459412058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.3
459412058
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.3304277287
Short name T101
Test name
Test status
Simulation time 71546493600 ps
CPU time 480.93 seconds
Started Jun 05 06:03:07 PM PDT 24
Finished Jun 05 06:11:08 PM PDT 24
Peak memory 273136 kb
Host smart-5296b592-875f-4326-8d2f-f4cb53045991
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304277287 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.3304277287
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.2089672470
Short name T873
Test name
Test status
Simulation time 145443400 ps
CPU time 109.39 seconds
Started Jun 05 06:03:06 PM PDT 24
Finished Jun 05 06:04:56 PM PDT 24
Peak memory 264200 kb
Host smart-f96924f4-7309-435e-94cc-5ea51458e194
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089672470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.2089672470
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.4154712292
Short name T196
Test name
Test status
Simulation time 62903700 ps
CPU time 114.04 seconds
Started Jun 05 06:02:59 PM PDT 24
Finished Jun 05 06:04:53 PM PDT 24
Peak memory 262200 kb
Host smart-af3eea37-949e-4cab-9e25-b6f22949a569
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4154712292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.4154712292
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.117207601
Short name T561
Test name
Test status
Simulation time 30035800 ps
CPU time 13.85 seconds
Started Jun 05 06:03:05 PM PDT 24
Finished Jun 05 06:03:19 PM PDT 24
Peak memory 258396 kb
Host smart-66aa67f6-ca80-47d7-bdb7-dbd308d48aed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117207601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_res
et.117207601
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.2166336166
Short name T456
Test name
Test status
Simulation time 65806700 ps
CPU time 266.76 seconds
Started Jun 05 06:02:59 PM PDT 24
Finished Jun 05 06:07:26 PM PDT 24
Peak memory 276684 kb
Host smart-57d31403-4935-4eb2-a235-d163ad941762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166336166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.2166336166
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.2658812661
Short name T267
Test name
Test status
Simulation time 501580000 ps
CPU time 107.93 seconds
Started Jun 05 06:03:07 PM PDT 24
Finished Jun 05 06:04:55 PM PDT 24
Peak memory 296896 kb
Host smart-0d858a6b-f9c9-496a-8568-dad93eb33596
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658812661 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_ro.2658812661
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.285247815
Short name T471
Test name
Test status
Simulation time 13383674400 ps
CPU time 573.8 seconds
Started Jun 05 06:03:08 PM PDT 24
Finished Jun 05 06:12:42 PM PDT 24
Peak memory 309084 kb
Host smart-f2ad6e66-eaf6-4864-8390-5335ed6a64f3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285247815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.flash_ctrl_rw.285247815
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.1465773371
Short name T937
Test name
Test status
Simulation time 40218300 ps
CPU time 30.89 seconds
Started Jun 05 06:03:06 PM PDT 24
Finished Jun 05 06:03:37 PM PDT 24
Peak memory 268812 kb
Host smart-94c1a197-cd03-4d12-8ada-d7f8c6001c90
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465773371 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.1465773371
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.1535155752
Short name T1029
Test name
Test status
Simulation time 850571600 ps
CPU time 53.42 seconds
Started Jun 05 06:03:08 PM PDT 24
Finished Jun 05 06:04:02 PM PDT 24
Peak memory 262964 kb
Host smart-a1f1959c-811b-4675-91e1-5d5da1ee219d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535155752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.1535155752
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.2210165987
Short name T503
Test name
Test status
Simulation time 161018300 ps
CPU time 146.66 seconds
Started Jun 05 06:03:01 PM PDT 24
Finished Jun 05 06:05:29 PM PDT 24
Peak memory 275944 kb
Host smart-ba394b5e-e7f7-44a2-9954-7b3a6e62d5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210165987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.2210165987
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.765434189
Short name T512
Test name
Test status
Simulation time 2867664200 ps
CPU time 240.25 seconds
Started Jun 05 06:03:08 PM PDT 24
Finished Jun 05 06:07:09 PM PDT 24
Peak memory 264828 kb
Host smart-05bd5bd0-2be2-4595-9902-a10e3cc27218
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765434189 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.flash_ctrl_wo.765434189
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.722800809
Short name T518
Test name
Test status
Simulation time 18023500 ps
CPU time 13.94 seconds
Started Jun 05 06:03:22 PM PDT 24
Finished Jun 05 06:03:36 PM PDT 24
Peak memory 258008 kb
Host smart-9f4f75e4-c312-445b-a1cc-09f99697333e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722800809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.722800809
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.658287086
Short name T536
Test name
Test status
Simulation time 25728400 ps
CPU time 15.52 seconds
Started Jun 05 06:03:12 PM PDT 24
Finished Jun 05 06:03:28 PM PDT 24
Peak memory 275568 kb
Host smart-94fc8f5e-7e23-477d-8dfa-25807531fef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658287086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.658287086
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.2322451246
Short name T603
Test name
Test status
Simulation time 62567700 ps
CPU time 20.26 seconds
Started Jun 05 06:03:11 PM PDT 24
Finished Jun 05 06:03:32 PM PDT 24
Peak memory 273032 kb
Host smart-96a9e982-3098-4ef7-8515-5982a3e2773c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322451246 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.2322451246
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.3813517419
Short name T149
Test name
Test status
Simulation time 10013167900 ps
CPU time 105.47 seconds
Started Jun 05 06:03:14 PM PDT 24
Finished Jun 05 06:05:00 PM PDT 24
Peak memory 298100 kb
Host smart-03fbc5c4-f6c4-401e-9da3-de82410da30b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813517419 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.3813517419
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.3659654247
Short name T625
Test name
Test status
Simulation time 23069400 ps
CPU time 13.56 seconds
Started Jun 05 06:03:13 PM PDT 24
Finished Jun 05 06:03:27 PM PDT 24
Peak memory 258924 kb
Host smart-cfffabe5-70a9-480e-b06d-7b37f8c36ea8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659654247 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.3659654247
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.3004254852
Short name T1041
Test name
Test status
Simulation time 80145446600 ps
CPU time 863.14 seconds
Started Jun 05 06:03:12 PM PDT 24
Finished Jun 05 06:17:35 PM PDT 24
Peak memory 263008 kb
Host smart-7fc4f7ee-3cb6-48ea-bcd9-1a9fe38b9fea
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004254852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.3004254852
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.332968970
Short name T272
Test name
Test status
Simulation time 3075318000 ps
CPU time 137.62 seconds
Started Jun 05 06:03:12 PM PDT 24
Finished Jun 05 06:05:31 PM PDT 24
Peak memory 289416 kb
Host smart-7120cbb0-1505-4633-b9ed-ec375436f562
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332968970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flas
h_ctrl_intr_rd.332968970
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.440180077
Short name T251
Test name
Test status
Simulation time 62585515500 ps
CPU time 155.76 seconds
Started Jun 05 06:03:14 PM PDT 24
Finished Jun 05 06:05:51 PM PDT 24
Peak memory 292840 kb
Host smart-f83523ad-165c-4239-aef4-ae9da6777121
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440180077 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.440180077
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.3844959376
Short name T568
Test name
Test status
Simulation time 6797189700 ps
CPU time 70.76 seconds
Started Jun 05 06:03:12 PM PDT 24
Finished Jun 05 06:04:24 PM PDT 24
Peak memory 259920 kb
Host smart-566fc547-70b7-4b76-b958-4cf95a197cb2
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844959376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3
844959376
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.938550493
Short name T138
Test name
Test status
Simulation time 46640300 ps
CPU time 13.61 seconds
Started Jun 05 06:03:13 PM PDT 24
Finished Jun 05 06:03:27 PM PDT 24
Peak memory 260184 kb
Host smart-e6bce049-39dc-4876-84be-3aec810b55a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938550493 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.938550493
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.937506801
Short name T105
Test name
Test status
Simulation time 36775629100 ps
CPU time 475.68 seconds
Started Jun 05 06:03:14 PM PDT 24
Finished Jun 05 06:11:10 PM PDT 24
Peak memory 274092 kb
Host smart-fc752092-3751-436b-bbcd-5cde980d89b6
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937506801 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_mp_regions.937506801
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.2614216922
Short name T908
Test name
Test status
Simulation time 508930000 ps
CPU time 132.1 seconds
Started Jun 05 06:03:14 PM PDT 24
Finished Jun 05 06:05:27 PM PDT 24
Peak memory 264144 kb
Host smart-621fc28e-15d7-4f7a-8125-878ab250bb41
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614216922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.2614216922
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.2862196440
Short name T848
Test name
Test status
Simulation time 45404700 ps
CPU time 70.14 seconds
Started Jun 05 06:03:10 PM PDT 24
Finished Jun 05 06:04:21 PM PDT 24
Peak memory 262108 kb
Host smart-e189ed0f-48e3-47b4-adc8-a7339bdf8a2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2862196440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.2862196440
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.2289697584
Short name T825
Test name
Test status
Simulation time 2857959300 ps
CPU time 222.14 seconds
Started Jun 05 06:03:13 PM PDT 24
Finished Jun 05 06:06:55 PM PDT 24
Peak memory 258880 kb
Host smart-5fc76d6b-e28c-4a2e-892b-7bb29e05d12c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289697584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.2289697584
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.3095583976
Short name T606
Test name
Test status
Simulation time 1045646200 ps
CPU time 1116.09 seconds
Started Jun 05 06:03:10 PM PDT 24
Finished Jun 05 06:21:47 PM PDT 24
Peak memory 285964 kb
Host smart-ee928293-8e02-4d4e-80f6-7dc2437928d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095583976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.3095583976
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.2244755161
Short name T828
Test name
Test status
Simulation time 77849800 ps
CPU time 31.22 seconds
Started Jun 05 06:03:14 PM PDT 24
Finished Jun 05 06:03:46 PM PDT 24
Peak memory 273128 kb
Host smart-7a297759-9662-4bdb-a657-1940618edac6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244755161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.2244755161
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.3759330775
Short name T528
Test name
Test status
Simulation time 859026200 ps
CPU time 111.64 seconds
Started Jun 05 06:03:13 PM PDT 24
Finished Jun 05 06:05:06 PM PDT 24
Peak memory 281280 kb
Host smart-036e5f30-1bad-49a4-ace5-7c53083e34ec
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759330775 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.3759330775
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.2317842177
Short name T616
Test name
Test status
Simulation time 3458708100 ps
CPU time 558.6 seconds
Started Jun 05 06:03:12 PM PDT 24
Finished Jun 05 06:12:31 PM PDT 24
Peak memory 309160 kb
Host smart-66bd15e9-3e4d-4885-8b1a-bc2a405bb732
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317842177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_rw.2317842177
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.1677589651
Short name T268
Test name
Test status
Simulation time 68095900 ps
CPU time 30.44 seconds
Started Jun 05 06:03:12 PM PDT 24
Finished Jun 05 06:03:43 PM PDT 24
Peak memory 273168 kb
Host smart-7b2b2cb9-91ff-4780-8630-da29dfd134af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677589651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.1677589651
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.2661701294
Short name T590
Test name
Test status
Simulation time 28813500 ps
CPU time 31.73 seconds
Started Jun 05 06:03:12 PM PDT 24
Finished Jun 05 06:03:45 PM PDT 24
Peak memory 274444 kb
Host smart-cb7b9721-540f-423c-a583-fa7f0109874d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661701294 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.2661701294
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.2512052132
Short name T655
Test name
Test status
Simulation time 114782900 ps
CPU time 51.83 seconds
Started Jun 05 06:03:06 PM PDT 24
Finished Jun 05 06:03:58 PM PDT 24
Peak memory 270360 kb
Host smart-ec3858a4-2ff8-4c35-93fa-5aad5a7fb1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512052132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.2512052132
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.572301032
Short name T533
Test name
Test status
Simulation time 2678459400 ps
CPU time 145.7 seconds
Started Jun 05 06:03:13 PM PDT 24
Finished Jun 05 06:05:39 PM PDT 24
Peak memory 264800 kb
Host smart-7157e363-c648-494f-a81b-da0dad1f4783
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572301032 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.flash_ctrl_wo.572301032
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.1159151585
Short name T1021
Test name
Test status
Simulation time 20066400 ps
CPU time 13.25 seconds
Started Jun 05 06:03:28 PM PDT 24
Finished Jun 05 06:03:42 PM PDT 24
Peak memory 264792 kb
Host smart-55d0b70a-ba06-4410-a4ae-0b31bdfb5024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159151585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
1159151585
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.4257061576
Short name T422
Test name
Test status
Simulation time 174572000 ps
CPU time 15.47 seconds
Started Jun 05 06:03:27 PM PDT 24
Finished Jun 05 06:03:44 PM PDT 24
Peak memory 275884 kb
Host smart-7f1bfcd0-51ac-482b-98a9-c794715cc6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257061576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.4257061576
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.4130971608
Short name T172
Test name
Test status
Simulation time 10018558900 ps
CPU time 88.93 seconds
Started Jun 05 06:03:29 PM PDT 24
Finished Jun 05 06:04:59 PM PDT 24
Peak memory 321656 kb
Host smart-e813e848-cb00-4ac7-b930-1a86544d3d6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130971608 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.4130971608
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.3451427807
Short name T832
Test name
Test status
Simulation time 65379200 ps
CPU time 13.4 seconds
Started Jun 05 06:03:27 PM PDT 24
Finished Jun 05 06:03:41 PM PDT 24
Peak memory 264464 kb
Host smart-e765d8c2-577b-4482-9bef-e69483607c0f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451427807 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.3451427807
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.534743848
Short name T412
Test name
Test status
Simulation time 2196627400 ps
CPU time 68.85 seconds
Started Jun 05 06:03:22 PM PDT 24
Finished Jun 05 06:04:32 PM PDT 24
Peak memory 262276 kb
Host smart-163d616d-e7d6-49c3-a606-bbadcc07cc58
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534743848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_h
w_sec_otp.534743848
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.2698700800
Short name T443
Test name
Test status
Simulation time 2888876600 ps
CPU time 142.76 seconds
Started Jun 05 06:03:23 PM PDT 24
Finished Jun 05 06:05:46 PM PDT 24
Peak memory 297404 kb
Host smart-aaf60dec-28c0-4f5b-b1b5-120506b97330
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698700800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.2698700800
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.1502474113
Short name T583
Test name
Test status
Simulation time 5803457100 ps
CPU time 144.8 seconds
Started Jun 05 06:03:23 PM PDT 24
Finished Jun 05 06:05:48 PM PDT 24
Peak memory 292520 kb
Host smart-697f518a-eaec-4223-85aa-911bdd90d067
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502474113 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.1502474113
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.4023065753
Short name T341
Test name
Test status
Simulation time 1946450500 ps
CPU time 87.62 seconds
Started Jun 05 06:03:21 PM PDT 24
Finished Jun 05 06:04:49 PM PDT 24
Peak memory 259548 kb
Host smart-f6059934-5ffe-4d16-a46f-40e6b1daca4c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023065753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.4
023065753
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1085086392
Short name T286
Test name
Test status
Simulation time 47033800 ps
CPU time 13.6 seconds
Started Jun 05 06:03:25 PM PDT 24
Finished Jun 05 06:03:39 PM PDT 24
Peak memory 264760 kb
Host smart-68a18f07-51bb-468f-a178-56a3afa2b9c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085086392 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.1085086392
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.3693249935
Short name T45
Test name
Test status
Simulation time 10176186100 ps
CPU time 238.98 seconds
Started Jun 05 06:03:19 PM PDT 24
Finished Jun 05 06:07:19 PM PDT 24
Peak memory 274096 kb
Host smart-bc765f04-7016-4d43-9512-aed85ddfa5ff
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693249935 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.3693249935
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.2091803723
Short name T491
Test name
Test status
Simulation time 142116300 ps
CPU time 135.89 seconds
Started Jun 05 06:03:23 PM PDT 24
Finished Jun 05 06:05:39 PM PDT 24
Peak memory 259780 kb
Host smart-788f6ffa-dd81-435c-986b-fdafbaa519e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091803723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.2091803723
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.2416413211
Short name T468
Test name
Test status
Simulation time 36538000 ps
CPU time 112.33 seconds
Started Jun 05 06:03:19 PM PDT 24
Finished Jun 05 06:05:11 PM PDT 24
Peak memory 261460 kb
Host smart-f4d06891-494f-4f27-8df6-f236320475dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416413211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.2416413211
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.1965092897
Short name T1064
Test name
Test status
Simulation time 20745800 ps
CPU time 13.47 seconds
Started Jun 05 06:03:20 PM PDT 24
Finished Jun 05 06:03:34 PM PDT 24
Peak memory 258356 kb
Host smart-f2f99b50-dd11-47b8-88d4-f65e0b8625cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965092897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.1965092897
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.2611338266
Short name T118
Test name
Test status
Simulation time 64328700 ps
CPU time 564.07 seconds
Started Jun 05 06:03:20 PM PDT 24
Finished Jun 05 06:12:44 PM PDT 24
Peak memory 283196 kb
Host smart-dafed4aa-3195-4fab-a013-1ecd5525e016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611338266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2611338266
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.2372053097
Short name T935
Test name
Test status
Simulation time 103876500 ps
CPU time 33.4 seconds
Started Jun 05 06:03:26 PM PDT 24
Finished Jun 05 06:04:00 PM PDT 24
Peak memory 274144 kb
Host smart-f0d42de0-b5e1-453d-ae1f-1eb42046ec07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372053097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.2372053097
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.1587630575
Short name T947
Test name
Test status
Simulation time 1676592500 ps
CPU time 96.14 seconds
Started Jun 05 06:03:21 PM PDT 24
Finished Jun 05 06:04:57 PM PDT 24
Peak memory 281252 kb
Host smart-12d88cf5-f764-4893-804d-c8a00d1cf587
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587630575 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.flash_ctrl_ro.1587630575
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.2245661328
Short name T276
Test name
Test status
Simulation time 44518325000 ps
CPU time 613.88 seconds
Started Jun 05 06:03:21 PM PDT 24
Finished Jun 05 06:13:35 PM PDT 24
Peak memory 313396 kb
Host smart-0306a19c-78c1-4352-b651-f00ade982118
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245661328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.flash_ctrl_rw.2245661328
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.921027380
Short name T992
Test name
Test status
Simulation time 71508000 ps
CPU time 31.33 seconds
Started Jun 05 06:03:22 PM PDT 24
Finished Jun 05 06:03:54 PM PDT 24
Peak memory 273124 kb
Host smart-bbd9dac5-d6d0-43a9-b0c1-0957d8c173db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921027380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_rw_evict.921027380
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.497705937
Short name T380
Test name
Test status
Simulation time 2646356500 ps
CPU time 70.57 seconds
Started Jun 05 06:03:25 PM PDT 24
Finished Jun 05 06:04:35 PM PDT 24
Peak memory 263124 kb
Host smart-bbb1d75e-2d3d-4de0-bfc9-6fe655f183c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497705937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.497705937
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.4015544105
Short name T877
Test name
Test status
Simulation time 73346600 ps
CPU time 146.18 seconds
Started Jun 05 06:03:21 PM PDT 24
Finished Jun 05 06:05:48 PM PDT 24
Peak memory 276136 kb
Host smart-a45f8838-ab2d-4e42-9617-b8dc11efecbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015544105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.4015544105
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.3698468071
Short name T1068
Test name
Test status
Simulation time 1871246500 ps
CPU time 127.16 seconds
Started Jun 05 06:03:22 PM PDT 24
Finished Jun 05 06:05:29 PM PDT 24
Peak memory 259240 kb
Host smart-e5909560-5904-4da2-9b63-4b811d4272a7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698468071 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.flash_ctrl_wo.3698468071
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.3781635089
Short name T1059
Test name
Test status
Simulation time 28864000 ps
CPU time 13.43 seconds
Started Jun 05 06:03:36 PM PDT 24
Finished Jun 05 06:03:50 PM PDT 24
Peak memory 264796 kb
Host smart-c9359fb7-9e51-4edb-9765-56c1061b4ad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781635089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
3781635089
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.280125807
Short name T394
Test name
Test status
Simulation time 39715200 ps
CPU time 13.43 seconds
Started Jun 05 06:03:36 PM PDT 24
Finished Jun 05 06:03:49 PM PDT 24
Peak memory 275540 kb
Host smart-6a7cdebe-de21-4359-9384-753755a213a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280125807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.280125807
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.2009932408
Short name T184
Test name
Test status
Simulation time 16261200 ps
CPU time 21.64 seconds
Started Jun 05 06:03:35 PM PDT 24
Finished Jun 05 06:03:57 PM PDT 24
Peak memory 273120 kb
Host smart-f615f8a1-127e-48dd-9b9c-6d64b0ef0792
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009932408 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.2009932408
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2893743312
Short name T901
Test name
Test status
Simulation time 10020492500 ps
CPU time 73.57 seconds
Started Jun 05 06:03:33 PM PDT 24
Finished Jun 05 06:04:47 PM PDT 24
Peak memory 285896 kb
Host smart-ebf0a97f-8c60-4492-a9ee-320368695135
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893743312 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.2893743312
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.3892194274
Short name T1083
Test name
Test status
Simulation time 21352700 ps
CPU time 13.69 seconds
Started Jun 05 06:03:34 PM PDT 24
Finished Jun 05 06:03:49 PM PDT 24
Peak memory 264792 kb
Host smart-bd17ab29-4482-4c66-a6f8-bf2d1135788d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892194274 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.3892194274
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.1568108340
Short name T849
Test name
Test status
Simulation time 480331576300 ps
CPU time 908.16 seconds
Started Jun 05 06:03:30 PM PDT 24
Finished Jun 05 06:18:39 PM PDT 24
Peak memory 264056 kb
Host smart-83308300-9cfd-4a85-9bfb-1520cab400dc
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568108340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.1568108340
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.1503943250
Short name T761
Test name
Test status
Simulation time 3417651500 ps
CPU time 101.76 seconds
Started Jun 05 06:03:28 PM PDT 24
Finished Jun 05 06:05:11 PM PDT 24
Peak memory 262308 kb
Host smart-6ca19483-9d42-4352-8122-231b924f8a5c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503943250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.1503943250
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.2861135465
Short name T608
Test name
Test status
Simulation time 3576701600 ps
CPU time 169.78 seconds
Started Jun 05 06:03:35 PM PDT 24
Finished Jun 05 06:06:25 PM PDT 24
Peak memory 292108 kb
Host smart-dca6edd6-ddff-4485-8a65-f6a947c4d55c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861135465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.2861135465
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3397286201
Short name T916
Test name
Test status
Simulation time 49827100600 ps
CPU time 309.19 seconds
Started Jun 05 06:03:34 PM PDT 24
Finished Jun 05 06:08:43 PM PDT 24
Peak memory 291376 kb
Host smart-65bdf1e2-5d22-4a7a-8868-71cd89d0bb79
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397286201 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.3397286201
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.4087562008
Short name T688
Test name
Test status
Simulation time 6840066900 ps
CPU time 63.87 seconds
Started Jun 05 06:03:29 PM PDT 24
Finished Jun 05 06:04:34 PM PDT 24
Peak memory 260380 kb
Host smart-b67d2cc3-1c9e-46f6-9865-6d08752d6e8c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087562008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.4
087562008
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2235775057
Short name T968
Test name
Test status
Simulation time 26330900 ps
CPU time 14.17 seconds
Started Jun 05 06:03:34 PM PDT 24
Finished Jun 05 06:03:49 PM PDT 24
Peak memory 259252 kb
Host smart-2edd21c7-8547-42a3-ab0c-d816ddccecd3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235775057 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.2235775057
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.3352982354
Short name T756
Test name
Test status
Simulation time 40368300 ps
CPU time 109.93 seconds
Started Jun 05 06:03:28 PM PDT 24
Finished Jun 05 06:05:19 PM PDT 24
Peak memory 263784 kb
Host smart-9e93c80f-f301-45f6-921d-a04f7d59e5b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352982354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.3352982354
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.1584892904
Short name T824
Test name
Test status
Simulation time 52802100 ps
CPU time 158.38 seconds
Started Jun 05 06:03:27 PM PDT 24
Finished Jun 05 06:06:06 PM PDT 24
Peak memory 261460 kb
Host smart-17a0442f-5ad7-45c3-bb30-d9ffbca9e10f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1584892904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1584892904
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.732195648
Short name T856
Test name
Test status
Simulation time 2382086800 ps
CPU time 192.25 seconds
Started Jun 05 06:03:34 PM PDT 24
Finished Jun 05 06:06:47 PM PDT 24
Peak memory 264816 kb
Host smart-64f0d449-66e9-4b77-8816-308cb86603ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732195648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_res
et.732195648
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.197653573
Short name T910
Test name
Test status
Simulation time 946775600 ps
CPU time 275.75 seconds
Started Jun 05 06:03:27 PM PDT 24
Finished Jun 05 06:08:04 PM PDT 24
Peak memory 281208 kb
Host smart-55029676-9f5e-42c8-ace6-3d142bde03e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197653573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.197653573
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.808902389
Short name T322
Test name
Test status
Simulation time 980458600 ps
CPU time 35.54 seconds
Started Jun 05 06:03:35 PM PDT 24
Finished Jun 05 06:04:11 PM PDT 24
Peak memory 273132 kb
Host smart-044f5ffa-765e-40be-9aab-824f2f7b9072
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808902389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_re_evict.808902389
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.2194302788
Short name T577
Test name
Test status
Simulation time 1147732600 ps
CPU time 112.85 seconds
Started Jun 05 06:03:28 PM PDT 24
Finished Jun 05 06:05:22 PM PDT 24
Peak memory 296752 kb
Host smart-92f93b4f-f9ec-4ad0-87c9-2350165a4697
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194302788 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.2194302788
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.1976267352
Short name T844
Test name
Test status
Simulation time 48479929200 ps
CPU time 511.6 seconds
Started Jun 05 06:03:28 PM PDT 24
Finished Jun 05 06:12:01 PM PDT 24
Peak memory 310084 kb
Host smart-ca1d3aac-4c84-49d3-8b86-9550f89ee0e1
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976267352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.flash_ctrl_rw.1976267352
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.1136305283
Short name T772
Test name
Test status
Simulation time 121850900 ps
CPU time 31.59 seconds
Started Jun 05 06:03:36 PM PDT 24
Finished Jun 05 06:04:08 PM PDT 24
Peak memory 274440 kb
Host smart-d8d23e86-2568-4ec4-92d5-2d026d29dc52
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136305283 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.1136305283
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.3756731426
Short name T932
Test name
Test status
Simulation time 2748762700 ps
CPU time 67.64 seconds
Started Jun 05 06:03:33 PM PDT 24
Finished Jun 05 06:04:41 PM PDT 24
Peak memory 262640 kb
Host smart-0cb92cb6-437d-493a-9450-244b2236f00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756731426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.3756731426
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.1051898079
Short name T74
Test name
Test status
Simulation time 3966288100 ps
CPU time 180.51 seconds
Started Jun 05 06:03:27 PM PDT 24
Finished Jun 05 06:06:29 PM PDT 24
Peak memory 281220 kb
Host smart-8083f389-30e6-4cef-a324-ebfa51805b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051898079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.1051898079
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.1570203874
Short name T744
Test name
Test status
Simulation time 2120414500 ps
CPU time 158.24 seconds
Started Jun 05 06:03:29 PM PDT 24
Finished Jun 05 06:06:08 PM PDT 24
Peak memory 259152 kb
Host smart-06499e21-3786-4bf0-97ed-f1c52d325a51
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570203874 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.1570203874
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.4123261785
Short name T882
Test name
Test status
Simulation time 64514800 ps
CPU time 14.26 seconds
Started Jun 05 06:03:49 PM PDT 24
Finished Jun 05 06:04:03 PM PDT 24
Peak memory 257868 kb
Host smart-6e998682-4971-4a5f-a63c-d4b034d1ae93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123261785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
4123261785
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.4003871292
Short name T586
Test name
Test status
Simulation time 16719400 ps
CPU time 15.78 seconds
Started Jun 05 06:03:54 PM PDT 24
Finished Jun 05 06:04:10 PM PDT 24
Peak memory 275540 kb
Host smart-0a9518ef-6640-4c05-8d7e-b13654f821ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003871292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.4003871292
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.2388489946
Short name T842
Test name
Test status
Simulation time 49062600 ps
CPU time 21.9 seconds
Started Jun 05 06:03:47 PM PDT 24
Finished Jun 05 06:04:09 PM PDT 24
Peak memory 273092 kb
Host smart-013030b7-45b8-46e7-bd5b-4d5805f79141
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388489946 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.2388489946
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.757883544
Short name T283
Test name
Test status
Simulation time 10034701600 ps
CPU time 54.37 seconds
Started Jun 05 06:03:49 PM PDT 24
Finished Jun 05 06:04:44 PM PDT 24
Peak memory 285920 kb
Host smart-5b0f9a7f-a733-4718-96d1-65d063f9f84c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757883544 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.757883544
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.3436299205
Short name T281
Test name
Test status
Simulation time 85453600 ps
CPU time 13.46 seconds
Started Jun 05 06:03:53 PM PDT 24
Finished Jun 05 06:04:07 PM PDT 24
Peak memory 264992 kb
Host smart-0545fd33-c29a-48c6-ab48-4c058a705040
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436299205 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.3436299205
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.4222013071
Short name T163
Test name
Test status
Simulation time 40120867900 ps
CPU time 835.01 seconds
Started Jun 05 06:03:43 PM PDT 24
Finished Jun 05 06:17:38 PM PDT 24
Peak memory 263592 kb
Host smart-8eca4b5d-2ec9-4d31-bd01-e5e180ea2b1b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222013071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.4222013071
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.2393928952
Short name T857
Test name
Test status
Simulation time 6360953600 ps
CPU time 108.09 seconds
Started Jun 05 06:03:43 PM PDT 24
Finished Jun 05 06:05:31 PM PDT 24
Peak memory 262372 kb
Host smart-6a76c6ea-ab93-406e-891d-c4dd458ecfc5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393928952 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.2393928952
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.3424366614
Short name T335
Test name
Test status
Simulation time 894361900 ps
CPU time 131.76 seconds
Started Jun 05 06:03:43 PM PDT 24
Finished Jun 05 06:05:55 PM PDT 24
Peak memory 290480 kb
Host smart-d8585a11-c3c7-4330-8594-8335f77cf816
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424366614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.3424366614
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.1655116982
Short name T337
Test name
Test status
Simulation time 42198215900 ps
CPU time 146.87 seconds
Started Jun 05 06:03:45 PM PDT 24
Finished Jun 05 06:06:12 PM PDT 24
Peak memory 293112 kb
Host smart-e65c2dad-db17-4f18-9d0f-243009497daf
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655116982 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.1655116982
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.2793898659
Short name T581
Test name
Test status
Simulation time 8368750100 ps
CPU time 71.41 seconds
Started Jun 05 06:03:48 PM PDT 24
Finished Jun 05 06:05:00 PM PDT 24
Peak memory 259740 kb
Host smart-b43813d4-98f6-45be-83ee-87db1c0ca9bb
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793898659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2
793898659
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.3701787328
Short name T1011
Test name
Test status
Simulation time 45740900 ps
CPU time 13.33 seconds
Started Jun 05 06:03:52 PM PDT 24
Finished Jun 05 06:04:06 PM PDT 24
Peak memory 264812 kb
Host smart-c48e1e86-ad10-4928-a8dd-8f13b2607179
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701787328 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.3701787328
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.768833845
Short name T766
Test name
Test status
Simulation time 9361777800 ps
CPU time 183.41 seconds
Started Jun 05 06:03:45 PM PDT 24
Finished Jun 05 06:06:49 PM PDT 24
Peak memory 262056 kb
Host smart-26038015-6da4-47c4-aef8-0e6c381af80d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768833845 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_mp_regions.768833845
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.1767107073
Short name T141
Test name
Test status
Simulation time 68742400 ps
CPU time 110.75 seconds
Started Jun 05 06:03:45 PM PDT 24
Finished Jun 05 06:05:37 PM PDT 24
Peak memory 264160 kb
Host smart-f77ab123-b8e1-49d8-8460-e1d4be2a2540
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767107073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.1767107073
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.2403415291
Short name T497
Test name
Test status
Simulation time 773628800 ps
CPU time 485 seconds
Started Jun 05 06:03:42 PM PDT 24
Finished Jun 05 06:11:48 PM PDT 24
Peak memory 261412 kb
Host smart-dc14ac39-ccd6-47fc-aca1-ba3190d1b1b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2403415291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.2403415291
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.3399301241
Short name T622
Test name
Test status
Simulation time 30492200 ps
CPU time 13.47 seconds
Started Jun 05 06:03:42 PM PDT 24
Finished Jun 05 06:03:56 PM PDT 24
Peak memory 258440 kb
Host smart-0a39ca6e-6fba-4428-8f7e-feff3e8c0105
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399301241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.3399301241
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.1942697139
Short name T852
Test name
Test status
Simulation time 71163700 ps
CPU time 129.96 seconds
Started Jun 05 06:03:43 PM PDT 24
Finished Jun 05 06:05:53 PM PDT 24
Peak memory 277768 kb
Host smart-4e69ffc9-7cac-4f6c-88ed-94824a4698fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942697139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1942697139
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.3497889432
Short name T492
Test name
Test status
Simulation time 209521000 ps
CPU time 34.34 seconds
Started Jun 05 06:03:43 PM PDT 24
Finished Jun 05 06:04:18 PM PDT 24
Peak memory 266976 kb
Host smart-2c8200eb-9fb1-4db7-9bb2-81e2b7f6748c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497889432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.3497889432
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.2091253747
Short name T214
Test name
Test status
Simulation time 543312800 ps
CPU time 111.62 seconds
Started Jun 05 06:03:44 PM PDT 24
Finished Jun 05 06:05:36 PM PDT 24
Peak memory 281380 kb
Host smart-070c1721-2e95-4518-8c08-efcf4c8c56df
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091253747 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.flash_ctrl_ro.2091253747
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.1707154731
Short name T216
Test name
Test status
Simulation time 5990253700 ps
CPU time 535.01 seconds
Started Jun 05 06:03:43 PM PDT 24
Finished Jun 05 06:12:38 PM PDT 24
Peak memory 309516 kb
Host smart-ec9afe44-8b39-41d5-b1ef-adbd44d0ceb4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707154731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.1707154731
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.3623165745
Short name T207
Test name
Test status
Simulation time 50712600 ps
CPU time 31.18 seconds
Started Jun 05 06:03:43 PM PDT 24
Finished Jun 05 06:04:15 PM PDT 24
Peak memory 273108 kb
Host smart-b53081c0-7186-4595-bedf-1e0fb4a522d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623165745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.3623165745
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.2932003765
Short name T574
Test name
Test status
Simulation time 28177300 ps
CPU time 31.01 seconds
Started Jun 05 06:03:44 PM PDT 24
Finished Jun 05 06:04:15 PM PDT 24
Peak memory 275744 kb
Host smart-0ad29a03-dd9c-4467-a1df-2690946c72f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932003765 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.2932003765
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.2185858178
Short name T400
Test name
Test status
Simulation time 1194526300 ps
CPU time 67.42 seconds
Started Jun 05 06:03:50 PM PDT 24
Finished Jun 05 06:04:58 PM PDT 24
Peak memory 262132 kb
Host smart-3fda8f6f-47d0-4885-831d-e522dfdeb820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185858178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.2185858178
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.2893659386
Short name T779
Test name
Test status
Simulation time 99133700 ps
CPU time 142.86 seconds
Started Jun 05 06:03:34 PM PDT 24
Finished Jun 05 06:05:57 PM PDT 24
Peak memory 276012 kb
Host smart-bd545b3f-e8c0-4d2a-966f-2175c7f7d725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893659386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.2893659386
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.2979180507
Short name T440
Test name
Test status
Simulation time 4852145100 ps
CPU time 164.62 seconds
Started Jun 05 06:03:42 PM PDT 24
Finished Jun 05 06:06:27 PM PDT 24
Peak memory 258908 kb
Host smart-aea45812-5119-4f0e-b4ee-e8b6b0b7af2a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979180507 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.flash_ctrl_wo.2979180507
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.564444532
Short name T46
Test name
Test status
Simulation time 24818600 ps
CPU time 13.72 seconds
Started Jun 05 06:01:27 PM PDT 24
Finished Jun 05 06:01:41 PM PDT 24
Peak memory 264796 kb
Host smart-e3e7e235-e77d-45c9-83c6-b58c13255852
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564444532 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.564444532
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.4027649306
Short name T808
Test name
Test status
Simulation time 175780400 ps
CPU time 13.72 seconds
Started Jun 05 06:01:22 PM PDT 24
Finished Jun 05 06:01:37 PM PDT 24
Peak memory 257804 kb
Host smart-61ca37c3-6996-4d4f-b3ed-2a1dc3c641dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027649306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.4
027649306
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.3106043040
Short name T435
Test name
Test status
Simulation time 14183300 ps
CPU time 15.6 seconds
Started Jun 05 06:01:28 PM PDT 24
Finished Jun 05 06:01:44 PM PDT 24
Peak memory 275560 kb
Host smart-4dbc7032-3f27-4440-9721-e199719fa1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106043040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.3106043040
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.882403394
Short name T56
Test name
Test status
Simulation time 120223000 ps
CPU time 103.83 seconds
Started Jun 05 06:01:23 PM PDT 24
Finished Jun 05 06:03:07 PM PDT 24
Peak memory 272384 kb
Host smart-5905f128-6ab3-4850-8752-69167fc0d31e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882403394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_derr_detect.882403394
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.3432349406
Short name T809
Test name
Test status
Simulation time 58035400 ps
CPU time 20.99 seconds
Started Jun 05 06:01:26 PM PDT 24
Finished Jun 05 06:01:48 PM PDT 24
Peak memory 273180 kb
Host smart-438fe6ff-d56b-4ba6-abb8-77d22224396f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432349406 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.3432349406
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.4207705642
Short name T550
Test name
Test status
Simulation time 5862116500 ps
CPU time 2300.53 seconds
Started Jun 05 06:01:09 PM PDT 24
Finished Jun 05 06:39:31 PM PDT 24
Peak memory 262384 kb
Host smart-c84ccd00-74ee-491f-9de0-69203c1d118b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207705642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.4207705642
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.1757922517
Short name T177
Test name
Test status
Simulation time 3982822200 ps
CPU time 2612.37 seconds
Started Jun 05 06:01:26 PM PDT 24
Finished Jun 05 06:44:59 PM PDT 24
Peak memory 264828 kb
Host smart-1a628189-f3e7-45fb-b06c-518812097b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757922517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.1757922517
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.2708261981
Short name T51
Test name
Test status
Simulation time 407715600 ps
CPU time 21.42 seconds
Started Jun 05 06:01:18 PM PDT 24
Finished Jun 05 06:01:40 PM PDT 24
Peak memory 264896 kb
Host smart-92812099-4a43-44cb-b275-5748f2b6ec0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708261981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.2708261981
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.2749965006
Short name T106
Test name
Test status
Simulation time 87347041100 ps
CPU time 2730 seconds
Started Jun 05 06:01:17 PM PDT 24
Finished Jun 05 06:46:47 PM PDT 24
Peak memory 261808 kb
Host smart-f1abf71c-d920-4a05-80bd-16b37da9fc88
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749965006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.2749965006
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.1256648529
Short name T3
Test name
Test status
Simulation time 39456500 ps
CPU time 56.03 seconds
Started Jun 05 06:01:15 PM PDT 24
Finished Jun 05 06:02:11 PM PDT 24
Peak memory 264860 kb
Host smart-fce3eba1-fac3-4f19-9dd6-27fa9be39a73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1256648529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.1256648529
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.1853817159
Short name T942
Test name
Test status
Simulation time 15424800 ps
CPU time 13.45 seconds
Started Jun 05 06:01:29 PM PDT 24
Finished Jun 05 06:01:43 PM PDT 24
Peak memory 264792 kb
Host smart-38479f86-8d60-45a2-85e8-89b6be25bda5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853817159 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.1853817159
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.2416375972
Short name T735
Test name
Test status
Simulation time 334813448700 ps
CPU time 2029.22 seconds
Started Jun 05 06:01:16 PM PDT 24
Finished Jun 05 06:35:06 PM PDT 24
Peak memory 263668 kb
Host smart-8e74512b-300e-45e2-afc2-a272230a5aa1
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416375972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.2416375972
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.324538338
Short name T928
Test name
Test status
Simulation time 160177157700 ps
CPU time 798.45 seconds
Started Jun 05 06:01:09 PM PDT 24
Finished Jun 05 06:14:28 PM PDT 24
Peak memory 264108 kb
Host smart-baef84d8-de98-4ae5-820a-1754b20983cc
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324538338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_hw_rma_reset.324538338
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.1730136018
Short name T311
Test name
Test status
Simulation time 9248908800 ps
CPU time 95.07 seconds
Started Jun 05 06:01:18 PM PDT 24
Finished Jun 05 06:02:54 PM PDT 24
Peak memory 262308 kb
Host smart-51c7d956-b899-4952-8ff0-d97512ac30f9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730136018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.1730136018
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.3331774419
Short name T784
Test name
Test status
Simulation time 1335517900 ps
CPU time 122.07 seconds
Started Jun 05 06:01:22 PM PDT 24
Finished Jun 05 06:03:25 PM PDT 24
Peak memory 289444 kb
Host smart-dbf98c19-768d-4f97-b532-3e61878f86ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331774419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.3331774419
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3896947198
Short name T562
Test name
Test status
Simulation time 33312030400 ps
CPU time 287.86 seconds
Started Jun 05 06:01:21 PM PDT 24
Finished Jun 05 06:06:10 PM PDT 24
Peak memory 292376 kb
Host smart-051ea657-cfc9-40e7-bf72-4d5e49b3d326
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896947198 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.3896947198
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.717352739
Short name T770
Test name
Test status
Simulation time 2881590400 ps
CPU time 63 seconds
Started Jun 05 06:01:15 PM PDT 24
Finished Jun 05 06:02:18 PM PDT 24
Peak memory 259788 kb
Host smart-86da34ee-768a-4691-862d-a3647aa8615c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717352739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_intr_wr.717352739
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1835839093
Short name T748
Test name
Test status
Simulation time 17782715900 ps
CPU time 146.95 seconds
Started Jun 05 06:01:19 PM PDT 24
Finished Jun 05 06:03:46 PM PDT 24
Peak memory 259940 kb
Host smart-ad0b2d50-d963-4a28-8a46-2b4da282dbce
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183
5839093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1835839093
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.3485955811
Short name T483
Test name
Test status
Simulation time 987514000 ps
CPU time 86.81 seconds
Started Jun 05 06:01:08 PM PDT 24
Finished Jun 05 06:02:36 PM PDT 24
Peak memory 260560 kb
Host smart-09870b9e-5871-4a95-bb54-b84a5edbc4cf
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485955811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3485955811
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.1392916295
Short name T137
Test name
Test status
Simulation time 25514700 ps
CPU time 13.57 seconds
Started Jun 05 06:01:23 PM PDT 24
Finished Jun 05 06:01:37 PM PDT 24
Peak memory 260132 kb
Host smart-3fde5216-09c6-46d5-bf0f-0fee8ec79bdd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392916295 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.1392916295
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.1603925286
Short name T122
Test name
Test status
Simulation time 13663665700 ps
CPU time 73.23 seconds
Started Jun 05 06:01:20 PM PDT 24
Finished Jun 05 06:02:33 PM PDT 24
Peak memory 259792 kb
Host smart-230b821e-922b-430e-bcff-67bf2854f94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603925286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.1603925286
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.986949048
Short name T116
Test name
Test status
Simulation time 13183264000 ps
CPU time 314.75 seconds
Started Jun 05 06:01:11 PM PDT 24
Finished Jun 05 06:06:26 PM PDT 24
Peak memory 274116 kb
Host smart-4c998afa-13c2-4c1f-a106-072e6f3d6e28
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986949048 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_mp_regions.986949048
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.2344715912
Short name T695
Test name
Test status
Simulation time 102569500 ps
CPU time 114.77 seconds
Started Jun 05 06:01:25 PM PDT 24
Finished Jun 05 06:03:20 PM PDT 24
Peak memory 260008 kb
Host smart-9293fe71-ff7d-4f4a-b1bb-0fa4691d3290
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344715912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.2344715912
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.1321941004
Short name T63
Test name
Test status
Simulation time 107527300 ps
CPU time 13.74 seconds
Started Jun 05 06:01:22 PM PDT 24
Finished Jun 05 06:01:36 PM PDT 24
Peak memory 276448 kb
Host smart-f356d49d-4492-4293-b645-2f1ef9806ad4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1321941004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.1321941004
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.3949835150
Short name T475
Test name
Test status
Simulation time 510265000 ps
CPU time 189.16 seconds
Started Jun 05 06:01:25 PM PDT 24
Finished Jun 05 06:04:35 PM PDT 24
Peak memory 262240 kb
Host smart-7e913a1b-425c-4dd5-8e90-06da1dc63a01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949835150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.3949835150
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.3456873757
Short name T220
Test name
Test status
Simulation time 42497300 ps
CPU time 13.81 seconds
Started Jun 05 06:01:15 PM PDT 24
Finished Jun 05 06:01:30 PM PDT 24
Peak memory 264972 kb
Host smart-bf123951-3423-4416-88e0-69fd70a89640
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456873757 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.3456873757
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.2122431924
Short name T478
Test name
Test status
Simulation time 54929100 ps
CPU time 13.65 seconds
Started Jun 05 06:01:30 PM PDT 24
Finished Jun 05 06:01:44 PM PDT 24
Peak memory 264824 kb
Host smart-f36ad3e7-7414-4927-adbc-2cd187d4b1ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122431924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.2122431924
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.2895393986
Short name T1100
Test name
Test status
Simulation time 3511940600 ps
CPU time 1064.79 seconds
Started Jun 05 06:01:25 PM PDT 24
Finished Jun 05 06:19:10 PM PDT 24
Peak memory 283912 kb
Host smart-70d75d72-0fea-4c1f-821a-0efa4b2d5a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895393986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.2895393986
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.2425638130
Short name T646
Test name
Test status
Simulation time 226751900 ps
CPU time 102.69 seconds
Started Jun 05 06:01:12 PM PDT 24
Finished Jun 05 06:02:55 PM PDT 24
Peak memory 264964 kb
Host smart-79c88ced-acaf-4ad6-a7ca-71435e8f4c37
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2425638130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.2425638130
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.4102118584
Short name T1030
Test name
Test status
Simulation time 64912500 ps
CPU time 29.81 seconds
Started Jun 05 06:01:17 PM PDT 24
Finished Jun 05 06:01:47 PM PDT 24
Peak memory 279072 kb
Host smart-bba87ea6-381d-4552-a598-cdf575ac9296
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102118584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.4102118584
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.3184553537
Short name T510
Test name
Test status
Simulation time 35717000 ps
CPU time 21.42 seconds
Started Jun 05 06:01:27 PM PDT 24
Finished Jun 05 06:01:49 PM PDT 24
Peak memory 264608 kb
Host smart-52c4e5b4-635c-451e-a428-c3263dd4efae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184553537 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.3184553537
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.1694689885
Short name T1037
Test name
Test status
Simulation time 531506400 ps
CPU time 99.63 seconds
Started Jun 05 06:01:17 PM PDT 24
Finished Jun 05 06:02:57 PM PDT 24
Peak memory 296792 kb
Host smart-b2382d07-134a-47c8-a840-313f607d07ad
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694689885 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_ro.1694689885
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.496579072
Short name T717
Test name
Test status
Simulation time 1303174800 ps
CPU time 118 seconds
Started Jun 05 06:01:14 PM PDT 24
Finished Jun 05 06:03:12 PM PDT 24
Peak memory 281780 kb
Host smart-972b1213-620c-4036-aaf7-796765bedfab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
496579072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.496579072
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.3462320995
Short name T382
Test name
Test status
Simulation time 762968300 ps
CPU time 134.73 seconds
Started Jun 05 06:01:12 PM PDT 24
Finished Jun 05 06:03:27 PM PDT 24
Peak memory 294104 kb
Host smart-f60011a8-9edb-4083-8416-c37639b21090
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462320995 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.3462320995
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.2149642500
Short name T619
Test name
Test status
Simulation time 3812410200 ps
CPU time 516.83 seconds
Started Jun 05 06:01:25 PM PDT 24
Finished Jun 05 06:10:02 PM PDT 24
Peak memory 323316 kb
Host smart-02cdc128-005a-41bf-8c3d-b8e01147f532
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149642500 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_rw_derr.2149642500
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.4129257851
Short name T630
Test name
Test status
Simulation time 48400900 ps
CPU time 31.83 seconds
Started Jun 05 06:01:29 PM PDT 24
Finished Jun 05 06:02:01 PM PDT 24
Peak memory 266964 kb
Host smart-317d6d7b-5f81-47c3-a4f7-791d7f11c2fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129257851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.4129257851
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.3784867769
Short name T643
Test name
Test status
Simulation time 67626300 ps
CPU time 31.56 seconds
Started Jun 05 06:01:26 PM PDT 24
Finished Jun 05 06:01:58 PM PDT 24
Peak memory 274496 kb
Host smart-5c548fb5-ba71-4207-af9b-30475905483a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784867769 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.3784867769
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.3564738493
Short name T898
Test name
Test status
Simulation time 3730064000 ps
CPU time 569.49 seconds
Started Jun 05 06:01:15 PM PDT 24
Finished Jun 05 06:10:45 PM PDT 24
Peak memory 311572 kb
Host smart-c1698804-a53e-480a-a184-727b7f9e69e2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564738493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s
err.3564738493
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_cm.3569800835
Short name T194
Test name
Test status
Simulation time 1297266100 ps
CPU time 4700.67 seconds
Started Jun 05 06:01:24 PM PDT 24
Finished Jun 05 07:19:45 PM PDT 24
Peak memory 287068 kb
Host smart-58cacd8b-4a77-4c97-b9fe-a7414cd5b4c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569800835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.3569800835
Directory /workspace/2.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.4169708797
Short name T846
Test name
Test status
Simulation time 492824000 ps
CPU time 59.64 seconds
Started Jun 05 06:01:21 PM PDT 24
Finished Jun 05 06:02:21 PM PDT 24
Peak memory 261772 kb
Host smart-691aa8a5-2f29-4639-9dc7-3609ebc04a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169708797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.4169708797
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.2058263681
Short name T676
Test name
Test status
Simulation time 616419200 ps
CPU time 67.01 seconds
Started Jun 05 06:01:28 PM PDT 24
Finished Jun 05 06:02:35 PM PDT 24
Peak memory 264864 kb
Host smart-415b08c9-49a7-43b4-a752-ac14f67d8466
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058263681 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.2058263681
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.944598705
Short name T547
Test name
Test status
Simulation time 3101084600 ps
CPU time 106.92 seconds
Started Jun 05 06:01:27 PM PDT 24
Finished Jun 05 06:03:14 PM PDT 24
Peak memory 273160 kb
Host smart-3dc0da5a-7ce3-4260-a16f-1dd59635ba35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944598705 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_counter.944598705
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.3963118426
Short name T631
Test name
Test status
Simulation time 21205700 ps
CPU time 49.31 seconds
Started Jun 05 06:01:07 PM PDT 24
Finished Jun 05 06:01:57 PM PDT 24
Peak memory 270364 kb
Host smart-7edb7f94-4218-48f6-9d1f-bc3b3b7cbdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963118426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.3963118426
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.1677274888
Short name T792
Test name
Test status
Simulation time 16289800 ps
CPU time 26.44 seconds
Started Jun 05 06:01:15 PM PDT 24
Finished Jun 05 06:01:42 PM PDT 24
Peak memory 258876 kb
Host smart-df642652-b286-4771-918c-e103322ff6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677274888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.1677274888
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.1426883247
Short name T919
Test name
Test status
Simulation time 380187900 ps
CPU time 924.36 seconds
Started Jun 05 06:01:27 PM PDT 24
Finished Jun 05 06:16:52 PM PDT 24
Peak memory 285620 kb
Host smart-d7117530-721c-4aed-a0b3-8a4533ea3af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426883247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.1426883247
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.1713278419
Short name T235
Test name
Test status
Simulation time 67359800 ps
CPU time 24.31 seconds
Started Jun 05 06:01:15 PM PDT 24
Finished Jun 05 06:01:40 PM PDT 24
Peak memory 261344 kb
Host smart-f9c51610-64db-4102-b8aa-0f7f9213890d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713278419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.1713278419
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.2520692844
Short name T980
Test name
Test status
Simulation time 3824180800 ps
CPU time 137.55 seconds
Started Jun 05 06:01:16 PM PDT 24
Finished Jun 05 06:03:34 PM PDT 24
Peak memory 259916 kb
Host smart-80af41f2-ba4c-4662-894c-1d8ce41d5315
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520692844 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_wo.2520692844
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.3586818608
Short name T595
Test name
Test status
Simulation time 119804500 ps
CPU time 13.57 seconds
Started Jun 05 06:03:49 PM PDT 24
Finished Jun 05 06:04:03 PM PDT 24
Peak memory 264820 kb
Host smart-bd55c2cc-99c3-44f5-bf93-d135218fea1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586818608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
3586818608
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.1159225551
Short name T424
Test name
Test status
Simulation time 14691300 ps
CPU time 13.71 seconds
Started Jun 05 06:03:50 PM PDT 24
Finished Jun 05 06:04:04 PM PDT 24
Peak memory 275884 kb
Host smart-5bd1b242-4c06-4b82-abee-dfa122d863ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159225551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.1159225551
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.609602032
Short name T373
Test name
Test status
Simulation time 12234000 ps
CPU time 22.17 seconds
Started Jun 05 06:03:48 PM PDT 24
Finished Jun 05 06:04:11 PM PDT 24
Peak memory 264812 kb
Host smart-86e40517-107c-41ea-b29a-a64bbccf07b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609602032 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.609602032
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.1170445694
Short name T893
Test name
Test status
Simulation time 3461396400 ps
CPU time 139.27 seconds
Started Jun 05 06:03:48 PM PDT 24
Finished Jun 05 06:06:07 PM PDT 24
Peak memory 262496 kb
Host smart-4641f420-f7d7-449e-aaa5-57087af48d10
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170445694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.1170445694
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.3544049239
Short name T1013
Test name
Test status
Simulation time 781386900 ps
CPU time 127.9 seconds
Started Jun 05 06:03:52 PM PDT 24
Finished Jun 05 06:06:00 PM PDT 24
Peak memory 292720 kb
Host smart-41be2c6a-d13b-4113-a39d-af40a52de129
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544049239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.3544049239
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.1672952862
Short name T990
Test name
Test status
Simulation time 46991297400 ps
CPU time 313.44 seconds
Started Jun 05 06:03:49 PM PDT 24
Finished Jun 05 06:09:03 PM PDT 24
Peak memory 283920 kb
Host smart-60fc8f7f-d433-4c35-ac8d-99ebf8ac5016
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672952862 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.1672952862
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.3977676572
Short name T618
Test name
Test status
Simulation time 53631300 ps
CPU time 130.6 seconds
Started Jun 05 06:03:48 PM PDT 24
Finished Jun 05 06:05:59 PM PDT 24
Peak memory 259576 kb
Host smart-0268dad9-c67f-4dc6-b7fd-35e78f116d1f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977676572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.3977676572
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.1743185189
Short name T529
Test name
Test status
Simulation time 2731798600 ps
CPU time 194.85 seconds
Started Jun 05 06:03:52 PM PDT 24
Finished Jun 05 06:07:08 PM PDT 24
Peak memory 259208 kb
Host smart-c1bd3316-790c-4594-9c63-ecb8ef50350a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743185189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.1743185189
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.2534482620
Short name T711
Test name
Test status
Simulation time 30498200 ps
CPU time 31.59 seconds
Started Jun 05 06:03:47 PM PDT 24
Finished Jun 05 06:04:19 PM PDT 24
Peak memory 274544 kb
Host smart-d9925a4a-905c-4027-9065-e2cbdcc0a839
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534482620 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.2534482620
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.46499020
Short name T974
Test name
Test status
Simulation time 88157400 ps
CPU time 119.4 seconds
Started Jun 05 06:03:52 PM PDT 24
Finished Jun 05 06:05:52 PM PDT 24
Peak memory 275444 kb
Host smart-06440065-0af1-422a-bdaf-2285edc1800c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46499020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.46499020
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.2373061833
Short name T391
Test name
Test status
Simulation time 30824200 ps
CPU time 13.95 seconds
Started Jun 05 06:03:54 PM PDT 24
Finished Jun 05 06:04:08 PM PDT 24
Peak memory 257952 kb
Host smart-2f68ea1e-02f4-4ca7-ac1d-b811f4ec8e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373061833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
2373061833
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.537556863
Short name T470
Test name
Test status
Simulation time 13127000 ps
CPU time 15.83 seconds
Started Jun 05 06:03:54 PM PDT 24
Finished Jun 05 06:04:11 PM PDT 24
Peak memory 275920 kb
Host smart-d8e78cc9-3e26-42bc-87f0-50d8c459a0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537556863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.537556863
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.3381336210
Short name T881
Test name
Test status
Simulation time 17200800 ps
CPU time 20.16 seconds
Started Jun 05 06:03:59 PM PDT 24
Finished Jun 05 06:04:19 PM PDT 24
Peak memory 273076 kb
Host smart-06ccc685-8d63-4450-8fd8-b03b7614d5b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381336210 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.3381336210
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2348850808
Short name T889
Test name
Test status
Simulation time 3400628400 ps
CPU time 126.21 seconds
Started Jun 05 06:03:52 PM PDT 24
Finished Jun 05 06:05:58 PM PDT 24
Peak memory 262400 kb
Host smart-b8909944-2e7c-448c-9c98-8faa173c47a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348850808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.2348850808
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.2479250877
Short name T725
Test name
Test status
Simulation time 1421264000 ps
CPU time 147.97 seconds
Started Jun 05 06:03:49 PM PDT 24
Finished Jun 05 06:06:17 PM PDT 24
Peak memory 289532 kb
Host smart-92f24320-9dc0-41b4-857e-ee16fc41db32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479250877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.2479250877
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.2683174464
Short name T80
Test name
Test status
Simulation time 97041400 ps
CPU time 130.08 seconds
Started Jun 05 06:03:50 PM PDT 24
Finished Jun 05 06:06:00 PM PDT 24
Peak memory 259816 kb
Host smart-33124218-2491-4616-b720-2a9c31efb512
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683174464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.2683174464
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.3759140838
Short name T500
Test name
Test status
Simulation time 27156700 ps
CPU time 13.62 seconds
Started Jun 05 06:03:55 PM PDT 24
Finished Jun 05 06:04:09 PM PDT 24
Peak memory 258392 kb
Host smart-03930e27-22f1-47c7-8b0d-72a47406b5c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759140838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_re
set.3759140838
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.1583976697
Short name T1090
Test name
Test status
Simulation time 425790800 ps
CPU time 31.23 seconds
Started Jun 05 06:03:55 PM PDT 24
Finished Jun 05 06:04:26 PM PDT 24
Peak memory 273168 kb
Host smart-ebad72a9-63f9-4a35-b87e-be4b71798126
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583976697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl
ash_ctrl_rw_evict.1583976697
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.3913836786
Short name T819
Test name
Test status
Simulation time 101177500 ps
CPU time 30.93 seconds
Started Jun 05 06:03:56 PM PDT 24
Finished Jun 05 06:04:28 PM PDT 24
Peak memory 274392 kb
Host smart-f382579a-6a79-4b19-b4c8-b1ac3f99f33d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913836786 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.3913836786
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.1731088068
Short name T862
Test name
Test status
Simulation time 1194947200 ps
CPU time 69.57 seconds
Started Jun 05 06:03:58 PM PDT 24
Finished Jun 05 06:05:08 PM PDT 24
Peak memory 263104 kb
Host smart-165df111-eab1-45fe-bcfe-3dde58350421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731088068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.1731088068
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.170292245
Short name T1088
Test name
Test status
Simulation time 48965600 ps
CPU time 74.2 seconds
Started Jun 05 06:03:47 PM PDT 24
Finished Jun 05 06:05:01 PM PDT 24
Peak memory 274732 kb
Host smart-3b912242-53af-4249-89ad-3aa2bfdbf410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170292245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.170292245
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.4236996003
Short name T747
Test name
Test status
Simulation time 52880200 ps
CPU time 13.49 seconds
Started Jun 05 06:04:04 PM PDT 24
Finished Jun 05 06:04:18 PM PDT 24
Peak memory 257920 kb
Host smart-174dc4e5-f92f-4095-991d-47e071b6dc1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236996003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
4236996003
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.4012887235
Short name T522
Test name
Test status
Simulation time 26883900 ps
CPU time 14.22 seconds
Started Jun 05 06:04:01 PM PDT 24
Finished Jun 05 06:04:16 PM PDT 24
Peak memory 275620 kb
Host smart-33b15517-c2c2-42e9-8c15-9c858c08a098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012887235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.4012887235
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.1259195255
Short name T1089
Test name
Test status
Simulation time 65999800 ps
CPU time 21.66 seconds
Started Jun 05 06:03:56 PM PDT 24
Finished Jun 05 06:04:18 PM PDT 24
Peak memory 273172 kb
Host smart-0a34c095-0e4a-4e0b-aaab-37355ce8caf7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259195255 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.1259195255
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.3369167413
Short name T765
Test name
Test status
Simulation time 19384816600 ps
CPU time 88.76 seconds
Started Jun 05 06:03:57 PM PDT 24
Finished Jun 05 06:05:27 PM PDT 24
Peak memory 261684 kb
Host smart-27e4751b-bb87-4fdb-89de-d55fdb7e6804
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369167413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.3369167413
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.232224816
Short name T538
Test name
Test status
Simulation time 707671200 ps
CPU time 143.82 seconds
Started Jun 05 06:03:55 PM PDT 24
Finished Jun 05 06:06:19 PM PDT 24
Peak memory 289468 kb
Host smart-5da1a067-35c6-4037-a3fb-1851045a4040
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232224816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flas
h_ctrl_intr_rd.232224816
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.2567488536
Short name T740
Test name
Test status
Simulation time 5941503700 ps
CPU time 146.5 seconds
Started Jun 05 06:03:56 PM PDT 24
Finished Jun 05 06:06:23 PM PDT 24
Peak memory 293164 kb
Host smart-c62c7c6e-cd3a-41ac-9a84-12f5700d08e9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567488536 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.2567488536
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.3475081206
Short name T566
Test name
Test status
Simulation time 188403500 ps
CPU time 113.2 seconds
Started Jun 05 06:03:58 PM PDT 24
Finished Jun 05 06:05:52 PM PDT 24
Peak memory 264232 kb
Host smart-7e2101a5-1517-4e11-904f-f3997e459b50
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475081206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.3475081206
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.3486475914
Short name T431
Test name
Test status
Simulation time 62384600 ps
CPU time 13.54 seconds
Started Jun 05 06:03:55 PM PDT 24
Finished Jun 05 06:04:09 PM PDT 24
Peak memory 258344 kb
Host smart-8b18fbad-1a18-4b2c-8a97-ad4b18852ef1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486475914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.3486475914
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.597052488
Short name T693
Test name
Test status
Simulation time 44701200 ps
CPU time 30.91 seconds
Started Jun 05 06:03:56 PM PDT 24
Finished Jun 05 06:04:27 PM PDT 24
Peak memory 275172 kb
Host smart-ed84d6c1-b956-4623-b5d8-03de50c757a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597052488 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.597052488
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.2229394375
Short name T1055
Test name
Test status
Simulation time 2214389700 ps
CPU time 70.14 seconds
Started Jun 05 06:03:55 PM PDT 24
Finished Jun 05 06:05:06 PM PDT 24
Peak memory 263788 kb
Host smart-fbfccbe8-8320-45cc-b730-098028fdc7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229394375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.2229394375
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.1177635379
Short name T242
Test name
Test status
Simulation time 40616200 ps
CPU time 142.51 seconds
Started Jun 05 06:03:56 PM PDT 24
Finished Jun 05 06:06:19 PM PDT 24
Peak memory 277424 kb
Host smart-b0d819db-d997-4ebb-acf2-25001760ceec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177635379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.1177635379
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.1161541913
Short name T854
Test name
Test status
Simulation time 25574100 ps
CPU time 13.34 seconds
Started Jun 05 06:04:03 PM PDT 24
Finished Jun 05 06:04:16 PM PDT 24
Peak memory 257956 kb
Host smart-eb05bc42-6e7b-4367-ae06-a3ddb9b484bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161541913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
1161541913
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.2710769418
Short name T1085
Test name
Test status
Simulation time 27618100 ps
CPU time 13.26 seconds
Started Jun 05 06:04:03 PM PDT 24
Finished Jun 05 06:04:17 PM PDT 24
Peak memory 275420 kb
Host smart-5f6211ec-a3d5-41b7-9220-008ae796b150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710769418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.2710769418
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.3237693802
Short name T162
Test name
Test status
Simulation time 21242400 ps
CPU time 22.13 seconds
Started Jun 05 06:04:03 PM PDT 24
Finished Jun 05 06:04:26 PM PDT 24
Peak memory 272948 kb
Host smart-7a3c6449-002b-46ee-b4a3-2ad3863cf976
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237693802 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.3237693802
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.1632883989
Short name T401
Test name
Test status
Simulation time 12217114200 ps
CPU time 194.94 seconds
Started Jun 05 06:04:01 PM PDT 24
Finished Jun 05 06:07:17 PM PDT 24
Peak memory 262408 kb
Host smart-95a58887-9d93-4023-a5da-951ef7afe112
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632883989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.1632883989
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2611296499
Short name T815
Test name
Test status
Simulation time 22654396700 ps
CPU time 128.8 seconds
Started Jun 05 06:04:03 PM PDT 24
Finished Jun 05 06:06:12 PM PDT 24
Peak memory 293100 kb
Host smart-520d667d-5b94-4074-b24b-d0e411dfe211
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611296499 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2611296499
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.4061907281
Short name T773
Test name
Test status
Simulation time 44654600 ps
CPU time 109.67 seconds
Started Jun 05 06:04:01 PM PDT 24
Finished Jun 05 06:05:51 PM PDT 24
Peak memory 259820 kb
Host smart-8e59baa7-6aaf-41e6-ac70-0dd5527f68cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061907281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.4061907281
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.1965027105
Short name T749
Test name
Test status
Simulation time 64272600 ps
CPU time 13.72 seconds
Started Jun 05 06:04:03 PM PDT 24
Finished Jun 05 06:04:17 PM PDT 24
Peak memory 264812 kb
Host smart-699227fb-a76f-4ba0-a5cf-d48662829948
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965027105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.1965027105
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict.4184911276
Short name T1082
Test name
Test status
Simulation time 46175600 ps
CPU time 28.94 seconds
Started Jun 05 06:04:02 PM PDT 24
Finished Jun 05 06:04:32 PM PDT 24
Peak memory 273132 kb
Host smart-41bbded1-03b7-4eb8-a58e-fb8ee4b3fc00
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184911276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl
ash_ctrl_rw_evict.4184911276
Directory /workspace/23.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.711402498
Short name T762
Test name
Test status
Simulation time 69617600 ps
CPU time 31.83 seconds
Started Jun 05 06:04:03 PM PDT 24
Finished Jun 05 06:04:35 PM PDT 24
Peak memory 275744 kb
Host smart-724a5860-8556-44fc-a326-0b30e999a18a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711402498 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.711402498
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.2396755731
Short name T378
Test name
Test status
Simulation time 4028040500 ps
CPU time 71.6 seconds
Started Jun 05 06:04:04 PM PDT 24
Finished Jun 05 06:05:16 PM PDT 24
Peak memory 262996 kb
Host smart-034ac2b9-e696-4f1e-b2d3-c619e3ac2a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396755731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.2396755731
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.856705892
Short name T925
Test name
Test status
Simulation time 44120500 ps
CPU time 122.49 seconds
Started Jun 05 06:04:02 PM PDT 24
Finished Jun 05 06:06:05 PM PDT 24
Peak memory 276528 kb
Host smart-1d6ae973-8ca0-4e8b-b5c7-ee9b89d12121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856705892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.856705892
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.3260278517
Short name T428
Test name
Test status
Simulation time 195966900 ps
CPU time 13.72 seconds
Started Jun 05 06:04:07 PM PDT 24
Finished Jun 05 06:04:21 PM PDT 24
Peak memory 264812 kb
Host smart-c17424a4-f273-463f-a713-7626281027e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260278517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
3260278517
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.2830204294
Short name T490
Test name
Test status
Simulation time 62614000 ps
CPU time 15.55 seconds
Started Jun 05 06:04:03 PM PDT 24
Finished Jun 05 06:04:20 PM PDT 24
Peak memory 275784 kb
Host smart-9c84098c-8889-473f-a8e4-ed16d563af2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830204294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.2830204294
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.1459699910
Short name T1075
Test name
Test status
Simulation time 6568587700 ps
CPU time 279.96 seconds
Started Jun 05 06:04:02 PM PDT 24
Finished Jun 05 06:08:42 PM PDT 24
Peak memory 262588 kb
Host smart-a2a99cbc-1376-476f-b332-069f34980e45
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459699910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.1459699910
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.802776046
Short name T243
Test name
Test status
Simulation time 1725358600 ps
CPU time 294.45 seconds
Started Jun 05 06:04:02 PM PDT 24
Finished Jun 05 06:08:57 PM PDT 24
Peak memory 283732 kb
Host smart-53c21ac1-7c48-4b14-b0fe-ca02338c7719
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802776046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flas
h_ctrl_intr_rd.802776046
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3442754955
Short name T403
Test name
Test status
Simulation time 23309575300 ps
CPU time 122.53 seconds
Started Jun 05 06:04:02 PM PDT 24
Finished Jun 05 06:06:05 PM PDT 24
Peak memory 292956 kb
Host smart-8c2e03e7-5901-42dd-ab97-94b17025d48b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442754955 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.3442754955
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.1008800316
Short name T136
Test name
Test status
Simulation time 184284500 ps
CPU time 134.66 seconds
Started Jun 05 06:04:03 PM PDT 24
Finished Jun 05 06:06:19 PM PDT 24
Peak memory 259776 kb
Host smart-03806521-4fe1-46c2-8b1e-1219eaa1e50c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008800316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o
tp_reset.1008800316
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.3638738442
Short name T426
Test name
Test status
Simulation time 17882400 ps
CPU time 13.32 seconds
Started Jun 05 06:04:02 PM PDT 24
Finished Jun 05 06:04:16 PM PDT 24
Peak memory 258344 kb
Host smart-d4884226-14e4-44ef-98f8-9612baeca3f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638738442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.3638738442
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.3084967045
Short name T324
Test name
Test status
Simulation time 74257600 ps
CPU time 30.77 seconds
Started Jun 05 06:04:03 PM PDT 24
Finished Jun 05 06:04:35 PM PDT 24
Peak memory 273132 kb
Host smart-49df98eb-2cc8-4f1c-b56d-69e2673d1820
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084967045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fl
ash_ctrl_rw_evict.3084967045
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.3894946534
Short name T459
Test name
Test status
Simulation time 67130300 ps
CPU time 31.76 seconds
Started Jun 05 06:04:04 PM PDT 24
Finished Jun 05 06:04:36 PM PDT 24
Peak memory 275928 kb
Host smart-21f8421c-35c3-4824-a203-d536c7fba0cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894946534 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.3894946534
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.321593141
Short name T34
Test name
Test status
Simulation time 1376890900 ps
CPU time 60.76 seconds
Started Jun 05 06:04:03 PM PDT 24
Finished Jun 05 06:05:05 PM PDT 24
Peak memory 262436 kb
Host smart-41195de6-d19b-40e6-b257-1dc31951bed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321593141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.321593141
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.681139258
Short name T514
Test name
Test status
Simulation time 936116500 ps
CPU time 219.13 seconds
Started Jun 05 06:04:04 PM PDT 24
Finished Jun 05 06:07:44 PM PDT 24
Peak memory 281168 kb
Host smart-c4b4f0ab-3b79-45a1-97cb-834914a1053a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681139258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.681139258
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.384956577
Short name T1026
Test name
Test status
Simulation time 89836900 ps
CPU time 13.87 seconds
Started Jun 05 06:04:10 PM PDT 24
Finished Jun 05 06:04:24 PM PDT 24
Peak memory 264828 kb
Host smart-6727a306-50f5-4da9-8053-77772c96cdba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384956577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.384956577
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.1750091189
Short name T546
Test name
Test status
Simulation time 131052400 ps
CPU time 15.88 seconds
Started Jun 05 06:04:11 PM PDT 24
Finished Jun 05 06:04:27 PM PDT 24
Peak memory 275576 kb
Host smart-b99871d0-9992-4abe-b430-0b66e08004a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750091189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1750091189
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.1381725004
Short name T972
Test name
Test status
Simulation time 3180504500 ps
CPU time 246.54 seconds
Started Jun 05 06:04:10 PM PDT 24
Finished Jun 05 06:08:17 PM PDT 24
Peak memory 262352 kb
Host smart-617045df-7f02-4303-8bc9-08100f21aa45
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381725004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.1381725004
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.11523009
Short name T788
Test name
Test status
Simulation time 1611507900 ps
CPU time 126.38 seconds
Started Jun 05 06:04:10 PM PDT 24
Finished Jun 05 06:06:17 PM PDT 24
Peak memory 284128 kb
Host smart-0db056e2-a34c-4718-a2fb-ae298a324525
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11523009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash
_ctrl_intr_rd.11523009
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.2279003593
Short name T691
Test name
Test status
Simulation time 49897212700 ps
CPU time 279.65 seconds
Started Jun 05 06:04:09 PM PDT 24
Finished Jun 05 06:08:49 PM PDT 24
Peak memory 292856 kb
Host smart-d3260f69-721f-473c-98c0-204e8152b5ad
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279003593 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.2279003593
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.2461465593
Short name T151
Test name
Test status
Simulation time 200050200 ps
CPU time 110.89 seconds
Started Jun 05 06:04:09 PM PDT 24
Finished Jun 05 06:06:00 PM PDT 24
Peak memory 263988 kb
Host smart-306b24e5-bb61-4c83-9710-c92d8d9b698d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461465593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.2461465593
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.4146894739
Short name T385
Test name
Test status
Simulation time 60432200 ps
CPU time 14.37 seconds
Started Jun 05 06:04:10 PM PDT 24
Finished Jun 05 06:04:25 PM PDT 24
Peak memory 264832 kb
Host smart-5575510e-8f49-488e-836f-eef2175eb688
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146894739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.4146894739
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.4239866412
Short name T516
Test name
Test status
Simulation time 219526900 ps
CPU time 30.99 seconds
Started Jun 05 06:04:09 PM PDT 24
Finished Jun 05 06:04:40 PM PDT 24
Peak memory 273176 kb
Host smart-b47f0e3b-10f8-49b2-a728-60c34f1fd9e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239866412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.4239866412
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.342020378
Short name T551
Test name
Test status
Simulation time 40165500 ps
CPU time 31.17 seconds
Started Jun 05 06:04:07 PM PDT 24
Finished Jun 05 06:04:39 PM PDT 24
Peak memory 275168 kb
Host smart-ce71f284-7fc3-4edd-81b6-8d72837f3062
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342020378 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.342020378
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.3315789162
Short name T883
Test name
Test status
Simulation time 97585400 ps
CPU time 96.76 seconds
Started Jun 05 06:04:08 PM PDT 24
Finished Jun 05 06:05:45 PM PDT 24
Peak memory 275096 kb
Host smart-c1d266f8-7635-4a89-977d-cecf3d3d59af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315789162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.3315789162
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.428324595
Short name T623
Test name
Test status
Simulation time 32037000 ps
CPU time 13.82 seconds
Started Jun 05 06:04:15 PM PDT 24
Finished Jun 05 06:04:29 PM PDT 24
Peak memory 264804 kb
Host smart-f8f8fc63-253d-476b-b1fe-a87e224488bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428324595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.428324595
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.3128401285
Short name T569
Test name
Test status
Simulation time 66150900 ps
CPU time 13.12 seconds
Started Jun 05 06:04:18 PM PDT 24
Finished Jun 05 06:04:32 PM PDT 24
Peak memory 275568 kb
Host smart-3296528d-6569-4249-aa81-b25fb423fc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128401285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.3128401285
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.174234951
Short name T1020
Test name
Test status
Simulation time 51944316500 ps
CPU time 102.37 seconds
Started Jun 05 06:04:18 PM PDT 24
Finished Jun 05 06:06:00 PM PDT 24
Peak memory 262268 kb
Host smart-50331a31-b62e-4aa3-9d83-35e72c322522
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174234951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_h
w_sec_otp.174234951
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.3775824168
Short name T797
Test name
Test status
Simulation time 1043905400 ps
CPU time 150.31 seconds
Started Jun 05 06:04:10 PM PDT 24
Finished Jun 05 06:06:41 PM PDT 24
Peak memory 291796 kb
Host smart-f47ffbb4-3c56-4838-afcc-3754ba2f76fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775824168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.3775824168
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.4110104907
Short name T223
Test name
Test status
Simulation time 50490059200 ps
CPU time 306.72 seconds
Started Jun 05 06:04:09 PM PDT 24
Finished Jun 05 06:09:17 PM PDT 24
Peak memory 292852 kb
Host smart-dbd206b5-20cd-4170-937d-125b398b72c1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110104907 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.4110104907
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.2292398257
Short name T642
Test name
Test status
Simulation time 137761600 ps
CPU time 113.61 seconds
Started Jun 05 06:04:20 PM PDT 24
Finished Jun 05 06:06:14 PM PDT 24
Peak memory 259960 kb
Host smart-1cb06913-f5fe-4349-bbcb-cc2692805c6a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292398257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.2292398257
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.1854181441
Short name T943
Test name
Test status
Simulation time 88111600 ps
CPU time 18.61 seconds
Started Jun 05 06:04:09 PM PDT 24
Finished Jun 05 06:04:28 PM PDT 24
Peak memory 258588 kb
Host smart-82873418-f0a9-45cf-bedf-a173b01bd32c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854181441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.1854181441
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.1131951343
Short name T614
Test name
Test status
Simulation time 194498400 ps
CPU time 31.53 seconds
Started Jun 05 06:04:11 PM PDT 24
Finished Jun 05 06:04:43 PM PDT 24
Peak memory 275848 kb
Host smart-d9665938-af49-4176-b587-3f63562ee51d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131951343 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.1131951343
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.1955611710
Short name T870
Test name
Test status
Simulation time 3820612300 ps
CPU time 67.81 seconds
Started Jun 05 06:04:16 PM PDT 24
Finished Jun 05 06:05:25 PM PDT 24
Peak memory 262072 kb
Host smart-167f0a54-f076-4705-b511-0136a4c2cf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955611710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.1955611710
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.203869223
Short name T429
Test name
Test status
Simulation time 104337600 ps
CPU time 98.99 seconds
Started Jun 05 06:04:17 PM PDT 24
Finished Jun 05 06:05:57 PM PDT 24
Peak memory 275184 kb
Host smart-e13f5f40-503c-4413-bb2a-da98009eea9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203869223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.203869223
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.2391667271
Short name T816
Test name
Test status
Simulation time 277398800 ps
CPU time 14.5 seconds
Started Jun 05 06:04:16 PM PDT 24
Finished Jun 05 06:04:31 PM PDT 24
Peak memory 263992 kb
Host smart-d617dd40-917c-47be-8cc0-f48b88b9a6ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391667271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
2391667271
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.3124843638
Short name T699
Test name
Test status
Simulation time 52669200 ps
CPU time 13.17 seconds
Started Jun 05 06:04:17 PM PDT 24
Finished Jun 05 06:04:31 PM PDT 24
Peak memory 275540 kb
Host smart-2534afcd-fb32-4cd4-92d0-6f5d756bee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124843638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3124843638
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.3878142091
Short name T372
Test name
Test status
Simulation time 24881400 ps
CPU time 22.05 seconds
Started Jun 05 06:04:16 PM PDT 24
Finished Jun 05 06:04:38 PM PDT 24
Peak memory 273116 kb
Host smart-4e74e9f3-c50d-4e72-9748-10372b245f0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878142091 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.3878142091
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.3133920955
Short name T107
Test name
Test status
Simulation time 3319515600 ps
CPU time 38.1 seconds
Started Jun 05 06:04:20 PM PDT 24
Finished Jun 05 06:04:58 PM PDT 24
Peak memory 262480 kb
Host smart-14708c1f-e9cf-48a2-8407-4b4d9a737027
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133920955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.3133920955
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.2834395605
Short name T872
Test name
Test status
Simulation time 3282299000 ps
CPU time 206.71 seconds
Started Jun 05 06:04:18 PM PDT 24
Finished Jun 05 06:07:45 PM PDT 24
Peak memory 290680 kb
Host smart-ce66fdff-75e6-403e-9aa1-474c4312ba8b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834395605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.2834395605
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1342230032
Short name T523
Test name
Test status
Simulation time 11649465500 ps
CPU time 132.65 seconds
Started Jun 05 06:04:18 PM PDT 24
Finished Jun 05 06:06:31 PM PDT 24
Peak memory 291532 kb
Host smart-b86dd9a9-45a0-418d-8e03-cbfe63a17560
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342230032 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1342230032
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.836151692
Short name T817
Test name
Test status
Simulation time 342351200 ps
CPU time 130.66 seconds
Started Jun 05 06:04:19 PM PDT 24
Finished Jun 05 06:06:30 PM PDT 24
Peak memory 264464 kb
Host smart-22b87d75-fd85-4edb-9faf-146e609bfeba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836151692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_ot
p_reset.836151692
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.725986826
Short name T731
Test name
Test status
Simulation time 8681017400 ps
CPU time 150.23 seconds
Started Jun 05 06:04:17 PM PDT 24
Finished Jun 05 06:06:47 PM PDT 24
Peak memory 259356 kb
Host smart-654c59be-77de-4d3f-9979-e3b134cfe94d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725986826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_res
et.725986826
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.979776774
Short name T329
Test name
Test status
Simulation time 96389900 ps
CPU time 30.4 seconds
Started Jun 05 06:04:18 PM PDT 24
Finished Jun 05 06:04:49 PM PDT 24
Peak memory 266948 kb
Host smart-1480f36c-df9a-41ab-a078-5f5faa3439f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979776774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_rw_evict.979776774
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.1085478424
Short name T563
Test name
Test status
Simulation time 42863800 ps
CPU time 31.2 seconds
Started Jun 05 06:04:20 PM PDT 24
Finished Jun 05 06:04:52 PM PDT 24
Peak memory 276048 kb
Host smart-adc0fdef-5445-49a8-b0d6-7dcd41be000c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085478424 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.1085478424
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.236708551
Short name T764
Test name
Test status
Simulation time 4179496900 ps
CPU time 64.79 seconds
Started Jun 05 06:04:15 PM PDT 24
Finished Jun 05 06:05:20 PM PDT 24
Peak memory 261672 kb
Host smart-1fd70a3b-7d18-437b-ba9b-5bc94baa0008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236708551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.236708551
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.2555274989
Short name T402
Test name
Test status
Simulation time 94619900 ps
CPU time 169.14 seconds
Started Jun 05 06:04:16 PM PDT 24
Finished Jun 05 06:07:06 PM PDT 24
Peak memory 278700 kb
Host smart-9f6ff8fa-214b-459d-b3f6-c38f7c715bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555274989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.2555274989
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.66990173
Short name T420
Test name
Test status
Simulation time 89643500 ps
CPU time 13.68 seconds
Started Jun 05 06:04:25 PM PDT 24
Finished Jun 05 06:04:39 PM PDT 24
Peak memory 264840 kb
Host smart-014c20b2-b585-4458-a56a-9c902e1fa1c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66990173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.66990173
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.1280136668
Short name T774
Test name
Test status
Simulation time 14272300 ps
CPU time 15.85 seconds
Started Jun 05 06:04:24 PM PDT 24
Finished Jun 05 06:04:40 PM PDT 24
Peak memory 275476 kb
Host smart-d5af3a10-ee2c-469c-a548-bfe7ddf72783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280136668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1280136668
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.1868811987
Short name T826
Test name
Test status
Simulation time 12646000 ps
CPU time 22.07 seconds
Started Jun 05 06:04:27 PM PDT 24
Finished Jun 05 06:04:49 PM PDT 24
Peak memory 273184 kb
Host smart-2aa63d3e-6b7d-4bc9-b8ae-8f22829ee524
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868811987 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.1868811987
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.1944642227
Short name T751
Test name
Test status
Simulation time 2543014100 ps
CPU time 93.47 seconds
Started Jun 05 06:04:25 PM PDT 24
Finished Jun 05 06:05:59 PM PDT 24
Peak memory 259132 kb
Host smart-291ea64d-69b2-4f2f-99c0-660049d8abdf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944642227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.1944642227
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.3416518021
Short name T732
Test name
Test status
Simulation time 967949100 ps
CPU time 133.5 seconds
Started Jun 05 06:04:25 PM PDT 24
Finished Jun 05 06:06:39 PM PDT 24
Peak memory 289520 kb
Host smart-9b878fd4-efa1-4a9d-8d27-9e6d235f0a0b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416518021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_intr_rd.3416518021
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.1580840762
Short name T439
Test name
Test status
Simulation time 12921672500 ps
CPU time 268.37 seconds
Started Jun 05 06:04:23 PM PDT 24
Finished Jun 05 06:08:52 PM PDT 24
Peak memory 293008 kb
Host smart-b89b8463-3980-45a3-b9ab-fb869a22fa69
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580840762 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.1580840762
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.3763824783
Short name T519
Test name
Test status
Simulation time 136198900 ps
CPU time 131.81 seconds
Started Jun 05 06:04:25 PM PDT 24
Finished Jun 05 06:06:37 PM PDT 24
Peak memory 259856 kb
Host smart-daa8b941-f01d-4d55-84ce-6f4c96a2c241
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763824783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.3763824783
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.479696677
Short name T108
Test name
Test status
Simulation time 9043778400 ps
CPU time 167.66 seconds
Started Jun 05 06:04:25 PM PDT 24
Finished Jun 05 06:07:13 PM PDT 24
Peak memory 258892 kb
Host smart-ac017aac-46b0-43fd-84c4-9e0a9805c801
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479696677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_res
et.479696677
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.1519585178
Short name T537
Test name
Test status
Simulation time 47656300 ps
CPU time 31.14 seconds
Started Jun 05 06:04:23 PM PDT 24
Finished Jun 05 06:04:55 PM PDT 24
Peak memory 273340 kb
Host smart-a156cee3-88c6-47fd-a78f-323ba8241d4e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519585178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.1519585178
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.3995434063
Short name T1046
Test name
Test status
Simulation time 29111300 ps
CPU time 32.24 seconds
Started Jun 05 06:04:23 PM PDT 24
Finished Jun 05 06:04:56 PM PDT 24
Peak memory 273120 kb
Host smart-9917d260-94ca-4cbf-8044-0cf7ef560a42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995434063 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.3995434063
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.980065046
Short name T778
Test name
Test status
Simulation time 553151900 ps
CPU time 65.87 seconds
Started Jun 05 06:04:25 PM PDT 24
Finished Jun 05 06:05:31 PM PDT 24
Peak memory 262828 kb
Host smart-f7c0a8df-6fbb-4a22-a524-01b78ba3e3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980065046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.980065046
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.2787633686
Short name T388
Test name
Test status
Simulation time 32971400 ps
CPU time 52.53 seconds
Started Jun 05 06:04:24 PM PDT 24
Finished Jun 05 06:05:17 PM PDT 24
Peak memory 270476 kb
Host smart-8b114948-f783-406d-95fb-c098f408458c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787633686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.2787633686
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.2327099334
Short name T604
Test name
Test status
Simulation time 167128400 ps
CPU time 13.99 seconds
Started Jun 05 06:04:31 PM PDT 24
Finished Jun 05 06:04:45 PM PDT 24
Peak memory 257900 kb
Host smart-3bd81d63-c764-4548-a889-6a1dddbc9a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327099334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
2327099334
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.1227094025
Short name T1094
Test name
Test status
Simulation time 27370300 ps
CPU time 15.7 seconds
Started Jun 05 06:04:32 PM PDT 24
Finished Jun 05 06:04:48 PM PDT 24
Peak memory 275936 kb
Host smart-6b55705d-9ab4-4dfc-8408-44746b198ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227094025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.1227094025
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.1047334906
Short name T495
Test name
Test status
Simulation time 26660500 ps
CPU time 22.41 seconds
Started Jun 05 06:04:31 PM PDT 24
Finished Jun 05 06:04:54 PM PDT 24
Peak memory 264916 kb
Host smart-47f92899-7f95-4ca6-8d71-d9870100e91d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047334906 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.1047334906
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.1952715244
Short name T1052
Test name
Test status
Simulation time 1687274600 ps
CPU time 141.21 seconds
Started Jun 05 06:04:24 PM PDT 24
Finished Jun 05 06:06:46 PM PDT 24
Peak memory 262268 kb
Host smart-b674b255-2f5d-4777-b584-2fc216e0642c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952715244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.1952715244
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.3570826639
Short name T768
Test name
Test status
Simulation time 3139111400 ps
CPU time 219.23 seconds
Started Jun 05 06:04:24 PM PDT 24
Finished Jun 05 06:08:03 PM PDT 24
Peak memory 283752 kb
Host smart-539342e9-8bea-43d3-92fd-27e5deadbb01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570826639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.3570826639
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.960565092
Short name T963
Test name
Test status
Simulation time 11865785200 ps
CPU time 124.45 seconds
Started Jun 05 06:04:25 PM PDT 24
Finished Jun 05 06:06:30 PM PDT 24
Peak memory 291708 kb
Host smart-e0d92f77-cf3d-459b-836d-c16953ad26db
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960565092 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.960565092
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.2501535680
Short name T140
Test name
Test status
Simulation time 36156500 ps
CPU time 130.46 seconds
Started Jun 05 06:04:24 PM PDT 24
Finished Jun 05 06:06:35 PM PDT 24
Peak memory 260836 kb
Host smart-47600517-cc60-4eee-8c68-f9da535c6503
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501535680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.2501535680
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.2928089016
Short name T920
Test name
Test status
Simulation time 38149900 ps
CPU time 13.64 seconds
Started Jun 05 06:04:23 PM PDT 24
Finished Jun 05 06:04:37 PM PDT 24
Peak memory 264796 kb
Host smart-46865d12-353a-4c94-ac7e-997497f3931f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928089016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.2928089016
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.3126359375
Short name T416
Test name
Test status
Simulation time 33720100 ps
CPU time 31.39 seconds
Started Jun 05 06:04:25 PM PDT 24
Finished Jun 05 06:04:57 PM PDT 24
Peak memory 266972 kb
Host smart-7ddc768f-e70f-40bb-a4ae-6812ea66dac7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126359375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.3126359375
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.292012813
Short name T892
Test name
Test status
Simulation time 29273000 ps
CPU time 31.59 seconds
Started Jun 05 06:04:32 PM PDT 24
Finished Jun 05 06:05:04 PM PDT 24
Peak memory 274428 kb
Host smart-8f1d4e8e-7d33-4132-9b85-b8c014b615ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292012813 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.292012813
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.800801485
Short name T376
Test name
Test status
Simulation time 2829660200 ps
CPU time 71.59 seconds
Started Jun 05 06:04:29 PM PDT 24
Finished Jun 05 06:05:41 PM PDT 24
Peak memory 262208 kb
Host smart-f1c1d5cb-cb69-4437-ab38-36b2003c59ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800801485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.800801485
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.315998860
Short name T790
Test name
Test status
Simulation time 71933100 ps
CPU time 125.39 seconds
Started Jun 05 06:04:26 PM PDT 24
Finished Jun 05 06:06:32 PM PDT 24
Peak memory 275580 kb
Host smart-f25e4164-7665-476e-a29a-e41364c317c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315998860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.315998860
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.156369436
Short name T451
Test name
Test status
Simulation time 44389900 ps
CPU time 13.65 seconds
Started Jun 05 06:01:30 PM PDT 24
Finished Jun 05 06:01:44 PM PDT 24
Peak memory 264796 kb
Host smart-6115ce3a-aa5c-4378-945c-5c03a01509aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156369436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.156369436
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.2724043957
Short name T752
Test name
Test status
Simulation time 70077300 ps
CPU time 15.51 seconds
Started Jun 05 06:01:32 PM PDT 24
Finished Jun 05 06:01:48 PM PDT 24
Peak memory 275892 kb
Host smart-a68f721f-6d72-4464-bf70-11fbe66f5250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724043957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2724043957
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.1878797679
Short name T909
Test name
Test status
Simulation time 127505300 ps
CPU time 103.19 seconds
Started Jun 05 06:01:24 PM PDT 24
Finished Jun 05 06:03:08 PM PDT 24
Peak memory 272112 kb
Host smart-52ca98d0-69ee-4deb-9e5e-4199dfd12a09
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878797679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_derr_detect.1878797679
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.2093542735
Short name T93
Test name
Test status
Simulation time 15739300 ps
CPU time 21.58 seconds
Started Jun 05 06:01:31 PM PDT 24
Finished Jun 05 06:01:53 PM PDT 24
Peak memory 273240 kb
Host smart-024276e8-798e-4c96-8dac-cedb344be405
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093542735 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.2093542735
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.315235724
Short name T984
Test name
Test status
Simulation time 12012829400 ps
CPU time 423.72 seconds
Started Jun 05 06:01:24 PM PDT 24
Finished Jun 05 06:08:28 PM PDT 24
Peak memory 262832 kb
Host smart-1d6b666d-0633-4b20-94e7-43b881e505f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315235724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.315235724
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.1740204707
Short name T498
Test name
Test status
Simulation time 52088579000 ps
CPU time 2321.73 seconds
Started Jun 05 06:01:22 PM PDT 24
Finished Jun 05 06:40:04 PM PDT 24
Peak memory 264560 kb
Host smart-d14107e6-b8a2-4b5d-ba12-18cce25b49a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740204707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.1740204707
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.3631858161
Short name T173
Test name
Test status
Simulation time 1915825600 ps
CPU time 2503.8 seconds
Started Jun 05 06:01:28 PM PDT 24
Finished Jun 05 06:43:12 PM PDT 24
Peak memory 263756 kb
Host smart-ffdea60d-52da-4320-8684-510369bcb3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631858161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.3631858161
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.3601791900
Short name T559
Test name
Test status
Simulation time 1255381200 ps
CPU time 785.75 seconds
Started Jun 05 06:01:21 PM PDT 24
Finished Jun 05 06:14:27 PM PDT 24
Peak memory 264848 kb
Host smart-ef4979a6-193c-4a12-9018-9f2946d5e0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601791900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.3601791900
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.3357322148
Short name T55
Test name
Test status
Simulation time 506528000 ps
CPU time 27.89 seconds
Started Jun 05 06:01:26 PM PDT 24
Finished Jun 05 06:01:55 PM PDT 24
Peak memory 264852 kb
Host smart-78e4e1cd-abd7-42a7-84be-ac358b8c1f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357322148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.3357322148
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.3908135352
Short name T1015
Test name
Test status
Simulation time 304210700 ps
CPU time 34.34 seconds
Started Jun 05 06:01:32 PM PDT 24
Finished Jun 05 06:02:07 PM PDT 24
Peak memory 261784 kb
Host smart-2bf3f64b-dd9f-439d-816b-c9907800a8c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908135352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.3908135352
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.973948997
Short name T1060
Test name
Test status
Simulation time 212277925100 ps
CPU time 4028.78 seconds
Started Jun 05 06:01:29 PM PDT 24
Finished Jun 05 07:08:39 PM PDT 24
Peak memory 264712 kb
Host smart-c34cf9bb-c441-4b0d-a5f7-0f227fef5a98
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973948997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_full_mem_access.973948997
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.2962604852
Short name T156
Test name
Test status
Simulation time 673728766800 ps
CPU time 2246.95 seconds
Started Jun 05 06:01:22 PM PDT 24
Finished Jun 05 06:38:50 PM PDT 24
Peak memory 264928 kb
Host smart-a4a523c3-203b-45df-a21a-d9b24fe72964
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962604852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.2962604852
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.1851478037
Short name T624
Test name
Test status
Simulation time 198973600 ps
CPU time 92.17 seconds
Started Jun 05 06:01:26 PM PDT 24
Finished Jun 05 06:02:58 PM PDT 24
Peak memory 264836 kb
Host smart-69111978-4a10-44f3-85ef-c76ac0043e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1851478037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.1851478037
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1980071104
Short name T868
Test name
Test status
Simulation time 10023856300 ps
CPU time 67.6 seconds
Started Jun 05 06:01:35 PM PDT 24
Finished Jun 05 06:02:43 PM PDT 24
Peak memory 285920 kb
Host smart-8ef4126c-f83c-4df9-bb39-90670e965d3a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980071104 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.1980071104
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.3122591990
Short name T131
Test name
Test status
Simulation time 34148000 ps
CPU time 13.4 seconds
Started Jun 05 06:01:31 PM PDT 24
Finished Jun 05 06:01:45 PM PDT 24
Peak memory 257892 kb
Host smart-d8bbdf2b-56e9-4cce-aa47-dad13481cb7d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122591990 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.3122591990
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.2224040966
Short name T1034
Test name
Test status
Simulation time 290228200400 ps
CPU time 785.14 seconds
Started Jun 05 06:01:23 PM PDT 24
Finished Jun 05 06:14:28 PM PDT 24
Peak memory 264864 kb
Host smart-d95116b2-84cc-4c1d-9aad-4323932b0d4d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224040966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_hw_rma_reset.2224040966
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.2814032453
Short name T610
Test name
Test status
Simulation time 835885600 ps
CPU time 43.09 seconds
Started Jun 05 06:01:22 PM PDT 24
Finished Jun 05 06:02:05 PM PDT 24
Peak memory 262500 kb
Host smart-6213ced4-176e-4a50-978e-ff11c427e81f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814032453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.2814032453
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.2779410484
Short name T245
Test name
Test status
Simulation time 37373518800 ps
CPU time 762.78 seconds
Started Jun 05 06:01:32 PM PDT 24
Finished Jun 05 06:14:16 PM PDT 24
Peak memory 343380 kb
Host smart-dc767adb-0350-44aa-b4cc-4cbfa10db0e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779410484 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_integrity.2779410484
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.2741946954
Short name T807
Test name
Test status
Simulation time 2329353700 ps
CPU time 153.79 seconds
Started Jun 05 06:01:24 PM PDT 24
Finished Jun 05 06:03:58 PM PDT 24
Peak memory 292964 kb
Host smart-ff99faa0-30b8-4f41-b0c5-0e6bde64fa98
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741946954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.2741946954
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.2160949493
Short name T334
Test name
Test status
Simulation time 12095346300 ps
CPU time 243.75 seconds
Started Jun 05 06:01:30 PM PDT 24
Finished Jun 05 06:05:34 PM PDT 24
Peak memory 293076 kb
Host smart-300021ef-1d91-4cfd-82ee-ebd91adb6c1e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160949493 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.2160949493
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.551617529
Short name T896
Test name
Test status
Simulation time 6158410900 ps
CPU time 70.03 seconds
Started Jun 05 06:01:24 PM PDT 24
Finished Jun 05 06:02:35 PM PDT 24
Peak memory 264896 kb
Host smart-2da538e6-4207-4ed2-bd45-629b05a60ebd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551617529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_intr_wr.551617529
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1263730392
Short name T706
Test name
Test status
Simulation time 21113382100 ps
CPU time 162.45 seconds
Started Jun 05 06:01:45 PM PDT 24
Finished Jun 05 06:04:28 PM PDT 24
Peak memory 259436 kb
Host smart-672881f6-5711-40c2-8277-d26eb4c9fb91
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126
3730392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.1263730392
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.2603778224
Short name T113
Test name
Test status
Simulation time 2088537500 ps
CPU time 65.44 seconds
Started Jun 05 06:01:24 PM PDT 24
Finished Jun 05 06:02:30 PM PDT 24
Peak memory 260424 kb
Host smart-9acbf314-4ec6-4125-8e4a-411df5ebab1c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603778224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.2603778224
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.3680241316
Short name T570
Test name
Test status
Simulation time 117349100 ps
CPU time 13.76 seconds
Started Jun 05 06:01:38 PM PDT 24
Finished Jun 05 06:01:52 PM PDT 24
Peak memory 259984 kb
Host smart-572b971a-c4ed-4582-b54d-29f2c85146c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680241316 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.3680241316
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.1636296520
Short name T104
Test name
Test status
Simulation time 18700075500 ps
CPU time 305.46 seconds
Started Jun 05 06:01:22 PM PDT 24
Finished Jun 05 06:06:28 PM PDT 24
Peak memory 274576 kb
Host smart-8503bac8-32e4-4e9e-9038-3c825d6a3982
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636296520 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.1636296520
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.1868490642
Short name T969
Test name
Test status
Simulation time 131597700 ps
CPU time 134.87 seconds
Started Jun 05 06:01:31 PM PDT 24
Finished Jun 05 06:03:47 PM PDT 24
Peak memory 264452 kb
Host smart-f945bc42-43e7-4d14-ae4b-3f83d7528d8c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868490642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.1868490642
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.2569617296
Short name T924
Test name
Test status
Simulation time 6458239500 ps
CPU time 185.84 seconds
Started Jun 05 06:01:24 PM PDT 24
Finished Jun 05 06:04:31 PM PDT 24
Peak memory 289464 kb
Host smart-4bb37076-258f-44ce-a008-873170db6cb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569617296 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.2569617296
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.1494224259
Short name T212
Test name
Test status
Simulation time 1556269400 ps
CPU time 406.59 seconds
Started Jun 05 06:01:25 PM PDT 24
Finished Jun 05 06:08:13 PM PDT 24
Peak memory 261460 kb
Host smart-770fc21c-c4c6-42e8-9b4a-e5a923467aad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1494224259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1494224259
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.224752862
Short name T465
Test name
Test status
Simulation time 247773500 ps
CPU time 14.61 seconds
Started Jun 05 06:01:34 PM PDT 24
Finished Jun 05 06:01:49 PM PDT 24
Peak memory 264704 kb
Host smart-03831bda-1c85-433a-9962-c4b963bbc47b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224752862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_rese
t.224752862
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.228965511
Short name T1017
Test name
Test status
Simulation time 148121600 ps
CPU time 528.49 seconds
Started Jun 05 06:01:28 PM PDT 24
Finished Jun 05 06:10:17 PM PDT 24
Peak memory 284156 kb
Host smart-0bdc8dda-b20c-4eb9-9d59-ff5cff80b876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228965511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.228965511
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.2800810876
Short name T224
Test name
Test status
Simulation time 2770192000 ps
CPU time 128.94 seconds
Started Jun 05 06:01:23 PM PDT 24
Finished Jun 05 06:03:32 PM PDT 24
Peak memory 264972 kb
Host smart-687d215b-5b9e-4623-b173-d4247daed0c7
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2800810876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.2800810876
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.756991103
Short name T489
Test name
Test status
Simulation time 47505400 ps
CPU time 32.1 seconds
Started Jun 05 06:01:32 PM PDT 24
Finished Jun 05 06:02:05 PM PDT 24
Peak memory 266964 kb
Host smart-11012c48-d642-43a3-9bc5-16d8ceed95bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756991103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_re_evict.756991103
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.1055270482
Short name T436
Test name
Test status
Simulation time 28445500 ps
CPU time 22.31 seconds
Started Jun 05 06:01:23 PM PDT 24
Finished Jun 05 06:01:46 PM PDT 24
Peak memory 264132 kb
Host smart-59910f89-ffdd-411c-a180-c3a82fc506b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055270482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.1055270482
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.1749912336
Short name T6
Test name
Test status
Simulation time 467585700 ps
CPU time 101 seconds
Started Jun 05 06:01:31 PM PDT 24
Finished Jun 05 06:03:12 PM PDT 24
Peak memory 296680 kb
Host smart-d5110f66-b320-478b-b851-6599060d90d6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749912336 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.1749912336
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.4097460552
Short name T203
Test name
Test status
Simulation time 626506600 ps
CPU time 139.9 seconds
Started Jun 05 06:01:24 PM PDT 24
Finished Jun 05 06:03:44 PM PDT 24
Peak memory 281252 kb
Host smart-b0785c84-39b6-446d-a1e6-9bdcc335b46f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4097460552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.4097460552
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.270773821
Short name T602
Test name
Test status
Simulation time 647154300 ps
CPU time 129.51 seconds
Started Jun 05 06:01:23 PM PDT 24
Finished Jun 05 06:03:33 PM PDT 24
Peak memory 281272 kb
Host smart-4e22da49-53fb-4a13-b106-474bd065ed4d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270773821 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.270773821
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.3698980764
Short name T669
Test name
Test status
Simulation time 6618627300 ps
CPU time 506.36 seconds
Started Jun 05 06:01:26 PM PDT 24
Finished Jun 05 06:09:53 PM PDT 24
Peak memory 313408 kb
Host smart-f9860eba-4f6b-4c5b-aa80-a0c16f29eb96
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698980764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_rw.3698980764
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.609725272
Short name T730
Test name
Test status
Simulation time 72826713400 ps
CPU time 795.01 seconds
Started Jun 05 06:01:29 PM PDT 24
Finished Jun 05 06:14:44 PM PDT 24
Peak memory 342436 kb
Host smart-8c24af5a-9a57-4945-aa48-c2d613b96827
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609725272 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.flash_ctrl_rw_derr.609725272
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.1682208463
Short name T733
Test name
Test status
Simulation time 68205100 ps
CPU time 31.43 seconds
Started Jun 05 06:01:29 PM PDT 24
Finished Jun 05 06:02:01 PM PDT 24
Peak memory 274364 kb
Host smart-d80970b3-1866-4f11-a243-fbe651e1d063
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682208463 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.1682208463
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.1379593013
Short name T16
Test name
Test status
Simulation time 2587740600 ps
CPU time 4718.05 seconds
Started Jun 05 06:01:30 PM PDT 24
Finished Jun 05 07:20:09 PM PDT 24
Peak memory 285452 kb
Host smart-0c119c73-a0d6-4b73-aa0d-961d38be4620
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379593013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.1379593013
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.2967334557
Short name T374
Test name
Test status
Simulation time 533953400 ps
CPU time 56.12 seconds
Started Jun 05 06:01:32 PM PDT 24
Finished Jun 05 06:02:29 PM PDT 24
Peak memory 262124 kb
Host smart-31852b72-f207-405f-ba23-55b1ef10863b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967334557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.2967334557
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.3294664327
Short name T617
Test name
Test status
Simulation time 1946201100 ps
CPU time 57.31 seconds
Started Jun 05 06:01:28 PM PDT 24
Finished Jun 05 06:02:25 PM PDT 24
Peak memory 264904 kb
Host smart-454637a3-e0b3-4d96-abed-2e1b48e9b6a2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294664327 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.3294664327
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.593449042
Short name T613
Test name
Test status
Simulation time 686585300 ps
CPU time 76.29 seconds
Started Jun 05 06:01:25 PM PDT 24
Finished Jun 05 06:02:41 PM PDT 24
Peak memory 273172 kb
Host smart-a104ec88-11fd-4851-8358-a8a88691c3be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593449042 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_counter.593449042
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.3822190078
Short name T703
Test name
Test status
Simulation time 147033700 ps
CPU time 122.25 seconds
Started Jun 05 06:01:24 PM PDT 24
Finished Jun 05 06:03:27 PM PDT 24
Peak memory 277004 kb
Host smart-0bdf4b88-cd18-4e76-8dd1-6550b045e278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822190078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.3822190078
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.1150334026
Short name T408
Test name
Test status
Simulation time 52400300 ps
CPU time 27.05 seconds
Started Jun 05 06:01:27 PM PDT 24
Finished Jun 05 06:01:55 PM PDT 24
Peak memory 258840 kb
Host smart-7dc4a1c0-1ba5-4af7-bdb9-c61c3c0e99f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150334026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1150334026
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.202524023
Short name T462
Test name
Test status
Simulation time 510111200 ps
CPU time 222.16 seconds
Started Jun 05 06:01:33 PM PDT 24
Finished Jun 05 06:05:16 PM PDT 24
Peak memory 281388 kb
Host smart-c43a1644-f5d1-4dd1-827c-02ae5546d9e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202524023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress
_all.202524023
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.1936562636
Short name T398
Test name
Test status
Simulation time 30118400 ps
CPU time 24.06 seconds
Started Jun 05 06:01:29 PM PDT 24
Finished Jun 05 06:01:54 PM PDT 24
Peak memory 261300 kb
Host smart-c979df4a-c110-46d1-8a59-b3b8998f0150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936562636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.1936562636
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.1535916827
Short name T110
Test name
Test status
Simulation time 19312872500 ps
CPU time 181.01 seconds
Started Jun 05 06:01:26 PM PDT 24
Finished Jun 05 06:04:28 PM PDT 24
Peak memory 258568 kb
Host smart-be11a6ab-88ab-48cf-8c72-3ae090d29f69
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535916827 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_wo.1535916827
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.3068636249
Short name T389
Test name
Test status
Simulation time 18927100 ps
CPU time 14.39 seconds
Started Jun 05 06:04:32 PM PDT 24
Finished Jun 05 06:04:46 PM PDT 24
Peak memory 264772 kb
Host smart-39860796-7bc0-401e-b7b5-6292d37c5be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068636249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
3068636249
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.41336002
Short name T837
Test name
Test status
Simulation time 50506300 ps
CPU time 15.66 seconds
Started Jun 05 06:04:32 PM PDT 24
Finished Jun 05 06:04:48 PM PDT 24
Peak memory 275864 kb
Host smart-b85c8d54-6101-4b3d-bb3c-0fa66fda604c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41336002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.41336002
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.3633687122
Short name T864
Test name
Test status
Simulation time 19161500 ps
CPU time 22.06 seconds
Started Jun 05 06:04:32 PM PDT 24
Finished Jun 05 06:04:54 PM PDT 24
Peak memory 273164 kb
Host smart-9d783f04-b64c-4197-a420-80825fbec4f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633687122 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.3633687122
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.3371965835
Short name T863
Test name
Test status
Simulation time 33896136700 ps
CPU time 137.55 seconds
Started Jun 05 06:04:30 PM PDT 24
Finished Jun 05 06:06:48 PM PDT 24
Peak memory 262272 kb
Host smart-4c77ae6c-7eec-4e1c-97f2-614c4cf418b0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371965835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.3371965835
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.1552937111
Short name T596
Test name
Test status
Simulation time 2877552200 ps
CPU time 150.53 seconds
Started Jun 05 06:04:33 PM PDT 24
Finished Jun 05 06:07:04 PM PDT 24
Peak memory 292784 kb
Host smart-727a2728-7e6f-4f00-a455-b11d282a5ada
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552937111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.1552937111
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.2139508320
Short name T384
Test name
Test status
Simulation time 42582382000 ps
CPU time 493.86 seconds
Started Jun 05 06:04:31 PM PDT 24
Finished Jun 05 06:12:45 PM PDT 24
Peak memory 291456 kb
Host smart-451f87ca-5548-437b-ab21-bc45bd860717
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139508320 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.2139508320
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.3751163331
Short name T446
Test name
Test status
Simulation time 85802000 ps
CPU time 131.48 seconds
Started Jun 05 06:04:32 PM PDT 24
Finished Jun 05 06:06:44 PM PDT 24
Peak memory 259820 kb
Host smart-d5643fcb-aeef-4269-b09a-56a1a87cde64
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751163331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.3751163331
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.4174451009
Short name T584
Test name
Test status
Simulation time 66838300 ps
CPU time 28.42 seconds
Started Jun 05 06:04:32 PM PDT 24
Finished Jun 05 06:05:01 PM PDT 24
Peak memory 273124 kb
Host smart-8106549b-49f5-4ac1-a374-ac13e35ccf87
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174451009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.4174451009
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.2357265165
Short name T800
Test name
Test status
Simulation time 29226400 ps
CPU time 28.64 seconds
Started Jun 05 06:04:30 PM PDT 24
Finished Jun 05 06:04:59 PM PDT 24
Peak memory 268864 kb
Host smart-db08f547-af23-4a92-92bd-8df764136bb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357265165 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.2357265165
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.2487835266
Short name T360
Test name
Test status
Simulation time 1870309200 ps
CPU time 74.85 seconds
Started Jun 05 06:04:31 PM PDT 24
Finished Jun 05 06:05:46 PM PDT 24
Peak memory 263200 kb
Host smart-53457b5d-1c09-4b81-8b99-4a5dd5980382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487835266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.2487835266
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.1148419714
Short name T667
Test name
Test status
Simulation time 26095100 ps
CPU time 122.4 seconds
Started Jun 05 06:04:31 PM PDT 24
Finished Jun 05 06:06:34 PM PDT 24
Peak memory 276888 kb
Host smart-cfd10f8d-7f4f-44a0-9641-ce43d06f1792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148419714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.1148419714
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.3402580747
Short name T1051
Test name
Test status
Simulation time 111132000 ps
CPU time 13.59 seconds
Started Jun 05 06:04:40 PM PDT 24
Finished Jun 05 06:04:55 PM PDT 24
Peak memory 257920 kb
Host smart-2a9f5712-4cd3-4c3b-8116-d3994d216a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402580747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
3402580747
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.1447061777
Short name T657
Test name
Test status
Simulation time 56000700 ps
CPU time 15.77 seconds
Started Jun 05 06:04:40 PM PDT 24
Finished Jun 05 06:04:57 PM PDT 24
Peak memory 275540 kb
Host smart-5b30136c-4ea8-4f0a-90e5-779e0fb1b6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447061777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.1447061777
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.1154349933
Short name T91
Test name
Test status
Simulation time 24798100 ps
CPU time 20.41 seconds
Started Jun 05 06:04:40 PM PDT 24
Finished Jun 05 06:05:01 PM PDT 24
Peak memory 264960 kb
Host smart-b2879658-a79d-4175-9141-b5cd95bfb830
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154349933 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.1154349933
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.3617188342
Short name T307
Test name
Test status
Simulation time 3171881800 ps
CPU time 53.56 seconds
Started Jun 05 06:04:38 PM PDT 24
Finished Jun 05 06:05:32 PM PDT 24
Peak memory 262396 kb
Host smart-03d4b65c-73b3-4251-813b-f2a42d3c9c95
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617188342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.3617188342
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.840984158
Short name T829
Test name
Test status
Simulation time 3564089200 ps
CPU time 198.28 seconds
Started Jun 05 06:04:40 PM PDT 24
Finished Jun 05 06:07:59 PM PDT 24
Peak memory 289460 kb
Host smart-f06c29a0-b432-427d-a0c8-9e0bc28dd05e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840984158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flas
h_ctrl_intr_rd.840984158
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.1276484017
Short name T789
Test name
Test status
Simulation time 25799537900 ps
CPU time 325.73 seconds
Started Jun 05 06:04:36 PM PDT 24
Finished Jun 05 06:10:02 PM PDT 24
Peak memory 291548 kb
Host smart-ded603c6-0c6d-405a-b6d5-8fd1b5c4ce5c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276484017 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.1276484017
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.1407835973
Short name T951
Test name
Test status
Simulation time 46440800 ps
CPU time 111.22 seconds
Started Jun 05 06:04:39 PM PDT 24
Finished Jun 05 06:06:31 PM PDT 24
Peak memory 260856 kb
Host smart-3132c5cb-4634-42d2-a291-b5c7afb1e5c6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407835973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.1407835973
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.3138620133
Short name T912
Test name
Test status
Simulation time 46249900 ps
CPU time 31.45 seconds
Started Jun 05 06:04:41 PM PDT 24
Finished Jun 05 06:05:13 PM PDT 24
Peak memory 275756 kb
Host smart-72b82a57-a2f7-4b52-819c-e41af4d3b39b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138620133 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.3138620133
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.614019544
Short name T362
Test name
Test status
Simulation time 9546892200 ps
CPU time 81.76 seconds
Started Jun 05 06:04:40 PM PDT 24
Finished Jun 05 06:06:03 PM PDT 24
Peak memory 262060 kb
Host smart-d577a5bc-5856-48d2-aa6d-d74f2677cd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614019544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.614019544
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.3317760620
Short name T480
Test name
Test status
Simulation time 24693900 ps
CPU time 73.72 seconds
Started Jun 05 06:04:42 PM PDT 24
Finished Jun 05 06:05:57 PM PDT 24
Peak memory 274820 kb
Host smart-f75eb3e1-1a5a-42e2-9036-a3c009e63728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317760620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.3317760620
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.2537893161
Short name T576
Test name
Test status
Simulation time 24635800 ps
CPU time 13.94 seconds
Started Jun 05 06:04:49 PM PDT 24
Finished Jun 05 06:05:04 PM PDT 24
Peak memory 264220 kb
Host smart-952b58ad-ad7c-4669-9749-ad6b78b3c802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537893161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
2537893161
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.871872410
Short name T722
Test name
Test status
Simulation time 23354900 ps
CPU time 13.24 seconds
Started Jun 05 06:04:47 PM PDT 24
Finished Jun 05 06:05:00 PM PDT 24
Peak memory 274764 kb
Host smart-7f47cf5c-ceed-434d-8c8e-3cb201b08cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871872410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.871872410
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.3373374900
Short name T390
Test name
Test status
Simulation time 31845400 ps
CPU time 20.39 seconds
Started Jun 05 06:04:48 PM PDT 24
Finished Jun 05 06:05:09 PM PDT 24
Peak memory 273280 kb
Host smart-b2f9ed06-a742-44ac-97dd-8e14aaef0ac3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373374900 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.3373374900
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.4092578791
Short name T308
Test name
Test status
Simulation time 2171873500 ps
CPU time 171.64 seconds
Started Jun 05 06:04:44 PM PDT 24
Finished Jun 05 06:07:36 PM PDT 24
Peak memory 262216 kb
Host smart-7ff3a810-32c7-4eb6-a1ef-8fcf2778e62f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092578791 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.4092578791
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.3530123003
Short name T605
Test name
Test status
Simulation time 1181762400 ps
CPU time 142.91 seconds
Started Jun 05 06:04:38 PM PDT 24
Finished Jun 05 06:07:02 PM PDT 24
Peak memory 291764 kb
Host smart-43b5b92a-388b-40eb-9ce0-9b74ae186bf2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530123003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.3530123003
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1390483913
Short name T331
Test name
Test status
Simulation time 41271963700 ps
CPU time 432.99 seconds
Started Jun 05 06:04:47 PM PDT 24
Finished Jun 05 06:12:01 PM PDT 24
Peak memory 293000 kb
Host smart-53030bce-cc8e-4caf-a351-6728911ffb09
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390483913 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.1390483913
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.821309763
Short name T477
Test name
Test status
Simulation time 35135400 ps
CPU time 129.43 seconds
Started Jun 05 06:04:39 PM PDT 24
Finished Jun 05 06:06:49 PM PDT 24
Peak memory 260732 kb
Host smart-a39243ba-278c-4bf4-a35f-e61d2c9ddeed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821309763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ot
p_reset.821309763
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.3719871644
Short name T593
Test name
Test status
Simulation time 74008600 ps
CPU time 31.07 seconds
Started Jun 05 06:04:49 PM PDT 24
Finished Jun 05 06:05:20 PM PDT 24
Peak memory 275212 kb
Host smart-7bcb6baf-2905-4161-beb1-16825a3c14f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719871644 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.3719871644
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.192109974
Short name T745
Test name
Test status
Simulation time 497805900 ps
CPU time 53.89 seconds
Started Jun 05 06:04:49 PM PDT 24
Finished Jun 05 06:05:44 PM PDT 24
Peak memory 262228 kb
Host smart-a719d110-4360-4118-94b6-8eae2b6816fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192109974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.192109974
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.3126266033
Short name T1
Test name
Test status
Simulation time 64685600 ps
CPU time 143.42 seconds
Started Jun 05 06:04:38 PM PDT 24
Finished Jun 05 06:07:02 PM PDT 24
Peak memory 276224 kb
Host smart-b8243d09-5ef8-4138-babf-777af53ff6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126266033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.3126266033
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.1367810650
Short name T677
Test name
Test status
Simulation time 34214200 ps
CPU time 13.36 seconds
Started Jun 05 06:04:48 PM PDT 24
Finished Jun 05 06:05:02 PM PDT 24
Peak memory 257940 kb
Host smart-75632f1b-1d65-4dd4-be05-f4b3cad3a7ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367810650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
1367810650
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.2233810361
Short name T524
Test name
Test status
Simulation time 207082300 ps
CPU time 16.24 seconds
Started Jun 05 06:04:49 PM PDT 24
Finished Jun 05 06:05:06 PM PDT 24
Peak memory 275464 kb
Host smart-8238dc03-f380-40b7-b8ae-11f37cd236a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233810361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2233810361
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.3778192807
Short name T353
Test name
Test status
Simulation time 36937800 ps
CPU time 20.81 seconds
Started Jun 05 06:04:50 PM PDT 24
Finished Jun 05 06:05:11 PM PDT 24
Peak memory 273172 kb
Host smart-2806bf01-981a-4d47-808d-03a24ddd3b03
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778192807 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.3778192807
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.2631696748
Short name T702
Test name
Test status
Simulation time 7443406500 ps
CPU time 154.4 seconds
Started Jun 05 06:04:48 PM PDT 24
Finished Jun 05 06:07:23 PM PDT 24
Peak memory 262500 kb
Host smart-299e913f-eae7-4ee1-a2f1-46d63d6e075d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631696748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.2631696748
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.3136597787
Short name T957
Test name
Test status
Simulation time 8603480000 ps
CPU time 221.27 seconds
Started Jun 05 06:04:49 PM PDT 24
Finished Jun 05 06:08:31 PM PDT 24
Peak memory 289528 kb
Host smart-dd87ddbd-1a24-4121-b973-4cfc482fd5b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136597787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.3136597787
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.741574896
Short name T342
Test name
Test status
Simulation time 5967349000 ps
CPU time 149.36 seconds
Started Jun 05 06:04:48 PM PDT 24
Finished Jun 05 06:07:17 PM PDT 24
Peak memory 293568 kb
Host smart-5c879a65-5bfd-4291-9db9-178e2ddff510
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741574896 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.741574896
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.1689553696
Short name T1092
Test name
Test status
Simulation time 137917100 ps
CPU time 131.06 seconds
Started Jun 05 06:04:50 PM PDT 24
Finished Jun 05 06:07:02 PM PDT 24
Peak memory 264044 kb
Host smart-db9ad5bb-ba38-4385-9d40-4f5859a5fea3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689553696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.1689553696
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.662365171
Short name T567
Test name
Test status
Simulation time 92291300 ps
CPU time 31.23 seconds
Started Jun 05 06:04:47 PM PDT 24
Finished Jun 05 06:05:18 PM PDT 24
Peak memory 266972 kb
Host smart-c77f08df-f4fd-4d10-8b6d-59956607ffc7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662365171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_rw_evict.662365171
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.3367251583
Short name T404
Test name
Test status
Simulation time 32448700 ps
CPU time 31.01 seconds
Started Jun 05 06:04:49 PM PDT 24
Finished Jun 05 06:05:21 PM PDT 24
Peak memory 275136 kb
Host smart-db44f0b5-fc61-47e1-8c58-a2c864f4d1d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367251583 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.3367251583
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.2829971577
Short name T175
Test name
Test status
Simulation time 826703200 ps
CPU time 58.14 seconds
Started Jun 05 06:04:48 PM PDT 24
Finished Jun 05 06:05:47 PM PDT 24
Peak memory 263304 kb
Host smart-b8e88e34-0d72-4c77-a0d0-b0696ec7284b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829971577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.2829971577
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.1461572338
Short name T923
Test name
Test status
Simulation time 96818400 ps
CPU time 144.59 seconds
Started Jun 05 06:04:48 PM PDT 24
Finished Jun 05 06:07:13 PM PDT 24
Peak memory 277352 kb
Host smart-f01fb53b-dc63-459d-8774-6469d303739f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461572338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.1461572338
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.2385013846
Short name T1096
Test name
Test status
Simulation time 40445900 ps
CPU time 13.38 seconds
Started Jun 05 06:04:53 PM PDT 24
Finished Jun 05 06:05:07 PM PDT 24
Peak memory 264752 kb
Host smart-3a13b31c-a216-41f5-a9ad-c0bfac93d88b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385013846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
2385013846
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.3911901201
Short name T821
Test name
Test status
Simulation time 50451600 ps
CPU time 15.43 seconds
Started Jun 05 06:04:58 PM PDT 24
Finished Jun 05 06:05:14 PM PDT 24
Peak memory 275812 kb
Host smart-af6aa7e9-7753-4297-ac60-4ce1ea45a35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911901201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.3911901201
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.1487069897
Short name T782
Test name
Test status
Simulation time 13259000 ps
CPU time 21.9 seconds
Started Jun 05 06:04:55 PM PDT 24
Finished Jun 05 06:05:18 PM PDT 24
Peak memory 264908 kb
Host smart-c86b1b15-cd52-4347-8713-fd2a037e10c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487069897 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.1487069897
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.997015812
Short name T933
Test name
Test status
Simulation time 18701327800 ps
CPU time 145.13 seconds
Started Jun 05 06:04:49 PM PDT 24
Finished Jun 05 06:07:15 PM PDT 24
Peak memory 262284 kb
Host smart-8dbe8aa7-22ec-4a95-abc0-a02c297f0776
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997015812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_h
w_sec_otp.997015812
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.434719776
Short name T333
Test name
Test status
Simulation time 118985421200 ps
CPU time 393.57 seconds
Started Jun 05 06:04:53 PM PDT 24
Finished Jun 05 06:11:27 PM PDT 24
Peak memory 293048 kb
Host smart-193c17e1-2e70-4ca0-9d56-eaa7fb24015d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434719776 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.434719776
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.3232993789
Short name T911
Test name
Test status
Simulation time 369133500 ps
CPU time 131.45 seconds
Started Jun 05 06:04:57 PM PDT 24
Finished Jun 05 06:07:09 PM PDT 24
Peak memory 263972 kb
Host smart-01a6184a-1c9b-4aa0-9f84-4e83f8d5ac00
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232993789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.3232993789
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.3426991535
Short name T1093
Test name
Test status
Simulation time 34393100 ps
CPU time 31.42 seconds
Started Jun 05 06:04:54 PM PDT 24
Finished Jun 05 06:05:26 PM PDT 24
Peak memory 274148 kb
Host smart-12b33d49-72a8-40e2-823e-1601b62e1288
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426991535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.3426991535
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.4125640523
Short name T423
Test name
Test status
Simulation time 33917800 ps
CPU time 30.97 seconds
Started Jun 05 06:04:55 PM PDT 24
Finished Jun 05 06:05:26 PM PDT 24
Peak memory 273064 kb
Host smart-f0ab1f0c-9367-419e-b142-61d0156a9676
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125640523 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.4125640523
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.3329348519
Short name T381
Test name
Test status
Simulation time 1909831900 ps
CPU time 73.56 seconds
Started Jun 05 06:04:55 PM PDT 24
Finished Jun 05 06:06:10 PM PDT 24
Peak memory 264780 kb
Host smart-1019da8b-2590-4ddd-90e8-e4b5373a7d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329348519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3329348519
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.740709092
Short name T899
Test name
Test status
Simulation time 33715400 ps
CPU time 75.85 seconds
Started Jun 05 06:04:48 PM PDT 24
Finished Jun 05 06:06:05 PM PDT 24
Peak memory 275916 kb
Host smart-864dca33-d346-461e-8e88-ff299928ffd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740709092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.740709092
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.368816756
Short name T387
Test name
Test status
Simulation time 96865900 ps
CPU time 13.75 seconds
Started Jun 05 06:04:57 PM PDT 24
Finished Jun 05 06:05:11 PM PDT 24
Peak memory 257856 kb
Host smart-afe7f929-4373-4210-8f6c-122f43767dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368816756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.368816756
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.42439805
Short name T750
Test name
Test status
Simulation time 16731500 ps
CPU time 13.52 seconds
Started Jun 05 06:04:53 PM PDT 24
Finished Jun 05 06:05:07 PM PDT 24
Peak memory 276040 kb
Host smart-731472ba-3ef6-45eb-985f-66782878c6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42439805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.42439805
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.217719394
Short name T726
Test name
Test status
Simulation time 25707300 ps
CPU time 22.01 seconds
Started Jun 05 06:04:56 PM PDT 24
Finished Jun 05 06:05:18 PM PDT 24
Peak memory 280004 kb
Host smart-85c8da12-778e-488e-8242-073a555fe0f6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217719394 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.217719394
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.2300903869
Short name T759
Test name
Test status
Simulation time 1644878700 ps
CPU time 187 seconds
Started Jun 05 06:04:57 PM PDT 24
Finished Jun 05 06:08:05 PM PDT 24
Peak memory 289452 kb
Host smart-bcc08bf4-071b-4bc4-99e7-77bdee45200d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300903869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fla
sh_ctrl_intr_rd.2300903869
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.604494012
Short name T508
Test name
Test status
Simulation time 17196237000 ps
CPU time 269.66 seconds
Started Jun 05 06:04:57 PM PDT 24
Finished Jun 05 06:09:28 PM PDT 24
Peak memory 292908 kb
Host smart-092c9efa-b8b3-4c47-b9b2-457f94b60628
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604494012 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.604494012
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.1911370580
Short name T330
Test name
Test status
Simulation time 73084300 ps
CPU time 28.49 seconds
Started Jun 05 06:04:56 PM PDT 24
Finished Jun 05 06:05:25 PM PDT 24
Peak memory 274472 kb
Host smart-a0430f3d-34a0-4baa-9e37-74f04ce594bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911370580 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.1911370580
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.399580063
Short name T682
Test name
Test status
Simulation time 7431225600 ps
CPU time 79.11 seconds
Started Jun 05 06:04:53 PM PDT 24
Finished Jun 05 06:06:12 PM PDT 24
Peak memory 264756 kb
Host smart-b46762cc-5877-45ff-a3a0-1dde385109bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399580063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.399580063
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.1070881826
Short name T895
Test name
Test status
Simulation time 293459900 ps
CPU time 197.18 seconds
Started Jun 05 06:04:53 PM PDT 24
Finished Jun 05 06:08:11 PM PDT 24
Peak memory 276752 kb
Host smart-7f6460bc-1fd4-4b51-a77d-368bb7b34ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070881826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.1070881826
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.1391167909
Short name T820
Test name
Test status
Simulation time 139736000 ps
CPU time 13.67 seconds
Started Jun 05 06:04:52 PM PDT 24
Finished Jun 05 06:05:07 PM PDT 24
Peak memory 264820 kb
Host smart-81fe72cc-11df-441e-925d-6dcec6b37c0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391167909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
1391167909
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.218285043
Short name T713
Test name
Test status
Simulation time 44724600 ps
CPU time 15.93 seconds
Started Jun 05 06:04:56 PM PDT 24
Finished Jun 05 06:05:12 PM PDT 24
Peak memory 275860 kb
Host smart-4167349e-4cc2-487a-a3ce-1448ec93b639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218285043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.218285043
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.390580427
Short name T678
Test name
Test status
Simulation time 29377100 ps
CPU time 21.14 seconds
Started Jun 05 06:04:55 PM PDT 24
Finished Jun 05 06:05:17 PM PDT 24
Peak memory 273116 kb
Host smart-21897d16-dc34-473f-9ce8-0308ba34e2cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390580427 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.390580427
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.3918663208
Short name T1014
Test name
Test status
Simulation time 3276960300 ps
CPU time 33.82 seconds
Started Jun 05 06:04:55 PM PDT 24
Finished Jun 05 06:05:29 PM PDT 24
Peak memory 262368 kb
Host smart-2eb8eb20-f164-4705-8fb0-a2514a2f0e1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918663208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.3918663208
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.101610776
Short name T437
Test name
Test status
Simulation time 7430649400 ps
CPU time 136.42 seconds
Started Jun 05 06:04:54 PM PDT 24
Finished Jun 05 06:07:11 PM PDT 24
Peak memory 292788 kb
Host smart-b9886ea5-30c3-4cb1-a90c-aa70f60bf4fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101610776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flas
h_ctrl_intr_rd.101610776
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3938026514
Short name T781
Test name
Test status
Simulation time 5718706900 ps
CPU time 133.65 seconds
Started Jun 05 06:04:55 PM PDT 24
Finished Jun 05 06:07:09 PM PDT 24
Peak memory 292544 kb
Host smart-493c3776-c91d-4615-820a-038f974d4b5b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938026514 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.3938026514
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.556853951
Short name T674
Test name
Test status
Simulation time 140976500 ps
CPU time 113.47 seconds
Started Jun 05 06:04:55 PM PDT 24
Finished Jun 05 06:06:49 PM PDT 24
Peak memory 263764 kb
Host smart-e1bb5edc-929c-4c7e-a06a-891360e2bc97
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556853951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_ot
p_reset.556853951
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.3932227239
Short name T434
Test name
Test status
Simulation time 79320300 ps
CPU time 31.11 seconds
Started Jun 05 06:04:59 PM PDT 24
Finished Jun 05 06:05:31 PM PDT 24
Peak memory 272980 kb
Host smart-2fe22920-dea0-4aea-bdbb-99b7fdd51229
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932227239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.3932227239
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.3216817251
Short name T612
Test name
Test status
Simulation time 33882400 ps
CPU time 28.43 seconds
Started Jun 05 06:04:56 PM PDT 24
Finished Jun 05 06:05:25 PM PDT 24
Peak memory 274496 kb
Host smart-8ce892f5-c599-4ce5-b237-fdd9f7803b9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216817251 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.3216817251
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.3543816832
Short name T629
Test name
Test status
Simulation time 2481032400 ps
CPU time 61.49 seconds
Started Jun 05 06:04:59 PM PDT 24
Finished Jun 05 06:06:01 PM PDT 24
Peak memory 263044 kb
Host smart-155ac2a9-b5df-4999-b936-e78f05a927c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543816832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.3543816832
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.1830697840
Short name T681
Test name
Test status
Simulation time 22000900 ps
CPU time 147.91 seconds
Started Jun 05 06:04:51 PM PDT 24
Finished Jun 05 06:07:20 PM PDT 24
Peak memory 276956 kb
Host smart-7a815048-a00f-4230-a1d8-736a8e036895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830697840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.1830697840
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.1934097334
Short name T505
Test name
Test status
Simulation time 213264900 ps
CPU time 13.98 seconds
Started Jun 05 06:05:02 PM PDT 24
Finished Jun 05 06:05:17 PM PDT 24
Peak memory 264796 kb
Host smart-033976dc-b4c8-475e-912c-69f67d4f7311
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934097334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
1934097334
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.2429646065
Short name T354
Test name
Test status
Simulation time 127680300 ps
CPU time 21.71 seconds
Started Jun 05 06:05:02 PM PDT 24
Finished Jun 05 06:05:24 PM PDT 24
Peak memory 273196 kb
Host smart-fea24db4-f934-4769-8bcb-7b2f0d90bc02
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429646065 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.2429646065
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1235928419
Short name T418
Test name
Test status
Simulation time 4833969000 ps
CPU time 44.99 seconds
Started Jun 05 06:04:56 PM PDT 24
Finished Jun 05 06:05:42 PM PDT 24
Peak memory 262480 kb
Host smart-62b04656-4336-4756-aedb-da1186ab12c3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235928419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.1235928419
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.2451162843
Short name T588
Test name
Test status
Simulation time 1348296800 ps
CPU time 141.82 seconds
Started Jun 05 06:05:02 PM PDT 24
Finished Jun 05 06:07:25 PM PDT 24
Peak memory 292836 kb
Host smart-eaccffd6-fa61-44ec-8ced-7c4a9ecdafa0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451162843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.2451162843
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.3676285088
Short name T636
Test name
Test status
Simulation time 57751881100 ps
CPU time 159.36 seconds
Started Jun 05 06:05:02 PM PDT 24
Finished Jun 05 06:07:42 PM PDT 24
Peak memory 292968 kb
Host smart-fcde670a-b258-430e-a84f-116fa94b184d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676285088 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.3676285088
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.814566235
Short name T531
Test name
Test status
Simulation time 105793800 ps
CPU time 109.22 seconds
Started Jun 05 06:04:55 PM PDT 24
Finished Jun 05 06:06:45 PM PDT 24
Peak memory 259760 kb
Host smart-559f3393-e6b1-4005-bc17-364d80e8f74a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814566235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_ot
p_reset.814566235
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.1678767998
Short name T981
Test name
Test status
Simulation time 49858000 ps
CPU time 31.77 seconds
Started Jun 05 06:05:02 PM PDT 24
Finished Jun 05 06:05:34 PM PDT 24
Peak memory 273176 kb
Host smart-35296d5c-e039-46b2-8d42-cec4ea2955a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678767998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.1678767998
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3672794365
Short name T720
Test name
Test status
Simulation time 44646000 ps
CPU time 31.39 seconds
Started Jun 05 06:05:03 PM PDT 24
Finished Jun 05 06:05:34 PM PDT 24
Peak memory 275168 kb
Host smart-8f337eac-be90-42fe-a39f-79eac3177b48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672794365 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.3672794365
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.35038387
Short name T33
Test name
Test status
Simulation time 2872093100 ps
CPU time 64.11 seconds
Started Jun 05 06:05:00 PM PDT 24
Finished Jun 05 06:06:05 PM PDT 24
Peak memory 263240 kb
Host smart-93ed35e1-c6bc-40cf-985e-cab94ea00e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35038387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.35038387
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.1422912718
Short name T572
Test name
Test status
Simulation time 28127000 ps
CPU time 124.55 seconds
Started Jun 05 06:04:55 PM PDT 24
Finished Jun 05 06:07:00 PM PDT 24
Peak memory 276720 kb
Host smart-4f074607-f974-45ff-b493-6197e5694728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422912718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.1422912718
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.3828646391
Short name T469
Test name
Test status
Simulation time 68782000 ps
CPU time 13.49 seconds
Started Jun 05 06:05:09 PM PDT 24
Finished Jun 05 06:05:23 PM PDT 24
Peak memory 264848 kb
Host smart-3c2d6c19-349c-4a39-a6bb-7e4022fcc76c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828646391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
3828646391
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.3652172922
Short name T564
Test name
Test status
Simulation time 41898300 ps
CPU time 15.96 seconds
Started Jun 05 06:05:13 PM PDT 24
Finished Jun 05 06:05:29 PM PDT 24
Peak memory 275032 kb
Host smart-ac7606e8-722e-474a-acb7-9b2c0c0d5126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652172922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.3652172922
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.119497265
Short name T978
Test name
Test status
Simulation time 12605600 ps
CPU time 22.43 seconds
Started Jun 05 06:05:05 PM PDT 24
Finished Jun 05 06:05:28 PM PDT 24
Peak memory 273172 kb
Host smart-0f5d062b-8462-4110-85f1-b9787e9f3329
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119497265 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.119497265
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.347059628
Short name T690
Test name
Test status
Simulation time 7259861200 ps
CPU time 105.6 seconds
Started Jun 05 06:05:02 PM PDT 24
Finished Jun 05 06:06:48 PM PDT 24
Peak memory 262532 kb
Host smart-cd154818-1954-4618-b22d-fd149313f2b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347059628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_h
w_sec_otp.347059628
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.896205797
Short name T723
Test name
Test status
Simulation time 3237617300 ps
CPU time 151.05 seconds
Started Jun 05 06:05:03 PM PDT 24
Finished Jun 05 06:07:35 PM PDT 24
Peak memory 295468 kb
Host smart-28d160aa-74ca-49be-9d31-10011a31121d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896205797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flas
h_ctrl_intr_rd.896205797
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.2920914034
Short name T37
Test name
Test status
Simulation time 12916915600 ps
CPU time 135.84 seconds
Started Jun 05 06:05:00 PM PDT 24
Finished Jun 05 06:07:17 PM PDT 24
Peak memory 292468 kb
Host smart-8423ac47-c167-464d-95bb-d11b28f556a3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920914034 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.2920914034
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.4030881974
Short name T609
Test name
Test status
Simulation time 450773300 ps
CPU time 130.73 seconds
Started Jun 05 06:05:01 PM PDT 24
Finished Jun 05 06:07:12 PM PDT 24
Peak memory 259416 kb
Host smart-525c541e-5361-45c0-b19e-12c3e852577a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030881974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.4030881974
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.3399136132
Short name T26
Test name
Test status
Simulation time 243415800 ps
CPU time 30.49 seconds
Started Jun 05 06:05:04 PM PDT 24
Finished Jun 05 06:05:35 PM PDT 24
Peak memory 273108 kb
Host smart-1fe75ce6-d3ab-49c0-acd3-8a4ae7864d29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399136132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.3399136132
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.121547430
Short name T700
Test name
Test status
Simulation time 32342600 ps
CPU time 30.52 seconds
Started Jun 05 06:05:02 PM PDT 24
Finished Jun 05 06:05:33 PM PDT 24
Peak memory 274336 kb
Host smart-a8291bd3-6fe8-4219-855c-cc8bd2d6e51f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121547430 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.121547430
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.2968557219
Short name T377
Test name
Test status
Simulation time 2815151400 ps
CPU time 63.82 seconds
Started Jun 05 06:05:04 PM PDT 24
Finished Jun 05 06:06:09 PM PDT 24
Peak memory 262668 kb
Host smart-3d14fa39-dd2e-40fa-937a-65dc858b3fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968557219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2968557219
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.628836268
Short name T650
Test name
Test status
Simulation time 76499400 ps
CPU time 192.51 seconds
Started Jun 05 06:05:02 PM PDT 24
Finished Jun 05 06:08:15 PM PDT 24
Peak memory 277068 kb
Host smart-5e07328d-16a8-41c6-aa4c-d52f1618d02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628836268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.628836268
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.3088615787
Short name T1057
Test name
Test status
Simulation time 28887400 ps
CPU time 13.65 seconds
Started Jun 05 06:05:09 PM PDT 24
Finished Jun 05 06:05:23 PM PDT 24
Peak memory 257824 kb
Host smart-8473312b-7fda-4b28-9698-08f452a37878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088615787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
3088615787
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.2027794805
Short name T1048
Test name
Test status
Simulation time 46494700 ps
CPU time 13.42 seconds
Started Jun 05 06:05:07 PM PDT 24
Finished Jun 05 06:05:21 PM PDT 24
Peak memory 274820 kb
Host smart-fb462aaf-e4fe-4f6b-85a4-c5454627bd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027794805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2027794805
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.2348521360
Short name T92
Test name
Test status
Simulation time 11031700 ps
CPU time 21.55 seconds
Started Jun 05 06:05:10 PM PDT 24
Finished Jun 05 06:05:32 PM PDT 24
Peak memory 273188 kb
Host smart-79010581-9a7f-4a94-81f2-e4e5453aa6f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348521360 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.2348521360
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.2857105769
Short name T956
Test name
Test status
Simulation time 30375584700 ps
CPU time 118.03 seconds
Started Jun 05 06:05:08 PM PDT 24
Finished Jun 05 06:07:07 PM PDT 24
Peak memory 262388 kb
Host smart-3e96a69a-5d86-4f4a-b5b9-2def3cc40c2f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857105769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.2857105769
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.748473154
Short name T269
Test name
Test status
Simulation time 3628797000 ps
CPU time 156.94 seconds
Started Jun 05 06:05:11 PM PDT 24
Finished Jun 05 06:07:49 PM PDT 24
Peak memory 293072 kb
Host smart-a76c6051-e98e-4fce-bda7-f05d30198f46
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748473154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flas
h_ctrl_intr_rd.748473154
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.4277784627
Short name T698
Test name
Test status
Simulation time 12590797400 ps
CPU time 262.12 seconds
Started Jun 05 06:05:07 PM PDT 24
Finished Jun 05 06:09:30 PM PDT 24
Peak memory 290516 kb
Host smart-177cbb7a-54d7-4624-ae4c-b7d13848cf63
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277784627 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.4277784627
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.1494410435
Short name T1036
Test name
Test status
Simulation time 57249700 ps
CPU time 109.54 seconds
Started Jun 05 06:05:10 PM PDT 24
Finished Jun 05 06:07:00 PM PDT 24
Peak memory 263956 kb
Host smart-00445d23-80fb-4868-a188-889cf7fcf5bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494410435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.1494410435
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.1215227403
Short name T620
Test name
Test status
Simulation time 111035000 ps
CPU time 30.78 seconds
Started Jun 05 06:05:08 PM PDT 24
Finished Jun 05 06:05:40 PM PDT 24
Peak memory 274148 kb
Host smart-2f3571ef-ab4b-4c31-a462-5e60efb8b0e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215227403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.1215227403
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.2428480024
Short name T1081
Test name
Test status
Simulation time 76368200 ps
CPU time 123.84 seconds
Started Jun 05 06:05:09 PM PDT 24
Finished Jun 05 06:07:14 PM PDT 24
Peak memory 275596 kb
Host smart-afd636f2-a929-4cab-b22e-c78244d76c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428480024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.2428480024
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.2900449648
Short name T958
Test name
Test status
Simulation time 53555000 ps
CPU time 13.28 seconds
Started Jun 05 06:01:38 PM PDT 24
Finished Jun 05 06:01:52 PM PDT 24
Peak memory 257908 kb
Host smart-bd70c9e1-74d1-48ee-bc2b-348d57134ddd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900449648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.2
900449648
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.3428594506
Short name T352
Test name
Test status
Simulation time 32547400 ps
CPU time 13.78 seconds
Started Jun 05 06:01:38 PM PDT 24
Finished Jun 05 06:01:52 PM PDT 24
Peak memory 264844 kb
Host smart-da25decf-2290-4a61-a9e7-567db227283b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428594506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.3428594506
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.919187850
Short name T729
Test name
Test status
Simulation time 13328500 ps
CPU time 15.44 seconds
Started Jun 05 06:01:34 PM PDT 24
Finished Jun 05 06:01:50 PM PDT 24
Peak memory 274996 kb
Host smart-273537f3-e1cc-4962-8183-e3d86fdabd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919187850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.919187850
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.1828542016
Short name T913
Test name
Test status
Simulation time 157304700 ps
CPU time 103.98 seconds
Started Jun 05 06:01:39 PM PDT 24
Finished Jun 05 06:03:23 PM PDT 24
Peak memory 272180 kb
Host smart-7345d758-ee9c-4a5f-9b0a-70ca84a437ae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828542016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.1828542016
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.2664373812
Short name T836
Test name
Test status
Simulation time 15968800 ps
CPU time 20.36 seconds
Started Jun 05 06:01:39 PM PDT 24
Finished Jun 05 06:02:00 PM PDT 24
Peak memory 273196 kb
Host smart-583a7f30-0452-4a73-a7ff-64f3bfc0f6e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664373812 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.2664373812
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.3525736198
Short name T798
Test name
Test status
Simulation time 6379812800 ps
CPU time 389.18 seconds
Started Jun 05 06:01:32 PM PDT 24
Finished Jun 05 06:08:01 PM PDT 24
Peak memory 262752 kb
Host smart-8457e8b4-e69f-45a4-806e-db2a27304b77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525736198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.3525736198
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.933480364
Short name T673
Test name
Test status
Simulation time 15308752300 ps
CPU time 2316.89 seconds
Started Jun 05 06:01:34 PM PDT 24
Finished Jun 05 06:40:11 PM PDT 24
Peak memory 264476 kb
Host smart-a55052f8-db36-4a6a-9ad8-c3ba9cd3ea59
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933480364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erro
r_mp.933480364
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.2796938274
Short name T599
Test name
Test status
Simulation time 4413249400 ps
CPU time 2473.39 seconds
Started Jun 05 06:01:29 PM PDT 24
Finished Jun 05 06:42:44 PM PDT 24
Peak memory 263868 kb
Host smart-f1546bf6-2215-47ea-bf28-e65737611eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796938274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.2796938274
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.3721430285
Short name T1054
Test name
Test status
Simulation time 1168317900 ps
CPU time 712.2 seconds
Started Jun 05 06:01:31 PM PDT 24
Finished Jun 05 06:13:24 PM PDT 24
Peak memory 263440 kb
Host smart-512cb1ea-d124-4c17-800b-55ea9cf25dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721430285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.3721430285
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.1134717483
Short name T59
Test name
Test status
Simulation time 2435376200 ps
CPU time 32.3 seconds
Started Jun 05 06:01:32 PM PDT 24
Finished Jun 05 06:02:05 PM PDT 24
Peak memory 264880 kb
Host smart-e6b11041-1c3b-4223-b242-d243bb1f6e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134717483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.1134717483
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.410296108
Short name T328
Test name
Test status
Simulation time 394156200 ps
CPU time 40.18 seconds
Started Jun 05 06:01:43 PM PDT 24
Finished Jun 05 06:02:24 PM PDT 24
Peak memory 261776 kb
Host smart-be13af5f-a070-46ba-8e6e-fae6225e077c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410296108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_fs_sup.410296108
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.3642462083
Short name T888
Test name
Test status
Simulation time 1143949265300 ps
CPU time 3401.79 seconds
Started Jun 05 06:01:32 PM PDT 24
Finished Jun 05 06:58:15 PM PDT 24
Peak memory 264988 kb
Host smart-432c6893-6303-4ae5-bdd7-394470331598
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642462083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.3642462083
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1725561268
Short name T171
Test name
Test status
Simulation time 10038887500 ps
CPU time 53.13 seconds
Started Jun 05 06:01:37 PM PDT 24
Finished Jun 05 06:02:30 PM PDT 24
Peak memory 281216 kb
Host smart-ceb73803-e791-4c6e-8a32-9f4c2dfe8cf0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725561268 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1725561268
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.1113114150
Short name T982
Test name
Test status
Simulation time 44443800 ps
CPU time 13.38 seconds
Started Jun 05 06:01:44 PM PDT 24
Finished Jun 05 06:01:58 PM PDT 24
Peak memory 265052 kb
Host smart-4be2223b-d14c-4422-86c0-e63dea7ca6c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113114150 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.1113114150
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.780734368
Short name T441
Test name
Test status
Simulation time 8718014100 ps
CPU time 138.97 seconds
Started Jun 05 06:01:34 PM PDT 24
Finished Jun 05 06:03:54 PM PDT 24
Peak memory 262476 kb
Host smart-06724790-420a-46eb-9822-25a0b5f5d0b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780734368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw
_sec_otp.780734368
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.3400092170
Short name T246
Test name
Test status
Simulation time 3730573900 ps
CPU time 651.42 seconds
Started Jun 05 06:01:38 PM PDT 24
Finished Jun 05 06:12:30 PM PDT 24
Peak memory 330780 kb
Host smart-0077056f-bc49-4650-b86c-bfc4658217c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400092170 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.3400092170
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.2173100564
Short name T560
Test name
Test status
Simulation time 5109331900 ps
CPU time 244.31 seconds
Started Jun 05 06:01:48 PM PDT 24
Finished Jun 05 06:05:53 PM PDT 24
Peak memory 289392 kb
Host smart-6b9b3e1d-19eb-4dfe-9afb-54a373cb0b77
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173100564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.2173100564
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.852552077
Short name T125
Test name
Test status
Simulation time 12920142100 ps
CPU time 260.28 seconds
Started Jun 05 06:01:36 PM PDT 24
Finished Jun 05 06:05:56 PM PDT 24
Peak memory 290960 kb
Host smart-be43b15e-8052-43ee-a412-6d632aa11b07
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852552077 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.852552077
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.632125555
Short name T921
Test name
Test status
Simulation time 4207043100 ps
CPU time 73.57 seconds
Started Jun 05 06:01:36 PM PDT 24
Finished Jun 05 06:02:50 PM PDT 24
Peak memory 259212 kb
Host smart-3d482bb5-ece8-480f-a78c-45db22aba477
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632125555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_intr_wr.632125555
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3082497214
Short name T658
Test name
Test status
Simulation time 211478113400 ps
CPU time 291.47 seconds
Started Jun 05 06:01:41 PM PDT 24
Finished Jun 05 06:06:33 PM PDT 24
Peak memory 260016 kb
Host smart-5d7d7c94-60e3-4eb7-8200-4cab7f6193fa
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308
2497214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3082497214
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.2315541750
Short name T413
Test name
Test status
Simulation time 1704303000 ps
CPU time 62.3 seconds
Started Jun 05 06:01:31 PM PDT 24
Finished Jun 05 06:02:33 PM PDT 24
Peak memory 260452 kb
Host smart-b1e63d9c-10ff-4297-b2dd-72a66fcab036
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315541750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.2315541750
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.2218499855
Short name T955
Test name
Test status
Simulation time 49267800 ps
CPU time 13.78 seconds
Started Jun 05 06:01:36 PM PDT 24
Finished Jun 05 06:01:50 PM PDT 24
Peak memory 260164 kb
Host smart-66d2b4fb-63d5-46cb-ac43-928b4d31e92e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218499855 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.2218499855
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.329742209
Short name T123
Test name
Test status
Simulation time 1650629100 ps
CPU time 70.05 seconds
Started Jun 05 06:01:30 PM PDT 24
Finished Jun 05 06:02:41 PM PDT 24
Peak memory 259672 kb
Host smart-43eabd7f-f4bb-41ce-ab2a-ae1429d82f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329742209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.329742209
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.4214566497
Short name T839
Test name
Test status
Simulation time 42480700 ps
CPU time 129.1 seconds
Started Jun 05 06:01:37 PM PDT 24
Finished Jun 05 06:03:46 PM PDT 24
Peak memory 259932 kb
Host smart-70f94107-70a5-4ea2-b4a2-ec381a4b1290
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214566497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.4214566497
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.4211132421
Short name T43
Test name
Test status
Simulation time 2668894900 ps
CPU time 203.4 seconds
Started Jun 05 06:01:42 PM PDT 24
Finished Jun 05 06:05:06 PM PDT 24
Peak memory 281480 kb
Host smart-1c8112a0-adba-4b2e-a611-3190dc59dd6c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211132421 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.4211132421
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.2702550143
Short name T222
Test name
Test status
Simulation time 387451100 ps
CPU time 15.88 seconds
Started Jun 05 06:01:35 PM PDT 24
Finished Jun 05 06:01:51 PM PDT 24
Peak memory 264684 kb
Host smart-0d7daabe-7307-4059-8e88-cefd1aec0b10
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2702550143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.2702550143
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.3804034539
Short name T201
Test name
Test status
Simulation time 181725900 ps
CPU time 378.99 seconds
Started Jun 05 06:01:31 PM PDT 24
Finished Jun 05 06:07:51 PM PDT 24
Peak memory 262272 kb
Host smart-b74465f5-488d-417e-a2a9-853ef9c1a935
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804034539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.3804034539
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.633008437
Short name T221
Test name
Test status
Simulation time 15256300 ps
CPU time 13.94 seconds
Started Jun 05 06:01:39 PM PDT 24
Finished Jun 05 06:01:53 PM PDT 24
Peak memory 264480 kb
Host smart-1ceeb812-1f75-401d-90aa-72cb9049919a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633008437 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.633008437
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.946784228
Short name T425
Test name
Test status
Simulation time 68469600 ps
CPU time 13.7 seconds
Started Jun 05 06:01:43 PM PDT 24
Finished Jun 05 06:01:57 PM PDT 24
Peak memory 264828 kb
Host smart-fd424c32-e01c-4e13-821b-acd66931d537
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946784228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_rese
t.946784228
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.2130222451
Short name T109
Test name
Test status
Simulation time 3673579500 ps
CPU time 1441.96 seconds
Started Jun 05 06:01:35 PM PDT 24
Finished Jun 05 06:25:38 PM PDT 24
Peak memory 285504 kb
Host smart-d7a05314-0c5c-480b-a73d-dd4d1c4e1453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130222451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.2130222451
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2203451540
Short name T227
Test name
Test status
Simulation time 5515233400 ps
CPU time 138.15 seconds
Started Jun 05 06:01:35 PM PDT 24
Finished Jun 05 06:03:54 PM PDT 24
Peak memory 264956 kb
Host smart-56b058a5-6c3b-4f93-880b-b8abce9e9618
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2203451540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2203451540
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.1089665262
Short name T244
Test name
Test status
Simulation time 365852500 ps
CPU time 35.52 seconds
Started Jun 05 06:01:36 PM PDT 24
Finished Jun 05 06:02:12 PM PDT 24
Peak memory 273108 kb
Host smart-4bbae70c-5d53-431a-8205-86ef28d535f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089665262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.1089665262
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.375928411
Short name T540
Test name
Test status
Simulation time 92848100 ps
CPU time 21.21 seconds
Started Jun 05 06:01:46 PM PDT 24
Finished Jun 05 06:02:07 PM PDT 24
Peak memory 264060 kb
Host smart-9a444d42-3d91-453a-ad88-438fc07e19bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375928411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_read_word_sweep_serr.375928411
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.1993630223
Short name T275
Test name
Test status
Simulation time 525215300 ps
CPU time 102.05 seconds
Started Jun 05 06:01:33 PM PDT 24
Finished Jun 05 06:03:16 PM PDT 24
Peak memory 289580 kb
Host smart-16e6ca1c-c009-419f-bd20-cf668c385e34
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993630223 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_ro.1993630223
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.1526658354
Short name T976
Test name
Test status
Simulation time 672717100 ps
CPU time 130.18 seconds
Started Jun 05 06:01:33 PM PDT 24
Finished Jun 05 06:03:43 PM PDT 24
Peak memory 289640 kb
Host smart-0c2503b1-e2f2-4e79-adda-107c36298918
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526658354 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.1526658354
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.3291597271
Short name T945
Test name
Test status
Simulation time 42077826300 ps
CPU time 604.61 seconds
Started Jun 05 06:01:29 PM PDT 24
Finished Jun 05 06:11:34 PM PDT 24
Peak memory 309176 kb
Host smart-19672d4b-ff79-47d1-a313-521e89aa3fa3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291597271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_rw.3291597271
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.2981465853
Short name T973
Test name
Test status
Simulation time 45451200 ps
CPU time 31.82 seconds
Started Jun 05 06:01:43 PM PDT 24
Finished Jun 05 06:02:15 PM PDT 24
Peak memory 275164 kb
Host smart-c4512120-6c47-4d70-b2ab-9807c339fed7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981465853 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.2981465853
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.2131459119
Short name T270
Test name
Test status
Simulation time 34405956400 ps
CPU time 730.11 seconds
Started Jun 05 06:01:30 PM PDT 24
Finished Jun 05 06:13:40 PM PDT 24
Peak memory 311512 kb
Host smart-d89b54fc-cab2-4c63-9850-cdf3a0380b1a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131459119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_s
err.2131459119
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.3530652343
Short name T15
Test name
Test status
Simulation time 7268413400 ps
CPU time 4749.2 seconds
Started Jun 05 06:01:37 PM PDT 24
Finished Jun 05 07:20:47 PM PDT 24
Peak memory 284484 kb
Host smart-03521727-d4b0-4ff4-a707-9ef95a8049f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530652343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3530652343
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.666926779
Short name T542
Test name
Test status
Simulation time 512610700 ps
CPU time 57.82 seconds
Started Jun 05 06:01:35 PM PDT 24
Finished Jun 05 06:02:33 PM PDT 24
Peak memory 262396 kb
Host smart-423910a2-1bb9-457b-9ca2-01c464ca85b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666926779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.666926779
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.714728756
Short name T448
Test name
Test status
Simulation time 1673817400 ps
CPU time 52.76 seconds
Started Jun 05 06:01:36 PM PDT 24
Finished Jun 05 06:02:29 PM PDT 24
Peak memory 264900 kb
Host smart-e466437f-4629-4a58-a9ad-1bd1962064bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714728756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_serr_address.714728756
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.1237546317
Short name T915
Test name
Test status
Simulation time 759349100 ps
CPU time 70.6 seconds
Started Jun 05 06:01:32 PM PDT 24
Finished Jun 05 06:02:43 PM PDT 24
Peak memory 273168 kb
Host smart-efb3b1b0-82f8-4132-b17b-3d33d6e4b7dd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237546317 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_serr_counter.1237546317
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.835628366
Short name T628
Test name
Test status
Simulation time 24473800 ps
CPU time 75.83 seconds
Started Jun 05 06:01:31 PM PDT 24
Finished Jun 05 06:02:47 PM PDT 24
Peak memory 274732 kb
Host smart-c4b8000e-e1bd-44d0-8ca2-50b68af8e180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835628366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.835628366
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.1454425467
Short name T49
Test name
Test status
Simulation time 16094300 ps
CPU time 26.31 seconds
Started Jun 05 06:01:30 PM PDT 24
Finished Jun 05 06:01:56 PM PDT 24
Peak memory 258916 kb
Host smart-803e1e82-c0ae-4a45-b949-ea813b3940b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454425467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.1454425467
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.1039154252
Short name T226
Test name
Test status
Simulation time 3138608200 ps
CPU time 512.27 seconds
Started Jun 05 06:01:36 PM PDT 24
Finished Jun 05 06:10:09 PM PDT 24
Peak memory 289576 kb
Host smart-d4cd1f1c-6cd3-4915-b26a-ad12586dc60c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039154252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.1039154252
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.1560281175
Short name T195
Test name
Test status
Simulation time 54348800 ps
CPU time 26.24 seconds
Started Jun 05 06:01:34 PM PDT 24
Finished Jun 05 06:02:01 PM PDT 24
Peak memory 261240 kb
Host smart-5a2cea1d-16e2-49b7-9a8d-9c61aba0e3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560281175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.1560281175
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.1525121743
Short name T511
Test name
Test status
Simulation time 7817839600 ps
CPU time 159.64 seconds
Started Jun 05 06:01:35 PM PDT 24
Finished Jun 05 06:04:15 PM PDT 24
Peak memory 264816 kb
Host smart-2a776b12-2ab3-496d-b381-a60e2d505672
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525121743 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_wo.1525121743
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.25225044
Short name T1042
Test name
Test status
Simulation time 227447500 ps
CPU time 13.82 seconds
Started Jun 05 06:05:10 PM PDT 24
Finished Jun 05 06:05:25 PM PDT 24
Peak memory 264832 kb
Host smart-bf792d4e-93ce-4ebd-a294-b668b5aeea07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25225044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.25225044
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.2882969769
Short name T847
Test name
Test status
Simulation time 77556600 ps
CPU time 15.67 seconds
Started Jun 05 06:05:08 PM PDT 24
Finished Jun 05 06:05:25 PM PDT 24
Peak memory 275464 kb
Host smart-5e48e05f-6c89-4238-95fc-c7a8ce304d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882969769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.2882969769
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.3263571772
Short name T358
Test name
Test status
Simulation time 17650400 ps
CPU time 22 seconds
Started Jun 05 06:05:08 PM PDT 24
Finished Jun 05 06:05:31 PM PDT 24
Peak memory 273180 kb
Host smart-a4c1ecae-b601-4b51-8c2b-8e2b6875539f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263571772 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.3263571772
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.829232912
Short name T166
Test name
Test status
Simulation time 34130620900 ps
CPU time 132.69 seconds
Started Jun 05 06:05:07 PM PDT 24
Finished Jun 05 06:07:20 PM PDT 24
Peak memory 262452 kb
Host smart-b9615a28-1d0f-41c5-b505-065b0ea85687
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829232912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_h
w_sec_otp.829232912
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.1248831745
Short name T1012
Test name
Test status
Simulation time 70989700 ps
CPU time 133.12 seconds
Started Jun 05 06:05:10 PM PDT 24
Finished Jun 05 06:07:23 PM PDT 24
Peak memory 259936 kb
Host smart-1477d100-852f-4bfd-a3ad-fcd29e353f41
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248831745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.1248831745
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.1538527525
Short name T1023
Test name
Test status
Simulation time 1616186500 ps
CPU time 59.46 seconds
Started Jun 05 06:05:12 PM PDT 24
Finished Jun 05 06:06:12 PM PDT 24
Peak memory 262176 kb
Host smart-8ba8ffac-a606-4a20-ae93-b488411af4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538527525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.1538527525
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.355931267
Short name T964
Test name
Test status
Simulation time 21436400 ps
CPU time 122.58 seconds
Started Jun 05 06:05:11 PM PDT 24
Finished Jun 05 06:07:14 PM PDT 24
Peak memory 276492 kb
Host smart-45a707ca-4bc9-4df8-9810-3920b9a53ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355931267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.355931267
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.3756088045
Short name T886
Test name
Test status
Simulation time 48418600 ps
CPU time 13.73 seconds
Started Jun 05 06:05:10 PM PDT 24
Finished Jun 05 06:05:24 PM PDT 24
Peak memory 264820 kb
Host smart-3e53f205-7e38-4a03-be12-798dfaf6d834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756088045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
3756088045
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.445276691
Short name T1078
Test name
Test status
Simulation time 24210100 ps
CPU time 15.53 seconds
Started Jun 05 06:05:08 PM PDT 24
Finished Jun 05 06:05:25 PM PDT 24
Peak memory 275552 kb
Host smart-5d823d5a-9cc0-48ac-9f8f-9c83fceee352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445276691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.445276691
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.993203319
Short name T369
Test name
Test status
Simulation time 12790900 ps
CPU time 21.69 seconds
Started Jun 05 06:05:09 PM PDT 24
Finished Jun 05 06:05:31 PM PDT 24
Peak memory 273096 kb
Host smart-36bcbc8d-3b25-4c82-a677-360b510f2394
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993203319 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.993203319
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.1454650038
Short name T827
Test name
Test status
Simulation time 11114716500 ps
CPU time 131.83 seconds
Started Jun 05 06:05:07 PM PDT 24
Finished Jun 05 06:07:20 PM PDT 24
Peak memory 262448 kb
Host smart-e78f8972-fa8e-4186-8ea8-b506d674d19a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454650038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.1454650038
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.3599557123
Short name T715
Test name
Test status
Simulation time 75488600 ps
CPU time 133.83 seconds
Started Jun 05 06:05:08 PM PDT 24
Finished Jun 05 06:07:23 PM PDT 24
Peak memory 264396 kb
Host smart-fd0e4aaf-43b1-4f62-b3e7-76520e95a710
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599557123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.3599557123
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.3227005671
Short name T763
Test name
Test status
Simulation time 527058200 ps
CPU time 63.9 seconds
Started Jun 05 06:05:10 PM PDT 24
Finished Jun 05 06:06:14 PM PDT 24
Peak memory 262808 kb
Host smart-72c913f5-4d6b-4bc8-8710-f8e47d681b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227005671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.3227005671
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.1049990761
Short name T712
Test name
Test status
Simulation time 211060300 ps
CPU time 101.68 seconds
Started Jun 05 06:05:12 PM PDT 24
Finished Jun 05 06:06:54 PM PDT 24
Peak memory 276152 kb
Host smart-a6e0bc0d-349d-442a-b747-0d39be8d92e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049990761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.1049990761
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.2190779334
Short name T1033
Test name
Test status
Simulation time 332694600 ps
CPU time 14.09 seconds
Started Jun 05 06:05:17 PM PDT 24
Finished Jun 05 06:05:32 PM PDT 24
Peak memory 264796 kb
Host smart-9e72cd84-2194-41f2-bfd7-a223e3f33496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190779334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
2190779334
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.1528024155
Short name T666
Test name
Test status
Simulation time 22862200 ps
CPU time 16.13 seconds
Started Jun 05 06:05:16 PM PDT 24
Finished Jun 05 06:05:32 PM PDT 24
Peak memory 275920 kb
Host smart-6c7af34c-a515-497a-a6ea-0d2d9facec29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528024155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.1528024155
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.1280007468
Short name T97
Test name
Test status
Simulation time 25121200 ps
CPU time 21.81 seconds
Started Jun 05 06:05:16 PM PDT 24
Finished Jun 05 06:05:38 PM PDT 24
Peak memory 273156 kb
Host smart-70537c8b-a935-44fb-80ef-cec27dba877b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280007468 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.1280007468
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.1788801931
Short name T989
Test name
Test status
Simulation time 1868215400 ps
CPU time 47.9 seconds
Started Jun 05 06:05:18 PM PDT 24
Finished Jun 05 06:06:07 PM PDT 24
Peak memory 261748 kb
Host smart-1d5fec85-cce4-471b-9e69-b84442e5467d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788801931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.1788801931
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.2025226623
Short name T558
Test name
Test status
Simulation time 39889400 ps
CPU time 112.63 seconds
Started Jun 05 06:05:16 PM PDT 24
Finished Jun 05 06:07:09 PM PDT 24
Peak memory 260916 kb
Host smart-7ce63a65-7b9e-4c04-a4c0-0edc5cdde788
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025226623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.2025226623
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.496405330
Short name T366
Test name
Test status
Simulation time 1545097400 ps
CPU time 55.97 seconds
Started Jun 05 06:05:19 PM PDT 24
Finished Jun 05 06:06:15 PM PDT 24
Peak memory 263888 kb
Host smart-5c05efa7-c6bf-4b0f-b576-c933f190ac7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496405330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.496405330
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.1805042381
Short name T771
Test name
Test status
Simulation time 58567600 ps
CPU time 147.33 seconds
Started Jun 05 06:05:16 PM PDT 24
Finished Jun 05 06:07:44 PM PDT 24
Peak memory 276144 kb
Host smart-ca9436e7-852a-44e7-a61d-b7c1ceb0a503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805042381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.1805042381
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.2025545747
Short name T1095
Test name
Test status
Simulation time 133949600 ps
CPU time 13.81 seconds
Started Jun 05 06:05:15 PM PDT 24
Finished Jun 05 06:05:30 PM PDT 24
Peak memory 264856 kb
Host smart-81d6daae-cd4e-40b8-a761-ea7f445ad0a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025545747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
2025545747
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.2578557163
Short name T1061
Test name
Test status
Simulation time 28231800 ps
CPU time 13.54 seconds
Started Jun 05 06:05:17 PM PDT 24
Finished Jun 05 06:05:31 PM PDT 24
Peak memory 275788 kb
Host smart-1483bd61-d0f2-4ce3-9e37-7342a8967597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578557163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.2578557163
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.4139610400
Short name T464
Test name
Test status
Simulation time 34860700 ps
CPU time 22.25 seconds
Started Jun 05 06:05:15 PM PDT 24
Finished Jun 05 06:05:38 PM PDT 24
Peak memory 264908 kb
Host smart-e3acbe02-a954-451e-b451-245f52b40368
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139610400 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.4139610400
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.4186379505
Short name T680
Test name
Test status
Simulation time 733659000 ps
CPU time 34.61 seconds
Started Jun 05 06:05:15 PM PDT 24
Finished Jun 05 06:05:50 PM PDT 24
Peak memory 262380 kb
Host smart-9082409f-130c-4a6d-bd28-0bbd43496b77
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186379505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.4186379505
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.18511048
Short name T81
Test name
Test status
Simulation time 39695800 ps
CPU time 130.43 seconds
Started Jun 05 06:05:19 PM PDT 24
Finished Jun 05 06:07:29 PM PDT 24
Peak memory 259568 kb
Host smart-25b57dc1-9209-4623-b043-6af00ca63412
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18511048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_otp
_reset.18511048
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.3243408280
Short name T1001
Test name
Test status
Simulation time 1842249700 ps
CPU time 65.61 seconds
Started Jun 05 06:05:15 PM PDT 24
Finished Jun 05 06:06:21 PM PDT 24
Peak memory 262712 kb
Host smart-3f9c3a18-3c9b-4b15-bdfb-c87d98528cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243408280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.3243408280
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.594020913
Short name T793
Test name
Test status
Simulation time 21288900 ps
CPU time 74.27 seconds
Started Jun 05 06:05:14 PM PDT 24
Finished Jun 05 06:06:29 PM PDT 24
Peak memory 275916 kb
Host smart-8cafce5f-6f23-4b4c-8b09-ad0313c940fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594020913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.594020913
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.4286833853
Short name T754
Test name
Test status
Simulation time 44473900 ps
CPU time 13.89 seconds
Started Jun 05 06:05:16 PM PDT 24
Finished Jun 05 06:05:30 PM PDT 24
Peak memory 264852 kb
Host smart-3dd807c5-2740-4f46-a8a4-27687dd02a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286833853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
4286833853
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.4028629422
Short name T917
Test name
Test status
Simulation time 46394800 ps
CPU time 15.8 seconds
Started Jun 05 06:05:15 PM PDT 24
Finished Jun 05 06:05:32 PM PDT 24
Peak memory 275488 kb
Host smart-935e1fdc-ff85-4c79-a705-aeae670c5f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028629422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.4028629422
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.3805977532
Short name T1097
Test name
Test status
Simulation time 16087500 ps
CPU time 22.04 seconds
Started Jun 05 06:05:15 PM PDT 24
Finished Jun 05 06:05:38 PM PDT 24
Peak memory 264848 kb
Host smart-dc540d3a-4f80-4f96-963c-5a417c4fc48b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805977532 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.3805977532
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.2398598033
Short name T607
Test name
Test status
Simulation time 2894987400 ps
CPU time 54.58 seconds
Started Jun 05 06:05:17 PM PDT 24
Finished Jun 05 06:06:12 PM PDT 24
Peak memory 259952 kb
Host smart-8f3e60d2-738b-4ca2-a6f6-63386e42cb01
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398598033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.2398598033
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.3667221385
Short name T152
Test name
Test status
Simulation time 64380100 ps
CPU time 132.46 seconds
Started Jun 05 06:05:17 PM PDT 24
Finished Jun 05 06:07:30 PM PDT 24
Peak memory 259840 kb
Host smart-9b7267c6-52bd-4dca-a264-07cc8165ce37
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667221385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.3667221385
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.2272889765
Short name T876
Test name
Test status
Simulation time 1502466000 ps
CPU time 64.36 seconds
Started Jun 05 06:05:19 PM PDT 24
Finished Jun 05 06:06:24 PM PDT 24
Peak memory 264308 kb
Host smart-0127bac6-363e-40d9-be0b-f634697da47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272889765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.2272889765
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.762078593
Short name T880
Test name
Test status
Simulation time 22024800 ps
CPU time 146.33 seconds
Started Jun 05 06:05:16 PM PDT 24
Finished Jun 05 06:07:42 PM PDT 24
Peak memory 277076 kb
Host smart-137e4953-2698-4b8a-9df3-104412f93156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762078593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.762078593
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.391331537
Short name T460
Test name
Test status
Simulation time 73082600 ps
CPU time 14 seconds
Started Jun 05 06:05:24 PM PDT 24
Finished Jun 05 06:05:38 PM PDT 24
Peak memory 257892 kb
Host smart-146979ad-a0d8-4511-a4b4-380354fba6f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391331537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.391331537
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.2245815533
Short name T1006
Test name
Test status
Simulation time 50733000 ps
CPU time 15.37 seconds
Started Jun 05 06:05:24 PM PDT 24
Finished Jun 05 06:05:40 PM PDT 24
Peak memory 275556 kb
Host smart-3c92dbbc-1dbf-4357-846b-c6fa893b59c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245815533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2245815533
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.794050431
Short name T803
Test name
Test status
Simulation time 10462500 ps
CPU time 21.68 seconds
Started Jun 05 06:05:24 PM PDT 24
Finished Jun 05 06:05:46 PM PDT 24
Peak memory 279996 kb
Host smart-26e26b0d-de62-4139-9545-758c8d852688
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794050431 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.794050431
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.2705380207
Short name T513
Test name
Test status
Simulation time 2749629600 ps
CPU time 33.93 seconds
Started Jun 05 06:05:15 PM PDT 24
Finished Jun 05 06:05:49 PM PDT 24
Peak memory 262388 kb
Host smart-1011a5a1-b4af-465a-b8fa-efc36a3bccb6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705380207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.2705380207
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.1720962644
Short name T77
Test name
Test status
Simulation time 154949500 ps
CPU time 110.68 seconds
Started Jun 05 06:05:25 PM PDT 24
Finished Jun 05 06:07:16 PM PDT 24
Peak memory 259692 kb
Host smart-46bffb2c-0c37-4aec-85f6-5958aed19025
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720962644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.1720962644
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.2710440453
Short name T395
Test name
Test status
Simulation time 66223300 ps
CPU time 143.16 seconds
Started Jun 05 06:05:15 PM PDT 24
Finished Jun 05 06:07:38 PM PDT 24
Peak memory 275984 kb
Host smart-70ea252a-46fa-4e44-967b-97e56bafc6fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710440453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.2710440453
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.2010033784
Short name T419
Test name
Test status
Simulation time 49441700 ps
CPU time 14.04 seconds
Started Jun 05 06:05:31 PM PDT 24
Finished Jun 05 06:05:46 PM PDT 24
Peak memory 264812 kb
Host smart-e2b577f5-827b-493a-ac1e-138ec870a34d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010033784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
2010033784
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.2809169328
Short name T878
Test name
Test status
Simulation time 73359000 ps
CPU time 16.27 seconds
Started Jun 05 06:05:25 PM PDT 24
Finished Jun 05 06:05:41 PM PDT 24
Peak memory 275584 kb
Host smart-a527ffe5-b2cd-43a9-90f0-433327b4a74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809169328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.2809169328
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.4149359134
Short name T88
Test name
Test status
Simulation time 16249600 ps
CPU time 21.61 seconds
Started Jun 05 06:05:31 PM PDT 24
Finished Jun 05 06:05:54 PM PDT 24
Peak memory 273192 kb
Host smart-1965059d-519e-48ac-8205-05414d3f021f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149359134 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.4149359134
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.1033146538
Short name T592
Test name
Test status
Simulation time 9311055200 ps
CPU time 131.73 seconds
Started Jun 05 06:05:24 PM PDT 24
Finished Jun 05 06:07:37 PM PDT 24
Peak memory 262372 kb
Host smart-63f3f898-0297-462e-8a7d-a90f01f09385
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033146538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.1033146538
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.430176585
Short name T368
Test name
Test status
Simulation time 43185800 ps
CPU time 110.58 seconds
Started Jun 05 06:05:24 PM PDT 24
Finished Jun 05 06:07:15 PM PDT 24
Peak memory 259820 kb
Host smart-801b0006-e0c2-4658-b214-4d70efb470e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430176585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_ot
p_reset.430176585
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.3036778224
Short name T589
Test name
Test status
Simulation time 2075972200 ps
CPU time 63.14 seconds
Started Jun 05 06:05:22 PM PDT 24
Finished Jun 05 06:06:25 PM PDT 24
Peak memory 262772 kb
Host smart-a05c12fe-769c-44e3-9579-f8b6508fef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036778224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.3036778224
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.3648034457
Short name T241
Test name
Test status
Simulation time 264918900 ps
CPU time 122.32 seconds
Started Jun 05 06:05:23 PM PDT 24
Finished Jun 05 06:07:26 PM PDT 24
Peak memory 277828 kb
Host smart-e926bb4f-5ab5-46c8-8d09-b6c9a9077476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648034457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3648034457
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.3397930759
Short name T675
Test name
Test status
Simulation time 33452400 ps
CPU time 13.87 seconds
Started Jun 05 06:05:32 PM PDT 24
Finished Jun 05 06:05:46 PM PDT 24
Peak memory 264816 kb
Host smart-b88d58b0-5fcd-43df-9154-f05a47f1b7f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397930759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
3397930759
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.48607495
Short name T661
Test name
Test status
Simulation time 27639200 ps
CPU time 15.55 seconds
Started Jun 05 06:05:40 PM PDT 24
Finished Jun 05 06:05:56 PM PDT 24
Peak memory 275844 kb
Host smart-f85ece2f-9562-44c2-96b1-ff6180a6410a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48607495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.48607495
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.367589804
Short name T686
Test name
Test status
Simulation time 11106400 ps
CPU time 22.49 seconds
Started Jun 05 06:05:21 PM PDT 24
Finished Jun 05 06:05:44 PM PDT 24
Peak memory 273244 kb
Host smart-e90615ef-4346-45e2-9c7f-fb6e43fcbc7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367589804 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.367589804
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.28259000
Short name T1009
Test name
Test status
Simulation time 1406210400 ps
CPU time 61.98 seconds
Started Jun 05 06:05:23 PM PDT 24
Finished Jun 05 06:06:25 PM PDT 24
Peak memory 262292 kb
Host smart-992af083-3bba-488c-a201-73340174acea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28259000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_hw
_sec_otp.28259000
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.627495249
Short name T679
Test name
Test status
Simulation time 138924500 ps
CPU time 129.56 seconds
Started Jun 05 06:05:31 PM PDT 24
Finished Jun 05 06:07:41 PM PDT 24
Peak memory 259784 kb
Host smart-e2edc3ad-b2b7-44da-85af-d762a18f5e73
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627495249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ot
p_reset.627495249
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.251396664
Short name T746
Test name
Test status
Simulation time 1449234000 ps
CPU time 63.29 seconds
Started Jun 05 06:05:39 PM PDT 24
Finished Jun 05 06:06:43 PM PDT 24
Peak memory 263012 kb
Host smart-cc184988-9f6d-4ebf-8750-c1eb59465b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251396664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.251396664
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.2753065656
Short name T442
Test name
Test status
Simulation time 74092100 ps
CPU time 75.69 seconds
Started Jun 05 06:05:23 PM PDT 24
Finished Jun 05 06:06:39 PM PDT 24
Peak memory 274828 kb
Host smart-896a1d56-9f96-47a2-9c79-a8cfb42d50c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753065656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.2753065656
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.1373880463
Short name T1025
Test name
Test status
Simulation time 156745200 ps
CPU time 13.88 seconds
Started Jun 05 06:05:30 PM PDT 24
Finished Jun 05 06:05:45 PM PDT 24
Peak memory 264824 kb
Host smart-d4a9f565-96ff-493c-a131-26c2120f85e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373880463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
1373880463
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.100249917
Short name T191
Test name
Test status
Simulation time 16032800 ps
CPU time 15.58 seconds
Started Jun 05 06:05:40 PM PDT 24
Finished Jun 05 06:05:56 PM PDT 24
Peak memory 275528 kb
Host smart-23222eee-c7f0-4589-9bf1-14de55b12093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100249917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.100249917
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.4227864677
Short name T995
Test name
Test status
Simulation time 11932700 ps
CPU time 22.4 seconds
Started Jun 05 06:05:30 PM PDT 24
Finished Jun 05 06:05:52 PM PDT 24
Peak memory 264980 kb
Host smart-8a41052f-8037-486a-99cc-42de0bd79c2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227864677 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.4227864677
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.2465779099
Short name T525
Test name
Test status
Simulation time 3212305000 ps
CPU time 86.18 seconds
Started Jun 05 06:05:31 PM PDT 24
Finished Jun 05 06:06:58 PM PDT 24
Peak memory 262372 kb
Host smart-fce11c9a-07a4-40fe-af29-387d90d06163
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465779099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.2465779099
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.678384172
Short name T79
Test name
Test status
Simulation time 74196200 ps
CPU time 130.79 seconds
Started Jun 05 06:05:31 PM PDT 24
Finished Jun 05 06:07:42 PM PDT 24
Peak memory 260760 kb
Host smart-d27cadd6-840c-42b3-bb01-0975cfdae2e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678384172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_ot
p_reset.678384172
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.677074536
Short name T487
Test name
Test status
Simulation time 2595910500 ps
CPU time 58.7 seconds
Started Jun 05 06:05:31 PM PDT 24
Finished Jun 05 06:06:30 PM PDT 24
Peak memory 261288 kb
Host smart-3f8aa7b8-9faf-452f-b820-74b92dc5a16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677074536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.677074536
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.3554309814
Short name T1028
Test name
Test status
Simulation time 29120600 ps
CPU time 124.36 seconds
Started Jun 05 06:05:31 PM PDT 24
Finished Jun 05 06:07:36 PM PDT 24
Peak memory 275692 kb
Host smart-f888fcad-fc93-4d6e-bde4-b36bda1336e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554309814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.3554309814
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.3617205977
Short name T399
Test name
Test status
Simulation time 30957400 ps
CPU time 13.64 seconds
Started Jun 05 06:05:31 PM PDT 24
Finished Jun 05 06:05:45 PM PDT 24
Peak memory 264192 kb
Host smart-5297394d-ca34-40c8-bdf3-fe12470500b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617205977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
3617205977
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.883888267
Short name T193
Test name
Test status
Simulation time 52279700 ps
CPU time 13.16 seconds
Started Jun 05 06:05:31 PM PDT 24
Finished Jun 05 06:05:45 PM PDT 24
Peak memory 275560 kb
Host smart-658ba06a-0564-4540-a0c8-3fa2d4236f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883888267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.883888267
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.882843865
Short name T160
Test name
Test status
Simulation time 111507300 ps
CPU time 20.74 seconds
Started Jun 05 06:05:39 PM PDT 24
Finished Jun 05 06:06:01 PM PDT 24
Peak memory 273180 kb
Host smart-b9d1e8e2-6896-4382-83b3-53895ec918c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882843865 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.882843865
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.2956738536
Short name T306
Test name
Test status
Simulation time 6073426400 ps
CPU time 140.03 seconds
Started Jun 05 06:05:30 PM PDT 24
Finished Jun 05 06:07:51 PM PDT 24
Peak memory 262448 kb
Host smart-c201e4fb-b8d9-4054-903c-e5307a52eaea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956738536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.2956738536
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.2922646315
Short name T76
Test name
Test status
Simulation time 44405900 ps
CPU time 114.11 seconds
Started Jun 05 06:05:28 PM PDT 24
Finished Jun 05 06:07:23 PM PDT 24
Peak memory 259624 kb
Host smart-547b92d5-4310-43ac-bb53-1b7a6d6affc7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922646315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.2922646315
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.3384054481
Short name T363
Test name
Test status
Simulation time 2292071300 ps
CPU time 77.11 seconds
Started Jun 05 06:05:30 PM PDT 24
Finished Jun 05 06:06:48 PM PDT 24
Peak memory 263004 kb
Host smart-8059808e-5db6-4e8e-abc5-506ec5a2d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384054481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.3384054481
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.2885835346
Short name T502
Test name
Test status
Simulation time 65038400 ps
CPU time 146.65 seconds
Started Jun 05 06:05:39 PM PDT 24
Finished Jun 05 06:08:07 PM PDT 24
Peak memory 277428 kb
Host smart-56e52d38-068c-48ba-ba8b-bc10da6c1887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885835346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.2885835346
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.3028189855
Short name T597
Test name
Test status
Simulation time 16163700 ps
CPU time 15.64 seconds
Started Jun 05 06:01:52 PM PDT 24
Finished Jun 05 06:02:08 PM PDT 24
Peak memory 275488 kb
Host smart-130874aa-a630-4291-9757-c88914fca803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028189855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.3028189855
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.3219949439
Short name T161
Test name
Test status
Simulation time 17869300 ps
CPU time 22.56 seconds
Started Jun 05 06:01:47 PM PDT 24
Finished Jun 05 06:02:10 PM PDT 24
Peak memory 264856 kb
Host smart-7b761fcc-4305-4ba2-938b-31445b64af68
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219949439 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.3219949439
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.2561684746
Short name T75
Test name
Test status
Simulation time 6200359600 ps
CPU time 2404.83 seconds
Started Jun 05 06:01:48 PM PDT 24
Finished Jun 05 06:41:54 PM PDT 24
Peak memory 264524 kb
Host smart-9d8496a5-1703-40e0-973e-76e883400d15
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561684746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.2561684746
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.885754214
Short name T288
Test name
Test status
Simulation time 311027900 ps
CPU time 782.31 seconds
Started Jun 05 06:01:37 PM PDT 24
Finished Jun 05 06:14:40 PM PDT 24
Peak memory 273044 kb
Host smart-39c106b1-a3f7-46b9-94f9-2f4d89f0613a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885754214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.885754214
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.2061626714
Short name T53
Test name
Test status
Simulation time 395332100 ps
CPU time 25.93 seconds
Started Jun 05 06:01:39 PM PDT 24
Finished Jun 05 06:02:05 PM PDT 24
Peak memory 262332 kb
Host smart-c5c463c3-4a2f-484a-8367-f532e0e640f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061626714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.2061626714
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.4188698153
Short name T147
Test name
Test status
Simulation time 10015448600 ps
CPU time 210.42 seconds
Started Jun 05 06:01:48 PM PDT 24
Finished Jun 05 06:05:19 PM PDT 24
Peak memory 290768 kb
Host smart-7a5d90ed-4d26-408b-a44d-28d51d1b956c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188698153 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.4188698153
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.3692009686
Short name T890
Test name
Test status
Simulation time 51459500 ps
CPU time 13.23 seconds
Started Jun 05 06:01:46 PM PDT 24
Finished Jun 05 06:01:59 PM PDT 24
Peak memory 264800 kb
Host smart-e62b68ed-7e5f-4f76-a319-ed3c72be2b75
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692009686 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.3692009686
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.714193584
Short name T811
Test name
Test status
Simulation time 50127973200 ps
CPU time 912.83 seconds
Started Jun 05 06:01:37 PM PDT 24
Finished Jun 05 06:16:50 PM PDT 24
Peak memory 263188 kb
Host smart-b558a294-968f-403e-a394-01f4d367ab32
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714193584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.flash_ctrl_hw_rma_reset.714193584
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.2978586066
Short name T786
Test name
Test status
Simulation time 4309028900 ps
CPU time 82.07 seconds
Started Jun 05 06:01:43 PM PDT 24
Finished Jun 05 06:03:06 PM PDT 24
Peak memory 262280 kb
Host smart-f6688e1d-2220-4c6d-bb56-40a89acd3097
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978586066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.2978586066
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.3466791881
Short name T804
Test name
Test status
Simulation time 2267611800 ps
CPU time 126.22 seconds
Started Jun 05 06:01:50 PM PDT 24
Finished Jun 05 06:03:56 PM PDT 24
Peak memory 292804 kb
Host smart-d9ceafde-0344-45f1-863c-35643afd0100
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466791881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.3466791881
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.238175633
Short name T580
Test name
Test status
Simulation time 12118064900 ps
CPU time 281.23 seconds
Started Jun 05 06:01:49 PM PDT 24
Finished Jun 05 06:06:30 PM PDT 24
Peak memory 284036 kb
Host smart-b86bdbcd-b469-4a13-aa8e-64aeb469a788
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238175633 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.238175633
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.1305833133
Short name T1086
Test name
Test status
Simulation time 2131596100 ps
CPU time 65.48 seconds
Started Jun 05 06:01:56 PM PDT 24
Finished Jun 05 06:03:02 PM PDT 24
Peak memory 259896 kb
Host smart-e0d1d74c-f3ce-4aa7-89fb-ca0adeb07045
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305833133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.1305833133
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3964343172
Short name T32
Test name
Test status
Simulation time 46038274100 ps
CPU time 245.11 seconds
Started Jun 05 06:01:46 PM PDT 24
Finished Jun 05 06:05:52 PM PDT 24
Peak memory 260068 kb
Host smart-d72e19c6-387f-4b78-ac4c-0a1cfd8026e8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396
4343172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.3964343172
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.2960374020
Short name T1032
Test name
Test status
Simulation time 3245811900 ps
CPU time 62.56 seconds
Started Jun 05 06:01:49 PM PDT 24
Finished Jun 05 06:02:52 PM PDT 24
Peak memory 262556 kb
Host smart-5dc0e292-74e8-4650-8a88-4ff934b8a925
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960374020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.2960374020
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.3223094089
Short name T1022
Test name
Test status
Simulation time 25596800 ps
CPU time 13.21 seconds
Started Jun 05 06:01:44 PM PDT 24
Finished Jun 05 06:01:58 PM PDT 24
Peak memory 260040 kb
Host smart-5beac8bf-8ac4-44e2-8bf4-5b06f2ff20a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223094089 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.3223094089
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.3703058701
Short name T102
Test name
Test status
Simulation time 176210528900 ps
CPU time 450.15 seconds
Started Jun 05 06:01:37 PM PDT 24
Finished Jun 05 06:09:08 PM PDT 24
Peak memory 274108 kb
Host smart-2a9e142e-1ff7-4cdb-a8a8-decd9cf7eb7c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703058701 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.3703058701
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.1432898634
Short name T954
Test name
Test status
Simulation time 220480700 ps
CPU time 131.51 seconds
Started Jun 05 06:01:38 PM PDT 24
Finished Jun 05 06:03:50 PM PDT 24
Peak memory 264460 kb
Host smart-edc5a788-e2b0-4db5-9780-48244d4aa9c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432898634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.1432898634
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.2434886393
Short name T476
Test name
Test status
Simulation time 76923200 ps
CPU time 157.9 seconds
Started Jun 05 06:01:47 PM PDT 24
Finished Jun 05 06:04:26 PM PDT 24
Peak memory 261432 kb
Host smart-48640d6e-cd0b-4bc2-be29-f6d6da1127e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2434886393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.2434886393
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.2024849134
Short name T999
Test name
Test status
Simulation time 16080105700 ps
CPU time 196.59 seconds
Started Jun 05 06:01:52 PM PDT 24
Finished Jun 05 06:05:10 PM PDT 24
Peak memory 264824 kb
Host smart-7d052aee-ed46-443e-92b7-61d824259984
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024849134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.2024849134
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.4020964122
Short name T871
Test name
Test status
Simulation time 110991400 ps
CPU time 1136.08 seconds
Started Jun 05 06:01:43 PM PDT 24
Finished Jun 05 06:20:40 PM PDT 24
Peak memory 285256 kb
Host smart-26666817-dca4-4ba2-b8db-27770055166c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020964122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.4020964122
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.2797420349
Short name T840
Test name
Test status
Simulation time 568612700 ps
CPU time 37.38 seconds
Started Jun 05 06:01:48 PM PDT 24
Finished Jun 05 06:02:26 PM PDT 24
Peak memory 274188 kb
Host smart-c094c83a-2135-46e8-8e0f-cfa216b91b8a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797420349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.2797420349
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.25150476
Short name T215
Test name
Test status
Simulation time 3423501700 ps
CPU time 109.08 seconds
Started Jun 05 06:01:50 PM PDT 24
Finished Jun 05 06:03:39 PM PDT 24
Peak memory 288868 kb
Host smart-ace38c1c-8e87-4fe4-a780-9fc7591ba3a5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25150476 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.flash_ctrl_ro.25150476
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.2949286682
Short name T208
Test name
Test status
Simulation time 5780531700 ps
CPU time 141.5 seconds
Started Jun 05 06:01:44 PM PDT 24
Finished Jun 05 06:04:06 PM PDT 24
Peak memory 281748 kb
Host smart-9cf2aa7a-aea3-43d7-a824-2c458264fd3b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2949286682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.2949286682
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.3410135182
Short name T1035
Test name
Test status
Simulation time 1482549000 ps
CPU time 108.44 seconds
Started Jun 05 06:01:45 PM PDT 24
Finished Jun 05 06:03:34 PM PDT 24
Peak memory 291704 kb
Host smart-20174b96-2761-42d8-83c2-262be48e9a75
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410135182 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.3410135182
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.3674220285
Short name T670
Test name
Test status
Simulation time 17085082200 ps
CPU time 588.57 seconds
Started Jun 05 06:01:46 PM PDT 24
Finished Jun 05 06:11:35 PM PDT 24
Peak memory 331792 kb
Host smart-18d2eec0-5bf2-4f36-a78f-dd2fb92ff1f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674220285 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_rw_derr.3674220285
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.3969665505
Short name T545
Test name
Test status
Simulation time 113763200 ps
CPU time 28.91 seconds
Started Jun 05 06:01:44 PM PDT 24
Finished Jun 05 06:02:14 PM PDT 24
Peak memory 275124 kb
Host smart-0f0adac3-9c94-4582-a3b6-e8de84f53e05
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969665505 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.3969665505
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.2772410174
Short name T728
Test name
Test status
Simulation time 4090379400 ps
CPU time 659.83 seconds
Started Jun 05 06:01:48 PM PDT 24
Finished Jun 05 06:12:48 PM PDT 24
Peak memory 319864 kb
Host smart-81d7cee5-94b4-45c9-9894-b048328d7260
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772410174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.2772410174
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.371142046
Short name T818
Test name
Test status
Simulation time 1036398100 ps
CPU time 66.52 seconds
Started Jun 05 06:01:49 PM PDT 24
Finished Jun 05 06:02:56 PM PDT 24
Peak memory 263640 kb
Host smart-a9611589-b7c1-467a-a3cb-09e1fdd46a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371142046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.371142046
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.3181804859
Short name T575
Test name
Test status
Simulation time 43677700 ps
CPU time 145.78 seconds
Started Jun 05 06:01:47 PM PDT 24
Finished Jun 05 06:04:13 PM PDT 24
Peak memory 279584 kb
Host smart-c72d1bdf-be8e-447d-b4a4-d498494a0a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181804859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.3181804859
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.1868171349
Short name T571
Test name
Test status
Simulation time 2492467200 ps
CPU time 206.77 seconds
Started Jun 05 06:01:52 PM PDT 24
Finished Jun 05 06:05:20 PM PDT 24
Peak memory 258284 kb
Host smart-3194dbba-8da8-485a-bdf3-794000e16a10
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868171349 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.flash_ctrl_wo.1868171349
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.434322401
Short name T50
Test name
Test status
Simulation time 27633100 ps
CPU time 15.58 seconds
Started Jun 05 06:05:40 PM PDT 24
Finished Jun 05 06:05:56 PM PDT 24
Peak memory 275592 kb
Host smart-b85c5401-8764-460a-903d-587715bfa2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434322401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.434322401
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.3815782270
Short name T833
Test name
Test status
Simulation time 141115700 ps
CPU time 109.73 seconds
Started Jun 05 06:05:39 PM PDT 24
Finished Jun 05 06:07:29 PM PDT 24
Peak memory 259756 kb
Host smart-c75fe4d6-acc3-45a9-93e1-9287334370f9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815782270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.3815782270
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.3518462204
Short name T507
Test name
Test status
Simulation time 15477400 ps
CPU time 13.47 seconds
Started Jun 05 06:05:35 PM PDT 24
Finished Jun 05 06:05:49 PM PDT 24
Peak memory 274788 kb
Host smart-0a5d39ea-d411-42c6-a364-c9e143dfc058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518462204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.3518462204
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.13715310
Short name T757
Test name
Test status
Simulation time 69453700 ps
CPU time 132.13 seconds
Started Jun 05 06:05:36 PM PDT 24
Finished Jun 05 06:07:49 PM PDT 24
Peak memory 263992 kb
Host smart-2b4f8b2f-0f87-47a0-87a8-69bcb83f6079
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13715310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp
_reset.13715310
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.1578412469
Short name T952
Test name
Test status
Simulation time 195804800 ps
CPU time 15.98 seconds
Started Jun 05 06:05:36 PM PDT 24
Finished Jun 05 06:05:53 PM PDT 24
Peak memory 274808 kb
Host smart-2e6731b9-557d-47e0-a28e-fab048805edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578412469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1578412469
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.1008545600
Short name T634
Test name
Test status
Simulation time 38765500 ps
CPU time 130.92 seconds
Started Jun 05 06:05:36 PM PDT 24
Finished Jun 05 06:07:48 PM PDT 24
Peak memory 260784 kb
Host smart-ef8456bc-1dc5-41df-95c1-14a1b8cc24a3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008545600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.1008545600
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.491293805
Short name T961
Test name
Test status
Simulation time 32558000 ps
CPU time 15.41 seconds
Started Jun 05 06:05:39 PM PDT 24
Finished Jun 05 06:05:54 PM PDT 24
Peak memory 275800 kb
Host smart-5c226285-1218-4e02-8576-fa3a3edb4a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491293805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.491293805
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.940873831
Short name T651
Test name
Test status
Simulation time 40731600 ps
CPU time 129.82 seconds
Started Jun 05 06:05:36 PM PDT 24
Finished Jun 05 06:07:47 PM PDT 24
Peak memory 260620 kb
Host smart-56d85338-1af5-4c69-8cb4-8336c29553e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940873831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_ot
p_reset.940873831
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.55535722
Short name T930
Test name
Test status
Simulation time 15297800 ps
CPU time 15.85 seconds
Started Jun 05 06:05:36 PM PDT 24
Finished Jun 05 06:05:52 PM PDT 24
Peak memory 275776 kb
Host smart-261aff17-74fe-4264-a810-b320df726330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55535722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.55535722
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.2582645358
Short name T1062
Test name
Test status
Simulation time 159798500 ps
CPU time 131.49 seconds
Started Jun 05 06:05:38 PM PDT 24
Finished Jun 05 06:07:50 PM PDT 24
Peak memory 260956 kb
Host smart-c6562e34-404f-403f-8b0c-1c68d1593658
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582645358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.2582645358
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.485015987
Short name T903
Test name
Test status
Simulation time 14376700 ps
CPU time 15.55 seconds
Started Jun 05 06:05:38 PM PDT 24
Finished Jun 05 06:05:54 PM PDT 24
Peak memory 275584 kb
Host smart-c9ef4407-84b2-46f7-a35f-0c31d8846f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485015987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.485015987
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.1133207709
Short name T10
Test name
Test status
Simulation time 75492100 ps
CPU time 130.93 seconds
Started Jun 05 06:05:35 PM PDT 24
Finished Jun 05 06:07:46 PM PDT 24
Peak memory 261088 kb
Host smart-52b4a660-af46-43c7-b8ae-42a810728856
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133207709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.1133207709
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.2247256847
Short name T457
Test name
Test status
Simulation time 38216300 ps
CPU time 13.29 seconds
Started Jun 05 06:05:37 PM PDT 24
Finished Jun 05 06:05:51 PM PDT 24
Peak memory 275868 kb
Host smart-949b8fa3-d469-4b6d-ab4f-7bd16ce9ab50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247256847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2247256847
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.2430495686
Short name T14
Test name
Test status
Simulation time 166967700 ps
CPU time 132.53 seconds
Started Jun 05 06:05:37 PM PDT 24
Finished Jun 05 06:07:50 PM PDT 24
Peak memory 259500 kb
Host smart-4fc1a402-e38a-4032-90d9-ead5e0b37b09
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430495686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.2430495686
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.11280319
Short name T594
Test name
Test status
Simulation time 21193700 ps
CPU time 15.66 seconds
Started Jun 05 06:05:37 PM PDT 24
Finished Jun 05 06:05:53 PM PDT 24
Peak memory 275836 kb
Host smart-4ad13009-619c-4cce-9b64-05269acd7220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11280319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.11280319
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.648479446
Short name T632
Test name
Test status
Simulation time 74437900 ps
CPU time 130.35 seconds
Started Jun 05 06:05:37 PM PDT 24
Finished Jun 05 06:07:48 PM PDT 24
Peak memory 259636 kb
Host smart-902aee08-98f3-4ca9-9b32-d6b7b7ecf387
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648479446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_ot
p_reset.648479446
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.3921597716
Short name T444
Test name
Test status
Simulation time 58850800 ps
CPU time 15.29 seconds
Started Jun 05 06:05:38 PM PDT 24
Finished Jun 05 06:05:54 PM PDT 24
Peak memory 275908 kb
Host smart-31068b2d-60f7-4b3b-81e1-0bb6650652a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921597716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.3921597716
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.1541203256
Short name T753
Test name
Test status
Simulation time 38569100 ps
CPU time 137.3 seconds
Started Jun 05 06:05:37 PM PDT 24
Finished Jun 05 06:07:55 PM PDT 24
Peak memory 263968 kb
Host smart-8e146cdc-d8dd-43bc-a1a9-ab97a5d6d517
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541203256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.1541203256
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.4227112839
Short name T861
Test name
Test status
Simulation time 24028500 ps
CPU time 15.37 seconds
Started Jun 05 06:05:37 PM PDT 24
Finished Jun 05 06:05:53 PM PDT 24
Peak memory 275636 kb
Host smart-a7e330a6-eef8-4f7c-ae74-43230218ce76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227112839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.4227112839
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.2987451103
Short name T543
Test name
Test status
Simulation time 107726400 ps
CPU time 129.33 seconds
Started Jun 05 06:05:37 PM PDT 24
Finished Jun 05 06:07:47 PM PDT 24
Peak memory 260852 kb
Host smart-20bf14d3-65ae-46af-8870-eabd0cf5ed3a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987451103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.2987451103
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.3341179570
Short name T180
Test name
Test status
Simulation time 92387500 ps
CPU time 13.86 seconds
Started Jun 05 06:01:57 PM PDT 24
Finished Jun 05 06:02:12 PM PDT 24
Peak memory 257932 kb
Host smart-931305dd-dd38-46a1-9427-216f9d20ab8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341179570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3
341179570
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.559637981
Short name T405
Test name
Test status
Simulation time 20157700 ps
CPU time 15.98 seconds
Started Jun 05 06:01:58 PM PDT 24
Finished Jun 05 06:02:15 PM PDT 24
Peak memory 274820 kb
Host smart-362f74f1-b52d-469f-921d-5a491a1a8210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559637981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.559637981
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.3145433023
Short name T953
Test name
Test status
Simulation time 17821400 ps
CPU time 21.78 seconds
Started Jun 05 06:02:00 PM PDT 24
Finished Jun 05 06:02:22 PM PDT 24
Peak memory 273164 kb
Host smart-c1b8d180-c597-469d-b1e5-f09ab48d3866
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145433023 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.3145433023
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.3370364438
Short name T1007
Test name
Test status
Simulation time 4072285200 ps
CPU time 2254.66 seconds
Started Jun 05 06:01:45 PM PDT 24
Finished Jun 05 06:39:20 PM PDT 24
Peak memory 264864 kb
Host smart-db36f293-6a44-45d2-8512-eee31b4f08e2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370364438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.3370364438
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.315024230
Short name T174
Test name
Test status
Simulation time 2581779600 ps
CPU time 820.13 seconds
Started Jun 05 06:01:44 PM PDT 24
Finished Jun 05 06:15:25 PM PDT 24
Peak memory 273036 kb
Host smart-47780fd8-8d94-4cb9-8583-9a1ff6d543af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315024230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.315024230
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.4005217372
Short name T851
Test name
Test status
Simulation time 429383800 ps
CPU time 18.99 seconds
Started Jun 05 06:01:49 PM PDT 24
Finished Jun 05 06:02:08 PM PDT 24
Peak memory 264900 kb
Host smart-26911e2d-1cbd-44c1-a2ab-b8a2e9379cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005217372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.4005217372
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3098425354
Short name T929
Test name
Test status
Simulation time 10015646900 ps
CPU time 96.11 seconds
Started Jun 05 06:01:58 PM PDT 24
Finished Jun 05 06:03:35 PM PDT 24
Peak memory 312672 kb
Host smart-acea822f-523d-4c15-b1a6-4ede24433a71
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098425354 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.3098425354
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.2442432159
Short name T736
Test name
Test status
Simulation time 35627100 ps
CPU time 13.57 seconds
Started Jun 05 06:01:56 PM PDT 24
Finished Jun 05 06:02:11 PM PDT 24
Peak memory 258088 kb
Host smart-28c8c3d8-3a01-4f9d-85f4-0793df0f2f85
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442432159 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.2442432159
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.97206835
Short name T146
Test name
Test status
Simulation time 140168540300 ps
CPU time 788.27 seconds
Started Jun 05 06:01:55 PM PDT 24
Finished Jun 05 06:15:04 PM PDT 24
Peak memory 263492 kb
Host smart-8bb943f4-8469-4aff-b936-70e442600e46
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97206835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 6.flash_ctrl_hw_rma_reset.97206835
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.2250832602
Short name T438
Test name
Test status
Simulation time 1551524800 ps
CPU time 74.21 seconds
Started Jun 05 06:01:54 PM PDT 24
Finished Jun 05 06:03:08 PM PDT 24
Peak memory 262384 kb
Host smart-9323d094-6d37-4b55-8988-6ade51b9e6d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250832602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.2250832602
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3712792925
Short name T544
Test name
Test status
Simulation time 169743577900 ps
CPU time 417.93 seconds
Started Jun 05 06:01:57 PM PDT 24
Finished Jun 05 06:08:56 PM PDT 24
Peak memory 291760 kb
Host smart-2e1b7a7c-b3b5-43a5-8da2-4a0ad0e2b03d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712792925 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.3712792925
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.3367562578
Short name T767
Test name
Test status
Simulation time 2231981600 ps
CPU time 67.16 seconds
Started Jun 05 06:01:58 PM PDT 24
Finished Jun 05 06:03:06 PM PDT 24
Peak memory 264780 kb
Host smart-53b7e276-d542-49a4-a592-358684e0f1fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367562578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.3367562578
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2532954895
Short name T684
Test name
Test status
Simulation time 67626031600 ps
CPU time 158.3 seconds
Started Jun 05 06:01:58 PM PDT 24
Finished Jun 05 06:04:37 PM PDT 24
Peak memory 259984 kb
Host smart-a5f3f9d5-5733-418b-970a-006453dfab61
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253
2954895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.2532954895
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.14651064
Short name T755
Test name
Test status
Simulation time 972253400 ps
CPU time 90.14 seconds
Started Jun 05 06:01:43 PM PDT 24
Finished Jun 05 06:03:14 PM PDT 24
Peak memory 260416 kb
Host smart-8cbc0d25-29c2-4921-99b8-c614feb5ad95
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14651064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.14651064
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.3340025412
Short name T810
Test name
Test status
Simulation time 54994900 ps
CPU time 13.24 seconds
Started Jun 05 06:01:59 PM PDT 24
Finished Jun 05 06:02:13 PM PDT 24
Peak memory 259320 kb
Host smart-456350f6-c234-4278-861f-d6190a25ef98
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340025412 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.3340025412
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.2938983085
Short name T635
Test name
Test status
Simulation time 68398700 ps
CPU time 130.76 seconds
Started Jun 05 06:01:48 PM PDT 24
Finished Jun 05 06:03:59 PM PDT 24
Peak memory 259616 kb
Host smart-1177c8ac-3cc6-455b-8ad3-14bbc3729fee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938983085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.2938983085
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.3008794725
Short name T1073
Test name
Test status
Simulation time 3893433000 ps
CPU time 504.97 seconds
Started Jun 05 06:01:53 PM PDT 24
Finished Jun 05 06:10:18 PM PDT 24
Peak memory 264876 kb
Host smart-750143bb-8bc0-49cb-ab45-132c5dd92639
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3008794725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.3008794725
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.2890831809
Short name T132
Test name
Test status
Simulation time 24480700 ps
CPU time 13.68 seconds
Started Jun 05 06:01:58 PM PDT 24
Finished Jun 05 06:02:12 PM PDT 24
Peak memory 258392 kb
Host smart-c0b0e643-1356-48d5-b4e5-8e06fc5b8650
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890831809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.2890831809
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.489868413
Short name T73
Test name
Test status
Simulation time 3584138400 ps
CPU time 1266.07 seconds
Started Jun 05 06:01:54 PM PDT 24
Finished Jun 05 06:23:01 PM PDT 24
Peak memory 285508 kb
Host smart-8776ad3d-697d-49be-a0ae-72b854444de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489868413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.489868413
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.3574655772
Short name T432
Test name
Test status
Simulation time 137815900 ps
CPU time 35.65 seconds
Started Jun 05 06:01:59 PM PDT 24
Finished Jun 05 06:02:36 PM PDT 24
Peak memory 273120 kb
Host smart-0d77a9bb-bd1b-445e-b975-142a2cf5c40c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574655772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.3574655772
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.1682685774
Short name T707
Test name
Test status
Simulation time 4882423300 ps
CPU time 134.46 seconds
Started Jun 05 06:01:58 PM PDT 24
Finished Jun 05 06:04:14 PM PDT 24
Peak memory 296696 kb
Host smart-ab48eeca-2091-4e02-a588-5b34c0d07b68
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682685774 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_ro.1682685774
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.78715124
Short name T1039
Test name
Test status
Simulation time 750690800 ps
CPU time 133.51 seconds
Started Jun 05 06:01:59 PM PDT 24
Finished Jun 05 06:04:13 PM PDT 24
Peak memory 281264 kb
Host smart-f6ca443d-18a1-415a-9fd3-8b4489aed6f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
78715124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.78715124
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.1849059301
Short name T1008
Test name
Test status
Simulation time 1330124400 ps
CPU time 123.96 seconds
Started Jun 05 06:02:03 PM PDT 24
Finished Jun 05 06:04:07 PM PDT 24
Peak memory 281264 kb
Host smart-4f65b3e9-f3f8-480c-a796-ee7f45fdd87b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849059301 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.1849059301
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.380947958
Short name T68
Test name
Test status
Simulation time 7897245400 ps
CPU time 554.7 seconds
Started Jun 05 06:01:59 PM PDT 24
Finished Jun 05 06:11:15 PM PDT 24
Peak memory 313356 kb
Host smart-96d87e1c-81b6-42be-9e3c-a83e273e2fc7
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380947958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.flash_ctrl_rw.380947958
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.2767023531
Short name T454
Test name
Test status
Simulation time 110108200 ps
CPU time 31.18 seconds
Started Jun 05 06:01:59 PM PDT 24
Finished Jun 05 06:02:31 PM PDT 24
Peak memory 275104 kb
Host smart-d90e4e1d-acf0-4cdd-8ad9-f667b1e090ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767023531 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.2767023531
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.4003975804
Short name T659
Test name
Test status
Simulation time 4741949800 ps
CPU time 646.97 seconds
Started Jun 05 06:01:52 PM PDT 24
Finished Jun 05 06:12:39 PM PDT 24
Peak memory 311620 kb
Host smart-5514ad1a-9fca-48aa-8c87-ba3dc6501930
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003975804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.4003975804
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.390163409
Short name T671
Test name
Test status
Simulation time 1416577600 ps
CPU time 50.37 seconds
Started Jun 05 06:01:54 PM PDT 24
Finished Jun 05 06:02:45 PM PDT 24
Peak memory 262952 kb
Host smart-7172c7bd-04c7-45b9-b418-8891376b3e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390163409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.390163409
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.359785203
Short name T626
Test name
Test status
Simulation time 27410400 ps
CPU time 75.37 seconds
Started Jun 05 06:01:55 PM PDT 24
Finished Jun 05 06:03:11 PM PDT 24
Peak memory 274748 kb
Host smart-92017e9a-56d1-46ca-83bf-58b164032d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359785203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.359785203
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.75644980
Short name T557
Test name
Test status
Simulation time 1966119000 ps
CPU time 163.54 seconds
Started Jun 05 06:01:54 PM PDT 24
Finished Jun 05 06:04:38 PM PDT 24
Peak memory 259924 kb
Host smart-419261e8-5c2c-435a-a4a3-b7bd684785e7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75644980 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_wo.75644980
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.445950427
Short name T445
Test name
Test status
Simulation time 69339300 ps
CPU time 13.37 seconds
Started Jun 05 06:05:36 PM PDT 24
Finished Jun 05 06:05:50 PM PDT 24
Peak memory 275556 kb
Host smart-62c1c630-4763-4ef1-b1f6-a171eb8b325d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445950427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.445950427
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.2248706229
Short name T517
Test name
Test status
Simulation time 427459100 ps
CPU time 110.64 seconds
Started Jun 05 06:05:36 PM PDT 24
Finished Jun 05 06:07:27 PM PDT 24
Peak memory 260780 kb
Host smart-a7abe281-8b13-4d06-a5bf-5d8475662281
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248706229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.2248706229
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.2849663129
Short name T656
Test name
Test status
Simulation time 55459500 ps
CPU time 13.54 seconds
Started Jun 05 06:05:38 PM PDT 24
Finished Jun 05 06:05:52 PM PDT 24
Peak memory 275876 kb
Host smart-309f656a-1d3d-4576-b884-6c50c4b454fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849663129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.2849663129
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.2442147083
Short name T1071
Test name
Test status
Simulation time 23057900 ps
CPU time 15.6 seconds
Started Jun 05 06:05:46 PM PDT 24
Finished Jun 05 06:06:02 PM PDT 24
Peak memory 275472 kb
Host smart-53a351f1-cb1d-4166-b7b3-7931874603a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442147083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.2442147083
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.3725451197
Short name T565
Test name
Test status
Simulation time 42968000 ps
CPU time 130.1 seconds
Started Jun 05 06:05:39 PM PDT 24
Finished Jun 05 06:07:49 PM PDT 24
Peak memory 259948 kb
Host smart-806656aa-ce62-4f34-8710-194fd53ff686
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725451197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.3725451197
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.3812948620
Short name T458
Test name
Test status
Simulation time 21816100 ps
CPU time 15.5 seconds
Started Jun 05 06:05:45 PM PDT 24
Finished Jun 05 06:06:01 PM PDT 24
Peak memory 275424 kb
Host smart-dcd30db9-f7e9-481b-9d2a-6dcf552e57eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812948620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.3812948620
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.3705915969
Short name T1050
Test name
Test status
Simulation time 40850800 ps
CPU time 132.35 seconds
Started Jun 05 06:05:45 PM PDT 24
Finished Jun 05 06:07:58 PM PDT 24
Peak memory 264480 kb
Host smart-bba5a7f6-e6cf-469e-8961-a59a095b4de8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705915969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.3705915969
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.521055087
Short name T553
Test name
Test status
Simulation time 14981600 ps
CPU time 13.62 seconds
Started Jun 05 06:05:47 PM PDT 24
Finished Jun 05 06:06:01 PM PDT 24
Peak memory 275904 kb
Host smart-dcaf9f0d-667f-4b56-882c-1686c4e577bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521055087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.521055087
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.2604829297
Short name T1045
Test name
Test status
Simulation time 39809400 ps
CPU time 131.66 seconds
Started Jun 05 06:05:47 PM PDT 24
Finished Jun 05 06:07:59 PM PDT 24
Peak memory 260848 kb
Host smart-8c04e97b-ce6f-4f53-89ac-f5773cb602d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604829297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.2604829297
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.3396928033
Short name T627
Test name
Test status
Simulation time 17300400 ps
CPU time 15.89 seconds
Started Jun 05 06:05:47 PM PDT 24
Finished Jun 05 06:06:03 PM PDT 24
Peak memory 275552 kb
Host smart-028bf54b-92cd-417d-998e-05840057b2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396928033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.3396928033
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.2005484822
Short name T668
Test name
Test status
Simulation time 45651800 ps
CPU time 13.28 seconds
Started Jun 05 06:05:46 PM PDT 24
Finished Jun 05 06:05:59 PM PDT 24
Peak memory 275896 kb
Host smart-84513988-263e-46b7-bae5-3ec87910d8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005484822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2005484822
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.669521288
Short name T549
Test name
Test status
Simulation time 36523900 ps
CPU time 132.29 seconds
Started Jun 05 06:05:48 PM PDT 24
Finished Jun 05 06:08:00 PM PDT 24
Peak memory 259640 kb
Host smart-09b3dfe6-0189-4c5d-8d5d-66003c234ce0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669521288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_ot
p_reset.669521288
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.1283477947
Short name T1004
Test name
Test status
Simulation time 16865400 ps
CPU time 15.39 seconds
Started Jun 05 06:05:46 PM PDT 24
Finished Jun 05 06:06:02 PM PDT 24
Peak memory 275764 kb
Host smart-6ea57f59-0150-4b8c-a9a1-2f2e88b38dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283477947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1283477947
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.3725344495
Short name T148
Test name
Test status
Simulation time 40153800 ps
CPU time 130.82 seconds
Started Jun 05 06:05:47 PM PDT 24
Finished Jun 05 06:07:58 PM PDT 24
Peak memory 259772 kb
Host smart-fb557977-71f5-453f-b008-3169d817e25d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725344495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.3725344495
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.2858477427
Short name T578
Test name
Test status
Simulation time 37632200 ps
CPU time 13.46 seconds
Started Jun 05 06:05:46 PM PDT 24
Finished Jun 05 06:06:00 PM PDT 24
Peak memory 274852 kb
Host smart-075c658d-af2f-433a-b4be-2c7552653d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858477427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.2858477427
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.896932215
Short name T309
Test name
Test status
Simulation time 43187500 ps
CPU time 111.48 seconds
Started Jun 05 06:05:46 PM PDT 24
Finished Jun 05 06:07:38 PM PDT 24
Peak memory 259948 kb
Host smart-7259aa62-ffe7-471a-93a1-ea134c1efc03
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896932215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_ot
p_reset.896932215
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.452337149
Short name T1066
Test name
Test status
Simulation time 57589600 ps
CPU time 13.33 seconds
Started Jun 05 06:05:47 PM PDT 24
Finished Jun 05 06:06:01 PM PDT 24
Peak memory 274772 kb
Host smart-d2be9f07-b363-41d5-97fd-627179f63e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452337149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.452337149
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.1359313506
Short name T370
Test name
Test status
Simulation time 38016100 ps
CPU time 109.87 seconds
Started Jun 05 06:05:47 PM PDT 24
Finished Jun 05 06:07:37 PM PDT 24
Peak memory 259932 kb
Host smart-64421e98-b243-484b-8128-eef155758379
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359313506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.1359313506
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.1582568525
Short name T169
Test name
Test status
Simulation time 106320300 ps
CPU time 13.75 seconds
Started Jun 05 06:02:05 PM PDT 24
Finished Jun 05 06:02:19 PM PDT 24
Peak memory 257808 kb
Host smart-390f7da3-44c6-445e-bd18-9bf1db7e4c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582568525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1
582568525
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.999967040
Short name T189
Test name
Test status
Simulation time 47890900 ps
CPU time 16.1 seconds
Started Jun 05 06:02:02 PM PDT 24
Finished Jun 05 06:02:19 PM PDT 24
Peak memory 275784 kb
Host smart-dfc43213-bed7-437f-aa56-b19bc642fb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999967040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.999967040
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.218567068
Short name T103
Test name
Test status
Simulation time 13975700 ps
CPU time 21.22 seconds
Started Jun 05 06:01:59 PM PDT 24
Finished Jun 05 06:02:21 PM PDT 24
Peak memory 265016 kb
Host smart-e9b10e55-2e66-456b-80b1-21d22b5fc3b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218567068 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.218567068
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.2427189387
Short name T167
Test name
Test status
Simulation time 26224310800 ps
CPU time 2215.12 seconds
Started Jun 05 06:01:55 PM PDT 24
Finished Jun 05 06:38:51 PM PDT 24
Peak memory 264240 kb
Host smart-3901ddfd-5a4a-4c45-a8b4-fd43cf1536a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427189387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.2427189387
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.2749379878
Short name T653
Test name
Test status
Simulation time 2153335700 ps
CPU time 936.17 seconds
Started Jun 05 06:01:58 PM PDT 24
Finished Jun 05 06:17:35 PM PDT 24
Peak memory 273064 kb
Host smart-637c26c2-0c7b-4b1c-90b5-27ebe585aa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749379878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.2749379878
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3923922769
Short name T20
Test name
Test status
Simulation time 10021300000 ps
CPU time 180.17 seconds
Started Jun 05 06:02:03 PM PDT 24
Finished Jun 05 06:05:04 PM PDT 24
Peak memory 290904 kb
Host smart-3505c747-847c-4062-9682-74898c22ecba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923922769 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.3923922769
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.2976639263
Short name T841
Test name
Test status
Simulation time 15315000 ps
CPU time 13.61 seconds
Started Jun 05 06:02:01 PM PDT 24
Finished Jun 05 06:02:16 PM PDT 24
Peak memory 258100 kb
Host smart-6178614d-90c7-4377-8bfd-494c07a57360
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976639263 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.2976639263
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.3419185688
Short name T1099
Test name
Test status
Simulation time 80135052400 ps
CPU time 863.13 seconds
Started Jun 05 06:02:03 PM PDT 24
Finished Jun 05 06:16:26 PM PDT 24
Peak memory 263296 kb
Host smart-3962df15-5745-4712-acbd-7a640613d646
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419185688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.3419185688
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.3060021307
Short name T1056
Test name
Test status
Simulation time 9454828500 ps
CPU time 210.52 seconds
Started Jun 05 06:01:59 PM PDT 24
Finished Jun 05 06:05:30 PM PDT 24
Peak memory 262264 kb
Host smart-00db5f3a-9119-4103-94f0-99bf3cfed25f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060021307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.3060021307
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.2793929499
Short name T758
Test name
Test status
Simulation time 705178400 ps
CPU time 129.54 seconds
Started Jun 05 06:01:56 PM PDT 24
Finished Jun 05 06:04:06 PM PDT 24
Peak memory 292056 kb
Host smart-2de55d7d-5020-4dd8-a319-fbdff30e4330
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793929499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.2793929499
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.3964777038
Short name T1019
Test name
Test status
Simulation time 2572250800 ps
CPU time 71.19 seconds
Started Jun 05 06:01:59 PM PDT 24
Finished Jun 05 06:03:11 PM PDT 24
Peak memory 259380 kb
Host smart-020ac16f-ab6c-494b-b6ac-715cd997c342
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964777038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.3964777038
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2584518585
Short name T31
Test name
Test status
Simulation time 89409271800 ps
CPU time 194.73 seconds
Started Jun 05 06:02:01 PM PDT 24
Finished Jun 05 06:05:17 PM PDT 24
Peak memory 260040 kb
Host smart-8e29d6e9-f3bf-47e0-8c20-e562baf5d846
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258
4518585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.2584518585
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.548208208
Short name T944
Test name
Test status
Simulation time 19004389200 ps
CPU time 74.7 seconds
Started Jun 05 06:01:57 PM PDT 24
Finished Jun 05 06:03:12 PM PDT 24
Peak memory 259924 kb
Host smart-5f5eaadb-fb74-48a2-80ad-a27eb640f6af
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548208208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.548208208
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.2661574104
Short name T455
Test name
Test status
Simulation time 31986500 ps
CPU time 13.5 seconds
Started Jun 05 06:02:03 PM PDT 24
Finished Jun 05 06:02:17 PM PDT 24
Peak memory 260192 kb
Host smart-c823fa9f-5794-4f48-ad09-6f72b2f6d230
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661574104 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.2661574104
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.661465418
Short name T1027
Test name
Test status
Simulation time 4166479000 ps
CPU time 149.94 seconds
Started Jun 05 06:02:00 PM PDT 24
Finished Jun 05 06:04:31 PM PDT 24
Peak memory 262460 kb
Host smart-91a674f6-544c-4a75-ab81-093a8183e85f
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661465418 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_mp_regions.661465418
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.877615134
Short name T874
Test name
Test status
Simulation time 365870300 ps
CPU time 138.73 seconds
Started Jun 05 06:01:59 PM PDT 24
Finished Jun 05 06:04:18 PM PDT 24
Peak memory 259844 kb
Host smart-be553c79-b6ca-4365-9df4-83b7af02f1ec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877615134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp
_reset.877615134
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.2188343968
Short name T696
Test name
Test status
Simulation time 123613700 ps
CPU time 273.21 seconds
Started Jun 05 06:01:54 PM PDT 24
Finished Jun 05 06:06:28 PM PDT 24
Peak memory 264900 kb
Host smart-9869b377-47bc-4346-a701-0163164d7ebe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2188343968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.2188343968
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.515611134
Short name T521
Test name
Test status
Simulation time 31573100 ps
CPU time 13.47 seconds
Started Jun 05 06:02:01 PM PDT 24
Finished Jun 05 06:02:15 PM PDT 24
Peak memory 264776 kb
Host smart-9fd9b6a4-950c-484f-b289-d609f6ffe58a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515611134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_rese
t.515611134
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.3177577003
Short name T967
Test name
Test status
Simulation time 60372600 ps
CPU time 175.96 seconds
Started Jun 05 06:01:53 PM PDT 24
Finished Jun 05 06:04:50 PM PDT 24
Peak memory 271808 kb
Host smart-851c041b-5798-4a80-8e9c-71663bb0f6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177577003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.3177577003
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.2433075670
Short name T799
Test name
Test status
Simulation time 345947500 ps
CPU time 36.05 seconds
Started Jun 05 06:01:54 PM PDT 24
Finished Jun 05 06:02:30 PM PDT 24
Peak memory 273116 kb
Host smart-43ed1663-84f0-4af8-9010-72431b3a3bcb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433075670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.2433075670
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.4268461790
Short name T971
Test name
Test status
Simulation time 5978962100 ps
CPU time 119.41 seconds
Started Jun 05 06:01:57 PM PDT 24
Finished Jun 05 06:03:57 PM PDT 24
Peak memory 289044 kb
Host smart-e855c078-e0dc-47ad-aa16-849591076a09
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268461790 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.4268461790
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.3657195399
Short name T204
Test name
Test status
Simulation time 2292799700 ps
CPU time 134.35 seconds
Started Jun 05 06:01:58 PM PDT 24
Finished Jun 05 06:04:14 PM PDT 24
Peak memory 281388 kb
Host smart-149801d6-13d6-4821-9b21-b096c7198139
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3657195399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.3657195399
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.808148738
Short name T1040
Test name
Test status
Simulation time 3189586000 ps
CPU time 142.44 seconds
Started Jun 05 06:01:54 PM PDT 24
Finished Jun 05 06:04:17 PM PDT 24
Peak memory 293656 kb
Host smart-149e8372-75c8-402b-8b7b-df8c28559c0d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808148738 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.808148738
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.1428478088
Short name T900
Test name
Test status
Simulation time 4218740300 ps
CPU time 487.45 seconds
Started Jun 05 06:01:58 PM PDT 24
Finished Jun 05 06:10:06 PM PDT 24
Peak memory 309376 kb
Host smart-c939998e-fba1-4570-b190-85f04c00e370
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428478088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.flash_ctrl_rw.1428478088
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_derr.1767677562
Short name T247
Test name
Test status
Simulation time 8468782500 ps
CPU time 639.83 seconds
Started Jun 05 06:01:56 PM PDT 24
Finished Jun 05 06:12:36 PM PDT 24
Peak memory 338040 kb
Host smart-50842dfe-6d50-4dc1-b5e9-8b34f6bea9d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767677562 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_rw_derr.1767677562
Directory /workspace/7.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.2063448866
Short name T1074
Test name
Test status
Simulation time 45057500 ps
CPU time 30.48 seconds
Started Jun 05 06:01:55 PM PDT 24
Finished Jun 05 06:02:26 PM PDT 24
Peak memory 274136 kb
Host smart-727dc788-2ed6-4e39-b794-732b6ccb1b49
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063448866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.2063448866
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.947122336
Short name T1031
Test name
Test status
Simulation time 50324900 ps
CPU time 31.3 seconds
Started Jun 05 06:02:01 PM PDT 24
Finished Jun 05 06:02:33 PM PDT 24
Peak memory 274464 kb
Host smart-f0b33f02-b068-4203-b025-3712d7dff8d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947122336 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.947122336
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.3454656515
Short name T855
Test name
Test status
Simulation time 13438540400 ps
CPU time 608 seconds
Started Jun 05 06:01:59 PM PDT 24
Finished Jun 05 06:12:08 PM PDT 24
Peak memory 311748 kb
Host smart-082e540b-8174-4670-87e1-8074e0c46af7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454656515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s
err.3454656515
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.2205856723
Short name T831
Test name
Test status
Simulation time 1989833900 ps
CPU time 73.07 seconds
Started Jun 05 06:02:02 PM PDT 24
Finished Jun 05 06:03:16 PM PDT 24
Peak memory 264188 kb
Host smart-fab0b37f-b965-44ed-9e05-470f5ed19fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205856723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.2205856723
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.326027649
Short name T987
Test name
Test status
Simulation time 61339600 ps
CPU time 51.14 seconds
Started Jun 05 06:01:51 PM PDT 24
Finished Jun 05 06:02:43 PM PDT 24
Peak memory 270492 kb
Host smart-dec16231-5817-41ac-9cba-404ffeed8465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326027649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.326027649
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.973571653
Short name T777
Test name
Test status
Simulation time 20103589100 ps
CPU time 166.75 seconds
Started Jun 05 06:01:58 PM PDT 24
Finished Jun 05 06:04:46 PM PDT 24
Peak memory 264824 kb
Host smart-4ef176f2-7d76-4d2c-9404-386a27e0c7ee
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973571653 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.flash_ctrl_wo.973571653
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.1707256531
Short name T252
Test name
Test status
Simulation time 33921100 ps
CPU time 15.67 seconds
Started Jun 05 06:05:46 PM PDT 24
Finished Jun 05 06:06:03 PM PDT 24
Peak memory 275820 kb
Host smart-1272192f-db50-48eb-9d4a-8b87b474f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707256531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.1707256531
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.306064459
Short name T552
Test name
Test status
Simulation time 429509800 ps
CPU time 110.37 seconds
Started Jun 05 06:05:50 PM PDT 24
Finished Jun 05 06:07:41 PM PDT 24
Peak memory 260680 kb
Host smart-45286b22-473e-444f-895a-8fadf8eb38bf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306064459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_ot
p_reset.306064459
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.2920566900
Short name T579
Test name
Test status
Simulation time 24821900 ps
CPU time 15.44 seconds
Started Jun 05 06:05:46 PM PDT 24
Finished Jun 05 06:06:02 PM PDT 24
Peak memory 274996 kb
Host smart-37d6d3e0-759c-4f12-92ff-04d6dae02c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920566900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.2920566900
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.1524095951
Short name T724
Test name
Test status
Simulation time 116592500 ps
CPU time 110.88 seconds
Started Jun 05 06:05:44 PM PDT 24
Finished Jun 05 06:07:36 PM PDT 24
Peak memory 260980 kb
Host smart-342b2acb-ea06-4b2b-b532-1ddc3ce31de4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524095951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.1524095951
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.3579696519
Short name T485
Test name
Test status
Simulation time 16884500 ps
CPU time 16.06 seconds
Started Jun 05 06:05:47 PM PDT 24
Finished Jun 05 06:06:04 PM PDT 24
Peak memory 275548 kb
Host smart-324b618a-2aad-4755-ab78-88a0ea3fd8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579696519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.3579696519
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.3511763155
Short name T509
Test name
Test status
Simulation time 74726800 ps
CPU time 129.03 seconds
Started Jun 05 06:05:44 PM PDT 24
Finished Jun 05 06:07:54 PM PDT 24
Peak memory 260960 kb
Host smart-fbef1651-4d36-4544-9c50-9d1d6d85b99b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511763155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.3511763155
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.1819934823
Short name T727
Test name
Test status
Simulation time 14290000 ps
CPU time 13.39 seconds
Started Jun 05 06:05:50 PM PDT 24
Finished Jun 05 06:06:04 PM PDT 24
Peak memory 275884 kb
Host smart-b1f58729-46fb-4c66-aa73-f71a1bbca340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819934823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.1819934823
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.3951141523
Short name T482
Test name
Test status
Simulation time 21087500 ps
CPU time 13.38 seconds
Started Jun 05 06:05:52 PM PDT 24
Finished Jun 05 06:06:05 PM PDT 24
Peak memory 275588 kb
Host smart-d3b67704-e628-4868-8137-4e3400cd564d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951141523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.3951141523
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.726704354
Short name T649
Test name
Test status
Simulation time 67837000 ps
CPU time 116.35 seconds
Started Jun 05 06:05:59 PM PDT 24
Finished Jun 05 06:07:56 PM PDT 24
Peak memory 259868 kb
Host smart-4fa18ee2-9d8f-4c8c-bca5-4be0f3a9e24b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726704354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_ot
p_reset.726704354
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.1001584404
Short name T965
Test name
Test status
Simulation time 51513900 ps
CPU time 15.83 seconds
Started Jun 05 06:05:52 PM PDT 24
Finished Jun 05 06:06:08 PM PDT 24
Peak memory 275020 kb
Host smart-df871db9-bb8a-4b27-b7af-f6301639ba9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001584404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.1001584404
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.3400288934
Short name T582
Test name
Test status
Simulation time 335738700 ps
CPU time 131.17 seconds
Started Jun 05 06:05:52 PM PDT 24
Finished Jun 05 06:08:04 PM PDT 24
Peak memory 259836 kb
Host smart-0488088d-6e95-4895-82d5-82dd1edd194b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400288934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.3400288934
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.3677805548
Short name T515
Test name
Test status
Simulation time 13229100 ps
CPU time 15.82 seconds
Started Jun 05 06:05:52 PM PDT 24
Finished Jun 05 06:06:09 PM PDT 24
Peak memory 275568 kb
Host smart-9cb7c6e3-0ed7-4199-bd96-d525ae4353cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677805548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.3677805548
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.368107257
Short name T652
Test name
Test status
Simulation time 36423800 ps
CPU time 130.14 seconds
Started Jun 05 06:05:51 PM PDT 24
Finished Jun 05 06:08:02 PM PDT 24
Peak memory 259840 kb
Host smart-b7eb0e2b-2bbe-4e7a-a05c-fa9f94ef3f2d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368107257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_ot
p_reset.368107257
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.481013757
Short name T19
Test name
Test status
Simulation time 15566500 ps
CPU time 16.05 seconds
Started Jun 05 06:05:51 PM PDT 24
Finished Jun 05 06:06:07 PM PDT 24
Peak memory 275916 kb
Host smart-9d85b469-0fcf-45e4-a330-db6e16a0da15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481013757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.481013757
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.1286434167
Short name T739
Test name
Test status
Simulation time 103837900 ps
CPU time 135.57 seconds
Started Jun 05 06:05:54 PM PDT 24
Finished Jun 05 06:08:10 PM PDT 24
Peak memory 259728 kb
Host smart-55f3251d-cb9d-427f-bfe8-e8162e38fbbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286434167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.1286434167
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.2604067716
Short name T359
Test name
Test status
Simulation time 48077000 ps
CPU time 13.41 seconds
Started Jun 05 06:05:53 PM PDT 24
Finished Jun 05 06:06:06 PM PDT 24
Peak memory 274720 kb
Host smart-d9a6debd-d7bc-4daa-96a9-4c90bf44e6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604067716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.2604067716
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.2626154502
Short name T692
Test name
Test status
Simulation time 142693300 ps
CPU time 133.19 seconds
Started Jun 05 06:05:54 PM PDT 24
Finished Jun 05 06:08:08 PM PDT 24
Peak memory 259776 kb
Host smart-bd1c5ee7-6b99-421f-8845-0a2ae6d2058a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626154502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.2626154502
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.3600828072
Short name T484
Test name
Test status
Simulation time 24176700 ps
CPU time 13.65 seconds
Started Jun 05 06:05:53 PM PDT 24
Finished Jun 05 06:06:07 PM PDT 24
Peak memory 274812 kb
Host smart-1c271d9a-c862-4a8c-ad4b-836e3a496fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600828072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.3600828072
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.2283030804
Short name T938
Test name
Test status
Simulation time 91424000 ps
CPU time 131.89 seconds
Started Jun 05 06:05:52 PM PDT 24
Finished Jun 05 06:08:05 PM PDT 24
Peak memory 260844 kb
Host smart-b2472a0d-e4fe-4fc9-8626-1a41ffeb8eea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283030804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o
tp_reset.2283030804
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.2655913758
Short name T734
Test name
Test status
Simulation time 72623800 ps
CPU time 13.6 seconds
Started Jun 05 06:02:08 PM PDT 24
Finished Jun 05 06:02:22 PM PDT 24
Peak memory 257852 kb
Host smart-4887bbc5-f288-4bb6-bf7b-94147d1ae51d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655913758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.2
655913758
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.3762902360
Short name T1087
Test name
Test status
Simulation time 14695500 ps
CPU time 15.52 seconds
Started Jun 05 06:02:06 PM PDT 24
Finished Jun 05 06:02:22 PM PDT 24
Peak memory 275904 kb
Host smart-dfaf493d-aff2-4490-903f-92f3fc3abd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762902360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.3762902360
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.3573446879
Short name T355
Test name
Test status
Simulation time 45799400 ps
CPU time 21.8 seconds
Started Jun 05 06:02:05 PM PDT 24
Finished Jun 05 06:02:27 PM PDT 24
Peak memory 273204 kb
Host smart-f138a011-eabe-45d5-ab55-984ddf9c3a99
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573446879 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.3573446879
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.4160270136
Short name T287
Test name
Test status
Simulation time 10392378800 ps
CPU time 2223.7 seconds
Started Jun 05 06:02:05 PM PDT 24
Finished Jun 05 06:39:09 PM PDT 24
Peak memory 264544 kb
Host smart-8af405fc-3ac9-40d1-9134-d5a6d895d5df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160270136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.4160270136
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.3993817261
Short name T573
Test name
Test status
Simulation time 714861400 ps
CPU time 992.37 seconds
Started Jun 05 06:02:06 PM PDT 24
Finished Jun 05 06:18:39 PM PDT 24
Peak memory 273064 kb
Host smart-b98f7b6b-f5aa-44fd-bf18-73ad15d19a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993817261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3993817261
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.664259115
Short name T52
Test name
Test status
Simulation time 178476800 ps
CPU time 22.09 seconds
Started Jun 05 06:02:03 PM PDT 24
Finished Jun 05 06:02:25 PM PDT 24
Peak memory 264904 kb
Host smart-72632f64-e7bc-4a98-8e36-d80ab4c6203d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664259115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.664259115
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3418684112
Short name T284
Test name
Test status
Simulation time 10032987700 ps
CPU time 53.41 seconds
Started Jun 05 06:02:08 PM PDT 24
Finished Jun 05 06:03:02 PM PDT 24
Peak memory 270156 kb
Host smart-215d284e-a86b-47eb-9b7b-c484f00ec84f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418684112 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3418684112
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.220985969
Short name T660
Test name
Test status
Simulation time 15243500 ps
CPU time 13.37 seconds
Started Jun 05 06:02:07 PM PDT 24
Finished Jun 05 06:02:21 PM PDT 24
Peak memory 258060 kb
Host smart-ba95234a-a431-4db3-bfbe-6d8c569469d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220985969 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.220985969
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.2355529086
Short name T164
Test name
Test status
Simulation time 40123808400 ps
CPU time 800.11 seconds
Started Jun 05 06:02:04 PM PDT 24
Finished Jun 05 06:15:25 PM PDT 24
Peak memory 263240 kb
Host smart-2d94fab8-4490-450c-a8fd-54bfb1e1fa89
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355529086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.2355529086
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.1669064259
Short name T983
Test name
Test status
Simulation time 427587200 ps
CPU time 40.32 seconds
Started Jun 05 06:02:00 PM PDT 24
Finished Jun 05 06:02:41 PM PDT 24
Peak memory 262504 kb
Host smart-77f85724-3375-4157-8d7c-395379f754d8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669064259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.1669064259
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.1626701077
Short name T278
Test name
Test status
Simulation time 6493329400 ps
CPU time 203.02 seconds
Started Jun 05 06:02:04 PM PDT 24
Finished Jun 05 06:05:27 PM PDT 24
Peak memory 283548 kb
Host smart-4b4d5562-c409-4392-8c5a-97577ba0441d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626701077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.1626701077
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3449486438
Short name T822
Test name
Test status
Simulation time 11588946500 ps
CPU time 131.28 seconds
Started Jun 05 06:02:04 PM PDT 24
Finished Jun 05 06:04:16 PM PDT 24
Peak memory 291416 kb
Host smart-d0a4c2f8-5720-4652-8822-c8a8c20a5af2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449486438 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.3449486438
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.541358648
Short name T1002
Test name
Test status
Simulation time 10035629600 ps
CPU time 78 seconds
Started Jun 05 06:02:06 PM PDT 24
Finished Jun 05 06:03:25 PM PDT 24
Peak memory 258916 kb
Host smart-24ec9430-efad-42b6-a427-64079a716f19
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541358648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.flash_ctrl_intr_wr.541358648
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.2247580065
Short name T30
Test name
Test status
Simulation time 453897035600 ps
CPU time 584.77 seconds
Started Jun 05 06:02:12 PM PDT 24
Finished Jun 05 06:11:57 PM PDT 24
Peak memory 260264 kb
Host smart-ded7a6f3-e893-4232-95c1-14b99f7ccffe
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224
7580065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.2247580065
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.2838731386
Short name T415
Test name
Test status
Simulation time 7464446000 ps
CPU time 83.93 seconds
Started Jun 05 06:02:04 PM PDT 24
Finished Jun 05 06:03:28 PM PDT 24
Peak memory 260420 kb
Host smart-c63f4abe-c4f1-4a6f-a6c2-3a84dedf7db5
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838731386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.2838731386
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.709783241
Short name T966
Test name
Test status
Simulation time 15852300 ps
CPU time 13.42 seconds
Started Jun 05 06:02:09 PM PDT 24
Finished Jun 05 06:02:23 PM PDT 24
Peak memory 259204 kb
Host smart-02f4ec8c-4aed-45d5-9679-7961a09df95d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709783241 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.709783241
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.3642245961
Short name T741
Test name
Test status
Simulation time 26209344400 ps
CPU time 250.86 seconds
Started Jun 05 06:02:02 PM PDT 24
Finished Jun 05 06:06:13 PM PDT 24
Peak memory 273344 kb
Host smart-cd1f5794-c5ad-450d-a647-63835f1527c1
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642245961 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.3642245961
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.1377787570
Short name T450
Test name
Test status
Simulation time 316095600 ps
CPU time 132.5 seconds
Started Jun 05 06:02:01 PM PDT 24
Finished Jun 05 06:04:14 PM PDT 24
Peak memory 259760 kb
Host smart-5c7b1922-34ee-4a36-8cc3-867f99cde1b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377787570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.1377787570
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.3562182230
Short name T61
Test name
Test status
Simulation time 2912991300 ps
CPU time 301.26 seconds
Started Jun 05 06:02:04 PM PDT 24
Finished Jun 05 06:07:06 PM PDT 24
Peak memory 262160 kb
Host smart-d7df3b8f-c3fb-4e96-991b-3ea29ac1352f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3562182230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3562182230
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.1362119746
Short name T2
Test name
Test status
Simulation time 57376300 ps
CPU time 13.4 seconds
Started Jun 05 06:02:13 PM PDT 24
Finished Jun 05 06:02:27 PM PDT 24
Peak memory 264856 kb
Host smart-bb068378-0cb6-4a02-851c-5f6fd59c8ad8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362119746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.1362119746
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.2562908400
Short name T1102
Test name
Test status
Simulation time 152743800 ps
CPU time 151.92 seconds
Started Jun 05 06:02:02 PM PDT 24
Finished Jun 05 06:04:35 PM PDT 24
Peak memory 276752 kb
Host smart-37ebfc81-63b1-4500-bcc2-f10d0f28e9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562908400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.2562908400
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.1172415581
Short name T327
Test name
Test status
Simulation time 93930400 ps
CPU time 34.78 seconds
Started Jun 05 06:02:06 PM PDT 24
Finished Jun 05 06:02:41 PM PDT 24
Peak memory 273084 kb
Host smart-700aa658-9089-497a-8bd9-a375344fde3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172415581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.1172415581
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.645189664
Short name T600
Test name
Test status
Simulation time 511533200 ps
CPU time 96.96 seconds
Started Jun 05 06:02:07 PM PDT 24
Finished Jun 05 06:03:44 PM PDT 24
Peak memory 296952 kb
Host smart-25173bba-ea23-4f79-b254-840e6d3dd2c2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645189664 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.flash_ctrl_ro.645189664
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.2200422046
Short name T182
Test name
Test status
Simulation time 3095061400 ps
CPU time 181.17 seconds
Started Jun 05 06:02:06 PM PDT 24
Finished Jun 05 06:05:08 PM PDT 24
Peak memory 283664 kb
Host smart-c43adb68-af4c-4d46-981b-b6595a842901
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2200422046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2200422046
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.1859665381
Short name T940
Test name
Test status
Simulation time 637872800 ps
CPU time 131.95 seconds
Started Jun 05 06:02:04 PM PDT 24
Finished Jun 05 06:04:16 PM PDT 24
Peak memory 293552 kb
Host smart-627fb3b2-f68c-433a-9074-0dd136e502e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859665381 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.1859665381
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.2015532154
Short name T198
Test name
Test status
Simulation time 3626503400 ps
CPU time 555.1 seconds
Started Jun 05 06:02:05 PM PDT 24
Finished Jun 05 06:11:20 PM PDT 24
Peak memory 313304 kb
Host smart-5447c27f-e1da-48d5-b61b-cfdbb25d3fb4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015532154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.flash_ctrl_rw.2015532154
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.2316256461
Short name T860
Test name
Test status
Simulation time 3701913300 ps
CPU time 603.28 seconds
Started Jun 05 06:02:02 PM PDT 24
Finished Jun 05 06:12:06 PM PDT 24
Peak memory 314716 kb
Host smart-f3642f21-646b-4a11-a227-7953de57b800
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316256461 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_rw_derr.2316256461
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.1378151139
Short name T29
Test name
Test status
Simulation time 73551900 ps
CPU time 31.02 seconds
Started Jun 05 06:02:13 PM PDT 24
Finished Jun 05 06:02:44 PM PDT 24
Peak memory 268916 kb
Host smart-a351c5e1-d86a-42d2-89cc-38258a000b75
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378151139 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.1378151139
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.1414685466
Short name T181
Test name
Test status
Simulation time 22197453100 ps
CPU time 686.22 seconds
Started Jun 05 06:02:06 PM PDT 24
Finished Jun 05 06:13:32 PM PDT 24
Peak memory 319872 kb
Host smart-d803037d-604f-46d7-b5e5-7f9c17af96b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414685466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s
err.1414685466
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.3886328662
Short name T393
Test name
Test status
Simulation time 627385000 ps
CPU time 64.07 seconds
Started Jun 05 06:02:06 PM PDT 24
Finished Jun 05 06:03:11 PM PDT 24
Peak memory 263812 kb
Host smart-8a1bded8-2443-4809-badd-d2014af7cb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886328662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.3886328662
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.3020352747
Short name T427
Test name
Test status
Simulation time 16373800 ps
CPU time 95.83 seconds
Started Jun 05 06:02:00 PM PDT 24
Finished Jun 05 06:03:36 PM PDT 24
Peak memory 276188 kb
Host smart-b2b0a258-39af-42d6-ab32-a0ce0bd39a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020352747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.3020352747
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.1159730197
Short name T664
Test name
Test status
Simulation time 6394141900 ps
CPU time 173.82 seconds
Started Jun 05 06:02:03 PM PDT 24
Finished Jun 05 06:04:57 PM PDT 24
Peak memory 259208 kb
Host smart-c92044fc-9d9e-4ed1-9d85-4d6d4668ad43
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159730197 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.flash_ctrl_wo.1159730197
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.342143794
Short name T532
Test name
Test status
Simulation time 26416700 ps
CPU time 13.57 seconds
Started Jun 05 06:02:19 PM PDT 24
Finished Jun 05 06:02:34 PM PDT 24
Peak memory 257924 kb
Host smart-fe2dda47-c0df-4045-aa5c-ef0237517772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342143794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.342143794
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.242927431
Short name T814
Test name
Test status
Simulation time 47786700 ps
CPU time 13.5 seconds
Started Jun 05 06:02:20 PM PDT 24
Finished Jun 05 06:02:34 PM PDT 24
Peak memory 275908 kb
Host smart-8df35a43-50e5-4037-9296-6635f15567d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242927431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.242927431
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.2506607666
Short name T775
Test name
Test status
Simulation time 21456900 ps
CPU time 21.77 seconds
Started Jun 05 06:02:13 PM PDT 24
Finished Jun 05 06:02:35 PM PDT 24
Peak memory 273256 kb
Host smart-01d56f59-e2c2-416b-b16c-07b982c05a9b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506607666 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.2506607666
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.1252463050
Short name T1018
Test name
Test status
Simulation time 19980824200 ps
CPU time 2542.62 seconds
Started Jun 05 06:02:05 PM PDT 24
Finished Jun 05 06:44:29 PM PDT 24
Peak memory 263636 kb
Host smart-dc82be20-e7e2-45c8-846a-da487c2ece17
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252463050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.1252463050
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.1643253959
Short name T539
Test name
Test status
Simulation time 4678825600 ps
CPU time 816.53 seconds
Started Jun 05 06:02:12 PM PDT 24
Finished Jun 05 06:15:49 PM PDT 24
Peak memory 272960 kb
Host smart-2a741913-0836-409c-bb69-41f7930836fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643253959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.1643253959
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.3509668315
Short name T859
Test name
Test status
Simulation time 105693900 ps
CPU time 19.47 seconds
Started Jun 05 06:02:07 PM PDT 24
Finished Jun 05 06:02:27 PM PDT 24
Peak memory 264872 kb
Host smart-4a4d5fed-f75e-46ba-9ab8-c95ffaeba81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509668315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.3509668315
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2448424785
Short name T1076
Test name
Test status
Simulation time 10012034400 ps
CPU time 146.06 seconds
Started Jun 05 06:02:20 PM PDT 24
Finished Jun 05 06:04:46 PM PDT 24
Peak memory 373960 kb
Host smart-6b0555e0-3150-4cd5-813f-63191da16a04
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448424785 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.2448424785
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.3448360403
Short name T783
Test name
Test status
Simulation time 33349900 ps
CPU time 13.19 seconds
Started Jun 05 06:02:21 PM PDT 24
Finished Jun 05 06:02:35 PM PDT 24
Peak memory 258024 kb
Host smart-55a13f54-6046-4ca6-a8db-176e290218ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448360403 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.3448360403
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.133685824
Short name T143
Test name
Test status
Simulation time 290233249500 ps
CPU time 996.88 seconds
Started Jun 05 06:02:06 PM PDT 24
Finished Jun 05 06:18:44 PM PDT 24
Peak memory 263124 kb
Host smart-3f099b9d-d9e9-4735-9761-467116274276
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133685824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 9.flash_ctrl_hw_rma_reset.133685824
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.4004874723
Short name T392
Test name
Test status
Simulation time 19062187700 ps
CPU time 108.5 seconds
Started Jun 05 06:02:05 PM PDT 24
Finished Jun 05 06:03:54 PM PDT 24
Peak memory 262272 kb
Host smart-b3705bad-4dbf-4e58-8033-d3e4b9e09cd5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004874723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.4004874723
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.180128625
Short name T527
Test name
Test status
Simulation time 99698906200 ps
CPU time 360.73 seconds
Started Jun 05 06:02:19 PM PDT 24
Finished Jun 05 06:08:20 PM PDT 24
Peak memory 293012 kb
Host smart-0c7e2014-733a-4df3-baf0-cbefa8f621c4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180128625 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.180128625
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.2927507374
Short name T986
Test name
Test status
Simulation time 10803071400 ps
CPU time 76.41 seconds
Started Jun 05 06:02:11 PM PDT 24
Finished Jun 05 06:03:28 PM PDT 24
Peak memory 260572 kb
Host smart-94b78f8c-7577-441d-b18a-86344d116479
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927507374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.2927507374
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.118939650
Short name T780
Test name
Test status
Simulation time 19706679100 ps
CPU time 162.36 seconds
Started Jun 05 06:02:12 PM PDT 24
Finished Jun 05 06:04:55 PM PDT 24
Peak memory 259988 kb
Host smart-0376d2b8-7a2c-4a24-895d-992144a79e6a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118
939650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.118939650
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.475182732
Short name T534
Test name
Test status
Simulation time 15460200 ps
CPU time 13.39 seconds
Started Jun 05 06:02:22 PM PDT 24
Finished Jun 05 06:02:36 PM PDT 24
Peak memory 264800 kb
Host smart-69acd933-d6da-423f-8b38-86edfd621abb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475182732 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.475182732
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.4129557077
Short name T1016
Test name
Test status
Simulation time 9831251300 ps
CPU time 134.64 seconds
Started Jun 05 06:02:09 PM PDT 24
Finished Jun 05 06:04:24 PM PDT 24
Peak memory 264900 kb
Host smart-c35f5632-dcd9-49ac-863b-31f8d2a2320d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129557077 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.4129557077
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.549298149
Short name T467
Test name
Test status
Simulation time 72869500 ps
CPU time 133.2 seconds
Started Jun 05 06:02:09 PM PDT 24
Finished Jun 05 06:04:22 PM PDT 24
Peak memory 260832 kb
Host smart-5a366c7a-582a-40a2-a822-6c14e8ed22a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549298149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp
_reset.549298149
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.1948895240
Short name T447
Test name
Test status
Simulation time 137971100 ps
CPU time 240.9 seconds
Started Jun 05 06:02:08 PM PDT 24
Finished Jun 05 06:06:09 PM PDT 24
Peak memory 262064 kb
Host smart-7c718965-52b9-4db9-b79d-d25dd0797bdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1948895240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.1948895240
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.1594319664
Short name T453
Test name
Test status
Simulation time 18001300 ps
CPU time 13.53 seconds
Started Jun 05 06:02:11 PM PDT 24
Finished Jun 05 06:02:25 PM PDT 24
Peak memory 258412 kb
Host smart-45c777d6-8c8f-4b4c-b6ea-61c64c47c46e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594319664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.1594319664
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.2549718980
Short name T638
Test name
Test status
Simulation time 64314400 ps
CPU time 340.92 seconds
Started Jun 05 06:02:10 PM PDT 24
Finished Jun 05 06:07:52 PM PDT 24
Peak memory 281132 kb
Host smart-878be708-d581-4c9f-b307-58f87fe5bf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549718980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.2549718980
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.285356304
Short name T721
Test name
Test status
Simulation time 445423500 ps
CPU time 36.44 seconds
Started Jun 05 06:02:21 PM PDT 24
Finished Jun 05 06:02:58 PM PDT 24
Peak memory 266960 kb
Host smart-529cb410-98ea-4a41-89c3-496c353f20de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285356304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_re_evict.285356304
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.3354250479
Short name T213
Test name
Test status
Simulation time 1045841000 ps
CPU time 94.5 seconds
Started Jun 05 06:02:07 PM PDT 24
Finished Jun 05 06:03:42 PM PDT 24
Peak memory 281280 kb
Host smart-6ac18da6-a514-4f36-8a07-1199e23b587e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354250479 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_ro.3354250479
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.2586858304
Short name T1072
Test name
Test status
Simulation time 2613310700 ps
CPU time 132.22 seconds
Started Jun 05 06:02:13 PM PDT 24
Finished Jun 05 06:04:26 PM PDT 24
Peak memory 281680 kb
Host smart-cfa69d65-7046-4681-addd-9e596f037910
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2586858304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.2586858304
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.1568339000
Short name T685
Test name
Test status
Simulation time 2890431600 ps
CPU time 142.78 seconds
Started Jun 05 06:02:14 PM PDT 24
Finished Jun 05 06:04:37 PM PDT 24
Peak memory 294020 kb
Host smart-ba2203ad-ce4e-4b9e-ac42-61bfdc90d259
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568339000 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.1568339000
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.4251623025
Short name T875
Test name
Test status
Simulation time 14473334100 ps
CPU time 535.99 seconds
Started Jun 05 06:02:06 PM PDT 24
Finished Jun 05 06:11:02 PM PDT 24
Peak memory 313276 kb
Host smart-b73d8b6f-5f28-4ddf-8774-7b74f76355e9
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251623025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.flash_ctrl_rw.4251623025
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.2738184038
Short name T776
Test name
Test status
Simulation time 80447100 ps
CPU time 30.66 seconds
Started Jun 05 06:02:21 PM PDT 24
Finished Jun 05 06:02:52 PM PDT 24
Peak memory 266512 kb
Host smart-1ba0da7d-4f12-4322-a85f-9b8925e7b1e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738184038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.2738184038
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.463965664
Short name T496
Test name
Test status
Simulation time 27983200 ps
CPU time 31.03 seconds
Started Jun 05 06:02:14 PM PDT 24
Finished Jun 05 06:02:46 PM PDT 24
Peak memory 275172 kb
Host smart-5bf39f25-2c85-43f6-bbf1-05639367a7ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463965664 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.463965664
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.680090358
Short name T383
Test name
Test status
Simulation time 17128398000 ps
CPU time 639.53 seconds
Started Jun 05 06:02:13 PM PDT 24
Finished Jun 05 06:12:53 PM PDT 24
Peak memory 311980 kb
Host smart-69d32f31-da2b-441c-9810-8b68f55253bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680090358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_se
rr.680090358
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.2994615424
Short name T997
Test name
Test status
Simulation time 3936520200 ps
CPU time 61.52 seconds
Started Jun 05 06:02:21 PM PDT 24
Finished Jun 05 06:03:23 PM PDT 24
Peak memory 263676 kb
Host smart-97bd208c-5ed0-43c3-9c89-c04f963d833f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994615424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.2994615424
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.2968442782
Short name T689
Test name
Test status
Simulation time 99950600 ps
CPU time 100.38 seconds
Started Jun 05 06:02:08 PM PDT 24
Finished Jun 05 06:03:49 PM PDT 24
Peak memory 278532 kb
Host smart-e2c2808f-ea6c-4948-b0cc-746390d1c99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968442782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2968442782
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.1253341289
Short name T791
Test name
Test status
Simulation time 16485964500 ps
CPU time 189.64 seconds
Started Jun 05 06:02:14 PM PDT 24
Finished Jun 05 06:05:24 PM PDT 24
Peak memory 259208 kb
Host smart-dddfd775-100d-466b-9dad-f365e1b0c78a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253341289 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.flash_ctrl_wo.1253341289
Directory /workspace/9.flash_ctrl_wo/latest
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