Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	389899	1		T1	2		T2	1		T3	1
all_values[1]	389899	1		T1	2		T2	1		T3	1
all_values[2]	389899	1		T1	2		T2	1		T3	1
all_values[3]	389899	1		T1	2		T2	1		T3	1
all_values[4]	389899	1		T1	2		T2	1		T3	1
all_values[5]	389899	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	786013	1		T1	12		T2	6		T3	6
auto[1]	1553381	1		T32	6020		T8	12504		T35	5764

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1140296	1		T1	7		T2	4		T3	4
auto[1]	1199098	1		T1	5		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	389729	1		T1	2		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	170	1		T253	7		T254	5		T326	4
all_values[1]	auto[0]	auto[1]	389739	1		T1	2		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	160	1		T253	3		T254	2		T326	4
all_values[2]	auto[0]	auto[0]	1575	1		T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	61	1		T253	2		T254	3		T326	1
all_values[2]	auto[1]	auto[0]	388205	1		T32	1505		T8	3126		T35	1441
all_values[2]	auto[1]	auto[1]	58	1		T253	1		T254	2		T326	1
all_values[3]	auto[0]	auto[0]	1580	1		T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	58	1		T254	3		T326	1		T327	2
all_values[3]	auto[1]	auto[0]	78687	1		T32	1505		T8	1563		T35	1441
all_values[3]	auto[1]	auto[1]	309574	1		T8	1563		T38	1698		T41	3508
all_values[4]	auto[0]	auto[0]	1121	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	517	1		T1	1		T4	1		T17	1
all_values[4]	auto[1]	auto[0]	279419	1		T32	1		T8	1563		T35	1
all_values[4]	auto[1]	auto[1]	108842	1		T32	1504		T8	1563		T35	1440
all_values[5]	auto[0]	auto[0]	1498	1		T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	135	1		T17	1		T42	1		T43	1
all_values[5]	auto[1]	auto[0]	388211	1		T32	1505		T8	3126		T35	1441
all_values[5]	auto[1]	auto[1]	55	1		T253	2		T254	1		T327	3