Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	250679	1		T1	1558		T4	402		T5	40
auto[FlashEraseBank]	276059	1		T1	1691		T5	16		T17	314

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	264543	1		T1	1098		T4	7		T5	26
auto[FlashOpProgram]	241817	1		T1	2151		T4	384		T17	275
auto[FlashOpErase]	16378	1		T4	11		T5	30		T19	5
auto[FlashOpInvalid]	4000	1		T81	200		T106	200		T102	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	264543	1		T1	1098		T4	7		T5	26
op[FlashOpProgram]	241817	1		T1	2151		T4	384		T17	275
op[FlashOpErase]	16378	1		T4	11		T5	30		T19	5
read_erase_read	616	1		T5	7		T19	2		T6	9
read_prog_read	784	1		T1	5		T17	3		T6	18

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	383986	1		T1	2618		T5	48		T17	558
auto[FlashPartInfo]	139122	1		T1	618		T4	402		T5	7
auto[FlashPartInfo1]	904	1		T1	3		T17	1		T6	1
auto[FlashPartInfo2]	2726	1		T1	10		T5	1		T32	2

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	192853	1		T1	721		T5	18		T17	366
auto[FlashPartData]	auto[FlashOpProgram]	183397	1		T1	1897		T17	192		T18	73
auto[FlashPartData]	auto[FlashOpErase]	3816	1		T5	30		T6	26		T49	1
auto[FlashPartData]	auto[FlashOpInvalid]	3920	1		T81	194		T106	192		T102	198
auto[FlashPartInfo]	auto[FlashOpRead]	69144	1		T1	369		T4	7		T5	7
auto[FlashPartInfo]	auto[FlashOpProgram]	57365	1		T1	249		T4	384		T17	83
auto[FlashPartInfo]	auto[FlashOpErase]	12547	1		T4	11		T19	5		T57	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	66	1		T81	6		T106	8		T410	4
auto[FlashPartInfo1]	auto[FlashOpRead]	728	1		T1	3		T17	1		T7	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T6	1		T105	32		T86	32
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T70	1		T108	1		T91	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T108	2		T91	2		T411	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1818	1		T1	5		T5	1		T7	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	889	1		T1	5		T32	2		T7	5
auto[FlashPartInfo2]	auto[FlashOpErase]	11	1		T102	1		T392	1		T115	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T102	2		T108	2		T412	2