Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	8	24	75.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	8	24	75.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31693	1		T19	4		T6	24		T31	1
auto[1]	11	1		T313	1		T314	1		T315	2
auto[2]	31	1		T33	1		T128	4		T129	8
auto[3]	77	1		T34	2		T44	1		T22	5

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7950	1		T19	1		T6	6		T31	1
evic_idx[1]	7952	1		T19	1		T6	6		T57	3
evic_idx[2]	7956	1		T19	1		T6	6		T57	2
evic_idx[3]	7954	1		T19	1		T6	6		T57	2

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30836	1		T117	252		T119	300		T81	400
evic_op[2]	349	1		T19	4		T31	1		T33	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	8	24	75.00	8

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1] - auto[2]]	--	--	8

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7701	1		T117	63		T119	75		T81	100
evic_idx[0]	evic_op[1]	auto[3]	7	1		T22	2		T274	1		T272	2
evic_idx[0]	evic_op[2]	auto[0]	71	1		T19	1		T31	1		T83	8
evic_idx[0]	evic_op[2]	auto[1]	2	1		T316	1		T317	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	2	1		T33	1		T318	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	9	1		T34	1		T217	1		T319	1
evic_idx[1]	evic_op[1]	auto[0]	7701	1		T117	63		T119	75		T81	100
evic_idx[1]	evic_op[1]	auto[3]	8	1		T22	1		T274	2		T320	2
evic_idx[1]	evic_op[2]	auto[0]	71	1		T19	1		T83	8		T207	6
evic_idx[1]	evic_op[2]	auto[1]	2	1		T315	1		T316	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	1	1		T318	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	12	1		T161	1		T217	1		T321	1
evic_idx[2]	evic_op[1]	auto[0]	7701	1		T117	63		T119	75		T81	100
evic_idx[2]	evic_op[1]	auto[3]	7	1		T274	2		T320	2		T322	1
evic_idx[2]	evic_op[2]	auto[0]	73	1		T19	1		T83	8		T207	6
evic_idx[2]	evic_op[2]	auto[1]	3	1		T315	1		T316	1		T323	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T318	1		T324	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	14	1		T44	1		T64	1		T163	1
evic_idx[3]	evic_op[1]	auto[0]	7701	1		T117	63		T119	75		T81	100
evic_idx[3]	evic_op[1]	auto[3]	10	1		T22	2		T274	2		T272	2
evic_idx[3]	evic_op[2]	auto[0]	71	1		T19	1		T83	8		T162	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T313	1		T314	1		T316	1
evic_idx[3]	evic_op[2]	auto[2]	2	1		T315	1		T318	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	10	1		T34	1		T325	1		T217	1