Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	55929	1		T269	1419		T332	2807		T333	2447
rd_lvl[2]	41609	1		T269	2058		T332	2218		T333	1352
rd_lvl[3]	10222	1		T269	715		T334	1249		T335	1036
rd_lvl[4]	52462	1		T127	5443		T269	1475		T336	5617
rd_lvl[5]	19561	1		T127	1361		T269	449		T336	1011
rd_lvl[6]	15325	1		T269	1037		T175	2616		T337	44
rd_lvl[7]	6556	1		T269	334		T336	29		T338	2
rd_lvl[8]	16345	1		T41	3078		T269	315		T336	29
rd_lvl[9]	4968	1		T41	430		T269	1224		T39	55
rd_lvl[10]	9993	1		T8	1216		T269	289		T39	19
rd_lvl[11]	5705	1		T8	347		T269	1848		T339	13
rd_lvl[12]	3733	1		T39	1		T40	152		T339	1
rd_lvl[13]	4668	1		T340	690		T40	226		T339	2
rd_lvl[14]	7636	1		T340	1000		T341	1234		T342	995
rd_lvl[15]	2869	1		T38	512		T40	230		T343	179