Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	389899	1		T1	2		T2	1		T3	1
all_pins[1]	389899	1		T1	2		T2	1		T3	1
all_pins[2]	389899	1		T1	2		T2	1		T3	1
all_pins[3]	389899	1		T1	2		T2	1		T3	1
all_pins[4]	389899	1		T1	2		T2	1		T3	1
all_pins[5]	389899	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1950096	1		T1	12		T2	6		T3	6
values[0x1]	389298	1		T32	1504		T8	3126		T35	1440
transitions[0x0=>0x1]	340745	1		T32	1504		T8	3126		T35	1440
transitions[0x1=>0x0]	340722	1		T32	1504		T8	3126		T35	1440

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	389729	1		T1	2		T2	1		T3	1
all_pins[0]	values[0x1]	170	1		T253	7		T254	5		T326	4
all_pins[0]	transitions[0x0=>0x1]	79	1		T253	5		T254	5		T327	1
all_pins[0]	transitions[0x1=>0x0]	69	1		T253	1		T254	2		T327	1
all_pins[1]	values[0x0]	389739	1		T1	2		T2	1		T3	1
all_pins[1]	values[0x1]	160	1		T253	3		T254	2		T326	4
all_pins[1]	transitions[0x0=>0x1]	130	1		T253	3		T254	1		T326	3
all_pins[1]	transitions[0x1=>0x0]	4097	1		T38	1186		T343	113		T347	1607
all_pins[2]	values[0x0]	385772	1		T1	2		T2	1		T3	1
all_pins[2]	values[0x1]	4127	1		T38	1186		T343	113		T347	1607
all_pins[2]	transitions[0x0=>0x1]	44	1		T254	1		T326	1		T328	3
all_pins[2]	transitions[0x1=>0x0]	257689	1		T8	1563		T38	512		T41	3508
all_pins[3]	values[0x0]	128127	1		T1	2		T2	1		T3	1
all_pins[3]	values[0x1]	261772	1		T8	1563		T38	1698		T41	3508
all_pins[3]	transitions[0x0=>0x1]	217472	1		T8	1563		T38	512		T41	1754
all_pins[3]	transitions[0x1=>0x0]	78714	1		T32	1504		T8	1563		T35	1440
all_pins[4]	values[0x0]	266885	1		T1	2		T2	1		T3	1
all_pins[4]	values[0x1]	123014	1		T32	1504		T8	1563		T35	1440
all_pins[4]	transitions[0x0=>0x1]	122995	1		T32	1504		T8	1563		T35	1440
all_pins[4]	transitions[0x1=>0x0]	36	1		T327	3		T328	1		T330	3
all_pins[5]	values[0x0]	389844	1		T1	2		T2	1		T3	1
all_pins[5]	values[0x1]	55	1		T253	2		T254	1		T327	3
all_pins[5]	transitions[0x0=>0x1]	25	1		T253	1		T327	1		T328	1
all_pins[5]	transitions[0x1=>0x0]	117	1		T253	5		T254	3		T326	3