Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T253	7		T254	7		T326	4
all_values[1]	275	1		T253	7		T254	7		T326	4
all_values[2]	275	1		T253	7		T254	7		T326	4
all_values[3]	275	1		T253	7		T254	7		T326	4
all_values[4]	275	1		T253	7		T254	7		T326	4
all_values[5]	275	1		T253	7		T254	7		T326	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	887	1		T253	20		T254	18		T326	10
auto[1]	763	1		T253	22		T254	24		T326	14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	533	1		T253	13		T254	10		T326	7
auto[1]	1117	1		T253	29		T254	32		T326	17

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	973	1		T253	26		T254	19		T326	15
auto[1]	677	1		T253	16		T254	23		T326	9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	97	1		T253	1		T326	1		T327	2
all_values[0]	auto[0]	auto[1]	auto[1]	82	1		T253	2		T254	3		T326	2
all_values[0]	auto[1]	auto[0]	auto[1]	52	1		T253	1		T254	2		T328	4
all_values[0]	auto[1]	auto[1]	auto[1]	44	1		T253	3		T254	2		T326	1
all_values[1]	auto[0]	auto[0]	auto[1]	86	1		T253	3		T254	4		T327	1
all_values[1]	auto[0]	auto[1]	auto[1]	74	1		T253	2		T326	3		T327	2
all_values[1]	auto[1]	auto[0]	auto[1]	65	1		T253	1		T254	1		T326	1
all_values[1]	auto[1]	auto[1]	auto[1]	50	1		T253	1		T254	2		T327	1
all_values[2]	auto[0]	auto[0]	auto[0]	82	1		T254	2		T326	1		T327	3
all_values[2]	auto[0]	auto[1]	auto[0]	74	1		T253	4		T326	1		T327	1
all_values[2]	auto[1]	auto[0]	auto[1]	68	1		T253	3		T254	2		T326	1
all_values[2]	auto[1]	auto[1]	auto[1]	51	1		T254	3		T326	1		T328	3
all_values[3]	auto[0]	auto[0]	auto[0]	91	1		T253	2		T254	1		T326	2
all_values[3]	auto[0]	auto[1]	auto[0]	70	1		T253	3		T254	1		T328	1
all_values[3]	auto[1]	auto[0]	auto[1]	62	1		T253	1		T254	2		T326	1
all_values[3]	auto[1]	auto[1]	auto[1]	52	1		T253	1		T254	3		T326	1
all_values[4]	auto[0]	auto[0]	auto[0]	55	1		T253	1		T254	1		T327	2
all_values[4]	auto[0]	auto[0]	auto[1]	27	1		T253	1		T327	1		T329	1
all_values[4]	auto[0]	auto[1]	auto[0]	48	1		T254	1		T328	1		T330	4
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T253	2		T254	1		T326	2
all_values[4]	auto[1]	auto[0]	auto[1]	61	1		T253	1		T326	2		T327	1
all_values[4]	auto[1]	auto[1]	auto[1]	54	1		T253	2		T254	4		T328	1
all_values[5]	auto[0]	auto[0]	auto[0]	57	1		T253	3		T254	2		T326	1
all_values[5]	auto[0]	auto[0]	auto[1]	20	1		T253	1		T328	2		T330	1
all_values[5]	auto[0]	auto[1]	auto[0]	56	1		T254	2		T326	2		T331	2
all_values[5]	auto[0]	auto[1]	auto[1]	24	1		T253	1		T254	1		T327	1
all_values[5]	auto[1]	auto[0]	auto[1]	64	1		T253	1		T254	1		T327	1
all_values[5]	auto[1]	auto[1]	auto[1]	54	1		T253	1		T254	1		T326	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal