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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.27 95.67 94.12 97.54 92.52 98.08 98.03 97.97


Total test records in report: 1242
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T1073 /workspace/coverage/default/12.flash_ctrl_rand_ops.361017029 Jun 06 01:33:47 PM PDT 24 Jun 06 01:41:27 PM PDT 24 393624200 ps
T1074 /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3394679860 Jun 06 01:32:30 PM PDT 24 Jun 06 01:38:58 PM PDT 24 343127382000 ps
T1075 /workspace/coverage/default/2.flash_ctrl_ro_derr.466464606 Jun 06 01:32:10 PM PDT 24 Jun 06 01:34:55 PM PDT 24 581612400 ps
T1076 /workspace/coverage/default/3.flash_ctrl_config_regwen.4179149674 Jun 06 01:32:18 PM PDT 24 Jun 06 01:32:33 PM PDT 24 21920000 ps
T1077 /workspace/coverage/default/0.flash_ctrl_ro.2894921350 Jun 06 01:31:46 PM PDT 24 Jun 06 01:33:56 PM PDT 24 2680410500 ps
T1078 /workspace/coverage/default/4.flash_ctrl_erase_suspend.2036018192 Jun 06 01:32:20 PM PDT 24 Jun 06 01:36:20 PM PDT 24 1250424800 ps
T121 /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.4040145612 Jun 06 01:32:20 PM PDT 24 Jun 06 01:32:38 PM PDT 24 791597900 ps
T1079 /workspace/coverage/default/67.flash_ctrl_connect.4245139454 Jun 06 01:36:56 PM PDT 24 Jun 06 01:37:13 PM PDT 24 17429800 ps
T1080 /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.2692546890 Jun 06 01:35:30 PM PDT 24 Jun 06 01:39:14 PM PDT 24 5865716400 ps
T1081 /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.1500345563 Jun 06 01:34:08 PM PDT 24 Jun 06 01:34:22 PM PDT 24 25525000 ps
T1082 /workspace/coverage/default/16.flash_ctrl_alert_test.3012401835 Jun 06 01:34:08 PM PDT 24 Jun 06 01:34:23 PM PDT 24 316501600 ps
T1083 /workspace/coverage/default/71.flash_ctrl_connect.1030251717 Jun 06 01:37:04 PM PDT 24 Jun 06 01:37:18 PM PDT 24 13829400 ps
T1084 /workspace/coverage/default/14.flash_ctrl_re_evict.3333939184 Jun 06 01:34:01 PM PDT 24 Jun 06 01:34:36 PM PDT 24 198239800 ps
T1085 /workspace/coverage/default/16.flash_ctrl_sec_info_access.26939297 Jun 06 01:34:11 PM PDT 24 Jun 06 01:35:22 PM PDT 24 5374785900 ps
T1086 /workspace/coverage/default/51.flash_ctrl_connect.981710565 Jun 06 01:36:51 PM PDT 24 Jun 06 01:37:07 PM PDT 24 53357100 ps
T1087 /workspace/coverage/default/68.flash_ctrl_otp_reset.565893268 Jun 06 01:37:01 PM PDT 24 Jun 06 01:39:16 PM PDT 24 34171300 ps
T1088 /workspace/coverage/default/62.flash_ctrl_otp_reset.3176068080 Jun 06 01:37:01 PM PDT 24 Jun 06 01:39:15 PM PDT 24 77780300 ps
T1089 /workspace/coverage/default/3.flash_ctrl_stress_all.1459160522 Jun 06 01:32:18 PM PDT 24 Jun 06 01:43:32 PM PDT 24 263585700 ps
T1090 /workspace/coverage/default/3.flash_ctrl_re_evict.2285303176 Jun 06 01:32:28 PM PDT 24 Jun 06 01:33:05 PM PDT 24 92906500 ps
T1091 /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.200455891 Jun 06 01:34:29 PM PDT 24 Jun 06 01:34:43 PM PDT 24 15584600 ps
T1092 /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.911227463 Jun 06 01:31:46 PM PDT 24 Jun 06 01:32:18 PM PDT 24 143941700 ps
T1093 /workspace/coverage/default/3.flash_ctrl_alert_test.1104663133 Jun 06 01:32:20 PM PDT 24 Jun 06 01:32:36 PM PDT 24 82478800 ps
T1094 /workspace/coverage/default/52.flash_ctrl_otp_reset.931221007 Jun 06 01:36:52 PM PDT 24 Jun 06 01:39:06 PM PDT 24 77209900 ps
T1095 /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3120853800 Jun 06 01:36:08 PM PDT 24 Jun 06 01:40:39 PM PDT 24 11186953000 ps
T1096 /workspace/coverage/default/8.flash_ctrl_connect.4264924497 Jun 06 01:32:53 PM PDT 24 Jun 06 01:33:10 PM PDT 24 24971200 ps
T1097 /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.1965864314 Jun 06 01:32:08 PM PDT 24 Jun 06 01:32:24 PM PDT 24 51524400 ps
T1098 /workspace/coverage/default/6.flash_ctrl_alert_test.3486312741 Jun 06 01:32:37 PM PDT 24 Jun 06 01:32:51 PM PDT 24 67974800 ps
T182 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3000823783 Jun 06 01:30:55 PM PDT 24 Jun 06 01:31:13 PM PDT 24 38493100 ps
T183 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.270793787 Jun 06 01:30:50 PM PDT 24 Jun 06 01:31:11 PM PDT 24 115964800 ps
T1099 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3065494745 Jun 06 01:31:05 PM PDT 24 Jun 06 01:31:21 PM PDT 24 21708200 ps
T65 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3122159933 Jun 06 01:30:34 PM PDT 24 Jun 06 01:30:53 PM PDT 24 258553600 ps
T253 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.851019766 Jun 06 01:31:13 PM PDT 24 Jun 06 01:31:28 PM PDT 24 29396900 ps
T66 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.4052978830 Jun 06 01:30:53 PM PDT 24 Jun 06 01:31:13 PM PDT 24 154501800 ps
T254 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2296756280 Jun 06 01:31:05 PM PDT 24 Jun 06 01:31:19 PM PDT 24 17575500 ps
T214 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.494246603 Jun 06 01:31:08 PM PDT 24 Jun 06 01:31:25 PM PDT 24 32511400 ps
T67 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3832144560 Jun 06 01:30:57 PM PDT 24 Jun 06 01:31:29 PM PDT 24 31408600 ps
T1100 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1692228394 Jun 06 01:30:37 PM PDT 24 Jun 06 01:30:54 PM PDT 24 18667600 ps
T326 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3832217369 Jun 06 01:30:54 PM PDT 24 Jun 06 01:31:09 PM PDT 24 45261300 ps
T184 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3072195121 Jun 06 01:30:50 PM PDT 24 Jun 06 01:31:08 PM PDT 24 185528300 ps
T243 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.165954865 Jun 06 01:30:55 PM PDT 24 Jun 06 01:31:32 PM PDT 24 1372189800 ps
T1101 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.731714451 Jun 06 01:30:51 PM PDT 24 Jun 06 01:31:07 PM PDT 24 118534100 ps
T1102 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.222832822 Jun 06 01:30:48 PM PDT 24 Jun 06 01:31:02 PM PDT 24 28986400 ps
T327 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1960127871 Jun 06 01:31:18 PM PDT 24 Jun 06 01:31:34 PM PDT 24 229750600 ps
T328 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1474005904 Jun 06 01:31:08 PM PDT 24 Jun 06 01:31:23 PM PDT 24 30773300 ps
T330 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2300479586 Jun 06 01:31:21 PM PDT 24 Jun 06 01:31:37 PM PDT 24 71701000 ps
T244 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.875330164 Jun 06 01:31:10 PM PDT 24 Jun 06 01:31:31 PM PDT 24 115269500 ps
T185 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1346869966 Jun 06 01:31:07 PM PDT 24 Jun 06 01:31:26 PM PDT 24 133194700 ps
T228 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1428357722 Jun 06 01:30:42 PM PDT 24 Jun 06 01:31:01 PM PDT 24 207425400 ps
T229 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2020550130 Jun 06 01:31:21 PM PDT 24 Jun 06 01:31:39 PM PDT 24 57357600 ps
T1103 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3493766508 Jun 06 01:30:50 PM PDT 24 Jun 06 01:31:07 PM PDT 24 30063900 ps
T251 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.832640450 Jun 06 01:30:41 PM PDT 24 Jun 06 01:31:48 PM PDT 24 5001695900 ps
T245 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3092696731 Jun 06 01:30:50 PM PDT 24 Jun 06 01:31:08 PM PDT 24 58643900 ps
T246 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1532511944 Jun 06 01:31:06 PM PDT 24 Jun 06 01:31:24 PM PDT 24 177930000 ps
T1104 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3682282923 Jun 06 01:31:07 PM PDT 24 Jun 06 01:31:22 PM PDT 24 46841000 ps
T252 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.376828699 Jun 06 01:31:03 PM PDT 24 Jun 06 01:31:20 PM PDT 24 335706100 ps
T329 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1341449215 Jun 06 01:31:20 PM PDT 24 Jun 06 01:31:35 PM PDT 24 269055900 ps
T230 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.497902368 Jun 06 01:31:11 PM PDT 24 Jun 06 01:31:30 PM PDT 24 47372100 ps
T1105 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.419334302 Jun 06 01:31:17 PM PDT 24 Jun 06 01:31:32 PM PDT 24 96283100 ps
T1106 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3984329490 Jun 06 01:30:31 PM PDT 24 Jun 06 01:30:46 PM PDT 24 24462200 ps
T331 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.562873419 Jun 06 01:30:50 PM PDT 24 Jun 06 01:31:04 PM PDT 24 16575700 ps
T1107 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2538239044 Jun 06 01:30:53 PM PDT 24 Jun 06 01:31:08 PM PDT 24 43424200 ps
T215 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2746948774 Jun 06 01:30:32 PM PDT 24 Jun 06 01:30:53 PM PDT 24 56557100 ps
T216 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3897873712 Jun 06 01:31:07 PM PDT 24 Jun 06 01:46:08 PM PDT 24 1401553500 ps
T1108 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3026375346 Jun 06 01:31:12 PM PDT 24 Jun 06 01:31:28 PM PDT 24 12885600 ps
T1109 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3719265374 Jun 06 01:30:49 PM PDT 24 Jun 06 01:31:21 PM PDT 24 178129100 ps
T1110 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3990366880 Jun 06 01:30:47 PM PDT 24 Jun 06 01:31:01 PM PDT 24 34703400 ps
T256 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3095782127 Jun 06 01:31:06 PM PDT 24 Jun 06 01:31:23 PM PDT 24 195507600 ps
T295 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4243348992 Jun 06 01:30:39 PM PDT 24 Jun 06 01:31:54 PM PDT 24 5690264500 ps
T312 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.370386117 Jun 06 01:30:53 PM PDT 24 Jun 06 01:31:13 PM PDT 24 131978300 ps
T1111 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.499448044 Jun 06 01:30:53 PM PDT 24 Jun 06 01:31:08 PM PDT 24 13682500 ps
T1112 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2132525278 Jun 06 01:30:32 PM PDT 24 Jun 06 01:30:49 PM PDT 24 19818600 ps
T1113 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2750130065 Jun 06 01:31:08 PM PDT 24 Jun 06 01:31:23 PM PDT 24 60965100 ps
T1114 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.4030693325 Jun 06 01:31:17 PM PDT 24 Jun 06 01:31:31 PM PDT 24 89066600 ps
T248 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3220328647 Jun 06 01:30:39 PM PDT 24 Jun 06 01:43:22 PM PDT 24 3716525200 ps
T1115 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3830970460 Jun 06 01:31:08 PM PDT 24 Jun 06 01:31:27 PM PDT 24 85999200 ps
T360 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2447608341 Jun 06 01:30:40 PM PDT 24 Jun 06 01:31:49 PM PDT 24 9798147800 ps
T296 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.935673048 Jun 06 01:30:38 PM PDT 24 Jun 06 01:31:25 PM PDT 24 47686500 ps
T1116 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.997001901 Jun 06 01:30:39 PM PDT 24 Jun 06 01:31:11 PM PDT 24 56247200 ps
T249 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4043363021 Jun 06 01:31:05 PM PDT 24 Jun 06 01:37:29 PM PDT 24 179543000 ps
T1117 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3074465945 Jun 06 01:31:11 PM PDT 24 Jun 06 01:31:28 PM PDT 24 37007300 ps
T1118 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3359961397 Jun 06 01:31:27 PM PDT 24 Jun 06 01:31:42 PM PDT 24 31278600 ps
T1119 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.798975724 Jun 06 01:30:50 PM PDT 24 Jun 06 01:31:05 PM PDT 24 15335200 ps
T297 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1719735756 Jun 06 01:31:07 PM PDT 24 Jun 06 01:38:45 PM PDT 24 807802400 ps
T1120 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2805160830 Jun 06 01:31:14 PM PDT 24 Jun 06 01:31:28 PM PDT 24 82655000 ps
T349 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.151001252 Jun 06 01:31:05 PM PDT 24 Jun 06 01:38:41 PM PDT 24 183867500 ps
T1121 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2735494831 Jun 06 01:31:12 PM PDT 24 Jun 06 01:31:28 PM PDT 24 30533100 ps
T1122 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3390099736 Jun 06 01:30:48 PM PDT 24 Jun 06 01:31:19 PM PDT 24 380607500 ps
T1123 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1359380091 Jun 06 01:30:39 PM PDT 24 Jun 06 01:31:22 PM PDT 24 1149601900 ps
T1124 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1541052943 Jun 06 01:30:51 PM PDT 24 Jun 06 01:31:08 PM PDT 24 58431900 ps
T232 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.589057528 Jun 06 01:30:39 PM PDT 24 Jun 06 01:30:53 PM PDT 24 70940800 ps
T1125 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1776586695 Jun 06 01:30:50 PM PDT 24 Jun 06 01:31:11 PM PDT 24 3234897500 ps
T260 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1737867043 Jun 06 01:31:04 PM PDT 24 Jun 06 01:31:23 PM PDT 24 103255400 ps
T1126 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1885883046 Jun 06 01:31:07 PM PDT 24 Jun 06 01:31:28 PM PDT 24 316564400 ps
T1127 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1681065865 Jun 06 01:31:06 PM PDT 24 Jun 06 01:31:22 PM PDT 24 34408300 ps
T1128 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2124774105 Jun 06 01:31:07 PM PDT 24 Jun 06 01:31:43 PM PDT 24 608769800 ps
T1129 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3701031342 Jun 06 01:30:53 PM PDT 24 Jun 06 01:31:13 PM PDT 24 54217700 ps
T1130 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3048997813 Jun 06 01:31:12 PM PDT 24 Jun 06 01:31:26 PM PDT 24 54055700 ps
T233 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3622530747 Jun 06 01:30:38 PM PDT 24 Jun 06 01:30:53 PM PDT 24 239420000 ps
T1131 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.349308801 Jun 06 01:31:07 PM PDT 24 Jun 06 01:31:23 PM PDT 24 14160000 ps
T1132 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3929889512 Jun 06 01:31:18 PM PDT 24 Jun 06 01:31:34 PM PDT 24 24384100 ps
T1133 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2543363019 Jun 06 01:30:52 PM PDT 24 Jun 06 01:31:07 PM PDT 24 43733100 ps
T298 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3546772914 Jun 06 01:30:55 PM PDT 24 Jun 06 01:31:15 PM PDT 24 419516700 ps
T255 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1382205104 Jun 06 01:30:56 PM PDT 24 Jun 06 01:31:14 PM PDT 24 89289400 ps
T1134 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2386303403 Jun 06 01:30:52 PM PDT 24 Jun 06 01:31:10 PM PDT 24 26852500 ps
T1135 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3579997714 Jun 06 01:30:38 PM PDT 24 Jun 06 01:30:54 PM PDT 24 93822000 ps
T1136 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1042335711 Jun 06 01:30:52 PM PDT 24 Jun 06 01:31:07 PM PDT 24 29034400 ps
T350 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.775807214 Jun 06 01:30:53 PM PDT 24 Jun 06 01:45:47 PM PDT 24 2728446600 ps
T1137 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2862491172 Jun 06 01:30:48 PM PDT 24 Jun 06 01:31:02 PM PDT 24 15840900 ps
T1138 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2989649198 Jun 06 01:31:17 PM PDT 24 Jun 06 01:31:31 PM PDT 24 52611000 ps
T299 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1641626347 Jun 06 01:30:39 PM PDT 24 Jun 06 01:31:21 PM PDT 24 1650644000 ps
T1139 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2371332789 Jun 06 01:31:10 PM PDT 24 Jun 06 01:31:27 PM PDT 24 48047900 ps
T301 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.4118147885 Jun 06 01:30:31 PM PDT 24 Jun 06 01:31:02 PM PDT 24 57257200 ps
T1140 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1555769852 Jun 06 01:30:56 PM PDT 24 Jun 06 01:31:17 PM PDT 24 316504500 ps
T264 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4281241326 Jun 06 01:30:53 PM PDT 24 Jun 06 01:45:55 PM PDT 24 1463909800 ps
T261 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1903539645 Jun 06 01:30:41 PM PDT 24 Jun 06 01:30:59 PM PDT 24 35657600 ps
T1141 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2910725067 Jun 06 01:31:06 PM PDT 24 Jun 06 01:31:20 PM PDT 24 47373900 ps
T300 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.21348601 Jun 06 01:30:32 PM PDT 24 Jun 06 01:30:50 PM PDT 24 39949300 ps
T1142 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2005639592 Jun 06 01:31:09 PM PDT 24 Jun 06 01:31:24 PM PDT 24 220661500 ps
T302 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.586716148 Jun 06 01:30:54 PM PDT 24 Jun 06 01:31:27 PM PDT 24 229881400 ps
T1143 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.330868200 Jun 06 01:31:08 PM PDT 24 Jun 06 01:31:26 PM PDT 24 19421000 ps
T1144 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3205158258 Jun 06 01:31:11 PM PDT 24 Jun 06 01:31:28 PM PDT 24 14469800 ps
T1145 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.425532255 Jun 06 01:30:50 PM PDT 24 Jun 06 01:31:09 PM PDT 24 46762700 ps
T1146 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3890835426 Jun 06 01:31:09 PM PDT 24 Jun 06 01:31:26 PM PDT 24 12980400 ps
T303 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1986035282 Jun 06 01:30:40 PM PDT 24 Jun 06 01:31:32 PM PDT 24 6604409400 ps
T1147 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.229981079 Jun 06 01:31:11 PM PDT 24 Jun 06 01:31:26 PM PDT 24 30889700 ps
T1148 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2565064422 Jun 06 01:30:38 PM PDT 24 Jun 06 01:30:55 PM PDT 24 20641900 ps
T265 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3468677811 Jun 06 01:31:06 PM PDT 24 Jun 06 01:38:53 PM PDT 24 409027400 ps
T304 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.137111095 Jun 06 01:30:52 PM PDT 24 Jun 06 01:31:11 PM PDT 24 110353900 ps
T1149 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.871501342 Jun 06 01:31:10 PM PDT 24 Jun 06 01:31:47 PM PDT 24 117698000 ps
T1150 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1132390424 Jun 06 01:31:07 PM PDT 24 Jun 06 01:31:25 PM PDT 24 67916800 ps
T1151 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1449175988 Jun 06 01:30:57 PM PDT 24 Jun 06 01:31:14 PM PDT 24 34529500 ps
T257 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1121918197 Jun 06 01:30:50 PM PDT 24 Jun 06 01:31:06 PM PDT 24 59938400 ps
T1152 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3666195222 Jun 06 01:30:39 PM PDT 24 Jun 06 01:30:56 PM PDT 24 165860700 ps
T1153 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1217822831 Jun 06 01:30:42 PM PDT 24 Jun 06 01:31:22 PM PDT 24 76171900 ps
T1154 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.732605066 Jun 06 01:31:16 PM PDT 24 Jun 06 01:31:30 PM PDT 24 24657300 ps
T1155 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1038412157 Jun 06 01:30:44 PM PDT 24 Jun 06 01:30:58 PM PDT 24 14214300 ps
T1156 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.72617767 Jun 06 01:31:09 PM PDT 24 Jun 06 01:31:26 PM PDT 24 44677300 ps
T1157 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.555561858 Jun 06 01:31:07 PM PDT 24 Jun 06 01:31:26 PM PDT 24 62739800 ps
T263 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3758464483 Jun 06 01:31:07 PM PDT 24 Jun 06 01:38:45 PM PDT 24 455658800 ps
T1158 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1715650787 Jun 06 01:31:11 PM PDT 24 Jun 06 01:31:28 PM PDT 24 38631700 ps
T356 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.279006050 Jun 06 01:30:40 PM PDT 24 Jun 06 01:38:19 PM PDT 24 1281512500 ps
T1159 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1315479594 Jun 06 01:30:57 PM PDT 24 Jun 06 01:31:16 PM PDT 24 248331300 ps
T1160 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3849341402 Jun 06 01:30:53 PM PDT 24 Jun 06 01:31:10 PM PDT 24 52195100 ps
T1161 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3483558294 Jun 06 01:30:51 PM PDT 24 Jun 06 01:31:05 PM PDT 24 18409200 ps
T1162 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2487707296 Jun 06 01:30:39 PM PDT 24 Jun 06 01:30:53 PM PDT 24 51205900 ps
T1163 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1796685305 Jun 06 01:30:31 PM PDT 24 Jun 06 01:30:47 PM PDT 24 54464100 ps
T1164 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.712004728 Jun 06 01:30:41 PM PDT 24 Jun 06 01:30:55 PM PDT 24 17824700 ps
T1165 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1137215205 Jun 06 01:31:19 PM PDT 24 Jun 06 01:31:34 PM PDT 24 27056600 ps
T1166 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.325754356 Jun 06 01:31:16 PM PDT 24 Jun 06 01:31:30 PM PDT 24 17537800 ps
T1167 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.150665319 Jun 06 01:31:06 PM PDT 24 Jun 06 01:31:23 PM PDT 24 22037300 ps
T234 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1783541991 Jun 06 01:30:41 PM PDT 24 Jun 06 01:30:55 PM PDT 24 16907500 ps
T1168 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2792785255 Jun 06 01:30:51 PM PDT 24 Jun 06 01:31:07 PM PDT 24 84403200 ps
T1169 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1837446841 Jun 06 01:31:08 PM PDT 24 Jun 06 01:31:24 PM PDT 24 58775700 ps
T262 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2235488127 Jun 06 01:31:10 PM PDT 24 Jun 06 01:31:30 PM PDT 24 321817500 ps
T258 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2129265813 Jun 06 01:31:07 PM PDT 24 Jun 06 01:31:29 PM PDT 24 133856200 ps
T266 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2181587991 Jun 06 01:31:05 PM PDT 24 Jun 06 01:31:23 PM PDT 24 24405600 ps
T1170 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2269880230 Jun 06 01:31:20 PM PDT 24 Jun 06 01:31:35 PM PDT 24 17133500 ps
T1171 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.507066707 Jun 06 01:31:07 PM PDT 24 Jun 06 01:31:26 PM PDT 24 152798100 ps
T1172 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3070947146 Jun 06 01:30:53 PM PDT 24 Jun 06 01:31:11 PM PDT 24 11400400 ps
T1173 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.371123385 Jun 06 01:31:06 PM PDT 24 Jun 06 01:31:23 PM PDT 24 24955300 ps
T1174 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.4076304273 Jun 06 01:30:39 PM PDT 24 Jun 06 01:30:56 PM PDT 24 44379700 ps
T1175 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2698051462 Jun 06 01:30:33 PM PDT 24 Jun 06 01:30:48 PM PDT 24 23910100 ps
T352 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1719913271 Jun 06 01:30:52 PM PDT 24 Jun 06 01:38:37 PM PDT 24 2329412700 ps
T355 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1533158233 Jun 06 01:30:55 PM PDT 24 Jun 06 01:43:41 PM PDT 24 8174938300 ps
T1176 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.4099839646 Jun 06 01:31:08 PM PDT 24 Jun 06 01:31:23 PM PDT 24 78145500 ps
T1177 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2159258005 Jun 06 01:31:07 PM PDT 24 Jun 06 01:31:22 PM PDT 24 25504700 ps
T1178 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3902001213 Jun 06 01:31:05 PM PDT 24 Jun 06 01:31:22 PM PDT 24 111016300 ps
T354 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3021959040 Jun 06 01:30:38 PM PDT 24 Jun 06 01:38:17 PM PDT 24 641842800 ps
T259 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1444893834 Jun 06 01:30:53 PM PDT 24 Jun 06 01:31:10 PM PDT 24 66014300 ps
T1179 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.177257935 Jun 06 01:30:55 PM PDT 24 Jun 06 01:31:15 PM PDT 24 77165800 ps
T235 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.630730754 Jun 06 01:30:32 PM PDT 24 Jun 06 01:30:48 PM PDT 24 26172600 ps
T1180 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.966878794 Jun 06 01:31:22 PM PDT 24 Jun 06 01:31:39 PM PDT 24 61309300 ps
T351 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2038895151 Jun 06 01:30:50 PM PDT 24 Jun 06 01:45:47 PM PDT 24 457682100 ps
T1181 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1772237284 Jun 06 01:30:53 PM PDT 24 Jun 06 01:31:13 PM PDT 24 68773600 ps
T1182 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1875976954 Jun 06 01:30:48 PM PDT 24 Jun 06 01:31:04 PM PDT 24 116627000 ps
T1183 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3033812589 Jun 06 01:30:41 PM PDT 24 Jun 06 01:30:57 PM PDT 24 55393500 ps
T1184 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2589915854 Jun 06 01:31:15 PM PDT 24 Jun 06 01:31:29 PM PDT 24 144374000 ps
T1185 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.470526945 Jun 06 01:31:17 PM PDT 24 Jun 06 01:31:32 PM PDT 24 25869700 ps
T1186 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2661436008 Jun 06 01:31:16 PM PDT 24 Jun 06 01:31:30 PM PDT 24 30310300 ps
T1187 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3576207599 Jun 06 01:31:09 PM PDT 24 Jun 06 01:31:24 PM PDT 24 92807100 ps
T1188 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1385399971 Jun 06 01:30:37 PM PDT 24 Jun 06 01:31:25 PM PDT 24 11605118800 ps
T305 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1268268973 Jun 06 01:30:54 PM PDT 24 Jun 06 01:31:15 PM PDT 24 174511200 ps
T1189 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2565781220 Jun 06 01:30:55 PM PDT 24 Jun 06 01:31:11 PM PDT 24 35590800 ps
T1190 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1950332702 Jun 06 01:30:39 PM PDT 24 Jun 06 01:30:57 PM PDT 24 369023900 ps
T1191 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.520114868 Jun 06 01:31:04 PM PDT 24 Jun 06 01:31:20 PM PDT 24 13662000 ps
T1192 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.390333221 Jun 06 01:30:32 PM PDT 24 Jun 06 01:30:50 PM PDT 24 25491100 ps
T1193 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.104953022 Jun 06 01:30:34 PM PDT 24 Jun 06 01:30:55 PM PDT 24 54381400 ps
T1194 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3273469322 Jun 06 01:31:17 PM PDT 24 Jun 06 01:31:32 PM PDT 24 14793100 ps
T1195 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1139592451 Jun 06 01:30:48 PM PDT 24 Jun 06 01:31:09 PM PDT 24 381614300 ps
T1196 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1338975533 Jun 06 01:30:39 PM PDT 24 Jun 06 01:30:56 PM PDT 24 96422400 ps
T1197 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3903254146 Jun 06 01:30:33 PM PDT 24 Jun 06 01:30:50 PM PDT 24 18930500 ps
T1198 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1899166872 Jun 06 01:30:55 PM PDT 24 Jun 06 01:37:22 PM PDT 24 335758500 ps
T1199 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.592404327 Jun 06 01:31:16 PM PDT 24 Jun 06 01:31:30 PM PDT 24 34187300 ps
T358 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2291358892 Jun 06 01:30:33 PM PDT 24 Jun 06 01:36:57 PM PDT 24 330873500 ps
T1200 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.4129737536 Jun 06 01:30:41 PM PDT 24 Jun 06 01:30:56 PM PDT 24 53386400 ps
T1201 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3000381302 Jun 06 01:30:50 PM PDT 24 Jun 06 01:31:05 PM PDT 24 22547600 ps
T1202 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4275149875 Jun 06 01:31:17 PM PDT 24 Jun 06 01:31:31 PM PDT 24 32459400 ps
T306 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.343309870 Jun 06 01:31:07 PM PDT 24 Jun 06 01:31:24 PM PDT 24 228606400 ps
T1203 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2194608977 Jun 06 01:30:52 PM PDT 24 Jun 06 01:31:09 PM PDT 24 12170100 ps
T1204 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2780990857 Jun 06 01:30:49 PM PDT 24 Jun 06 01:31:03 PM PDT 24 35818300 ps
T1205 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2002863223 Jun 06 01:31:06 PM PDT 24 Jun 06 01:31:25 PM PDT 24 49160500 ps
T1206 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1349341835 Jun 06 01:30:52 PM PDT 24 Jun 06 01:31:08 PM PDT 24 63585800 ps
T1207 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2987020677 Jun 06 01:31:07 PM PDT 24 Jun 06 01:31:22 PM PDT 24 15480600 ps
T1208 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2760216414 Jun 06 01:30:53 PM PDT 24 Jun 06 01:31:08 PM PDT 24 21453300 ps
T1209 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4092949758 Jun 06 01:30:50 PM PDT 24 Jun 06 01:31:05 PM PDT 24 16838900 ps
T1210 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3689442405 Jun 06 01:30:33 PM PDT 24 Jun 06 01:30:51 PM PDT 24 87219700 ps
T1211 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.464152573 Jun 06 01:30:39 PM PDT 24 Jun 06 01:30:56 PM PDT 24 24752800 ps
T1212 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2313579617 Jun 06 01:30:51 PM PDT 24 Jun 06 01:31:10 PM PDT 24 133128900 ps
T1213 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.841907437 Jun 06 01:30:37 PM PDT 24 Jun 06 01:30:54 PM PDT 24 22948600 ps
T1214 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1926958895 Jun 06 01:30:43 PM PDT 24 Jun 06 01:31:05 PM PDT 24 789043200 ps
T1215 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3373075359 Jun 06 01:31:17 PM PDT 24 Jun 06 01:31:31 PM PDT 24 16037100 ps
T1216 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1249891433 Jun 06 01:30:49 PM PDT 24 Jun 06 01:31:07 PM PDT 24 34108000 ps
T1217 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1549728193 Jun 06 01:31:08 PM PDT 24 Jun 06 01:31:23 PM PDT 24 17957800 ps
T1218 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.645557933 Jun 06 01:30:54 PM PDT 24 Jun 06 01:31:09 PM PDT 24 47144300 ps
T353 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1279543171 Jun 06 01:30:52 PM PDT 24 Jun 06 01:46:10 PM PDT 24 767038300 ps
T1219 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1087538826 Jun 06 01:30:42 PM PDT 24 Jun 06 01:31:12 PM PDT 24 248360400 ps
T1220 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1404849701 Jun 06 01:31:11 PM PDT 24 Jun 06 01:31:28 PM PDT 24 73431300 ps
T1221 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3345965219 Jun 06 01:30:46 PM PDT 24 Jun 06 01:31:04 PM PDT 24 43485100 ps
T1222 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2812255002 Jun 06 01:30:34 PM PDT 24 Jun 06 01:31:56 PM PDT 24 6084596600 ps
T1223 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2326498454 Jun 06 01:30:44 PM PDT 24 Jun 06 01:31:00 PM PDT 24 25485300 ps
T1224 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1467228177 Jun 06 01:30:31 PM PDT 24 Jun 06 01:31:41 PM PDT 24 1842652900 ps
T357 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1161027869 Jun 06 01:30:42 PM PDT 24 Jun 06 01:45:40 PM PDT 24 1240969600 ps
T1225 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1952702994 Jun 06 01:31:11 PM PDT 24 Jun 06 01:31:31 PM PDT 24 82286800 ps
T1226 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3301595074 Jun 06 01:30:39 PM PDT 24 Jun 06 01:31:28 PM PDT 24 859583700 ps
T1227 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.73258276 Jun 06 01:30:39 PM PDT 24 Jun 06 01:30:54 PM PDT 24 31166700 ps
T1228 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2774596439 Jun 06 01:31:09 PM PDT 24 Jun 06 01:31:26 PM PDT 24 47970000 ps
T1229 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.59478727 Jun 06 01:30:42 PM PDT 24 Jun 06 01:31:01 PM PDT 24 105243800 ps
T1230 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2792366994 Jun 06 01:30:52 PM PDT 24 Jun 06 01:31:10 PM PDT 24 126555100 ps
T1231 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3241926624 Jun 06 01:30:51 PM PDT 24 Jun 06 01:31:08 PM PDT 24 11226400 ps
T1232 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3042215236 Jun 06 01:30:53 PM PDT 24 Jun 06 01:31:09 PM PDT 24 17867400 ps
T348 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1475056689 Jun 06 01:30:31 PM PDT 24 Jun 06 01:38:14 PM PDT 24 699998700 ps
T1233 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.743715947 Jun 06 01:30:49 PM PDT 24 Jun 06 01:38:34 PM PDT 24 676262700 ps
T1234 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1919216539 Jun 06 01:30:52 PM PDT 24 Jun 06 01:31:09 PM PDT 24 118414300 ps
T1235 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2671444097 Jun 06 01:31:08 PM PDT 24 Jun 06 01:31:24 PM PDT 24 71408500 ps
T1236 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.472505266 Jun 06 01:30:39 PM PDT 24 Jun 06 01:30:53 PM PDT 24 61811000 ps
T1237 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3063699341 Jun 06 01:31:16 PM PDT 24 Jun 06 01:31:30 PM PDT 24 40018600 ps
T1238 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1730507998 Jun 06 01:31:09 PM PDT 24 Jun 06 01:31:24 PM PDT 24 45746700 ps
T1239 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3015115632 Jun 06 01:31:16 PM PDT 24 Jun 06 01:31:30 PM PDT 24 14404100 ps
T1240 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2581753193 Jun 06 01:30:50 PM PDT 24 Jun 06 01:31:11 PM PDT 24 609888500 ps
T1241 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.77298678 Jun 06 01:30:42 PM PDT 24 Jun 06 01:30:56 PM PDT 24 13114000 ps
T1242 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2730876090 Jun 06 01:31:16 PM PDT 24 Jun 06 01:31:30 PM PDT 24 111122600 ps
T236 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.252150999 Jun 06 01:30:39 PM PDT 24 Jun 06 01:30:54 PM PDT 24 18117800 ps

Test location /workspace/coverage/default/10.flash_ctrl_rw.188608809
Short name T1
Test name
Test status
Simulation time 9223577800 ps
CPU time 566.15 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:43:10 PM PDT 24
Peak memory 310080 kb
Host smart-d2254113-5e71-4078-9a7b-3b132e6be2ba
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188608809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.flash_ctrl_rw.188608809
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.2157077415
Short name T18
Test name
Test status
Simulation time 329682400 ps
CPU time 806.08 seconds
Started Jun 06 01:32:09 PM PDT 24
Finished Jun 06 01:45:36 PM PDT 24
Peak memory 273376 kb
Host smart-f3763360-a1bc-478a-8441-e81d030b0f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157077415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.2157077415
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.4052978830
Short name T66
Test name
Test status
Simulation time 154501800 ps
CPU time 17.61 seconds
Started Jun 06 01:30:53 PM PDT 24
Finished Jun 06 01:31:13 PM PDT 24
Peak memory 261060 kb
Host smart-1edc0b0a-f25f-40ab-90db-4c9fd048edfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052978830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.4052978830
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.456402277
Short name T13
Test name
Test status
Simulation time 71441000 ps
CPU time 112.51 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:34:29 PM PDT 24
Peak memory 259824 kb
Host smart-823699bf-e96a-4468-8997-842f528e0fe3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456402277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp
_reset.456402277
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.214104039
Short name T72
Test name
Test status
Simulation time 49343827300 ps
CPU time 357.77 seconds
Started Jun 06 01:33:54 PM PDT 24
Finished Jun 06 01:39:52 PM PDT 24
Peak memory 274696 kb
Host smart-0ef4d1bd-d5bb-481d-8172-cf8660135055
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214104039 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_mp_regions.214104039
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.1555069007
Short name T79
Test name
Test status
Simulation time 543571990400 ps
CPU time 2229.18 seconds
Started Jun 06 01:31:46 PM PDT 24
Finished Jun 06 02:08:56 PM PDT 24
Peak memory 263976 kb
Host smart-357582bc-3d21-4bb6-9849-32bf0072e6f7
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555069007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.1555069007
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.3178643188
Short name T117
Test name
Test status
Simulation time 20111473100 ps
CPU time 61.56 seconds
Started Jun 06 01:33:07 PM PDT 24
Finished Jun 06 01:34:09 PM PDT 24
Peak memory 262876 kb
Host smart-b2b3ef3c-6ec3-41a9-82bd-445645717f7c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178643188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.3178643188
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3897873712
Short name T216
Test name
Test status
Simulation time 1401553500 ps
CPU time 898.82 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:46:08 PM PDT 24
Peak memory 263920 kb
Host smart-a59c0d2c-43f4-4a6c-b16e-1aa46a55fb5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897873712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.3897873712
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.1696377085
Short name T16
Test name
Test status
Simulation time 11294113600 ps
CPU time 6251 seconds
Started Jun 06 01:32:28 PM PDT 24
Finished Jun 06 03:16:41 PM PDT 24
Peak memory 287272 kb
Host smart-13844abf-295b-4c56-b2b4-1bca5c236386
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696377085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.1696377085
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.3954507222
Short name T34
Test name
Test status
Simulation time 265091400 ps
CPU time 30.7 seconds
Started Jun 06 01:33:55 PM PDT 24
Finished Jun 06 01:34:26 PM PDT 24
Peak memory 273556 kb
Host smart-559fd01b-d8d6-4f1f-b41c-17ba7ee38753
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954507222 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.3954507222
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.3318716649
Short name T134
Test name
Test status
Simulation time 4293382000 ps
CPU time 70.18 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 01:33:08 PM PDT 24
Peak memory 260492 kb
Host smart-1575540f-2096-460a-9ad1-c4125119bb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318716649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.3318716649
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.270793787
Short name T183
Test name
Test status
Simulation time 115964800 ps
CPU time 20.06 seconds
Started Jun 06 01:30:50 PM PDT 24
Finished Jun 06 01:31:11 PM PDT 24
Peak memory 263848 kb
Host smart-015c7215-ebef-4898-8a6c-04484f8c103b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270793787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.270793787
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.1379616622
Short name T128
Test name
Test status
Simulation time 6315694900 ps
CPU time 367.76 seconds
Started Jun 06 01:32:21 PM PDT 24
Finished Jun 06 01:38:30 PM PDT 24
Peak memory 263180 kb
Host smart-779fee08-2172-4e42-8201-ce1bf5c15e4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379616622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.1379616622
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.2142123417
Short name T148
Test name
Test status
Simulation time 240164100 ps
CPU time 110.62 seconds
Started Jun 06 01:34:08 PM PDT 24
Finished Jun 06 01:36:00 PM PDT 24
Peak memory 259684 kb
Host smart-22ecbc61-de48-4052-b27d-76d2906aaecd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142123417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.2142123417
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.4001146538
Short name T14
Test name
Test status
Simulation time 44952100 ps
CPU time 13.87 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:32:23 PM PDT 24
Peak memory 262344 kb
Host smart-2c2793c8-c9bb-4f4b-b6f4-0b28cc5e9ce6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001146538 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.4001146538
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.2973111268
Short name T9
Test name
Test status
Simulation time 42994700 ps
CPU time 15.34 seconds
Started Jun 06 01:32:07 PM PDT 24
Finished Jun 06 01:32:24 PM PDT 24
Peak memory 260408 kb
Host smart-7616065f-0318-4861-896f-893d457f90d9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973111268 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.2973111268
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.977197205
Short name T43
Test name
Test status
Simulation time 13980131300 ps
CPU time 571.21 seconds
Started Jun 06 01:32:24 PM PDT 24
Finished Jun 06 01:41:57 PM PDT 24
Peak memory 329220 kb
Host smart-2c96d902-24ee-495b-9cbc-ea2c99f57a08
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977197205 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.flash_ctrl_rw_derr.977197205
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2300479586
Short name T330
Test name
Test status
Simulation time 71701000 ps
CPU time 13.6 seconds
Started Jun 06 01:31:21 PM PDT 24
Finished Jun 06 01:31:37 PM PDT 24
Peak memory 261092 kb
Host smart-f7bf26c1-4e2e-48c2-81d4-3609e7aca9be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300479586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
2300479586
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.1739954930
Short name T643
Test name
Test status
Simulation time 67156500 ps
CPU time 112.21 seconds
Started Jun 06 01:36:57 PM PDT 24
Finished Jun 06 01:38:50 PM PDT 24
Peak memory 259708 kb
Host smart-721cb6f2-f1e7-4129-a4a3-a89b7ad853d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739954930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.1739954930
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.474181574
Short name T143
Test name
Test status
Simulation time 71745500 ps
CPU time 131.74 seconds
Started Jun 06 01:35:48 PM PDT 24
Finished Jun 06 01:38:01 PM PDT 24
Peak memory 259832 kb
Host smart-5b149553-7f4e-4b5b-a625-1ad7dd6ec63c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474181574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ot
p_reset.474181574
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.668072637
Short name T269
Test name
Test status
Simulation time 1368415000 ps
CPU time 245.45 seconds
Started Jun 06 01:35:09 PM PDT 24
Finished Jun 06 01:39:15 PM PDT 24
Peak memory 291008 kb
Host smart-c26c1589-f0a4-45aa-9558-56b4607a3da2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668072637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flas
h_ctrl_intr_rd.668072637
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.2009798779
Short name T21
Test name
Test status
Simulation time 284560800 ps
CPU time 24.91 seconds
Started Jun 06 01:31:47 PM PDT 24
Finished Jun 06 01:32:13 PM PDT 24
Peak memory 262244 kb
Host smart-a053651d-ebd1-4960-8561-fc8e9e70dd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009798779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.2009798779
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.2809555644
Short name T19
Test name
Test status
Simulation time 2278074700 ps
CPU time 96.41 seconds
Started Jun 06 01:33:50 PM PDT 24
Finished Jun 06 01:35:27 PM PDT 24
Peak memory 263660 kb
Host smart-bab70370-2134-456b-895a-545f7a3f3144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809555644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.2809555644
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.4286507494
Short name T178
Test name
Test status
Simulation time 33722800 ps
CPU time 13.73 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:33:57 PM PDT 24
Peak memory 264788 kb
Host smart-d0ee0332-98ac-4a83-b41b-33cdd1fc67c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286507494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
4286507494
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.3720021049
Short name T140
Test name
Test status
Simulation time 358611536000 ps
CPU time 1088.45 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:50:37 PM PDT 24
Peak memory 262536 kb
Host smart-0bec2f71-3156-4e00-922c-8789a7e6b4c2
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720021049 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.3720021049
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.3534274674
Short name T126
Test name
Test status
Simulation time 2563178700 ps
CPU time 69.35 seconds
Started Jun 06 01:31:46 PM PDT 24
Finished Jun 06 01:32:56 PM PDT 24
Peak memory 260628 kb
Host smart-8ccd89b7-2cc6-4b76-892d-12bc01371246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534274674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.3534274674
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.1834488637
Short name T152
Test name
Test status
Simulation time 275943203600 ps
CPU time 2811.71 seconds
Started Jun 06 01:32:09 PM PDT 24
Finished Jun 06 02:19:03 PM PDT 24
Peak memory 264836 kb
Host smart-b4d512b6-1809-4d4b-a736-98de2f7d2a88
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834488637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.1834488637
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.861261681
Short name T130
Test name
Test status
Simulation time 841259400 ps
CPU time 68.02 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:33:37 PM PDT 24
Peak memory 260152 kb
Host smart-348c408e-98b7-4bc8-8020-bbfa16c1493c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861261681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.861261681
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3220328647
Short name T248
Test name
Test status
Simulation time 3716525200 ps
CPU time 762.02 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:43:22 PM PDT 24
Peak memory 263924 kb
Host smart-dca9ddea-b57d-4e24-91da-37b9c55ecd62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220328647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.3220328647
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.1747910190
Short name T307
Test name
Test status
Simulation time 4026351700 ps
CPU time 116.78 seconds
Started Jun 06 01:32:09 PM PDT 24
Finished Jun 06 01:34:08 PM PDT 24
Peak memory 263020 kb
Host smart-69b446c4-b77a-46c8-8019-eaa9d3ad23ce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747910190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.1747910190
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.684926946
Short name T166
Test name
Test status
Simulation time 16017726400 ps
CPU time 2453.72 seconds
Started Jun 06 01:32:24 PM PDT 24
Finished Jun 06 02:13:20 PM PDT 24
Peak memory 263836 kb
Host smart-6835d8b7-3edd-4e09-b088-744054d0520b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684926946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.684926946
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.2119009957
Short name T108
Test name
Test status
Simulation time 1948901500 ps
CPU time 59.41 seconds
Started Jun 06 01:34:01 PM PDT 24
Finished Jun 06 01:35:01 PM PDT 24
Peak memory 260380 kb
Host smart-19e535be-5d63-4e71-8108-87e6466e8794
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119009957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.2
119009957
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.4046379195
Short name T15
Test name
Test status
Simulation time 15358600 ps
CPU time 13.8 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:32:34 PM PDT 24
Peak memory 265260 kb
Host smart-56fb1a82-5249-4bee-b442-278c705598e0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046379195 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.4046379195
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.3586464243
Short name T339
Test name
Test status
Simulation time 11480111900 ps
CPU time 160.9 seconds
Started Jun 06 01:35:27 PM PDT 24
Finished Jun 06 01:38:08 PM PDT 24
Peak memory 291904 kb
Host smart-fb6ca71a-de5b-40a0-b0b5-8d616538bbc7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586464243 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.3586464243
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.589057528
Short name T232
Test name
Test status
Simulation time 70940800 ps
CPU time 13.65 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:30:53 PM PDT 24
Peak memory 262740 kb
Host smart-3ced2c06-a247-45a2-a081-1d7a6d4d07e2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589057528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_mem_partial_access.589057528
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1656901296
Short name T603
Test name
Test status
Simulation time 10018770800 ps
CPU time 73.61 seconds
Started Jun 06 01:32:06 PM PDT 24
Finished Jun 06 01:33:21 PM PDT 24
Peak memory 299556 kb
Host smart-7179c24e-8d0b-4ed1-a066-b212adc6148f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656901296 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.1656901296
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3000823783
Short name T182
Test name
Test status
Simulation time 38493100 ps
CPU time 16.59 seconds
Started Jun 06 01:30:55 PM PDT 24
Finished Jun 06 01:31:13 PM PDT 24
Peak memory 263856 kb
Host smart-dffe0f55-d2f9-4dc2-b3f7-ca0ef1c494f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000823783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
3000823783
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2296756280
Short name T254
Test name
Test status
Simulation time 17575500 ps
CPU time 13.35 seconds
Started Jun 06 01:31:05 PM PDT 24
Finished Jun 06 01:31:19 PM PDT 24
Peak memory 261168 kb
Host smart-3bb1a818-e322-45be-a805-243c5ec33b67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296756280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
2296756280
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.963279172
Short name T12
Test name
Test status
Simulation time 15381100 ps
CPU time 21.92 seconds
Started Jun 06 01:35:56 PM PDT 24
Finished Jun 06 01:36:19 PM PDT 24
Peak memory 273588 kb
Host smart-535ef665-cb81-4e7e-a544-143d03251f0f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963279172 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.963279172
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.4040145612
Short name T121
Test name
Test status
Simulation time 791597900 ps
CPU time 16.19 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:32:38 PM PDT 24
Peak memory 262632 kb
Host smart-a706ea72-e7f9-4179-8388-e309b4912654
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040145612 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.4040145612
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.2281872798
Short name T316
Test name
Test status
Simulation time 804227900 ps
CPU time 41.06 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 01:32:38 PM PDT 24
Peak memory 262676 kb
Host smart-25be4032-636f-431c-a8c8-3217983ee752
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281872798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.2281872798
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.3023435962
Short name T78
Test name
Test status
Simulation time 28584900 ps
CPU time 20.87 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 01:32:45 PM PDT 24
Peak memory 273552 kb
Host smart-bb923f49-927b-41e8-b5a8-c3c567fe7738
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023435962 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.3023435962
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.1696961495
Short name T22
Test name
Test status
Simulation time 92272000 ps
CPU time 33.56 seconds
Started Jun 06 01:32:33 PM PDT 24
Finished Jun 06 01:33:07 PM PDT 24
Peak memory 273472 kb
Host smart-69b591ef-43b8-464b-acee-8c57153016f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696961495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.1696961495
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.761461496
Short name T47
Test name
Test status
Simulation time 15043200 ps
CPU time 14.32 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:32:27 PM PDT 24
Peak memory 269052 kb
Host smart-14ca9476-919e-4943-8336-e9e65f1c9a3d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=761461496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.761461496
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4281241326
Short name T264
Test name
Test status
Simulation time 1463909800 ps
CPU time 899.84 seconds
Started Jun 06 01:30:53 PM PDT 24
Finished Jun 06 01:45:55 PM PDT 24
Peak memory 263944 kb
Host smart-59d403d4-e08a-403d-ad4d-cdb662caf209
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281241326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.4281241326
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.2304006571
Short name T318
Test name
Test status
Simulation time 7124349000 ps
CPU time 623.36 seconds
Started Jun 06 01:33:56 PM PDT 24
Finished Jun 06 01:44:20 PM PDT 24
Peak memory 324924 kb
Host smart-25d02d85-aafe-4eec-bcfc-1a649d71dce6
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304006571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.flash_ctrl_rw.2304006571
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.3240905484
Short name T107
Test name
Test status
Simulation time 20396057000 ps
CPU time 171.93 seconds
Started Jun 06 01:32:12 PM PDT 24
Finished Jun 06 01:35:06 PM PDT 24
Peak memory 265140 kb
Host smart-92a5eb97-ab46-4880-8bc9-9eaa32c5ac88
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240905484 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.3240905484
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1346869966
Short name T185
Test name
Test status
Simulation time 133194700 ps
CPU time 17.59 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:31:26 PM PDT 24
Peak memory 263340 kb
Host smart-9af5cee5-2f49-4da5-bcfb-ac2e181b1b83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346869966 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.1346869966
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.1697305408
Short name T211
Test name
Test status
Simulation time 823662800 ps
CPU time 109.63 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:38:05 PM PDT 24
Peak memory 290976 kb
Host smart-f80dc789-b2bc-4b08-a528-e2f70bd8f379
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697305408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.1697305408
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.1667874728
Short name T4
Test name
Test status
Simulation time 3440822400 ps
CPU time 69.2 seconds
Started Jun 06 01:33:40 PM PDT 24
Finished Jun 06 01:34:50 PM PDT 24
Peak memory 265004 kb
Host smart-be37759d-dfce-4e5c-a04e-8ae6ce819411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667874728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.1667874728
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2186317133
Short name T425
Test name
Test status
Simulation time 46337500 ps
CPU time 13.34 seconds
Started Jun 06 01:33:53 PM PDT 24
Finished Jun 06 01:34:08 PM PDT 24
Peak memory 264632 kb
Host smart-bf09f334-5226-4331-b98b-0b0fa70e1c02
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186317133 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2186317133
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3021959040
Short name T354
Test name
Test status
Simulation time 641842800 ps
CPU time 457.29 seconds
Started Jun 06 01:30:38 PM PDT 24
Finished Jun 06 01:38:17 PM PDT 24
Peak memory 262212 kb
Host smart-ac521b05-71df-4eb3-91e2-2c57191d4db1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021959040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.3021959040
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.3389139448
Short name T553
Test name
Test status
Simulation time 45966000 ps
CPU time 13.71 seconds
Started Jun 06 01:33:46 PM PDT 24
Finished Jun 06 01:34:01 PM PDT 24
Peak memory 258992 kb
Host smart-ea45c3fa-5075-45ca-80da-11f545bc5470
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389139448 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.3389139448
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.63410211
Short name T93
Test name
Test status
Simulation time 19758500 ps
CPU time 13.99 seconds
Started Jun 06 01:36:51 PM PDT 24
Finished Jun 06 01:37:06 PM PDT 24
Peak memory 274572 kb
Host smart-dd713f1d-c98f-49ed-a98f-7d51de7e7454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63410211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.63410211
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.2776166170
Short name T63
Test name
Test status
Simulation time 616998200 ps
CPU time 18.97 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:32:31 PM PDT 24
Peak memory 262888 kb
Host smart-35f483e9-ddfd-4ec4-a4d4-bf7236bba573
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776166170 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.2776166170
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2129265813
Short name T258
Test name
Test status
Simulation time 133856200 ps
CPU time 21.22 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:31:29 PM PDT 24
Peak memory 263884 kb
Host smart-590180aa-61fd-47d7-b92d-8067ef9b13bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129265813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
2129265813
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3154140606
Short name T856
Test name
Test status
Simulation time 10012952800 ps
CPU time 106.57 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 01:33:44 PM PDT 24
Peak memory 291776 kb
Host smart-7e7ec0ed-52d7-4fe9-814f-f8c1618bcd7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154140606 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.3154140606
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.3657511175
Short name T284
Test name
Test status
Simulation time 47923600 ps
CPU time 13.59 seconds
Started Jun 06 01:31:57 PM PDT 24
Finished Jun 06 01:32:12 PM PDT 24
Peak memory 258288 kb
Host smart-f6d17e7a-87db-47fb-a352-89fc6235453f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657511175 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.3657511175
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.3118014981
Short name T26
Test name
Test status
Simulation time 10011727100 ps
CPU time 337.45 seconds
Started Jun 06 01:33:53 PM PDT 24
Finished Jun 06 01:39:32 PM PDT 24
Peak memory 339260 kb
Host smart-f3f60f9f-b1e5-4d8c-a27e-aaa2338381fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118014981 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.3118014981
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.1970013315
Short name T217
Test name
Test status
Simulation time 4879531700 ps
CPU time 669.22 seconds
Started Jun 06 01:34:36 PM PDT 24
Finished Jun 06 01:45:46 PM PDT 24
Peak memory 309536 kb
Host smart-2aec14c6-0e03-4220-a3f4-21e8098d5e83
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970013315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.flash_ctrl_rw.1970013315
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.4037929503
Short name T340
Test name
Test status
Simulation time 71777938800 ps
CPU time 329.13 seconds
Started Jun 06 01:35:21 PM PDT 24
Finished Jun 06 01:40:50 PM PDT 24
Peak memory 291404 kb
Host smart-e495bd32-98c9-4b14-87ab-308d69f108cd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037929503 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.4037929503
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.1832457036
Short name T957
Test name
Test status
Simulation time 7880354100 ps
CPU time 74.21 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:36:54 PM PDT 24
Peak memory 259320 kb
Host smart-76ad8eb3-a161-432f-b9e9-e05ffd14de0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832457036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.1832457036
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.3796994282
Short name T105
Test name
Test status
Simulation time 232821876300 ps
CPU time 3480.45 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 02:30:24 PM PDT 24
Peak memory 264516 kb
Host smart-ad5dc904-5dbe-477c-bcdf-52e27a0801a2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796994282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.3796994282
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.3765165399
Short name T196
Test name
Test status
Simulation time 3669866200 ps
CPU time 587.11 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:41:59 PM PDT 24
Peak memory 330220 kb
Host smart-22975a42-e8bf-4317-ae18-f3b0f8b7c9ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765165399 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_rw_derr.3765165399
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.3981173395
Short name T119
Test name
Test status
Simulation time 1489531700 ps
CPU time 98.49 seconds
Started Jun 06 01:34:01 PM PDT 24
Finished Jun 06 01:35:40 PM PDT 24
Peak memory 262916 kb
Host smart-f0ca2f04-d830-4ec0-bc57-0ea7293753d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981173395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.3981173395
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.2224034053
Short name T80
Test name
Test status
Simulation time 10071900 ps
CPU time 22.07 seconds
Started Jun 06 01:35:20 PM PDT 24
Finished Jun 06 01:35:43 PM PDT 24
Peak memory 273496 kb
Host smart-4bb83788-d15b-4050-bdbb-3412b970e980
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224034053 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.2224034053
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.3965969245
Short name T11
Test name
Test status
Simulation time 23224600 ps
CPU time 13.89 seconds
Started Jun 06 01:32:05 PM PDT 24
Finished Jun 06 01:32:20 PM PDT 24
Peak memory 265300 kb
Host smart-0578b583-72e5-489f-913a-440d1fbb7d89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965969245 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3965969245
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.3333939184
Short name T1084
Test name
Test status
Simulation time 198239800 ps
CPU time 35.04 seconds
Started Jun 06 01:34:01 PM PDT 24
Finished Jun 06 01:34:36 PM PDT 24
Peak memory 275056 kb
Host smart-326e8be1-f492-4030-89f8-37ea8c681cff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333939184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.3333939184
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.3208758354
Short name T123
Test name
Test status
Simulation time 907111400 ps
CPU time 22.86 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:32:44 PM PDT 24
Peak memory 265344 kb
Host smart-e6952d88-4242-4275-8f3c-87e6b8fa0761
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208758354 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.3208758354
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.702038475
Short name T1032
Test name
Test status
Simulation time 15676700 ps
CPU time 13.83 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 01:32:12 PM PDT 24
Peak memory 259516 kb
Host smart-88d8fe73-144a-4c94-a032-faaf8fd214bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702038475 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.702038475
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3984329490
Short name T1106
Test name
Test status
Simulation time 24462200 ps
CPU time 13.5 seconds
Started Jun 06 01:30:31 PM PDT 24
Finished Jun 06 01:30:46 PM PDT 24
Peak memory 261228 kb
Host smart-66079208-217b-4a13-bade-67b434cb388b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984329490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.3
984329490
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.3595521710
Short name T250
Test name
Test status
Simulation time 21823200 ps
CPU time 14.04 seconds
Started Jun 06 01:31:58 PM PDT 24
Finished Jun 06 01:32:13 PM PDT 24
Peak memory 264576 kb
Host smart-fa825837-8438-489a-8939-1b8621592a6a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595521710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.3595521710
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.4100273395
Short name T361
Test name
Test status
Simulation time 21483700 ps
CPU time 22.24 seconds
Started Jun 06 01:31:45 PM PDT 24
Finished Jun 06 01:32:08 PM PDT 24
Peak memory 265348 kb
Host smart-3fc3b12d-b441-4364-9ced-db91931c0245
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100273395 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.4100273395
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.3686720192
Short name T408
Test name
Test status
Simulation time 423013700 ps
CPU time 60.21 seconds
Started Jun 06 01:32:01 PM PDT 24
Finished Jun 06 01:33:02 PM PDT 24
Peak memory 263472 kb
Host smart-a17ef522-9a3c-493f-a0c6-341e3c6d6688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686720192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3686720192
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.3487040003
Short name T684
Test name
Test status
Simulation time 19938500 ps
CPU time 20.84 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 01:32:19 PM PDT 24
Peak memory 273404 kb
Host smart-5fc30ca8-eac9-4f49-85e2-f9d6f9c24cb0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487040003 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.3487040003
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.80325161
Short name T89
Test name
Test status
Simulation time 12786189400 ps
CPU time 414.53 seconds
Started Jun 06 01:31:59 PM PDT 24
Finished Jun 06 01:38:54 PM PDT 24
Peak memory 273596 kb
Host smart-afc48d30-5228-4582-b5fe-a3b61594e7d7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80325161 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_mp_regions.80325161
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.908275391
Short name T377
Test name
Test status
Simulation time 10152403200 ps
CPU time 67.25 seconds
Started Jun 06 01:33:56 PM PDT 24
Finished Jun 06 01:35:04 PM PDT 24
Peak memory 263416 kb
Host smart-56b2d85f-a2b9-4824-8474-02105a5b499f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908275391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.908275391
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.290826541
Short name T68
Test name
Test status
Simulation time 48535600 ps
CPU time 21.6 seconds
Started Jun 06 01:33:57 PM PDT 24
Finished Jun 06 01:34:20 PM PDT 24
Peak memory 273476 kb
Host smart-168fc1bd-ea60-431e-9d84-4714c8715f31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290826541 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.290826541
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.2531795824
Short name T398
Test name
Test status
Simulation time 48392400 ps
CPU time 22.29 seconds
Started Jun 06 01:35:06 PM PDT 24
Finished Jun 06 01:35:30 PM PDT 24
Peak memory 273544 kb
Host smart-aee56d38-7eb7-467b-84b2-856dd1939a73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531795824 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_disable.2531795824
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.601828560
Short name T898
Test name
Test status
Simulation time 3177098100 ps
CPU time 78.41 seconds
Started Jun 06 01:35:27 PM PDT 24
Finished Jun 06 01:36:46 PM PDT 24
Peak memory 263280 kb
Host smart-26d51e1b-c8d9-4089-b48b-97c7da6ab8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601828560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.601828560
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.1369393045
Short name T404
Test name
Test status
Simulation time 2673908600 ps
CPU time 68.59 seconds
Started Jun 06 01:32:30 PM PDT 24
Finished Jun 06 01:33:40 PM PDT 24
Peak memory 263368 kb
Host smart-8cf67ee5-6997-4ad3-926d-440e656f3a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369393045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1369393045
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.2341313406
Short name T392
Test name
Test status
Simulation time 20281200 ps
CPU time 20.57 seconds
Started Jun 06 01:36:07 PM PDT 24
Finished Jun 06 01:36:28 PM PDT 24
Peak memory 264644 kb
Host smart-4023c9fa-74cb-4656-ace9-155eb5f289fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341313406 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.2341313406
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.3914133105
Short name T376
Test name
Test status
Simulation time 1292186700 ps
CPU time 71.43 seconds
Started Jun 06 01:32:18 PM PDT 24
Finished Jun 06 01:33:31 PM PDT 24
Peak memory 264944 kb
Host smart-39dc0896-6df8-48ae-b270-3497fa9ccfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914133105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.3914133105
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.494246603
Short name T214
Test name
Test status
Simulation time 32511400 ps
CPU time 15.74 seconds
Started Jun 06 01:31:08 PM PDT 24
Finished Jun 06 01:31:25 PM PDT 24
Peak memory 263864 kb
Host smart-a8e95241-a390-4d41-b155-6932ac19a871
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494246603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.494246603
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.1335310187
Short name T627
Test name
Test status
Simulation time 14468858300 ps
CPU time 64.43 seconds
Started Jun 06 01:31:46 PM PDT 24
Finished Jun 06 01:32:52 PM PDT 24
Peak memory 259660 kb
Host smart-c67e08e2-b614-455c-a97b-3e1cb7827e48
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335310187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.1335310187
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.3996937070
Short name T120
Test name
Test status
Simulation time 677329400 ps
CPU time 17.14 seconds
Started Jun 06 01:31:55 PM PDT 24
Finished Jun 06 01:32:15 PM PDT 24
Peak memory 262836 kb
Host smart-5b9932bc-cd41-42b5-951d-3bd607cf1202
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996937070 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.3996937070
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.254064309
Short name T197
Test name
Test status
Simulation time 1246097100 ps
CPU time 159.13 seconds
Started Jun 06 01:31:49 PM PDT 24
Finished Jun 06 01:34:29 PM PDT 24
Peak memory 282772 kb
Host smart-9fc5f91a-fe71-4a22-b325-46164a473146
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
254064309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.254064309
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.1662641858
Short name T139
Test name
Test status
Simulation time 40121973100 ps
CPU time 816.37 seconds
Started Jun 06 01:33:54 PM PDT 24
Finished Jun 06 01:47:31 PM PDT 24
Peak memory 264020 kb
Host smart-464d09a1-9a35-4bf7-bed1-a1c529677546
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662641858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.1662641858
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.1963417616
Short name T6
Test name
Test status
Simulation time 7653151600 ps
CPU time 2389.25 seconds
Started Jun 06 01:32:37 PM PDT 24
Finished Jun 06 02:12:28 PM PDT 24
Peak memory 262548 kb
Host smart-971a29d7-7ee3-4a8c-8935-d2d4134ad4e2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963417616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.1963417616
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2020550130
Short name T229
Test name
Test status
Simulation time 57357600 ps
CPU time 16.46 seconds
Started Jun 06 01:31:21 PM PDT 24
Finished Jun 06 01:31:39 PM PDT 24
Peak memory 263884 kb
Host smart-dbf59b40-2f41-4928-b218-c6424343cead
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020550130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
2020550130
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.3530588980
Short name T176
Test name
Test status
Simulation time 34162981100 ps
CPU time 183.75 seconds
Started Jun 06 01:31:47 PM PDT 24
Finished Jun 06 01:34:51 PM PDT 24
Peak memory 294796 kb
Host smart-78e0e3e5-327d-46d1-bade-7493f02f410f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530588980 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.3530588980
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.947655329
Short name T435
Test name
Test status
Simulation time 103724600 ps
CPU time 37.38 seconds
Started Jun 06 01:34:29 PM PDT 24
Finished Jun 06 01:35:07 PM PDT 24
Peak memory 275552 kb
Host smart-f70bda33-1899-4468-8308-2e7d039f6652
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947655329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_re_evict.947655329
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.3139784966
Short name T272
Test name
Test status
Simulation time 96832100 ps
CPU time 32.31 seconds
Started Jun 06 01:34:38 PM PDT 24
Finished Jun 06 01:35:11 PM PDT 24
Peak memory 275204 kb
Host smart-d9213242-4fd3-4d42-978e-974fe92864b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139784966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.3139784966
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_derr.2777296846
Short name T198
Test name
Test status
Simulation time 7375835300 ps
CPU time 599.85 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:42:37 PM PDT 24
Peak memory 335336 kb
Host smart-bf521f09-0125-4942-8eef-c7f17d854981
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777296846 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_rw_derr.2777296846
Directory /workspace/7.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2181587991
Short name T266
Test name
Test status
Simulation time 24405600 ps
CPU time 17.57 seconds
Started Jun 06 01:31:05 PM PDT 24
Finished Jun 06 01:31:23 PM PDT 24
Peak memory 277244 kb
Host smart-b255c3fe-b34a-41ee-8eb2-ac73fa5fce42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181587991 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.2181587991
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.1940766607
Short name T201
Test name
Test status
Simulation time 985385643900 ps
CPU time 2407.59 seconds
Started Jun 06 01:32:05 PM PDT 24
Finished Jun 06 02:12:13 PM PDT 24
Peak memory 263876 kb
Host smart-16ffcfc8-24cc-4f84-957f-1c367096f8e2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940766607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.1940766607
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.680451023
Short name T87
Test name
Test status
Simulation time 13177772800 ps
CPU time 417.12 seconds
Started Jun 06 01:31:50 PM PDT 24
Finished Jun 06 01:38:48 PM PDT 24
Peak memory 273812 kb
Host smart-18437ef1-a0bd-48f8-956e-356db527c373
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680451023 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_mp_regions.680451023
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.3164626931
Short name T10
Test name
Test status
Simulation time 167061100 ps
CPU time 15.51 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 01:32:14 PM PDT 24
Peak memory 260564 kb
Host smart-f46684b8-7e45-461c-b490-297ea0909515
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164626931 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.3164626931
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.2993553581
Short name T122
Test name
Test status
Simulation time 840683800 ps
CPU time 15.06 seconds
Started Jun 06 01:32:09 PM PDT 24
Finished Jun 06 01:32:26 PM PDT 24
Peak memory 265488 kb
Host smart-872252d0-f5c5-4235-aa2d-fe38f031fed9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993553581 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.2993553581
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.2732745596
Short name T276
Test name
Test status
Simulation time 1418333400 ps
CPU time 127.05 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:34:28 PM PDT 24
Peak memory 262432 kb
Host smart-0e9a728c-7d5a-43a7-9419-12fd880ac43d
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2732745596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.2732745596
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.457846772
Short name T151
Test name
Test status
Simulation time 273056270200 ps
CPU time 2760.35 seconds
Started Jun 06 01:32:21 PM PDT 24
Finished Jun 06 02:18:23 PM PDT 24
Peak memory 264884 kb
Host smart-98cf5613-09d8-466a-97fc-8c1e62f7969a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457846772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.flash_ctrl_host_ctrl_arb.457846772
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.3541015377
Short name T202
Test name
Test status
Simulation time 959921800 ps
CPU time 135.78 seconds
Started Jun 06 01:33:07 PM PDT 24
Finished Jun 06 01:35:23 PM PDT 24
Peak memory 282860 kb
Host smart-74189cbd-8714-4227-a349-a205c5787c40
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3541015377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.3541015377
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1467228177
Short name T1224
Test name
Test status
Simulation time 1842652900 ps
CPU time 68.49 seconds
Started Jun 06 01:30:31 PM PDT 24
Finished Jun 06 01:31:41 PM PDT 24
Peak memory 261056 kb
Host smart-fde7fdd9-d0e0-4126-8cce-6ce2837a108a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467228177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.1467228177
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2812255002
Short name T1222
Test name
Test status
Simulation time 6084596600 ps
CPU time 80.4 seconds
Started Jun 06 01:30:34 PM PDT 24
Finished Jun 06 01:31:56 PM PDT 24
Peak memory 262448 kb
Host smart-f09ef528-60d4-430e-8307-11ebafeaef69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812255002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.2812255002
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.4118147885
Short name T301
Test name
Test status
Simulation time 57257200 ps
CPU time 30.17 seconds
Started Jun 06 01:30:31 PM PDT 24
Finished Jun 06 01:31:02 PM PDT 24
Peak memory 263892 kb
Host smart-25ed62d9-47d8-42d7-8132-578769544704
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118147885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.4118147885
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3122159933
Short name T65
Test name
Test status
Simulation time 258553600 ps
CPU time 17.28 seconds
Started Jun 06 01:30:34 PM PDT 24
Finished Jun 06 01:30:53 PM PDT 24
Peak memory 263832 kb
Host smart-df52b278-1bc9-40bc-8b34-7ad0efbf654a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122159933 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3122159933
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.21348601
Short name T300
Test name
Test status
Simulation time 39949300 ps
CPU time 16.73 seconds
Started Jun 06 01:30:32 PM PDT 24
Finished Jun 06 01:30:50 PM PDT 24
Peak memory 261080 kb
Host smart-2eafe661-ff65-4aa9-809f-1ba8aeddc3c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21348601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_csr_rw.21348601
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.630730754
Short name T235
Test name
Test status
Simulation time 26172600 ps
CPU time 13.7 seconds
Started Jun 06 01:30:32 PM PDT 24
Finished Jun 06 01:30:48 PM PDT 24
Peak memory 262108 kb
Host smart-2f2e157b-e032-4ed6-9a18-4bc8e91bcd50
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630730754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_mem_partial_access.630730754
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1796685305
Short name T1163
Test name
Test status
Simulation time 54464100 ps
CPU time 13.76 seconds
Started Jun 06 01:30:31 PM PDT 24
Finished Jun 06 01:30:47 PM PDT 24
Peak memory 261088 kb
Host smart-d9eb0134-19f5-47d3-8f3a-e1c6a46eecf1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796685305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.1796685305
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3689442405
Short name T1210
Test name
Test status
Simulation time 87219700 ps
CPU time 15.75 seconds
Started Jun 06 01:30:33 PM PDT 24
Finished Jun 06 01:30:51 PM PDT 24
Peak memory 263944 kb
Host smart-29ba6d9b-0c96-4f58-b0e8-fd973afb37d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689442405 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.3689442405
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2132525278
Short name T1112
Test name
Test status
Simulation time 19818600 ps
CPU time 15.8 seconds
Started Jun 06 01:30:32 PM PDT 24
Finished Jun 06 01:30:49 PM PDT 24
Peak memory 252976 kb
Host smart-e74721c1-9a77-46e4-ad96-2ec1adea9c7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132525278 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.2132525278
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2698051462
Short name T1175
Test name
Test status
Simulation time 23910100 ps
CPU time 13.34 seconds
Started Jun 06 01:30:33 PM PDT 24
Finished Jun 06 01:30:48 PM PDT 24
Peak memory 252956 kb
Host smart-75496665-a90b-446f-9cbe-8f23f98dd3ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698051462 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.2698051462
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2746948774
Short name T215
Test name
Test status
Simulation time 56557100 ps
CPU time 18.68 seconds
Started Jun 06 01:30:32 PM PDT 24
Finished Jun 06 01:30:53 PM PDT 24
Peak memory 263868 kb
Host smart-dfd94009-7fa7-427e-9471-dd5e81168eee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746948774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.2
746948774
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1475056689
Short name T348
Test name
Test status
Simulation time 699998700 ps
CPU time 460.44 seconds
Started Jun 06 01:30:31 PM PDT 24
Finished Jun 06 01:38:14 PM PDT 24
Peak memory 262160 kb
Host smart-e3ba94e0-d66e-43cf-a946-94d2b5acba1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475056689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.1475056689
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1641626347
Short name T299
Test name
Test status
Simulation time 1650644000 ps
CPU time 40.54 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:31:21 PM PDT 24
Peak memory 262492 kb
Host smart-7dc9b186-d5b3-4ecf-bd68-72bec8b00bf7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641626347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.1641626347
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1359380091
Short name T1123
Test name
Test status
Simulation time 1149601900 ps
CPU time 42.36 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:31:22 PM PDT 24
Peak memory 262568 kb
Host smart-a181701c-ec91-465a-a311-94b13cf1e394
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359380091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.1359380091
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.997001901
Short name T1116
Test name
Test status
Simulation time 56247200 ps
CPU time 30.93 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:31:11 PM PDT 24
Peak memory 263916 kb
Host smart-ced5dfdf-ff4c-461d-b9fe-98eeb9797c33
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997001901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.flash_ctrl_csr_hw_reset.997001901
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1950332702
Short name T1190
Test name
Test status
Simulation time 369023900 ps
CPU time 17.11 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:30:57 PM PDT 24
Peak memory 273300 kb
Host smart-24ced4e0-35b0-4994-9750-5d6dbaa1fd22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950332702 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.1950332702
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3345965219
Short name T1221
Test name
Test status
Simulation time 43485100 ps
CPU time 17.21 seconds
Started Jun 06 01:30:46 PM PDT 24
Finished Jun 06 01:31:04 PM PDT 24
Peak memory 263876 kb
Host smart-7fa936e3-4d70-4a3a-95a5-b73008742a0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345965219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.3345965219
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.73258276
Short name T1227
Test name
Test status
Simulation time 31166700 ps
CPU time 13.64 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:30:54 PM PDT 24
Peak memory 261116 kb
Host smart-85ab8e35-adc3-4f71-b447-697c30c791a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73258276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.73258276
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1783541991
Short name T234
Test name
Test status
Simulation time 16907500 ps
CPU time 13.59 seconds
Started Jun 06 01:30:41 PM PDT 24
Finished Jun 06 01:30:55 PM PDT 24
Peak memory 262896 kb
Host smart-7613eeaf-2ea9-4fd0-87c7-eafe4575a53c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783541991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.1783541991
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.712004728
Short name T1164
Test name
Test status
Simulation time 17824700 ps
CPU time 13.48 seconds
Started Jun 06 01:30:41 PM PDT 24
Finished Jun 06 01:30:55 PM PDT 24
Peak memory 261040 kb
Host smart-ee0fe324-8d25-4ad0-bb37-361e17c7b44a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712004728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem
_walk.712004728
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1087538826
Short name T1219
Test name
Test status
Simulation time 248360400 ps
CPU time 29.21 seconds
Started Jun 06 01:30:42 PM PDT 24
Finished Jun 06 01:31:12 PM PDT 24
Peak memory 262880 kb
Host smart-d8b2f9a7-41f9-4dd5-925d-f89944daed40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087538826 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.1087538826
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.390333221
Short name T1192
Test name
Test status
Simulation time 25491100 ps
CPU time 15.45 seconds
Started Jun 06 01:30:32 PM PDT 24
Finished Jun 06 01:30:50 PM PDT 24
Peak memory 252884 kb
Host smart-01a1e1c4-9286-44e1-bd1e-5479fb0b9b34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390333221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.390333221
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3903254146
Short name T1197
Test name
Test status
Simulation time 18930500 ps
CPU time 15.75 seconds
Started Jun 06 01:30:33 PM PDT 24
Finished Jun 06 01:30:50 PM PDT 24
Peak memory 252932 kb
Host smart-6a5fe817-8af6-4da2-90e9-7f237036d0eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903254146 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.3903254146
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.104953022
Short name T1193
Test name
Test status
Simulation time 54381400 ps
CPU time 19.33 seconds
Started Jun 06 01:30:34 PM PDT 24
Finished Jun 06 01:30:55 PM PDT 24
Peak memory 263868 kb
Host smart-0da20c2c-922d-4d27-a384-fcb5aa0fe3ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104953022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.104953022
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2291358892
Short name T358
Test name
Test status
Simulation time 330873500 ps
CPU time 382.66 seconds
Started Jun 06 01:30:33 PM PDT 24
Finished Jun 06 01:36:57 PM PDT 24
Peak memory 263888 kb
Host smart-1c0d839d-041d-4b9b-b709-4d6f3ea4f8bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291358892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.2291358892
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.370386117
Short name T312
Test name
Test status
Simulation time 131978300 ps
CPU time 17.84 seconds
Started Jun 06 01:30:53 PM PDT 24
Finished Jun 06 01:31:13 PM PDT 24
Peak memory 272128 kb
Host smart-55e43cc1-942e-4635-ba76-3e0bd4610414
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370386117 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.370386117
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2760216414
Short name T1208
Test name
Test status
Simulation time 21453300 ps
CPU time 13.51 seconds
Started Jun 06 01:30:53 PM PDT 24
Finished Jun 06 01:31:08 PM PDT 24
Peak memory 261136 kb
Host smart-0ccb9703-4f18-4f76-aa59-a8040a735845
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760216414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
2760216414
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3830970460
Short name T1115
Test name
Test status
Simulation time 85999200 ps
CPU time 17.7 seconds
Started Jun 06 01:31:08 PM PDT 24
Finished Jun 06 01:31:27 PM PDT 24
Peak memory 262928 kb
Host smart-6b6d61b9-9aac-40e1-8975-f6eb7adc0079
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830970460 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.3830970460
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3493766508
Short name T1103
Test name
Test status
Simulation time 30063900 ps
CPU time 15.7 seconds
Started Jun 06 01:30:50 PM PDT 24
Finished Jun 06 01:31:07 PM PDT 24
Peak memory 252892 kb
Host smart-babca1fb-3873-4570-a4d5-f06153d59fb2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493766508 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.3493766508
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2543363019
Short name T1133
Test name
Test status
Simulation time 43733100 ps
CPU time 13.17 seconds
Started Jun 06 01:30:52 PM PDT 24
Finished Jun 06 01:31:07 PM PDT 24
Peak memory 252892 kb
Host smart-24d31fcd-7b8f-4871-8354-3615f71f9445
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543363019 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.2543363019
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1121918197
Short name T257
Test name
Test status
Simulation time 59938400 ps
CPU time 15.8 seconds
Started Jun 06 01:30:50 PM PDT 24
Finished Jun 06 01:31:06 PM PDT 24
Peak memory 264012 kb
Host smart-3b1e6d4d-da9b-46cc-8d41-060341919a9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121918197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
1121918197
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1279543171
Short name T353
Test name
Test status
Simulation time 767038300 ps
CPU time 915.82 seconds
Started Jun 06 01:30:52 PM PDT 24
Finished Jun 06 01:46:10 PM PDT 24
Peak memory 263848 kb
Host smart-88f5670e-4ff8-40d4-8180-bd76216ba6db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279543171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.1279543171
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1268268973
Short name T305
Test name
Test status
Simulation time 174511200 ps
CPU time 18.95 seconds
Started Jun 06 01:30:54 PM PDT 24
Finished Jun 06 01:31:15 PM PDT 24
Peak memory 272300 kb
Host smart-aae0d37d-5e3c-4f07-a48f-ce0e3667f524
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268268973 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.1268268973
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1315479594
Short name T1159
Test name
Test status
Simulation time 248331300 ps
CPU time 17.45 seconds
Started Jun 06 01:30:57 PM PDT 24
Finished Jun 06 01:31:16 PM PDT 24
Peak memory 263900 kb
Host smart-8fe7d609-33e2-494c-b3f9-37ee6f600589
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315479594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.1315479594
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.3042215236
Short name T1232
Test name
Test status
Simulation time 17867400 ps
CPU time 13.54 seconds
Started Jun 06 01:30:53 PM PDT 24
Finished Jun 06 01:31:09 PM PDT 24
Peak memory 261168 kb
Host smart-990b2b81-b1ea-4b20-b97b-3485409e91f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042215236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
3042215236
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.586716148
Short name T302
Test name
Test status
Simulation time 229881400 ps
CPU time 30.59 seconds
Started Jun 06 01:30:54 PM PDT 24
Finished Jun 06 01:31:27 PM PDT 24
Peak memory 262468 kb
Host smart-8c7f24e5-d4e2-4890-8b3c-69c5e92621d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586716148 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.586716148
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.371123385
Short name T1173
Test name
Test status
Simulation time 24955300 ps
CPU time 16.37 seconds
Started Jun 06 01:31:06 PM PDT 24
Finished Jun 06 01:31:23 PM PDT 24
Peak memory 252880 kb
Host smart-bf2684e5-8413-4b01-831a-9a681dea831f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371123385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.371123385
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3849341402
Short name T1160
Test name
Test status
Simulation time 52195100 ps
CPU time 15.68 seconds
Started Jun 06 01:30:53 PM PDT 24
Finished Jun 06 01:31:10 PM PDT 24
Peak memory 252944 kb
Host smart-724345b1-29b3-42de-ba41-27d539895bbb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849341402 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.3849341402
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1382205104
Short name T255
Test name
Test status
Simulation time 89289400 ps
CPU time 16.34 seconds
Started Jun 06 01:30:56 PM PDT 24
Finished Jun 06 01:31:14 PM PDT 24
Peak memory 263860 kb
Host smart-16c47b20-2234-419c-a9be-56a34aa8da84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382205104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
1382205104
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.775807214
Short name T350
Test name
Test status
Simulation time 2728446600 ps
CPU time 891.58 seconds
Started Jun 06 01:30:53 PM PDT 24
Finished Jun 06 01:45:47 PM PDT 24
Peak memory 263928 kb
Host smart-304e1e43-9a4e-4dcc-8038-763c410d71a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775807214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl
_tl_intg_err.775807214
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1555769852
Short name T1140
Test name
Test status
Simulation time 316504500 ps
CPU time 19.2 seconds
Started Jun 06 01:30:56 PM PDT 24
Finished Jun 06 01:31:17 PM PDT 24
Peak memory 271276 kb
Host smart-5d4f1dff-3c61-4273-a639-ba5435a8891b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555769852 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.1555769852
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1349341835
Short name T1206
Test name
Test status
Simulation time 63585800 ps
CPU time 14.94 seconds
Started Jun 06 01:30:52 PM PDT 24
Finished Jun 06 01:31:08 PM PDT 24
Peak memory 263956 kb
Host smart-2c239832-cc75-4ad9-a0cf-b2d212dc2096
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349341835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.1349341835
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3832217369
Short name T326
Test name
Test status
Simulation time 45261300 ps
CPU time 13.35 seconds
Started Jun 06 01:30:54 PM PDT 24
Finished Jun 06 01:31:09 PM PDT 24
Peak memory 261156 kb
Host smart-6a0af485-2afc-4765-898d-0a8a65eaad2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832217369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
3832217369
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3719265374
Short name T1109
Test name
Test status
Simulation time 178129100 ps
CPU time 31.38 seconds
Started Jun 06 01:30:49 PM PDT 24
Finished Jun 06 01:31:21 PM PDT 24
Peak memory 262300 kb
Host smart-61eb9e34-19e9-4f68-a888-bea231796ac8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719265374 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.3719265374
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3483558294
Short name T1161
Test name
Test status
Simulation time 18409200 ps
CPU time 13.31 seconds
Started Jun 06 01:30:51 PM PDT 24
Finished Jun 06 01:31:05 PM PDT 24
Peak memory 252948 kb
Host smart-2f0ca3c3-edb2-48e5-bed6-208e7f55aec4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483558294 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.3483558294
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2194608977
Short name T1203
Test name
Test status
Simulation time 12170100 ps
CPU time 15.7 seconds
Started Jun 06 01:30:52 PM PDT 24
Finished Jun 06 01:31:09 PM PDT 24
Peak memory 252932 kb
Host smart-c51ea12d-e955-4121-9cea-0b759c0af0d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194608977 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.2194608977
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1449175988
Short name T1151
Test name
Test status
Simulation time 34529500 ps
CPU time 16.07 seconds
Started Jun 06 01:30:57 PM PDT 24
Finished Jun 06 01:31:14 PM PDT 24
Peak memory 263864 kb
Host smart-01fd0f35-7a32-4304-a76c-d70afe42f074
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449175988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
1449175988
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.330868200
Short name T1143
Test name
Test status
Simulation time 19421000 ps
CPU time 16.47 seconds
Started Jun 06 01:31:08 PM PDT 24
Finished Jun 06 01:31:26 PM PDT 24
Peak memory 260976 kb
Host smart-a08085bc-61e7-4f1a-97fa-3719318c3a0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330868200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.flash_ctrl_csr_rw.330868200
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.229981079
Short name T1147
Test name
Test status
Simulation time 30889700 ps
CPU time 13.48 seconds
Started Jun 06 01:31:11 PM PDT 24
Finished Jun 06 01:31:26 PM PDT 24
Peak memory 261076 kb
Host smart-d5b5eef9-bed9-445c-bb2f-0f5ad79dfe5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229981079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.229981079
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.376828699
Short name T252
Test name
Test status
Simulation time 335706100 ps
CPU time 15.78 seconds
Started Jun 06 01:31:03 PM PDT 24
Finished Jun 06 01:31:20 PM PDT 24
Peak memory 262724 kb
Host smart-60e7972e-8a1e-4b6a-8ea3-eb5c8664964c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376828699 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.376828699
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3026375346
Short name T1108
Test name
Test status
Simulation time 12885600 ps
CPU time 15.66 seconds
Started Jun 06 01:31:12 PM PDT 24
Finished Jun 06 01:31:28 PM PDT 24
Peak memory 252780 kb
Host smart-8de155c3-e3f6-4431-be73-541fde0955da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026375346 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.3026375346
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.520114868
Short name T1191
Test name
Test status
Simulation time 13662000 ps
CPU time 15.66 seconds
Started Jun 06 01:31:04 PM PDT 24
Finished Jun 06 01:31:20 PM PDT 24
Peak memory 252956 kb
Host smart-121dfeeb-473b-41d6-b08a-5820e6c64ecd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520114868 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.520114868
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1719913271
Short name T352
Test name
Test status
Simulation time 2329412700 ps
CPU time 463.79 seconds
Started Jun 06 01:30:52 PM PDT 24
Finished Jun 06 01:38:37 PM PDT 24
Peak memory 261140 kb
Host smart-09f17238-627c-48ff-9b68-7298d175b927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719913271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.1719913271
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1532511944
Short name T246
Test name
Test status
Simulation time 177930000 ps
CPU time 17.43 seconds
Started Jun 06 01:31:06 PM PDT 24
Finished Jun 06 01:31:24 PM PDT 24
Peak memory 263852 kb
Host smart-ec685f83-06c8-4d35-8c9f-e50f0d5987c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532511944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.1532511944
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.2987020677
Short name T1207
Test name
Test status
Simulation time 15480600 ps
CPU time 13.57 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:31:22 PM PDT 24
Peak memory 261124 kb
Host smart-652cf90c-a254-4805-b462-72ee520e0572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987020677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.
2987020677
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.343309870
Short name T306
Test name
Test status
Simulation time 228606400 ps
CPU time 16.07 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:31:24 PM PDT 24
Peak memory 263152 kb
Host smart-7cbb64f2-f9f6-4916-99bc-610bee2561a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343309870 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.343309870
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2730876090
Short name T1242
Test name
Test status
Simulation time 111122600 ps
CPU time 13.45 seconds
Started Jun 06 01:31:16 PM PDT 24
Finished Jun 06 01:31:30 PM PDT 24
Peak memory 252908 kb
Host smart-193a8b41-1566-4d42-ab8c-7018e93f8196
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730876090 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.2730876090
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3074465945
Short name T1117
Test name
Test status
Simulation time 37007300 ps
CPU time 15.38 seconds
Started Jun 06 01:31:11 PM PDT 24
Finished Jun 06 01:31:28 PM PDT 24
Peak memory 252944 kb
Host smart-fa62a08c-de4e-4c71-aaef-5df920d9861e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074465945 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.3074465945
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.151001252
Short name T349
Test name
Test status
Simulation time 183867500 ps
CPU time 454.7 seconds
Started Jun 06 01:31:05 PM PDT 24
Finished Jun 06 01:38:41 PM PDT 24
Peak memory 262092 kb
Host smart-1270b1b0-3d4b-4d7e-b220-69acc32a1f8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151001252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl
_tl_intg_err.151001252
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1952702994
Short name T1225
Test name
Test status
Simulation time 82286800 ps
CPU time 18.48 seconds
Started Jun 06 01:31:11 PM PDT 24
Finished Jun 06 01:31:31 PM PDT 24
Peak memory 272148 kb
Host smart-9eb0214f-e2bf-4d98-9b10-071cab630755
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952702994 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.1952702994
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2671444097
Short name T1235
Test name
Test status
Simulation time 71408500 ps
CPU time 15.03 seconds
Started Jun 06 01:31:08 PM PDT 24
Finished Jun 06 01:31:24 PM PDT 24
Peak memory 261072 kb
Host smart-77434965-5d75-4594-9cc5-83c9a8eef01f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671444097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.2671444097
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3682282923
Short name T1104
Test name
Test status
Simulation time 46841000 ps
CPU time 13.47 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:31:22 PM PDT 24
Peak memory 261184 kb
Host smart-2dc92d0e-df27-4e3f-bedf-d6ce4b8d8e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682282923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
3682282923
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2124774105
Short name T1128
Test name
Test status
Simulation time 608769800 ps
CPU time 34.78 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:31:43 PM PDT 24
Peak memory 263808 kb
Host smart-fb49eb12-e44d-4005-be96-8af5776d4bf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124774105 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.2124774105
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2750130065
Short name T1113
Test name
Test status
Simulation time 60965100 ps
CPU time 13.36 seconds
Started Jun 06 01:31:08 PM PDT 24
Finished Jun 06 01:31:23 PM PDT 24
Peak memory 252904 kb
Host smart-26817d9f-3cf8-4e36-adcb-fe51670429ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750130065 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.2750130065
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1681065865
Short name T1127
Test name
Test status
Simulation time 34408300 ps
CPU time 15.62 seconds
Started Jun 06 01:31:06 PM PDT 24
Finished Jun 06 01:31:22 PM PDT 24
Peak memory 252928 kb
Host smart-01bf95b2-c042-43d5-9786-f6ea4922e8bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681065865 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.1681065865
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3095782127
Short name T256
Test name
Test status
Simulation time 195507600 ps
CPU time 17.11 seconds
Started Jun 06 01:31:06 PM PDT 24
Finished Jun 06 01:31:23 PM PDT 24
Peak memory 263916 kb
Host smart-2b85f6fe-4e44-4aab-adae-b5b91fab15da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095782127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
3095782127
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1719735756
Short name T297
Test name
Test status
Simulation time 807802400 ps
CPU time 457.41 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:38:45 PM PDT 24
Peak memory 263860 kb
Host smart-496b74fe-bc23-48fb-9ad8-6b6fb47f3f37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719735756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.1719735756
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.497902368
Short name T230
Test name
Test status
Simulation time 47372100 ps
CPU time 17.62 seconds
Started Jun 06 01:31:11 PM PDT 24
Finished Jun 06 01:31:30 PM PDT 24
Peak memory 264096 kb
Host smart-93f43bf3-ae13-4e3d-8189-8e4743ba7f2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497902368 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.497902368
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1715650787
Short name T1158
Test name
Test status
Simulation time 38631700 ps
CPU time 16.62 seconds
Started Jun 06 01:31:11 PM PDT 24
Finished Jun 06 01:31:28 PM PDT 24
Peak memory 261132 kb
Host smart-f0428793-01b1-4418-9d43-f6df8ab0a1ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715650787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.1715650787
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.875330164
Short name T244
Test name
Test status
Simulation time 115269500 ps
CPU time 19.69 seconds
Started Jun 06 01:31:10 PM PDT 24
Finished Jun 06 01:31:31 PM PDT 24
Peak memory 261332 kb
Host smart-b2a33b99-cb8c-4544-8d66-294e51a94283
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875330164 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.875330164
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.72617767
Short name T1156
Test name
Test status
Simulation time 44677300 ps
CPU time 15.89 seconds
Started Jun 06 01:31:09 PM PDT 24
Finished Jun 06 01:31:26 PM PDT 24
Peak memory 252884 kb
Host smart-7e6225e7-eddb-47b8-a6b1-da968b1227e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72617767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.72617767
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3065494745
Short name T1099
Test name
Test status
Simulation time 21708200 ps
CPU time 15.63 seconds
Started Jun 06 01:31:05 PM PDT 24
Finished Jun 06 01:31:21 PM PDT 24
Peak memory 252948 kb
Host smart-9b7f5516-3f74-4a14-bd92-24ee90c7fad1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065494745 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.3065494745
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2002863223
Short name T1205
Test name
Test status
Simulation time 49160500 ps
CPU time 18.19 seconds
Started Jun 06 01:31:06 PM PDT 24
Finished Jun 06 01:31:25 PM PDT 24
Peak memory 263828 kb
Host smart-2c258b91-b04d-4ff1-8e9c-63af36320f10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002863223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
2002863223
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.4043363021
Short name T249
Test name
Test status
Simulation time 179543000 ps
CPU time 383.69 seconds
Started Jun 06 01:31:05 PM PDT 24
Finished Jun 06 01:37:29 PM PDT 24
Peak memory 263896 kb
Host smart-00e2e6f2-c657-4383-9df6-84187e32628a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043363021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr
l_tl_intg_err.4043363021
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1404849701
Short name T1220
Test name
Test status
Simulation time 73431300 ps
CPU time 15.68 seconds
Started Jun 06 01:31:11 PM PDT 24
Finished Jun 06 01:31:28 PM PDT 24
Peak memory 272128 kb
Host smart-5ab687ce-46e6-4d00-9151-9aa208ea6ec8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404849701 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1404849701
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1132390424
Short name T1150
Test name
Test status
Simulation time 67916800 ps
CPU time 16.54 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:31:25 PM PDT 24
Peak memory 261128 kb
Host smart-e9b84018-4933-4a3f-a1f1-c274381097ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132390424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.1132390424
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3048997813
Short name T1130
Test name
Test status
Simulation time 54055700 ps
CPU time 13.25 seconds
Started Jun 06 01:31:12 PM PDT 24
Finished Jun 06 01:31:26 PM PDT 24
Peak memory 261164 kb
Host smart-6350cdc9-6776-4767-a33e-609f4352fc3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048997813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.
3048997813
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.555561858
Short name T1157
Test name
Test status
Simulation time 62739800 ps
CPU time 16.98 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:31:26 PM PDT 24
Peak memory 263056 kb
Host smart-3c773ae8-a547-42c7-b7cd-7346ba40b9c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555561858 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.555561858
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3205158258
Short name T1144
Test name
Test status
Simulation time 14469800 ps
CPU time 15.43 seconds
Started Jun 06 01:31:11 PM PDT 24
Finished Jun 06 01:31:28 PM PDT 24
Peak memory 252932 kb
Host smart-49ae18c2-7424-4d00-b8aa-7b2a8d5dc4c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205158258 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.3205158258
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.150665319
Short name T1167
Test name
Test status
Simulation time 22037300 ps
CPU time 15.73 seconds
Started Jun 06 01:31:06 PM PDT 24
Finished Jun 06 01:31:23 PM PDT 24
Peak memory 252876 kb
Host smart-a0226ba1-ebb3-4ef7-920b-cf1314574670
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150665319 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.150665319
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3468677811
Short name T265
Test name
Test status
Simulation time 409027400 ps
CPU time 466.36 seconds
Started Jun 06 01:31:06 PM PDT 24
Finished Jun 06 01:38:53 PM PDT 24
Peak memory 263876 kb
Host smart-793ebb24-771e-4ba3-9ad8-35db427ff29b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468677811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.3468677811
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1885883046
Short name T1126
Test name
Test status
Simulation time 316564400 ps
CPU time 19.24 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:31:28 PM PDT 24
Peak memory 272148 kb
Host smart-bc87c37f-47e1-45b7-8fb3-4860fa96113d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885883046 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.1885883046
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2774596439
Short name T1228
Test name
Test status
Simulation time 47970000 ps
CPU time 15.35 seconds
Started Jun 06 01:31:09 PM PDT 24
Finished Jun 06 01:31:26 PM PDT 24
Peak memory 261272 kb
Host smart-30524973-d1f0-4028-808c-af133fc8d1ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774596439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.2774596439
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2159258005
Short name T1177
Test name
Test status
Simulation time 25504700 ps
CPU time 13.28 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:31:22 PM PDT 24
Peak memory 261152 kb
Host smart-a9c1db7d-bf73-4a47-9aa8-98d2c9bd9158
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159258005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
2159258005
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.871501342
Short name T1149
Test name
Test status
Simulation time 117698000 ps
CPU time 35.16 seconds
Started Jun 06 01:31:10 PM PDT 24
Finished Jun 06 01:31:47 PM PDT 24
Peak memory 263808 kb
Host smart-43183a9d-d9f3-4ee2-8e1c-e567d4da3ef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871501342 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.871501342
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.349308801
Short name T1131
Test name
Test status
Simulation time 14160000 ps
CPU time 15.66 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:31:23 PM PDT 24
Peak memory 252908 kb
Host smart-b43992be-f38f-4eaf-afe1-a32ab242439d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349308801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.349308801
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2371332789
Short name T1139
Test name
Test status
Simulation time 48047900 ps
CPU time 15.86 seconds
Started Jun 06 01:31:10 PM PDT 24
Finished Jun 06 01:31:27 PM PDT 24
Peak memory 252928 kb
Host smart-4744031c-b485-45ba-bdc2-7e519ac0bffd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371332789 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.2371332789
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3758464483
Short name T263
Test name
Test status
Simulation time 455658800 ps
CPU time 457.35 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:38:45 PM PDT 24
Peak memory 263928 kb
Host smart-f0408b05-b21b-4f99-965f-aad975b87801
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758464483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.3758464483
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1837446841
Short name T1169
Test name
Test status
Simulation time 58775700 ps
CPU time 14.71 seconds
Started Jun 06 01:31:08 PM PDT 24
Finished Jun 06 01:31:24 PM PDT 24
Peak memory 270280 kb
Host smart-7c22be1c-2831-45ae-9114-55a4aef00bf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837446841 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.1837446841
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3902001213
Short name T1178
Test name
Test status
Simulation time 111016300 ps
CPU time 16.62 seconds
Started Jun 06 01:31:05 PM PDT 24
Finished Jun 06 01:31:22 PM PDT 24
Peak memory 261092 kb
Host smart-044a9a20-e924-456b-811d-4bbfb2283fd0
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902001213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.3902001213
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1474005904
Short name T328
Test name
Test status
Simulation time 30773300 ps
CPU time 13.51 seconds
Started Jun 06 01:31:08 PM PDT 24
Finished Jun 06 01:31:23 PM PDT 24
Peak memory 261092 kb
Host smart-33962d57-839c-4f03-9810-4c00a2775f6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474005904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
1474005904
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.507066707
Short name T1171
Test name
Test status
Simulation time 152798100 ps
CPU time 17.77 seconds
Started Jun 06 01:31:07 PM PDT 24
Finished Jun 06 01:31:26 PM PDT 24
Peak memory 262892 kb
Host smart-aa518820-bc5b-4c8c-89bd-4ae504c90a77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507066707 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.507066707
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2735494831
Short name T1121
Test name
Test status
Simulation time 30533100 ps
CPU time 15.69 seconds
Started Jun 06 01:31:12 PM PDT 24
Finished Jun 06 01:31:28 PM PDT 24
Peak memory 252844 kb
Host smart-c775c4d5-8d90-4262-8006-13cdb0b1f7f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735494831 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.2735494831
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3890835426
Short name T1146
Test name
Test status
Simulation time 12980400 ps
CPU time 15.77 seconds
Started Jun 06 01:31:09 PM PDT 24
Finished Jun 06 01:31:26 PM PDT 24
Peak memory 252932 kb
Host smart-ac17b77b-5516-41c4-b34b-a7368ccc2f24
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890835426 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.3890835426
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2235488127
Short name T262
Test name
Test status
Simulation time 321817500 ps
CPU time 19.33 seconds
Started Jun 06 01:31:10 PM PDT 24
Finished Jun 06 01:31:30 PM PDT 24
Peak memory 263872 kb
Host smart-16184809-d9cb-42ce-a0a4-d465f74af01c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235488127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
2235488127
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3301595074
Short name T1226
Test name
Test status
Simulation time 859583700 ps
CPU time 47.69 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:31:28 PM PDT 24
Peak memory 261088 kb
Host smart-cd8c90e1-0cc4-4eae-b46e-1ff63ee570e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301595074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.3301595074
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4243348992
Short name T295
Test name
Test status
Simulation time 5690264500 ps
CPU time 73.66 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:31:54 PM PDT 24
Peak memory 262792 kb
Host smart-7130c648-fd17-4108-8a19-5a2ff86fbc78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243348992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.4243348992
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.935673048
Short name T296
Test name
Test status
Simulation time 47686500 ps
CPU time 45.86 seconds
Started Jun 06 01:30:38 PM PDT 24
Finished Jun 06 01:31:25 PM PDT 24
Peak memory 263876 kb
Host smart-831d21a2-89ab-4562-8445-61dd63f8ec3e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935673048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.flash_ctrl_csr_hw_reset.935673048
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1338975533
Short name T1196
Test name
Test status
Simulation time 96422400 ps
CPU time 15.38 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:30:56 PM PDT 24
Peak memory 272140 kb
Host smart-9b37ce62-b851-48ac-920d-5623c80d7b66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338975533 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.1338975533
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3579997714
Short name T1135
Test name
Test status
Simulation time 93822000 ps
CPU time 14.76 seconds
Started Jun 06 01:30:38 PM PDT 24
Finished Jun 06 01:30:54 PM PDT 24
Peak memory 261088 kb
Host smart-87272b76-67c0-4078-a28f-5344ce3ea246
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579997714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.3579997714
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.4129737536
Short name T1200
Test name
Test status
Simulation time 53386400 ps
CPU time 13.82 seconds
Started Jun 06 01:30:41 PM PDT 24
Finished Jun 06 01:30:56 PM PDT 24
Peak memory 261052 kb
Host smart-2fbbd36c-67e1-4468-80c7-d018590c199c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129737536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.4
129737536
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.222832822
Short name T1102
Test name
Test status
Simulation time 28986400 ps
CPU time 13.32 seconds
Started Jun 06 01:30:48 PM PDT 24
Finished Jun 06 01:31:02 PM PDT 24
Peak memory 261080 kb
Host smart-3565254a-073d-4464-bd5d-cb7732ad57af
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222832822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem
_walk.222832822
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1139592451
Short name T1195
Test name
Test status
Simulation time 381614300 ps
CPU time 19.56 seconds
Started Jun 06 01:30:48 PM PDT 24
Finished Jun 06 01:31:09 PM PDT 24
Peak memory 263824 kb
Host smart-3b148bb0-0dd5-483b-998c-ec81ea97e47a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139592451 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.1139592451
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1692228394
Short name T1100
Test name
Test status
Simulation time 18667600 ps
CPU time 15.67 seconds
Started Jun 06 01:30:37 PM PDT 24
Finished Jun 06 01:30:54 PM PDT 24
Peak memory 252816 kb
Host smart-99bcedcf-02ca-4ac5-8609-5c60da4c6600
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692228394 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.1692228394
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.841907437
Short name T1213
Test name
Test status
Simulation time 22948600 ps
CPU time 15.63 seconds
Started Jun 06 01:30:37 PM PDT 24
Finished Jun 06 01:30:54 PM PDT 24
Peak memory 252924 kb
Host smart-62d27595-a3bc-455d-8beb-d38286d82f4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841907437 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.841907437
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1737867043
Short name T260
Test name
Test status
Simulation time 103255400 ps
CPU time 18.59 seconds
Started Jun 06 01:31:04 PM PDT 24
Finished Jun 06 01:31:23 PM PDT 24
Peak memory 263888 kb
Host smart-7e7d70d8-277a-42f9-a206-0289b8681295
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737867043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.1
737867043
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2910725067
Short name T1141
Test name
Test status
Simulation time 47373900 ps
CPU time 13.58 seconds
Started Jun 06 01:31:06 PM PDT 24
Finished Jun 06 01:31:20 PM PDT 24
Peak memory 261168 kb
Host smart-adda51b8-d4cb-4afe-a252-5196767c2c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910725067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
2910725067
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2805160830
Short name T1120
Test name
Test status
Simulation time 82655000 ps
CPU time 13.4 seconds
Started Jun 06 01:31:14 PM PDT 24
Finished Jun 06 01:31:28 PM PDT 24
Peak memory 261160 kb
Host smart-09c34300-ec2c-4d5e-986a-4f77af7ad226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805160830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
2805160830
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2005639592
Short name T1142
Test name
Test status
Simulation time 220661500 ps
CPU time 13.62 seconds
Started Jun 06 01:31:09 PM PDT 24
Finished Jun 06 01:31:24 PM PDT 24
Peak memory 261220 kb
Host smart-5e7b17e2-1ea4-4fe8-9798-1947d1e889d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005639592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
2005639592
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1549728193
Short name T1217
Test name
Test status
Simulation time 17957800 ps
CPU time 13.41 seconds
Started Jun 06 01:31:08 PM PDT 24
Finished Jun 06 01:31:23 PM PDT 24
Peak memory 261060 kb
Host smart-da4bde23-11bb-4cd3-a8c3-9209775092ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549728193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
1549728193
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3576207599
Short name T1187
Test name
Test status
Simulation time 92807100 ps
CPU time 13.9 seconds
Started Jun 06 01:31:09 PM PDT 24
Finished Jun 06 01:31:24 PM PDT 24
Peak memory 261120 kb
Host smart-52c11af7-dced-4089-849a-4ff23e439e4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576207599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
3576207599
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1730507998
Short name T1238
Test name
Test status
Simulation time 45746700 ps
CPU time 13.67 seconds
Started Jun 06 01:31:09 PM PDT 24
Finished Jun 06 01:31:24 PM PDT 24
Peak memory 261280 kb
Host smart-8fecee6d-5b27-4b2a-863e-984e79f5ddad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730507998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
1730507998
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.4099839646
Short name T1176
Test name
Test status
Simulation time 78145500 ps
CPU time 13.36 seconds
Started Jun 06 01:31:08 PM PDT 24
Finished Jun 06 01:31:23 PM PDT 24
Peak memory 261156 kb
Host smart-cf1907c6-0900-4af4-8363-465e12525c6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099839646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
4099839646
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.419334302
Short name T1105
Test name
Test status
Simulation time 96283100 ps
CPU time 13.55 seconds
Started Jun 06 01:31:17 PM PDT 24
Finished Jun 06 01:31:32 PM PDT 24
Peak memory 261120 kb
Host smart-abd43546-6017-4e60-ad76-b9d166ffb344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419334302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.419334302
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2989649198
Short name T1138
Test name
Test status
Simulation time 52611000 ps
CPU time 13.36 seconds
Started Jun 06 01:31:17 PM PDT 24
Finished Jun 06 01:31:31 PM PDT 24
Peak memory 261172 kb
Host smart-30297643-bc63-4846-a69f-a8136febae8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989649198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
2989649198
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.832640450
Short name T251
Test name
Test status
Simulation time 5001695900 ps
CPU time 65.45 seconds
Started Jun 06 01:30:41 PM PDT 24
Finished Jun 06 01:31:48 PM PDT 24
Peak memory 261116 kb
Host smart-c23c164f-3057-4019-84c4-5d70e0268d02
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832640450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.flash_ctrl_csr_aliasing.832640450
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1385399971
Short name T1188
Test name
Test status
Simulation time 11605118800 ps
CPU time 47.43 seconds
Started Jun 06 01:30:37 PM PDT 24
Finished Jun 06 01:31:25 PM PDT 24
Peak memory 262572 kb
Host smart-1e4dee9c-d983-4c7e-a616-62c3696a08f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385399971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.1385399971
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3832144560
Short name T67
Test name
Test status
Simulation time 31408600 ps
CPU time 31.14 seconds
Started Jun 06 01:30:57 PM PDT 24
Finished Jun 06 01:31:29 PM PDT 24
Peak memory 263904 kb
Host smart-de03417e-3c0a-4f3d-8170-b53755c08c0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832144560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.3832144560
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.59478727
Short name T1229
Test name
Test status
Simulation time 105243800 ps
CPU time 18.15 seconds
Started Jun 06 01:30:42 PM PDT 24
Finished Jun 06 01:31:01 PM PDT 24
Peak memory 271320 kb
Host smart-ca4bd0d7-13a6-4008-9675-c7c9200da3fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59478727 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.59478727
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2565064422
Short name T1148
Test name
Test status
Simulation time 20641900 ps
CPU time 16.33 seconds
Started Jun 06 01:30:38 PM PDT 24
Finished Jun 06 01:30:55 PM PDT 24
Peak memory 261112 kb
Host smart-f8a431f2-9fd1-420c-ac3f-f7158dfe94f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565064422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.2565064422
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.472505266
Short name T1236
Test name
Test status
Simulation time 61811000 ps
CPU time 13.39 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:30:53 PM PDT 24
Peak memory 261024 kb
Host smart-bca6f294-187a-4087-a87c-1edb7a657805
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472505266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.472505266
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3622530747
Short name T233
Test name
Test status
Simulation time 239420000 ps
CPU time 13.81 seconds
Started Jun 06 01:30:38 PM PDT 24
Finished Jun 06 01:30:53 PM PDT 24
Peak memory 262756 kb
Host smart-c999f22f-0219-4701-a7f3-421b35d63330
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622530747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.3622530747
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2862491172
Short name T1137
Test name
Test status
Simulation time 15840900 ps
CPU time 13.35 seconds
Started Jun 06 01:30:48 PM PDT 24
Finished Jun 06 01:31:02 PM PDT 24
Peak memory 261068 kb
Host smart-364c20cf-4168-4382-8343-3d369414f4f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862491172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.2862491172
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1926958895
Short name T1214
Test name
Test status
Simulation time 789043200 ps
CPU time 21.83 seconds
Started Jun 06 01:30:43 PM PDT 24
Finished Jun 06 01:31:05 PM PDT 24
Peak memory 263804 kb
Host smart-c6747585-fc62-4879-914a-5d547c2e80fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926958895 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.1926958895
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2326498454
Short name T1223
Test name
Test status
Simulation time 25485300 ps
CPU time 15.84 seconds
Started Jun 06 01:30:44 PM PDT 24
Finished Jun 06 01:31:00 PM PDT 24
Peak memory 252916 kb
Host smart-dcadad13-33dc-45c0-a16a-16518d1e6fb5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326498454 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.2326498454
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3666195222
Short name T1152
Test name
Test status
Simulation time 165860700 ps
CPU time 16.01 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:30:56 PM PDT 24
Peak memory 252964 kb
Host smart-97499e5a-be26-425b-a506-7037d33db2ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666195222 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.3666195222
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.4076304273
Short name T1174
Test name
Test status
Simulation time 44379700 ps
CPU time 16.08 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:30:56 PM PDT 24
Peak memory 263800 kb
Host smart-d5386eb5-835a-4776-ab71-e31229aa6685
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076304273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.4
076304273
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1161027869
Short name T357
Test name
Test status
Simulation time 1240969600 ps
CPU time 897.17 seconds
Started Jun 06 01:30:42 PM PDT 24
Finished Jun 06 01:45:40 PM PDT 24
Peak memory 263824 kb
Host smart-38922cb4-92db-4692-8de8-d985a0288274
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161027869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.1161027869
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3273469322
Short name T1194
Test name
Test status
Simulation time 14793100 ps
CPU time 13.72 seconds
Started Jun 06 01:31:17 PM PDT 24
Finished Jun 06 01:31:32 PM PDT 24
Peak memory 261152 kb
Host smart-effbac7c-4cd8-4520-9c96-62a9ff8d72ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273469322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
3273469322
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.4030693325
Short name T1114
Test name
Test status
Simulation time 89066600 ps
CPU time 13.51 seconds
Started Jun 06 01:31:17 PM PDT 24
Finished Jun 06 01:31:31 PM PDT 24
Peak memory 261216 kb
Host smart-6f5b5cb0-abfd-421d-b413-a0b3cbab49c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030693325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
4030693325
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.732605066
Short name T1154
Test name
Test status
Simulation time 24657300 ps
CPU time 13.58 seconds
Started Jun 06 01:31:16 PM PDT 24
Finished Jun 06 01:31:30 PM PDT 24
Peak memory 261084 kb
Host smart-d660622c-67a7-456e-b93b-335fa7fabe9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732605066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.732605066
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1960127871
Short name T327
Test name
Test status
Simulation time 229750600 ps
CPU time 13.65 seconds
Started Jun 06 01:31:18 PM PDT 24
Finished Jun 06 01:31:34 PM PDT 24
Peak memory 261132 kb
Host smart-36143517-69e0-4f9b-98b5-d19e30edbfa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960127871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
1960127871
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.966878794
Short name T1180
Test name
Test status
Simulation time 61309300 ps
CPU time 13.8 seconds
Started Jun 06 01:31:22 PM PDT 24
Finished Jun 06 01:31:39 PM PDT 24
Peak memory 261092 kb
Host smart-6c6a4388-04a5-45d4-adc7-ead34133dd7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966878794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.966878794
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1341449215
Short name T329
Test name
Test status
Simulation time 269055900 ps
CPU time 13.46 seconds
Started Jun 06 01:31:20 PM PDT 24
Finished Jun 06 01:31:35 PM PDT 24
Peak memory 261140 kb
Host smart-3e72102e-4e5e-4aa4-b663-b06179596889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341449215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
1341449215
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1137215205
Short name T1165
Test name
Test status
Simulation time 27056600 ps
CPU time 13.31 seconds
Started Jun 06 01:31:19 PM PDT 24
Finished Jun 06 01:31:34 PM PDT 24
Peak memory 261232 kb
Host smart-83d91230-dabb-4041-8dbe-f86fd50ee52f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137215205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
1137215205
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.470526945
Short name T1185
Test name
Test status
Simulation time 25869700 ps
CPU time 13.69 seconds
Started Jun 06 01:31:17 PM PDT 24
Finished Jun 06 01:31:32 PM PDT 24
Peak memory 261164 kb
Host smart-a2bd48c5-cba4-4599-a7e0-dbf9cb01f4a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470526945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.470526945
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2589915854
Short name T1184
Test name
Test status
Simulation time 144374000 ps
CPU time 13.22 seconds
Started Jun 06 01:31:15 PM PDT 24
Finished Jun 06 01:31:29 PM PDT 24
Peak memory 261148 kb
Host smart-4f7b401a-25f3-4580-bb0c-69fd73d4848c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589915854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
2589915854
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3015115632
Short name T1239
Test name
Test status
Simulation time 14404100 ps
CPU time 13.75 seconds
Started Jun 06 01:31:16 PM PDT 24
Finished Jun 06 01:31:30 PM PDT 24
Peak memory 261148 kb
Host smart-e49dbe6f-22ee-4040-8b18-5cea40b77608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015115632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
3015115632
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2447608341
Short name T360
Test name
Test status
Simulation time 9798147800 ps
CPU time 66.91 seconds
Started Jun 06 01:30:40 PM PDT 24
Finished Jun 06 01:31:49 PM PDT 24
Peak memory 261108 kb
Host smart-8735c19c-a6aa-4aee-8b5a-a32dcaf150a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447608341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.2447608341
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1986035282
Short name T303
Test name
Test status
Simulation time 6604409400 ps
CPU time 51.41 seconds
Started Jun 06 01:30:40 PM PDT 24
Finished Jun 06 01:31:32 PM PDT 24
Peak memory 262940 kb
Host smart-6342a1d8-0907-4822-b6de-9442df758fbd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986035282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.1986035282
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1217822831
Short name T1153
Test name
Test status
Simulation time 76171900 ps
CPU time 38.51 seconds
Started Jun 06 01:30:42 PM PDT 24
Finished Jun 06 01:31:22 PM PDT 24
Peak memory 263880 kb
Host smart-0081f13b-b801-422e-8162-ed358c7fdae5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217822831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.1217822831
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1875976954
Short name T1182
Test name
Test status
Simulation time 116627000 ps
CPU time 15.18 seconds
Started Jun 06 01:30:48 PM PDT 24
Finished Jun 06 01:31:04 PM PDT 24
Peak memory 263912 kb
Host smart-85f98abe-895a-4b4e-9c60-d9fc051897b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875976954 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1875976954
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3033812589
Short name T1183
Test name
Test status
Simulation time 55393500 ps
CPU time 14.73 seconds
Started Jun 06 01:30:41 PM PDT 24
Finished Jun 06 01:30:57 PM PDT 24
Peak memory 261128 kb
Host smart-4190aa3c-ffef-41d4-8f85-ff0fcb8abf37
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033812589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.3033812589
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3990366880
Short name T1110
Test name
Test status
Simulation time 34703400 ps
CPU time 13.56 seconds
Started Jun 06 01:30:47 PM PDT 24
Finished Jun 06 01:31:01 PM PDT 24
Peak memory 261164 kb
Host smart-034a1b1a-d544-4694-a752-ea658cbac2d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990366880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.3
990366880
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.252150999
Short name T236
Test name
Test status
Simulation time 18117800 ps
CPU time 13.51 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:30:54 PM PDT 24
Peak memory 261892 kb
Host smart-e3056a1b-a6bc-45fb-8b3a-b10be6255caa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252150999 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_mem_partial_access.252150999
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2487707296
Short name T1162
Test name
Test status
Simulation time 51205900 ps
CPU time 13.38 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:30:53 PM PDT 24
Peak memory 261192 kb
Host smart-b4c7b447-9ae6-497a-85af-f641686974c2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487707296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.2487707296
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3390099736
Short name T1122
Test name
Test status
Simulation time 380607500 ps
CPU time 30.08 seconds
Started Jun 06 01:30:48 PM PDT 24
Finished Jun 06 01:31:19 PM PDT 24
Peak memory 263400 kb
Host smart-f7dfa315-0d6c-4e9b-8876-52a8d5ea1d08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390099736 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.3390099736
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.464152573
Short name T1211
Test name
Test status
Simulation time 24752800 ps
CPU time 15.67 seconds
Started Jun 06 01:30:39 PM PDT 24
Finished Jun 06 01:30:56 PM PDT 24
Peak memory 252960 kb
Host smart-3a473cdc-ad8b-419b-8cf9-415e554ce193
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464152573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.464152573
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.77298678
Short name T1241
Test name
Test status
Simulation time 13114000 ps
CPU time 13.15 seconds
Started Jun 06 01:30:42 PM PDT 24
Finished Jun 06 01:30:56 PM PDT 24
Peak memory 252912 kb
Host smart-dd0f16c4-06de-4355-891f-0d10d1bed064
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77298678 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.77298678
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1428357722
Short name T228
Test name
Test status
Simulation time 207425400 ps
CPU time 18.68 seconds
Started Jun 06 01:30:42 PM PDT 24
Finished Jun 06 01:31:01 PM PDT 24
Peak memory 263888 kb
Host smart-00e83fa9-2d0f-46b9-9dbd-4331bc7a7b41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428357722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.1
428357722
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2661436008
Short name T1186
Test name
Test status
Simulation time 30310300 ps
CPU time 13.58 seconds
Started Jun 06 01:31:16 PM PDT 24
Finished Jun 06 01:31:30 PM PDT 24
Peak memory 261172 kb
Host smart-ec7f16dc-7151-4362-b1ee-589523588764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661436008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
2661436008
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.592404327
Short name T1199
Test name
Test status
Simulation time 34187300 ps
CPU time 13.58 seconds
Started Jun 06 01:31:16 PM PDT 24
Finished Jun 06 01:31:30 PM PDT 24
Peak memory 261144 kb
Host smart-a7169714-9786-4678-8018-8f0ef6b68de1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592404327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.592404327
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.851019766
Short name T253
Test name
Test status
Simulation time 29396900 ps
CPU time 13.85 seconds
Started Jun 06 01:31:13 PM PDT 24
Finished Jun 06 01:31:28 PM PDT 24
Peak memory 261084 kb
Host smart-d96b9d75-396a-465f-a07f-fcec63d509a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851019766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.851019766
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.325754356
Short name T1166
Test name
Test status
Simulation time 17537800 ps
CPU time 13.31 seconds
Started Jun 06 01:31:16 PM PDT 24
Finished Jun 06 01:31:30 PM PDT 24
Peak memory 261172 kb
Host smart-884203a6-9b3a-4295-ac70-54b0a8dc6244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325754356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.325754356
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2269880230
Short name T1170
Test name
Test status
Simulation time 17133500 ps
CPU time 13.88 seconds
Started Jun 06 01:31:20 PM PDT 24
Finished Jun 06 01:31:35 PM PDT 24
Peak memory 261164 kb
Host smart-2d85f932-c97f-4317-ad93-0de35d46c5f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269880230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
2269880230
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3359961397
Short name T1118
Test name
Test status
Simulation time 31278600 ps
CPU time 13.41 seconds
Started Jun 06 01:31:27 PM PDT 24
Finished Jun 06 01:31:42 PM PDT 24
Peak memory 261072 kb
Host smart-16dfb652-94af-4c15-b3e4-2d75e78194da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359961397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
3359961397
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3063699341
Short name T1237
Test name
Test status
Simulation time 40018600 ps
CPU time 13.37 seconds
Started Jun 06 01:31:16 PM PDT 24
Finished Jun 06 01:31:30 PM PDT 24
Peak memory 261140 kb
Host smart-09cf15a0-7a76-4b4f-905f-5ad3f3804b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063699341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
3063699341
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4275149875
Short name T1202
Test name
Test status
Simulation time 32459400 ps
CPU time 13.53 seconds
Started Jun 06 01:31:17 PM PDT 24
Finished Jun 06 01:31:31 PM PDT 24
Peak memory 261100 kb
Host smart-6d041e8c-001c-4377-96cc-9be415019d41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275149875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
4275149875
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3929889512
Short name T1132
Test name
Test status
Simulation time 24384100 ps
CPU time 14.25 seconds
Started Jun 06 01:31:18 PM PDT 24
Finished Jun 06 01:31:34 PM PDT 24
Peak memory 261164 kb
Host smart-1d4472f6-5ae1-407e-9ebb-afa544ef9eb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929889512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
3929889512
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3373075359
Short name T1215
Test name
Test status
Simulation time 16037100 ps
CPU time 13.34 seconds
Started Jun 06 01:31:17 PM PDT 24
Finished Jun 06 01:31:31 PM PDT 24
Peak memory 261168 kb
Host smart-d5fc1bba-cbd2-4e1f-a4d6-1827542a21ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373075359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
3373075359
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3072195121
Short name T184
Test name
Test status
Simulation time 185528300 ps
CPU time 17.39 seconds
Started Jun 06 01:30:50 PM PDT 24
Finished Jun 06 01:31:08 PM PDT 24
Peak memory 276324 kb
Host smart-76518782-b52a-45ae-912b-20cd350a3ccf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072195121 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.3072195121
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1919216539
Short name T1234
Test name
Test status
Simulation time 118414300 ps
CPU time 16.33 seconds
Started Jun 06 01:30:52 PM PDT 24
Finished Jun 06 01:31:09 PM PDT 24
Peak memory 261144 kb
Host smart-19afd5ec-015b-4340-bcf6-84b1114b928c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919216539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.1919216539
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.4092949758
Short name T1209
Test name
Test status
Simulation time 16838900 ps
CPU time 13.87 seconds
Started Jun 06 01:30:50 PM PDT 24
Finished Jun 06 01:31:05 PM PDT 24
Peak memory 261048 kb
Host smart-d1a261e4-b81b-4e61-a5d6-f8a94afa40f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092949758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.4
092949758
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2313579617
Short name T1212
Test name
Test status
Simulation time 133128900 ps
CPU time 18.18 seconds
Started Jun 06 01:30:51 PM PDT 24
Finished Jun 06 01:31:10 PM PDT 24
Peak memory 263764 kb
Host smart-8a40b5f2-eacc-4fb3-b1a4-6652a2497ddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313579617 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.2313579617
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1038412157
Short name T1155
Test name
Test status
Simulation time 14214300 ps
CPU time 13.21 seconds
Started Jun 06 01:30:44 PM PDT 24
Finished Jun 06 01:30:58 PM PDT 24
Peak memory 252828 kb
Host smart-5422a64e-2c15-412c-a056-b831afc2a0cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038412157 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.1038412157
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2792785255
Short name T1168
Test name
Test status
Simulation time 84403200 ps
CPU time 15.71 seconds
Started Jun 06 01:30:51 PM PDT 24
Finished Jun 06 01:31:07 PM PDT 24
Peak memory 252924 kb
Host smart-04eb31a3-b70b-41c3-95bf-8d435d1feb4b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792785255 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.2792785255
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1903539645
Short name T261
Test name
Test status
Simulation time 35657600 ps
CPU time 16.57 seconds
Started Jun 06 01:30:41 PM PDT 24
Finished Jun 06 01:30:59 PM PDT 24
Peak memory 263196 kb
Host smart-97b5b4a4-f03e-4b26-a425-f0546a6b1894
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903539645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.1
903539645
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.279006050
Short name T356
Test name
Test status
Simulation time 1281512500 ps
CPU time 457.9 seconds
Started Jun 06 01:30:40 PM PDT 24
Finished Jun 06 01:38:19 PM PDT 24
Peak memory 263924 kb
Host smart-fae92af4-e14b-4e26-9a98-f3453255485a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279006050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_
tl_intg_err.279006050
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.425532255
Short name T1145
Test name
Test status
Simulation time 46762700 ps
CPU time 17.42 seconds
Started Jun 06 01:30:50 PM PDT 24
Finished Jun 06 01:31:09 PM PDT 24
Peak memory 263936 kb
Host smart-d18efc23-f5b9-438b-877e-b29d2e0470d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425532255 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.425532255
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3092696731
Short name T245
Test name
Test status
Simulation time 58643900 ps
CPU time 16.4 seconds
Started Jun 06 01:30:50 PM PDT 24
Finished Jun 06 01:31:08 PM PDT 24
Peak memory 261120 kb
Host smart-305fae88-4b8f-4190-9fec-f7f476f5b205
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092696731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.3092696731
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.562873419
Short name T331
Test name
Test status
Simulation time 16575700 ps
CPU time 13.69 seconds
Started Jun 06 01:30:50 PM PDT 24
Finished Jun 06 01:31:04 PM PDT 24
Peak memory 261152 kb
Host smart-c5f70d2e-0206-4bf4-9796-56b1d81d18f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562873419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.562873419
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.165954865
Short name T243
Test name
Test status
Simulation time 1372189800 ps
CPU time 35.9 seconds
Started Jun 06 01:30:55 PM PDT 24
Finished Jun 06 01:31:32 PM PDT 24
Peak memory 263644 kb
Host smart-056f33c2-c596-43ac-9204-dcb82fe265f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165954865 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.165954865
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.731714451
Short name T1101
Test name
Test status
Simulation time 118534100 ps
CPU time 15.5 seconds
Started Jun 06 01:30:51 PM PDT 24
Finished Jun 06 01:31:07 PM PDT 24
Peak memory 252872 kb
Host smart-696d92df-328f-43e1-9798-c9fbbf6df6d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731714451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.731714451
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2780990857
Short name T1204
Test name
Test status
Simulation time 35818300 ps
CPU time 13.18 seconds
Started Jun 06 01:30:49 PM PDT 24
Finished Jun 06 01:31:03 PM PDT 24
Peak memory 252928 kb
Host smart-84f79e25-c27a-4dd4-b8f0-dc30f40861a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780990857 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.2780990857
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.743715947
Short name T1233
Test name
Test status
Simulation time 676262700 ps
CPU time 464.08 seconds
Started Jun 06 01:30:49 PM PDT 24
Finished Jun 06 01:38:34 PM PDT 24
Peak memory 262180 kb
Host smart-12f8441f-fff7-4961-8c9d-3c94305b94ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743715947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_
tl_intg_err.743715947
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2581753193
Short name T1240
Test name
Test status
Simulation time 609888500 ps
CPU time 19.31 seconds
Started Jun 06 01:30:50 PM PDT 24
Finished Jun 06 01:31:11 PM PDT 24
Peak memory 270444 kb
Host smart-5314a4ec-3c1b-4ed4-9566-fd7ee415f555
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581753193 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.2581753193
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1772237284
Short name T1181
Test name
Test status
Simulation time 68773600 ps
CPU time 17.44 seconds
Started Jun 06 01:30:53 PM PDT 24
Finished Jun 06 01:31:13 PM PDT 24
Peak memory 263928 kb
Host smart-92895f7c-c051-458c-8799-9d96b93416a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772237284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.1772237284
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1042335711
Short name T1136
Test name
Test status
Simulation time 29034400 ps
CPU time 13.6 seconds
Started Jun 06 01:30:52 PM PDT 24
Finished Jun 06 01:31:07 PM PDT 24
Peak memory 261168 kb
Host smart-9885e245-4fa2-4078-b469-deab482abbda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042335711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.1
042335711
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1776586695
Short name T1125
Test name
Test status
Simulation time 3234897500 ps
CPU time 19.68 seconds
Started Jun 06 01:30:50 PM PDT 24
Finished Jun 06 01:31:11 PM PDT 24
Peak memory 261260 kb
Host smart-3bd853c8-beef-4a05-b19b-0ee1389829de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776586695 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.1776586695
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1541052943
Short name T1124
Test name
Test status
Simulation time 58431900 ps
CPU time 15.96 seconds
Started Jun 06 01:30:51 PM PDT 24
Finished Jun 06 01:31:08 PM PDT 24
Peak memory 252944 kb
Host smart-42e63f3c-61e7-40d7-a467-80bdd3d495ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541052943 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.1541052943
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3000381302
Short name T1201
Test name
Test status
Simulation time 22547600 ps
CPU time 13.19 seconds
Started Jun 06 01:30:50 PM PDT 24
Finished Jun 06 01:31:05 PM PDT 24
Peak memory 252920 kb
Host smart-c8903cb2-702c-4cd2-98d4-ed156b808f86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000381302 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.3000381302
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1249891433
Short name T1216
Test name
Test status
Simulation time 34108000 ps
CPU time 16.93 seconds
Started Jun 06 01:30:49 PM PDT 24
Finished Jun 06 01:31:07 PM PDT 24
Peak memory 263900 kb
Host smart-716f5462-1dc2-4de4-98d4-48105ae7b905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249891433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.1
249891433
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2038895151
Short name T351
Test name
Test status
Simulation time 457682100 ps
CPU time 896.25 seconds
Started Jun 06 01:30:50 PM PDT 24
Finished Jun 06 01:45:47 PM PDT 24
Peak memory 262192 kb
Host smart-fa8ea25a-141d-470c-b2e9-ee3f30644e17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038895151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.2038895151
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.177257935
Short name T1179
Test name
Test status
Simulation time 77165800 ps
CPU time 18.83 seconds
Started Jun 06 01:30:55 PM PDT 24
Finished Jun 06 01:31:15 PM PDT 24
Peak memory 272120 kb
Host smart-e5e6722b-43a0-47aa-9471-cf9f84675cbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177257935 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.177257935
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3701031342
Short name T1129
Test name
Test status
Simulation time 54217700 ps
CPU time 17.52 seconds
Started Jun 06 01:30:53 PM PDT 24
Finished Jun 06 01:31:13 PM PDT 24
Peak memory 261116 kb
Host smart-b5ee3e8c-3783-404d-bb2e-21fcba2ba7a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701031342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.3701031342
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.798975724
Short name T1119
Test name
Test status
Simulation time 15335200 ps
CPU time 13.56 seconds
Started Jun 06 01:30:50 PM PDT 24
Finished Jun 06 01:31:05 PM PDT 24
Peak memory 261068 kb
Host smart-c062b695-1a39-4cc8-8e56-97de1cedaf02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798975724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.798975724
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3546772914
Short name T298
Test name
Test status
Simulation time 419516700 ps
CPU time 18.53 seconds
Started Jun 06 01:30:55 PM PDT 24
Finished Jun 06 01:31:15 PM PDT 24
Peak memory 261072 kb
Host smart-b9d08fe4-7660-4d51-9892-78ddddcd1d01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546772914 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.3546772914
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.3070947146
Short name T1172
Test name
Test status
Simulation time 11400400 ps
CPU time 15.98 seconds
Started Jun 06 01:30:53 PM PDT 24
Finished Jun 06 01:31:11 PM PDT 24
Peak memory 253060 kb
Host smart-ecf11778-3ea9-4ae1-b9df-a59d0c148e63
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070947146 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.3070947146
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3241926624
Short name T1231
Test name
Test status
Simulation time 11226400 ps
CPU time 15.93 seconds
Started Jun 06 01:30:51 PM PDT 24
Finished Jun 06 01:31:08 PM PDT 24
Peak memory 252812 kb
Host smart-4b0b8db0-b436-4695-86d6-8d47c8e1eb69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241926624 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.3241926624
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1444893834
Short name T259
Test name
Test status
Simulation time 66014300 ps
CPU time 15.65 seconds
Started Jun 06 01:30:53 PM PDT 24
Finished Jun 06 01:31:10 PM PDT 24
Peak memory 263896 kb
Host smart-dfc0a616-da0f-4456-b666-009729f7b9fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444893834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.1
444893834
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.1533158233
Short name T355
Test name
Test status
Simulation time 8174938300 ps
CPU time 764.66 seconds
Started Jun 06 01:30:55 PM PDT 24
Finished Jun 06 01:43:41 PM PDT 24
Peak memory 264064 kb
Host smart-94ff3159-187e-4ecd-aaf7-00950f3bc230
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533158233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.1533158233
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.137111095
Short name T304
Test name
Test status
Simulation time 110353900 ps
CPU time 17.03 seconds
Started Jun 06 01:30:52 PM PDT 24
Finished Jun 06 01:31:11 PM PDT 24
Peak memory 272092 kb
Host smart-d83ce99d-04d1-4b94-a265-e99f290e8f3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137111095 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.137111095
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2386303403
Short name T1134
Test name
Test status
Simulation time 26852500 ps
CPU time 16.64 seconds
Started Jun 06 01:30:52 PM PDT 24
Finished Jun 06 01:31:10 PM PDT 24
Peak memory 261092 kb
Host smart-66ea7303-73d3-4c87-a6f8-5ddfe855825c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386303403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.2386303403
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.645557933
Short name T1218
Test name
Test status
Simulation time 47144300 ps
CPU time 13.61 seconds
Started Jun 06 01:30:54 PM PDT 24
Finished Jun 06 01:31:09 PM PDT 24
Peak memory 261152 kb
Host smart-0d92a69f-1c0d-47e6-8dcc-de00aa59660b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645557933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.645557933
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2565781220
Short name T1189
Test name
Test status
Simulation time 35590800 ps
CPU time 14.66 seconds
Started Jun 06 01:30:55 PM PDT 24
Finished Jun 06 01:31:11 PM PDT 24
Peak memory 262424 kb
Host smart-50714815-399d-49c9-8216-565d4b748852
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565781220 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.2565781220
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2538239044
Short name T1107
Test name
Test status
Simulation time 43424200 ps
CPU time 13.24 seconds
Started Jun 06 01:30:53 PM PDT 24
Finished Jun 06 01:31:08 PM PDT 24
Peak memory 253060 kb
Host smart-f1e6d973-483f-435d-96fa-d265e4e9c7e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538239044 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.2538239044
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.499448044
Short name T1111
Test name
Test status
Simulation time 13682500 ps
CPU time 13.3 seconds
Started Jun 06 01:30:53 PM PDT 24
Finished Jun 06 01:31:08 PM PDT 24
Peak memory 252904 kb
Host smart-ef5723e2-98a5-4ca3-b2f5-cc33be33ae34
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499448044 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.499448044
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2792366994
Short name T1230
Test name
Test status
Simulation time 126555100 ps
CPU time 16.67 seconds
Started Jun 06 01:30:52 PM PDT 24
Finished Jun 06 01:31:10 PM PDT 24
Peak memory 263844 kb
Host smart-1f1959d7-55a9-4b04-83cb-25deff3fa5f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792366994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.2
792366994
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1899166872
Short name T1198
Test name
Test status
Simulation time 335758500 ps
CPU time 385.54 seconds
Started Jun 06 01:30:55 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 262408 kb
Host smart-3647f16f-af89-4be3-a3d2-1598f48716e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899166872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.1899166872
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.892841662
Short name T652
Test name
Test status
Simulation time 98082500 ps
CPU time 14.15 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 01:32:13 PM PDT 24
Peak memory 264700 kb
Host smart-1bdeb8c7-d35d-465d-a766-782eae16600e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892841662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.892841662
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.614745229
Short name T981
Test name
Test status
Simulation time 16001900 ps
CPU time 15.96 seconds
Started Jun 06 01:31:57 PM PDT 24
Finished Jun 06 01:32:15 PM PDT 24
Peak memory 274588 kb
Host smart-4c6332d0-1d27-4f64-ae71-0d4092996a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614745229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.614745229
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.2995556754
Short name T417
Test name
Test status
Simulation time 322130000 ps
CPU time 104.96 seconds
Started Jun 06 01:31:46 PM PDT 24
Finished Jun 06 01:33:32 PM PDT 24
Peak memory 281712 kb
Host smart-980f7c76-fc81-4b81-a44c-6d73bc7991b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995556754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_derr_detect.2995556754
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.2008934653
Short name T909
Test name
Test status
Simulation time 7291078900 ps
CPU time 448.48 seconds
Started Jun 06 01:31:47 PM PDT 24
Finished Jun 06 01:39:16 PM PDT 24
Peak memory 263192 kb
Host smart-98b1a448-4ab6-4ee3-928b-9a4305f2bd43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2008934653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.2008934653
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.1038057430
Short name T563
Test name
Test status
Simulation time 10213728500 ps
CPU time 2468.8 seconds
Started Jun 06 01:31:48 PM PDT 24
Finished Jun 06 02:12:58 PM PDT 24
Peak memory 262524 kb
Host smart-d4bd2e5a-6201-4214-9fb3-6fd58d771a03
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038057430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.1038057430
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.1078393272
Short name T174
Test name
Test status
Simulation time 656591600 ps
CPU time 1693.39 seconds
Started Jun 06 01:32:13 PM PDT 24
Finished Jun 06 02:00:28 PM PDT 24
Peak memory 264912 kb
Host smart-f612f889-cc43-4ae2-8d0a-83c217d77b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078393272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.1078393272
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.230324390
Short name T167
Test name
Test status
Simulation time 363120200 ps
CPU time 883.45 seconds
Started Jun 06 01:31:47 PM PDT 24
Finished Jun 06 01:46:31 PM PDT 24
Peak memory 273284 kb
Host smart-03bd1d2c-1134-4a96-9b1d-a88f598b442b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230324390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.230324390
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.3931142173
Short name T874
Test name
Test status
Simulation time 99780652500 ps
CPU time 4206.04 seconds
Started Jun 06 01:31:47 PM PDT 24
Finished Jun 06 02:41:54 PM PDT 24
Peak memory 265024 kb
Host smart-40eb76af-8dcd-451d-8061-370b441b8e7f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931142173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.3931142173
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.2185888518
Short name T924
Test name
Test status
Simulation time 53869000 ps
CPU time 101.4 seconds
Started Jun 06 01:31:37 PM PDT 24
Finished Jun 06 01:33:19 PM PDT 24
Peak memory 262356 kb
Host smart-2150cbda-9715-4da9-b4f2-f198bfa1f532
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2185888518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2185888518
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.1556356134
Short name T616
Test name
Test status
Simulation time 70137579000 ps
CPU time 850.56 seconds
Started Jun 06 01:31:45 PM PDT 24
Finished Jun 06 01:45:57 PM PDT 24
Peak memory 263948 kb
Host smart-7e4cffd5-59a4-4f61-8468-51ea351bfb61
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556356134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.1556356134
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.3919412473
Short name T788
Test name
Test status
Simulation time 4822806300 ps
CPU time 85.63 seconds
Started Jun 06 01:31:49 PM PDT 24
Finished Jun 06 01:33:16 PM PDT 24
Peak memory 260616 kb
Host smart-d08503e7-23db-47a8-b4bc-3ba243995e09
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919412473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.3919412473
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.2413314367
Short name T242
Test name
Test status
Simulation time 17275925900 ps
CPU time 741.11 seconds
Started Jun 06 01:31:52 PM PDT 24
Finished Jun 06 01:44:14 PM PDT 24
Peak memory 341008 kb
Host smart-fd4df0c9-f8fa-4605-ab65-739db4a9b852
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413314367 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_integrity.2413314367
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.873205712
Short name T332
Test name
Test status
Simulation time 7806295900 ps
CPU time 250.05 seconds
Started Jun 06 01:31:47 PM PDT 24
Finished Jun 06 01:35:59 PM PDT 24
Peak memory 290984 kb
Host smart-66a2bb5e-5260-427c-b499-8e0b5a69af59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873205712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_intr_rd.873205712
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.4100417443
Short name T518
Test name
Test status
Simulation time 155162622600 ps
CPU time 324.19 seconds
Started Jun 06 01:31:52 PM PDT 24
Finished Jun 06 01:37:16 PM PDT 24
Peak memory 264900 kb
Host smart-c228c5c7-e2aa-4013-9f10-4b6a2df7a033
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410
0417443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.4100417443
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.1754816793
Short name T871
Test name
Test status
Simulation time 1011927700 ps
CPU time 93.98 seconds
Started Jun 06 01:31:49 PM PDT 24
Finished Jun 06 01:33:24 PM PDT 24
Peak memory 260816 kb
Host smart-0883e986-7c2c-4e03-9924-24c51baf816e
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754816793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.1754816793
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.2679506918
Short name T581
Test name
Test status
Simulation time 79273500 ps
CPU time 136.16 seconds
Started Jun 06 01:32:14 PM PDT 24
Finished Jun 06 01:34:31 PM PDT 24
Peak memory 259760 kb
Host smart-a851f495-f4c3-4ffc-be4f-3d888bd36cf0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679506918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.2679506918
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.3427705129
Short name T58
Test name
Test status
Simulation time 1678712100 ps
CPU time 144.79 seconds
Started Jun 06 01:31:49 PM PDT 24
Finished Jun 06 01:34:14 PM PDT 24
Peak memory 281720 kb
Host smart-6a51f234-da2b-4653-94b8-e512e64fef75
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427705129 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.3427705129
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.2549596809
Short name T940
Test name
Test status
Simulation time 15564400 ps
CPU time 14.37 seconds
Started Jun 06 01:31:55 PM PDT 24
Finished Jun 06 01:32:11 PM PDT 24
Peak memory 276984 kb
Host smart-91fc1bc2-e814-4e68-a1d1-5db2d9cbf262
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2549596809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.2549596809
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.717924365
Short name T670
Test name
Test status
Simulation time 234508200 ps
CPU time 410.4 seconds
Started Jun 06 01:31:48 PM PDT 24
Finished Jun 06 01:38:40 PM PDT 24
Peak memory 262696 kb
Host smart-311465c7-3573-408d-8a2e-14ff4c4d9867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=717924365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.717924365
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.3373504677
Short name T169
Test name
Test status
Simulation time 44844600 ps
CPU time 13.93 seconds
Started Jun 06 01:31:57 PM PDT 24
Finished Jun 06 01:32:13 PM PDT 24
Peak memory 265404 kb
Host smart-41757a7e-b37f-4f65-9c92-fe6fdbcf8398
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373504677 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.3373504677
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.341128183
Short name T415
Test name
Test status
Simulation time 31419400 ps
CPU time 13.84 seconds
Started Jun 06 01:31:47 PM PDT 24
Finished Jun 06 01:32:02 PM PDT 24
Peak memory 258384 kb
Host smart-64ec33d2-878c-48ae-b01d-f1935c873822
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341128183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_rese
t.341128183
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.2859308878
Short name T73
Test name
Test status
Simulation time 11955374400 ps
CPU time 1245.07 seconds
Started Jun 06 01:31:37 PM PDT 24
Finished Jun 06 01:52:24 PM PDT 24
Peak memory 287296 kb
Host smart-a3498294-7988-4bcb-abb2-8866d055ee93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859308878 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.2859308878
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.3679592697
Short name T943
Test name
Test status
Simulation time 1444447700 ps
CPU time 128.13 seconds
Started Jun 06 01:31:38 PM PDT 24
Finished Jun 06 01:33:48 PM PDT 24
Peak memory 262520 kb
Host smart-929aa4ef-a3e8-4db5-b08d-4d9ec87f5a98
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3679592697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.3679592697
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.2561413161
Short name T663
Test name
Test status
Simulation time 256768300 ps
CPU time 31.92 seconds
Started Jun 06 01:31:54 PM PDT 24
Finished Jun 06 01:32:27 PM PDT 24
Peak memory 275496 kb
Host smart-466a71b8-73e3-4691-8d58-4e93909d6f2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561413161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.2561413161
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.1684966048
Short name T933
Test name
Test status
Simulation time 78241100 ps
CPU time 43.9 seconds
Started Jun 06 01:31:59 PM PDT 24
Finished Jun 06 01:32:43 PM PDT 24
Peak memory 275228 kb
Host smart-1eed619a-7e6f-47f2-99ce-934192f080ac
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684966048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.1684966048
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.1438159206
Short name T1025
Test name
Test status
Simulation time 116703100 ps
CPU time 38.88 seconds
Started Jun 06 01:31:49 PM PDT 24
Finished Jun 06 01:32:28 PM PDT 24
Peak memory 275084 kb
Host smart-2063bbb4-b241-4fe0-b716-3be5fdc9647d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438159206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.1438159206
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.1405559129
Short name T1017
Test name
Test status
Simulation time 56881500 ps
CPU time 13.9 seconds
Started Jun 06 01:31:49 PM PDT 24
Finished Jun 06 01:32:04 PM PDT 24
Peak memory 258124 kb
Host smart-1a5279b2-704e-4ada-8319-31eb076fb870
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1405559129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.1405559129
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.1658400487
Short name T936
Test name
Test status
Simulation time 18685400 ps
CPU time 22.81 seconds
Started Jun 06 01:31:49 PM PDT 24
Finished Jun 06 01:32:13 PM PDT 24
Peak memory 265264 kb
Host smart-b576285d-5e43-41a5-a1be-fca199671b4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658400487 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.1658400487
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.1098177182
Short name T465
Test name
Test status
Simulation time 61718200 ps
CPU time 21.52 seconds
Started Jun 06 01:31:47 PM PDT 24
Finished Jun 06 01:32:10 PM PDT 24
Peak memory 265100 kb
Host smart-c0608fda-ac0c-4b2b-a61d-54e2b40e6343
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098177182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.1098177182
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.379622348
Short name T154
Test name
Test status
Simulation time 251736515200 ps
CPU time 1202.49 seconds
Started Jun 06 01:31:57 PM PDT 24
Finished Jun 06 01:52:02 PM PDT 24
Peak memory 260880 kb
Host smart-aca374c2-6b85-4110-8bf7-8885650624bd
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379622348 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.379622348
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.2894921350
Short name T1077
Test name
Test status
Simulation time 2680410500 ps
CPU time 129.2 seconds
Started Jun 06 01:31:46 PM PDT 24
Finished Jun 06 01:33:56 PM PDT 24
Peak memory 281660 kb
Host smart-ddb0e3c6-536d-43c8-a798-3fb32e1e2c98
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894921350 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.2894921350
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.3643693973
Short name T267
Test name
Test status
Simulation time 2540222900 ps
CPU time 148.31 seconds
Started Jun 06 01:31:45 PM PDT 24
Finished Jun 06 01:34:14 PM PDT 24
Peak memory 281736 kb
Host smart-8a293099-94ed-4202-bb23-d3070f6635bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643693973 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.3643693973
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.1581749726
Short name T317
Test name
Test status
Simulation time 12856020200 ps
CPU time 520.18 seconds
Started Jun 06 01:31:48 PM PDT 24
Finished Jun 06 01:40:29 PM PDT 24
Peak memory 309472 kb
Host smart-f89c5ae3-9bb0-4c4a-b996-b13514666b1a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581749726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.1581749726
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.1081651616
Short name T239
Test name
Test status
Simulation time 18738523700 ps
CPU time 628.96 seconds
Started Jun 06 01:31:46 PM PDT 24
Finished Jun 06 01:42:16 PM PDT 24
Peak memory 344452 kb
Host smart-0b2b1c75-2703-4706-903c-ee083511c013
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081651616 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.1081651616
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.2101925831
Short name T762
Test name
Test status
Simulation time 28989900 ps
CPU time 31.18 seconds
Started Jun 06 01:31:46 PM PDT 24
Finished Jun 06 01:32:18 PM PDT 24
Peak memory 275156 kb
Host smart-442a406a-0dfa-4314-8f1f-2d8281f23f71
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101925831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.2101925831
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.911227463
Short name T1092
Test name
Test status
Simulation time 143941700 ps
CPU time 31.22 seconds
Started Jun 06 01:31:46 PM PDT 24
Finished Jun 06 01:32:18 PM PDT 24
Peak memory 275616 kb
Host smart-3ce95492-9985-4d00-b448-e9e02364f4c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911227463 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.911227463
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_serr.4142122260
Short name T952
Test name
Test status
Simulation time 3614036000 ps
CPU time 645.24 seconds
Started Jun 06 01:31:47 PM PDT 24
Finished Jun 06 01:42:34 PM PDT 24
Peak memory 326248 kb
Host smart-69474c24-06e0-42ab-a795-fc14143370b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142122260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_s
err.4142122260
Directory /workspace/0.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.2987918513
Short name T17
Test name
Test status
Simulation time 3513732900 ps
CPU time 83.25 seconds
Started Jun 06 01:31:49 PM PDT 24
Finished Jun 06 01:33:13 PM PDT 24
Peak memory 273556 kb
Host smart-ad839e58-dcb5-44bf-9e5d-70bacc3df85f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987918513 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.2987918513
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.1837120363
Short name T273
Test name
Test status
Simulation time 10274118600 ps
CPU time 91.6 seconds
Started Jun 06 01:31:48 PM PDT 24
Finished Jun 06 01:33:20 PM PDT 24
Peak memory 265268 kb
Host smart-428a08ca-f14a-4238-97a0-a9c336a456cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837120363 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.1837120363
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.2675863013
Short name T694
Test name
Test status
Simulation time 56546600 ps
CPU time 125.46 seconds
Started Jun 06 01:31:37 PM PDT 24
Finished Jun 06 01:33:44 PM PDT 24
Peak memory 276464 kb
Host smart-369af86d-44e5-4fb3-a7e3-0caf23fff7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675863013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2675863013
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.1843088574
Short name T422
Test name
Test status
Simulation time 14058100 ps
CPU time 27.19 seconds
Started Jun 06 01:31:41 PM PDT 24
Finished Jun 06 01:32:09 PM PDT 24
Peak memory 259228 kb
Host smart-b43ed11d-659a-44ae-a824-88220d915cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843088574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.1843088574
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.461786605
Short name T769
Test name
Test status
Simulation time 436686200 ps
CPU time 810.74 seconds
Started Jun 06 01:31:57 PM PDT 24
Finished Jun 06 01:45:30 PM PDT 24
Peak memory 284272 kb
Host smart-68ff7b9c-7bdb-40fd-a82a-4444fef82e79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461786605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress
_all.461786605
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.3900313852
Short name T931
Test name
Test status
Simulation time 22966900 ps
CPU time 27.57 seconds
Started Jun 06 01:31:38 PM PDT 24
Finished Jun 06 01:32:07 PM PDT 24
Peak memory 261960 kb
Host smart-aa027fe9-4aa9-4b71-803c-46883cbdf4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900313852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.3900313852
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.2180693510
Short name T895
Test name
Test status
Simulation time 2504169800 ps
CPU time 195.89 seconds
Started Jun 06 01:31:50 PM PDT 24
Finished Jun 06 01:35:06 PM PDT 24
Peak memory 265224 kb
Host smart-34eea7b1-e209-47ae-8b8f-87c3064e3818
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180693510 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_wo.2180693510
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.1037946503
Short name T633
Test name
Test status
Simulation time 39774900 ps
CPU time 15.46 seconds
Started Jun 06 01:31:52 PM PDT 24
Finished Jun 06 01:32:08 PM PDT 24
Peak memory 258512 kb
Host smart-29284b64-d418-467a-927c-af854822ff3f
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=1037946503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.1037946503
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.4215601253
Short name T24
Test name
Test status
Simulation time 12938000 ps
CPU time 13.67 seconds
Started Jun 06 01:32:07 PM PDT 24
Finished Jun 06 01:32:22 PM PDT 24
Peak memory 265232 kb
Host smart-c705cb04-7e25-4c2d-96da-e81b0e649619
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215601253 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.4215601253
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.2129863813
Short name T739
Test name
Test status
Simulation time 45317400 ps
CPU time 14.4 seconds
Started Jun 06 01:32:07 PM PDT 24
Finished Jun 06 01:32:23 PM PDT 24
Peak memory 264840 kb
Host smart-73da9095-8fba-454c-a5d3-152773e77f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129863813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.2
129863813
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.2809036535
Short name T862
Test name
Test status
Simulation time 19531500 ps
CPU time 14.08 seconds
Started Jun 06 01:32:07 PM PDT 24
Finished Jun 06 01:32:22 PM PDT 24
Peak memory 261312 kb
Host smart-890cefd4-44e7-46f6-82b2-acda2e6ae4e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809036535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.2809036535
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.438326518
Short name T507
Test name
Test status
Simulation time 28487900 ps
CPU time 13.74 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 01:32:12 PM PDT 24
Peak memory 274784 kb
Host smart-d17be772-dbd9-40a5-b4db-22a14de1408f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438326518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.438326518
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.2948857255
Short name T888
Test name
Test status
Simulation time 210746500 ps
CPU time 107.37 seconds
Started Jun 06 01:31:59 PM PDT 24
Finished Jun 06 01:33:48 PM PDT 24
Peak memory 281720 kb
Host smart-98afde83-3872-44de-a87c-cbd31f06bc82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948857255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.2948857255
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.3471945365
Short name T223
Test name
Test status
Simulation time 5578858600 ps
CPU time 348.22 seconds
Started Jun 06 01:31:57 PM PDT 24
Finished Jun 06 01:37:47 PM PDT 24
Peak memory 263204 kb
Host smart-e93a5d76-e5ab-4ac8-be3b-d335424ce04f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471945365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.3471945365
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.3159486398
Short name T902
Test name
Test status
Simulation time 13145473000 ps
CPU time 2610.45 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 02:15:29 PM PDT 24
Peak memory 264972 kb
Host smart-43c4c636-d3b6-41a6-b77b-a22575859acf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159486398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.3159486398
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.1073741729
Short name T1013
Test name
Test status
Simulation time 1926351200 ps
CPU time 2637.64 seconds
Started Jun 06 01:32:01 PM PDT 24
Finished Jun 06 02:16:00 PM PDT 24
Peak memory 264852 kb
Host smart-d702e668-2e6f-40e5-af25-6ae5308a4b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073741729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.1073741729
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.1425793447
Short name T468
Test name
Test status
Simulation time 2072330700 ps
CPU time 850 seconds
Started Jun 06 01:32:04 PM PDT 24
Finished Jun 06 01:46:15 PM PDT 24
Peak memory 273372 kb
Host smart-5d4846c2-ff2a-457b-9d93-c1782faf0c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425793447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.1425793447
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.4043986233
Short name T986
Test name
Test status
Simulation time 96502500 ps
CPU time 22.48 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 01:32:21 PM PDT 24
Peak memory 263304 kb
Host smart-9337ace4-3143-4b00-9ac4-bf8436769b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043986233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.4043986233
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.950544390
Short name T691
Test name
Test status
Simulation time 644444100 ps
CPU time 40.04 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:32:49 PM PDT 24
Peak memory 264904 kb
Host smart-73d8e6f6-ba9a-4389-9a05-778610ff315e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950544390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_fs_sup.950544390
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.2283783495
Short name T204
Test name
Test status
Simulation time 99781142700 ps
CPU time 3668.56 seconds
Started Jun 06 01:31:55 PM PDT 24
Finished Jun 06 02:33:06 PM PDT 24
Peak memory 265016 kb
Host smart-168f7f54-5d6d-45d1-8b05-29b84509a28f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283783495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.2283783495
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.1828020018
Short name T825
Test name
Test status
Simulation time 241752727100 ps
CPU time 2601.07 seconds
Started Jun 06 01:31:54 PM PDT 24
Finished Jun 06 02:15:17 PM PDT 24
Peak memory 265188 kb
Host smart-212cc17b-bcb3-4157-a8e2-fc4d4ce9b459
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828020018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.1828020018
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.3905883924
Short name T83
Test name
Test status
Simulation time 56889300 ps
CPU time 101.88 seconds
Started Jun 06 01:32:04 PM PDT 24
Finished Jun 06 01:33:47 PM PDT 24
Peak memory 262380 kb
Host smart-c39de257-2011-4c9b-9b5d-7a486a2e63be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905883924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3905883924
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.1965864314
Short name T1097
Test name
Test status
Simulation time 51524400 ps
CPU time 13.75 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:32:24 PM PDT 24
Peak memory 258148 kb
Host smart-8e9f3f9e-718b-48cb-bde0-2e6dd6621434
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965864314 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.1965864314
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.2587209933
Short name T595
Test name
Test status
Simulation time 731837510900 ps
CPU time 1986.81 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 02:05:05 PM PDT 24
Peak memory 263344 kb
Host smart-4feaa545-06c6-489e-93e4-b5dd9eb3d801
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587209933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.2587209933
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2281594015
Short name T673
Test name
Test status
Simulation time 260233948600 ps
CPU time 1052.31 seconds
Started Jun 06 01:31:57 PM PDT 24
Finished Jun 06 01:49:31 PM PDT 24
Peak memory 264156 kb
Host smart-ae430161-a4b1-48b8-a47f-669e06ee4006
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281594015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.2281594015
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.4177972697
Short name T558
Test name
Test status
Simulation time 9662553400 ps
CPU time 142.11 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 01:34:21 PM PDT 24
Peak memory 262264 kb
Host smart-8479f484-c19f-4b14-8490-11a222749e5a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177972697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h
w_sec_otp.4177972697
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.1104957634
Short name T241
Test name
Test status
Simulation time 8672313800 ps
CPU time 681.25 seconds
Started Jun 06 01:32:00 PM PDT 24
Finished Jun 06 01:43:22 PM PDT 24
Peak memory 337524 kb
Host smart-512a4752-b1b6-4a71-99b4-703c595ef3ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104957634 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.1104957634
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.4228691237
Short name T604
Test name
Test status
Simulation time 26244713700 ps
CPU time 209.37 seconds
Started Jun 06 01:32:12 PM PDT 24
Finished Jun 06 01:35:43 PM PDT 24
Peak memory 290816 kb
Host smart-010e95a0-21c5-416f-8103-d6b1d3c783d1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228691237 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.4228691237
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.4190478190
Short name T819
Test name
Test status
Simulation time 2298314500 ps
CPU time 67.97 seconds
Started Jun 06 01:32:11 PM PDT 24
Finished Jun 06 01:33:21 PM PDT 24
Peak memory 264912 kb
Host smart-4c5306ef-6b5a-4182-9402-4b658d547401
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190478190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.4190478190
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3751966867
Short name T1052
Test name
Test status
Simulation time 41734741800 ps
CPU time 184.33 seconds
Started Jun 06 01:32:11 PM PDT 24
Finished Jun 06 01:35:17 PM PDT 24
Peak memory 260092 kb
Host smart-3ea82689-0feb-48f9-a079-808c8f203860
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375
1966867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.3751966867
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.443206201
Short name T523
Test name
Test status
Simulation time 1023267000 ps
CPU time 98.84 seconds
Started Jun 06 01:31:57 PM PDT 24
Finished Jun 06 01:33:38 PM PDT 24
Peak memory 260456 kb
Host smart-9e7dfa15-13b6-410c-ac02-1cfbb54efc94
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443206201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.443206201
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.3018622560
Short name T426
Test name
Test status
Simulation time 44906800 ps
CPU time 13.77 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:32:23 PM PDT 24
Peak memory 259524 kb
Host smart-6cf6bd4f-d07d-4d42-b882-fcb80bd49f57
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018622560 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.3018622560
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.2648967901
Short name T76
Test name
Test status
Simulation time 39307600 ps
CPU time 135.97 seconds
Started Jun 06 01:32:00 PM PDT 24
Finished Jun 06 01:34:17 PM PDT 24
Peak memory 264436 kb
Host smart-3b798376-c1ac-4d05-a0ea-cf14524c15bf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648967901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot
p_reset.2648967901
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.4171478139
Short name T972
Test name
Test status
Simulation time 2495526900 ps
CPU time 198.6 seconds
Started Jun 06 01:32:00 PM PDT 24
Finished Jun 06 01:35:19 PM PDT 24
Peak memory 281672 kb
Host smart-f9aa205a-7733-4b46-b7bd-32531acd5664
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171478139 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.4171478139
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.2655864694
Short name T491
Test name
Test status
Simulation time 47775000 ps
CPU time 67.84 seconds
Started Jun 06 01:31:58 PM PDT 24
Finished Jun 06 01:33:07 PM PDT 24
Peak memory 262760 kb
Host smart-8e4e2176-3e10-4242-9ac5-54e1fb785934
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2655864694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2655864694
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.3191522133
Short name T597
Test name
Test status
Simulation time 22212400 ps
CPU time 13.98 seconds
Started Jun 06 01:32:12 PM PDT 24
Finished Jun 06 01:32:27 PM PDT 24
Peak memory 265012 kb
Host smart-c66ddee7-3200-46a3-a734-5e7b0e40ce57
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191522133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.3191522133
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.998403015
Short name T738
Test name
Test status
Simulation time 280326500 ps
CPU time 79.81 seconds
Started Jun 06 01:31:55 PM PDT 24
Finished Jun 06 01:33:16 PM PDT 24
Peak memory 269080 kb
Host smart-4edd7cd5-c823-41f7-b572-cf64e5e2ee10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998403015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.998403015
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.2989341527
Short name T756
Test name
Test status
Simulation time 1521089200 ps
CPU time 113.77 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 01:33:52 PM PDT 24
Peak memory 262480 kb
Host smart-937ff44c-3709-40f5-9b50-0f80e48a261e
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2989341527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.2989341527
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.2998830800
Short name T538
Test name
Test status
Simulation time 69526000 ps
CPU time 31.68 seconds
Started Jun 06 01:32:00 PM PDT 24
Finished Jun 06 01:32:33 PM PDT 24
Peak memory 275556 kb
Host smart-ab9c691a-bed6-4e5f-89eb-bd670d1a4a4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998830800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.2998830800
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.2177292812
Short name T5
Test name
Test status
Simulation time 428138100 ps
CPU time 34.55 seconds
Started Jun 06 01:32:01 PM PDT 24
Finished Jun 06 01:32:37 PM PDT 24
Peak memory 275132 kb
Host smart-fa8fb8e2-0da4-44b5-987f-46e4ad0953a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177292812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.2177292812
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.2601532470
Short name T42
Test name
Test status
Simulation time 363716100 ps
CPU time 23.08 seconds
Started Jun 06 01:32:01 PM PDT 24
Finished Jun 06 01:32:25 PM PDT 24
Peak memory 264724 kb
Host smart-d90a18de-9aa5-4559-8d31-9790a686dedb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601532470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.2601532470
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.2352610631
Short name T141
Test name
Test status
Simulation time 129738311000 ps
CPU time 991.95 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:48:42 PM PDT 24
Peak memory 260964 kb
Host smart-e166be04-5b5e-44e2-900b-6fdd65ae5923
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352610631 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.2352610631
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.2975727994
Short name T449
Test name
Test status
Simulation time 556591900 ps
CPU time 102.41 seconds
Started Jun 06 01:32:02 PM PDT 24
Finished Jun 06 01:33:45 PM PDT 24
Peak memory 289940 kb
Host smart-8d46fee9-6721-41a9-8db2-d5c44c6beee5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975727994 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_ro.2975727994
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.1134850250
Short name T172
Test name
Test status
Simulation time 1978811500 ps
CPU time 117.9 seconds
Started Jun 06 01:31:59 PM PDT 24
Finished Jun 06 01:33:57 PM PDT 24
Peak memory 281732 kb
Host smart-a95c602d-0cbb-4c41-b420-9d0cd7712378
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1134850250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.1134850250
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.2037330771
Short name T867
Test name
Test status
Simulation time 1084701800 ps
CPU time 114.6 seconds
Started Jun 06 01:32:00 PM PDT 24
Finished Jun 06 01:33:56 PM PDT 24
Peak memory 295048 kb
Host smart-6235c66e-5e4a-4822-8454-73d42c659dad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037330771 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2037330771
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.3112431098
Short name T443
Test name
Test status
Simulation time 4391803100 ps
CPU time 586.3 seconds
Started Jun 06 01:31:58 PM PDT 24
Finished Jun 06 01:41:46 PM PDT 24
Peak memory 309260 kb
Host smart-e9ce54b1-8f75-4cfe-b616-5abe3dfef93b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112431098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.flash_ctrl_rw.3112431098
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.2020604434
Short name T545
Test name
Test status
Simulation time 121860300 ps
CPU time 31.01 seconds
Started Jun 06 01:32:12 PM PDT 24
Finished Jun 06 01:32:44 PM PDT 24
Peak memory 275188 kb
Host smart-a911f199-a4e5-474d-bcce-1a56fdf40e83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020604434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.2020604434
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.1078102969
Short name T324
Test name
Test status
Simulation time 136444400 ps
CPU time 28.78 seconds
Started Jun 06 01:32:11 PM PDT 24
Finished Jun 06 01:32:42 PM PDT 24
Peak memory 275420 kb
Host smart-dafc07eb-4d86-4ecc-aa6e-99f25dbb989e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078102969 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.1078102969
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.3811399095
Short name T1023
Test name
Test status
Simulation time 3524795000 ps
CPU time 581.3 seconds
Started Jun 06 01:32:12 PM PDT 24
Finished Jun 06 01:41:55 PM PDT 24
Peak memory 320528 kb
Host smart-ac75c28f-5a54-4e1a-9cd8-294e5e3e6a03
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811399095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.3811399095
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.2350449758
Short name T375
Test name
Test status
Simulation time 8399292000 ps
CPU time 83.07 seconds
Started Jun 06 01:31:57 PM PDT 24
Finished Jun 06 01:33:22 PM PDT 24
Peak memory 259296 kb
Host smart-fc7c4b17-867c-48d3-ba37-e6c26c915290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350449758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.2350449758
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.1312285346
Short name T438
Test name
Test status
Simulation time 9867324200 ps
CPU time 72.21 seconds
Started Jun 06 01:32:01 PM PDT 24
Finished Jun 06 01:33:14 PM PDT 24
Peak memory 265324 kb
Host smart-6bcdf9e5-473e-4e93-87ec-825de6f4484c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312285346 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.1312285346
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.3821041888
Short name T661
Test name
Test status
Simulation time 893497200 ps
CPU time 78.87 seconds
Started Jun 06 01:31:56 PM PDT 24
Finished Jun 06 01:33:17 PM PDT 24
Peak memory 265580 kb
Host smart-48098ef5-b843-4497-8406-075773a8898e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821041888 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.3821041888
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.2924792611
Short name T231
Test name
Test status
Simulation time 57363400 ps
CPU time 124.51 seconds
Started Jun 06 01:31:59 PM PDT 24
Finished Jun 06 01:34:05 PM PDT 24
Peak memory 276424 kb
Host smart-3d800bb0-e716-4c90-97b3-4785bfa5a5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924792611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.2924792611
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.2667078951
Short name T54
Test name
Test status
Simulation time 49851700 ps
CPU time 26.58 seconds
Started Jun 06 01:31:57 PM PDT 24
Finished Jun 06 01:32:25 PM PDT 24
Peak memory 259356 kb
Host smart-f8ffc28b-cdd5-4b8a-8db7-27b069e5774c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667078951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.2667078951
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.907651000
Short name T55
Test name
Test status
Simulation time 300096800 ps
CPU time 665.52 seconds
Started Jun 06 01:31:59 PM PDT 24
Finished Jun 06 01:43:05 PM PDT 24
Peak memory 289780 kb
Host smart-5ba6d244-335b-4195-8dd4-0a167c78ed50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907651000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress
_all.907651000
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.4082218632
Short name T839
Test name
Test status
Simulation time 50656300 ps
CPU time 26.87 seconds
Started Jun 06 01:31:54 PM PDT 24
Finished Jun 06 01:32:23 PM PDT 24
Peak memory 261948 kb
Host smart-4891078c-7b9c-4a3a-8746-2807a25d0f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082218632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.4082218632
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.1176245019
Short name T678
Test name
Test status
Simulation time 6086585200 ps
CPU time 122.62 seconds
Started Jun 06 01:31:57 PM PDT 24
Finished Jun 06 01:34:02 PM PDT 24
Peak memory 265544 kb
Host smart-f1cb3487-f88a-4b7f-8b18-2eb1da919222
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176245019 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_wo.1176245019
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.1199699272
Short name T654
Test name
Test status
Simulation time 21978400 ps
CPU time 16.09 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:34:00 PM PDT 24
Peak memory 274528 kb
Host smart-1dc3508c-fe17-4fee-a3fc-ee41576e9166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199699272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1199699272
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.3718477752
Short name T191
Test name
Test status
Simulation time 36517900 ps
CPU time 20.89 seconds
Started Jun 06 01:33:43 PM PDT 24
Finished Jun 06 01:34:05 PM PDT 24
Peak memory 264984 kb
Host smart-9773de90-f3c7-4637-b601-e0eff2396e0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718477752 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.3718477752
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.195217113
Short name T288
Test name
Test status
Simulation time 10043685400 ps
CPU time 51.56 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:34:35 PM PDT 24
Peak memory 267476 kb
Host smart-81cfae02-a523-43d5-8aab-37a17739080f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195217113 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.195217113
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.453932311
Short name T286
Test name
Test status
Simulation time 15590700 ps
CPU time 13.6 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:33:57 PM PDT 24
Peak memory 258252 kb
Host smart-d0f53d70-b72d-4017-a4f0-b4d88f4ef76f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453932311 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.453932311
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.4197958114
Short name T859
Test name
Test status
Simulation time 160188285700 ps
CPU time 962.6 seconds
Started Jun 06 01:33:40 PM PDT 24
Finished Jun 06 01:49:44 PM PDT 24
Peak memory 263644 kb
Host smart-f80aec6a-6d07-4feb-9dfd-cb41ccf6b6d2
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197958114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.flash_ctrl_hw_rma_reset.4197958114
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.653360132
Short name T951
Test name
Test status
Simulation time 1105899300 ps
CPU time 60.71 seconds
Started Jun 06 01:33:39 PM PDT 24
Finished Jun 06 01:34:41 PM PDT 24
Peak memory 262836 kb
Host smart-7fb2d9f5-9432-4e8c-a202-fa82236548de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653360132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_h
w_sec_otp.653360132
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.1349359553
Short name T745
Test name
Test status
Simulation time 694508300 ps
CPU time 156.38 seconds
Started Jun 06 01:33:41 PM PDT 24
Finished Jun 06 01:36:18 PM PDT 24
Peak memory 293328 kb
Host smart-3c2c2d1c-dce7-4a4a-83a8-14702eece610
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349359553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.1349359553
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.859369934
Short name T1000
Test name
Test status
Simulation time 5674246900 ps
CPU time 136.48 seconds
Started Jun 06 01:33:43 PM PDT 24
Finished Jun 06 01:36:01 PM PDT 24
Peak memory 292332 kb
Host smart-fc13430d-41b9-496d-97ee-333f65280ab1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859369934 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.859369934
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.2045631886
Short name T568
Test name
Test status
Simulation time 26870921200 ps
CPU time 76.32 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:34:59 PM PDT 24
Peak memory 263428 kb
Host smart-b87a4c53-ea38-4f1d-8396-9343cec76f88
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045631886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.2
045631886
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.1143046129
Short name T436
Test name
Test status
Simulation time 15872900 ps
CPU time 13.51 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:33:57 PM PDT 24
Peak memory 259592 kb
Host smart-c1690d2d-d812-41f3-bdde-5001ea2be850
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143046129 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.1143046129
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.3699526069
Short name T222
Test name
Test status
Simulation time 13213279900 ps
CPU time 168.98 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:36:32 PM PDT 24
Peak memory 265168 kb
Host smart-56d47e77-be98-4b4d-9bce-e85830ec4148
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699526069 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.3699526069
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.364003890
Short name T916
Test name
Test status
Simulation time 179585000 ps
CPU time 112.89 seconds
Started Jun 06 01:33:41 PM PDT 24
Finished Jun 06 01:35:35 PM PDT 24
Peak memory 260028 kb
Host smart-2ce4fa57-1823-4697-88ac-3d3aa8daf41c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364003890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ot
p_reset.364003890
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.2490400616
Short name T59
Test name
Test status
Simulation time 83896200 ps
CPU time 155.09 seconds
Started Jun 06 01:33:39 PM PDT 24
Finished Jun 06 01:36:15 PM PDT 24
Peak memory 262780 kb
Host smart-a2cc375e-32d2-405d-b86b-5c3a127f55b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2490400616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.2490400616
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.3078936601
Short name T996
Test name
Test status
Simulation time 19592200 ps
CPU time 13.58 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:33:56 PM PDT 24
Peak memory 258380 kb
Host smart-9190b22c-a811-4143-9d15-3fd508a1abc0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078936601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.3078936601
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.2695538734
Short name T569
Test name
Test status
Simulation time 40833800 ps
CPU time 207.59 seconds
Started Jun 06 01:33:41 PM PDT 24
Finished Jun 06 01:37:09 PM PDT 24
Peak memory 281556 kb
Host smart-acecddf1-fa6e-4802-afe2-2ff02b54e0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695538734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2695538734
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.185544644
Short name T991
Test name
Test status
Simulation time 75677800 ps
CPU time 37.17 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:34:20 PM PDT 24
Peak memory 275512 kb
Host smart-a900a588-36d0-49e0-a215-d3fdf195e820
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185544644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_re_evict.185544644
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.148398741
Short name T212
Test name
Test status
Simulation time 924805200 ps
CPU time 109.43 seconds
Started Jun 06 01:33:43 PM PDT 24
Finished Jun 06 01:35:33 PM PDT 24
Peak memory 281748 kb
Host smart-91ba7017-61cd-485d-b2bc-d4702525f393
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148398741 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.flash_ctrl_ro.148398741
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.139390359
Short name T665
Test name
Test status
Simulation time 29523400 ps
CPU time 31.5 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:34:14 PM PDT 24
Peak memory 275596 kb
Host smart-63e69f77-39ec-4923-ab3c-a7ffb91dcb58
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139390359 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.139390359
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.3511891126
Short name T409
Test name
Test status
Simulation time 3568022200 ps
CPU time 70.4 seconds
Started Jun 06 01:33:43 PM PDT 24
Finished Jun 06 01:34:54 PM PDT 24
Peak memory 259288 kb
Host smart-60ab698a-465c-4293-b469-da24770ade78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511891126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.3511891126
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.2070961505
Short name T391
Test name
Test status
Simulation time 76299600 ps
CPU time 125.24 seconds
Started Jun 06 01:33:41 PM PDT 24
Finished Jun 06 01:35:47 PM PDT 24
Peak memory 277224 kb
Host smart-02a1033a-0a44-41d2-865e-9de029f2b6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070961505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.2070961505
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.436948231
Short name T875
Test name
Test status
Simulation time 3221273500 ps
CPU time 208.95 seconds
Started Jun 06 01:33:40 PM PDT 24
Finished Jun 06 01:37:10 PM PDT 24
Peak memory 265080 kb
Host smart-e7f536f4-84ed-4275-aed5-ca0bd6510bf7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436948231 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.flash_ctrl_wo.436948231
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.3567928864
Short name T430
Test name
Test status
Simulation time 24577500 ps
CPU time 13.7 seconds
Started Jun 06 01:33:50 PM PDT 24
Finished Jun 06 01:34:04 PM PDT 24
Peak memory 258036 kb
Host smart-d3668383-1859-4bb4-b8fe-0dacbb869f9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567928864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
3567928864
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.545727135
Short name T446
Test name
Test status
Simulation time 14522000 ps
CPU time 13.92 seconds
Started Jun 06 01:33:46 PM PDT 24
Finished Jun 06 01:34:01 PM PDT 24
Peak memory 274620 kb
Host smart-7230a12e-71fb-4855-89f0-b654c44e11c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545727135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.545727135
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.2198941403
Short name T69
Test name
Test status
Simulation time 14982900 ps
CPU time 21.1 seconds
Started Jun 06 01:33:50 PM PDT 24
Finished Jun 06 01:34:11 PM PDT 24
Peak memory 273584 kb
Host smart-92fe3fed-4f91-421e-8aa2-799d81a3d46a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198941403 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.2198941403
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2273784637
Short name T29
Test name
Test status
Simulation time 10031912300 ps
CPU time 61.79 seconds
Started Jun 06 01:33:46 PM PDT 24
Finished Jun 06 01:34:49 PM PDT 24
Peak memory 294284 kb
Host smart-ff7ce619-a0ea-42e1-a4ef-638dec70eeae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273784637 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.2273784637
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3784653267
Short name T158
Test name
Test status
Simulation time 40127384100 ps
CPU time 840.97 seconds
Started Jun 06 01:33:44 PM PDT 24
Finished Jun 06 01:47:45 PM PDT 24
Peak memory 263760 kb
Host smart-d20f6315-fff9-4713-8338-f4b6c717d574
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784653267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3784653267
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.2910679871
Short name T552
Test name
Test status
Simulation time 5346807600 ps
CPU time 97.45 seconds
Started Jun 06 01:33:45 PM PDT 24
Finished Jun 06 01:35:23 PM PDT 24
Peak memory 262876 kb
Host smart-dce1acd5-bea8-4fdd-9fb4-97edaa9c36a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910679871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.2910679871
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.413380542
Short name T728
Test name
Test status
Simulation time 1857469800 ps
CPU time 224.3 seconds
Started Jun 06 01:33:44 PM PDT 24
Finished Jun 06 01:37:29 PM PDT 24
Peak memory 292120 kb
Host smart-b268524a-c252-4ec2-9322-941e4bc2d9e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413380542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flas
h_ctrl_intr_rd.413380542
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.1008379037
Short name T504
Test name
Test status
Simulation time 23759971500 ps
CPU time 341.74 seconds
Started Jun 06 01:33:46 PM PDT 24
Finished Jun 06 01:39:28 PM PDT 24
Peak memory 284748 kb
Host smart-25e2e5f7-8457-4991-90c0-9a956c8c8c22
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008379037 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.1008379037
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.1914009340
Short name T942
Test name
Test status
Simulation time 4020757100 ps
CPU time 99.1 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:35:23 PM PDT 24
Peak memory 260432 kb
Host smart-193375eb-fc96-4c81-8b7a-4e31d85eea2a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914009340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.1
914009340
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.3347146432
Short name T878
Test name
Test status
Simulation time 26795400 ps
CPU time 13.92 seconds
Started Jun 06 01:33:45 PM PDT 24
Finished Jun 06 01:33:59 PM PDT 24
Peak memory 259452 kb
Host smart-32851a26-dcd0-44b4-91db-954d75758b6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347146432 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.3347146432
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.1732103556
Short name T85
Test name
Test status
Simulation time 36238279500 ps
CPU time 452.52 seconds
Started Jun 06 01:33:41 PM PDT 24
Finished Jun 06 01:41:15 PM PDT 24
Peak memory 274836 kb
Host smart-abe5560c-88b2-45aa-b560-6eb297ed23db
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732103556 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.1732103556
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.3654711512
Short name T591
Test name
Test status
Simulation time 146254000 ps
CPU time 135.44 seconds
Started Jun 06 01:33:46 PM PDT 24
Finished Jun 06 01:36:03 PM PDT 24
Peak memory 259628 kb
Host smart-9d36b9f9-b14d-4bb0-a944-3a6c40ff31ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654711512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.3654711512
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.631641251
Short name T480
Test name
Test status
Simulation time 54422000 ps
CPU time 153.58 seconds
Started Jun 06 01:33:43 PM PDT 24
Finished Jun 06 01:36:17 PM PDT 24
Peak memory 262696 kb
Host smart-011c39da-29fa-4b40-a18d-9b18971a439c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=631641251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.631641251
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.2482066822
Short name T382
Test name
Test status
Simulation time 25335777800 ps
CPU time 199.88 seconds
Started Jun 06 01:33:49 PM PDT 24
Finished Jun 06 01:37:09 PM PDT 24
Peak memory 260072 kb
Host smart-8059a509-dc41-406c-8f08-f598c4e54675
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482066822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.2482066822
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.979619091
Short name T557
Test name
Test status
Simulation time 29697400 ps
CPU time 76.82 seconds
Started Jun 06 01:33:43 PM PDT 24
Finished Jun 06 01:35:01 PM PDT 24
Peak memory 269732 kb
Host smart-32be29c0-6995-4201-a368-6c0243de7e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979619091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.979619091
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.3279966994
Short name T320
Test name
Test status
Simulation time 234351900 ps
CPU time 35.75 seconds
Started Jun 06 01:33:46 PM PDT 24
Finished Jun 06 01:34:23 PM PDT 24
Peak memory 275208 kb
Host smart-9c29ae6d-9376-431f-80e9-a246229505c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279966994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.3279966994
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.367142549
Short name T213
Test name
Test status
Simulation time 6130526800 ps
CPU time 148.05 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:36:11 PM PDT 24
Peak memory 281644 kb
Host smart-91eee8ea-f9d2-445c-b727-c3398660db16
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367142549 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.flash_ctrl_ro.367142549
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.3038481089
Short name T873
Test name
Test status
Simulation time 4901592700 ps
CPU time 612.35 seconds
Started Jun 06 01:33:44 PM PDT 24
Finished Jun 06 01:43:57 PM PDT 24
Peak memory 314268 kb
Host smart-674212b6-0b13-494f-acee-d22de1adb2c6
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038481089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_rw.3038481089
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.3766893704
Short name T484
Test name
Test status
Simulation time 26788800 ps
CPU time 30.92 seconds
Started Jun 06 01:33:43 PM PDT 24
Finished Jun 06 01:34:15 PM PDT 24
Peak memory 273576 kb
Host smart-70070efb-b6a9-4a76-842d-87b1ad464949
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766893704 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.3766893704
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.1144284872
Short name T696
Test name
Test status
Simulation time 4396864400 ps
CPU time 71.75 seconds
Started Jun 06 01:33:45 PM PDT 24
Finished Jun 06 01:34:57 PM PDT 24
Peak memory 263368 kb
Host smart-d4a3b8b8-8038-45cf-a784-014334be2488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144284872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.1144284872
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.3537729398
Short name T498
Test name
Test status
Simulation time 483668700 ps
CPU time 100.27 seconds
Started Jun 06 01:33:46 PM PDT 24
Finished Jun 06 01:35:28 PM PDT 24
Peak memory 275952 kb
Host smart-5bebd6a6-fe67-4455-8b16-87411bfef094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537729398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.3537729398
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.3558107049
Short name T1012
Test name
Test status
Simulation time 13608857100 ps
CPU time 225 seconds
Started Jun 06 01:33:46 PM PDT 24
Finished Jun 06 01:37:32 PM PDT 24
Peak memory 265224 kb
Host smart-3d58f642-5b1d-49f5-9a29-6431c83e6780
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558107049 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.flash_ctrl_wo.3558107049
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.259003344
Short name T785
Test name
Test status
Simulation time 109183400 ps
CPU time 13.91 seconds
Started Jun 06 01:33:54 PM PDT 24
Finished Jun 06 01:34:08 PM PDT 24
Peak memory 265176 kb
Host smart-12d9f02d-21f4-4974-b75f-3cb17f8ab1a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259003344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.259003344
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.1792617857
Short name T837
Test name
Test status
Simulation time 107269300 ps
CPU time 16.21 seconds
Started Jun 06 01:33:51 PM PDT 24
Finished Jun 06 01:34:08 PM PDT 24
Peak memory 274796 kb
Host smart-2e85525f-cb12-471e-9276-8c244584f40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792617857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.1792617857
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.1643991158
Short name T583
Test name
Test status
Simulation time 15328800 ps
CPU time 22.74 seconds
Started Jun 06 01:33:53 PM PDT 24
Finished Jun 06 01:34:16 PM PDT 24
Peak memory 274944 kb
Host smart-b77da054-819c-4a97-b0d8-dc5383e9f6e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643991158 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.1643991158
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1054237333
Short name T872
Test name
Test status
Simulation time 10011863100 ps
CPU time 113.31 seconds
Started Jun 06 01:33:50 PM PDT 24
Finished Jun 06 01:35:44 PM PDT 24
Peak memory 312880 kb
Host smart-cb785f9c-d207-43f3-b87e-2c604061fd89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054237333 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.1054237333
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.1201491304
Short name T628
Test name
Test status
Simulation time 68209500 ps
CPU time 13.49 seconds
Started Jun 06 01:33:51 PM PDT 24
Finished Jun 06 01:34:06 PM PDT 24
Peak memory 259140 kb
Host smart-f3cb3f01-3f55-416e-9e3a-3970c1b070c9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201491304 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1201491304
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.1280806811
Short name T510
Test name
Test status
Simulation time 200201888800 ps
CPU time 873.48 seconds
Started Jun 06 01:33:47 PM PDT 24
Finished Jun 06 01:48:22 PM PDT 24
Peak memory 264104 kb
Host smart-ee08e3f0-6c9e-48ab-9ec2-669edfd984ff
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280806811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.1280806811
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.2407110526
Short name T474
Test name
Test status
Simulation time 2145559300 ps
CPU time 57.32 seconds
Started Jun 06 01:33:49 PM PDT 24
Finished Jun 06 01:34:47 PM PDT 24
Peak memory 262972 kb
Host smart-c0c8633d-7661-402a-8cf1-8131f658df32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407110526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_
hw_sec_otp.2407110526
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.2490767035
Short name T992
Test name
Test status
Simulation time 3349227600 ps
CPU time 201.35 seconds
Started Jun 06 01:33:48 PM PDT 24
Finished Jun 06 01:37:10 PM PDT 24
Peak memory 291164 kb
Host smart-6b4e27b1-02cd-4a54-aed0-60e194806260
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490767035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.2490767035
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3057984622
Short name T744
Test name
Test status
Simulation time 44959565700 ps
CPU time 183.13 seconds
Started Jun 06 01:33:46 PM PDT 24
Finished Jun 06 01:36:50 PM PDT 24
Peak memory 292332 kb
Host smart-e52f8634-6f37-4bbf-b222-7729c21c63a8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057984622 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.3057984622
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.860041001
Short name T412
Test name
Test status
Simulation time 2963635500 ps
CPU time 68.02 seconds
Started Jun 06 01:33:48 PM PDT 24
Finished Jun 06 01:34:57 PM PDT 24
Peak memory 260460 kb
Host smart-7a94fa21-8dc2-44da-b973-084d7fbc5950
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860041001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.860041001
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.1186264714
Short name T920
Test name
Test status
Simulation time 26533800 ps
CPU time 13.86 seconds
Started Jun 06 01:33:54 PM PDT 24
Finished Jun 06 01:34:09 PM PDT 24
Peak memory 264684 kb
Host smart-6488a58b-4367-4b83-ab09-e9f92b820828
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186264714 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.1186264714
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.2131328668
Short name T801
Test name
Test status
Simulation time 59348900600 ps
CPU time 674.33 seconds
Started Jun 06 01:33:46 PM PDT 24
Finished Jun 06 01:45:01 PM PDT 24
Peak memory 274212 kb
Host smart-f0a71318-8028-4ade-8f80-929b78a26503
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131328668 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.2131328668
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.389689907
Short name T706
Test name
Test status
Simulation time 728159800 ps
CPU time 464.36 seconds
Started Jun 06 01:33:46 PM PDT 24
Finished Jun 06 01:41:31 PM PDT 24
Peak memory 262900 kb
Host smart-efd572ef-8f28-441b-b86d-ae6689c9762e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=389689907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.389689907
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.1385189154
Short name T414
Test name
Test status
Simulation time 217492800 ps
CPU time 19.38 seconds
Started Jun 06 01:33:53 PM PDT 24
Finished Jun 06 01:34:13 PM PDT 24
Peak memory 265064 kb
Host smart-b196f68d-770a-407f-8353-a55f7e9a3435
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385189154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.1385189154
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.361017029
Short name T1073
Test name
Test status
Simulation time 393624200 ps
CPU time 459.62 seconds
Started Jun 06 01:33:47 PM PDT 24
Finished Jun 06 01:41:27 PM PDT 24
Peak memory 281556 kb
Host smart-67f0defb-0310-4f3c-9206-daaf919ec643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361017029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.361017029
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.1591064080
Short name T280
Test name
Test status
Simulation time 417657400 ps
CPU time 37.59 seconds
Started Jun 06 01:33:54 PM PDT 24
Finished Jun 06 01:34:33 PM PDT 24
Peak memory 275212 kb
Host smart-b2ac6c27-844d-4d20-b4f4-a3027270cdf9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591064080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.1591064080
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.2676051850
Short name T686
Test name
Test status
Simulation time 479088900 ps
CPU time 101.06 seconds
Started Jun 06 01:33:48 PM PDT 24
Finished Jun 06 01:35:29 PM PDT 24
Peak memory 289928 kb
Host smart-259b0daf-6ec4-481a-a0fc-60e07ea20191
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676051850 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_ro.2676051850
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.3987060877
Short name T210
Test name
Test status
Simulation time 14598448700 ps
CPU time 521.97 seconds
Started Jun 06 01:33:47 PM PDT 24
Finished Jun 06 01:42:30 PM PDT 24
Peak memory 314380 kb
Host smart-9d085028-3c6a-4fd5-8f92-5086021f7c67
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987060877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.3987060877
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.2722264585
Short name T1020
Test name
Test status
Simulation time 63664100 ps
CPU time 31.28 seconds
Started Jun 06 01:33:55 PM PDT 24
Finished Jun 06 01:34:27 PM PDT 24
Peak memory 273564 kb
Host smart-e1bfcf6e-d3b7-4d4c-8fa7-1ae77f14c5c0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722264585 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.2722264585
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.209767892
Short name T464
Test name
Test status
Simulation time 47769100 ps
CPU time 73.71 seconds
Started Jun 06 01:33:48 PM PDT 24
Finished Jun 06 01:35:02 PM PDT 24
Peak memory 276388 kb
Host smart-bef5d847-a614-47a6-ac9d-633527bba2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209767892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.209767892
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.2422093034
Short name T389
Test name
Test status
Simulation time 8930153200 ps
CPU time 218.61 seconds
Started Jun 06 01:33:47 PM PDT 24
Finished Jun 06 01:37:26 PM PDT 24
Peak memory 259764 kb
Host smart-c479786e-ddfe-4851-87c2-ce14c56be582
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422093034 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.flash_ctrl_wo.2422093034
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.4233331239
Short name T754
Test name
Test status
Simulation time 76180700 ps
CPU time 13.87 seconds
Started Jun 06 01:34:00 PM PDT 24
Finished Jun 06 01:34:15 PM PDT 24
Peak memory 257964 kb
Host smart-842e5675-2c71-4b3f-8a93-3bf5febfa2cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233331239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
4233331239
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.1912036988
Short name T455
Test name
Test status
Simulation time 17430800 ps
CPU time 15.57 seconds
Started Jun 06 01:33:57 PM PDT 24
Finished Jun 06 01:34:14 PM PDT 24
Peak memory 274760 kb
Host smart-31a5c443-c077-4fad-ba77-a4b244984ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912036988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.1912036988
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.299443833
Short name T642
Test name
Test status
Simulation time 28295800 ps
CPU time 22.32 seconds
Started Jun 06 01:33:56 PM PDT 24
Finished Jun 06 01:34:19 PM PDT 24
Peak memory 264628 kb
Host smart-efafad94-87c8-477d-908d-e8bd87d0ff69
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299443833 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.299443833
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.1460162766
Short name T720
Test name
Test status
Simulation time 26498100 ps
CPU time 13.85 seconds
Started Jun 06 01:33:53 PM PDT 24
Finished Jun 06 01:34:08 PM PDT 24
Peak memory 264596 kb
Host smart-859d6944-02a7-4b1b-8419-8c4d5500d62d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460162766 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.1460162766
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3878059673
Short name T308
Test name
Test status
Simulation time 4094722300 ps
CPU time 124.58 seconds
Started Jun 06 01:33:54 PM PDT 24
Finished Jun 06 01:36:00 PM PDT 24
Peak memory 262900 kb
Host smart-71241df1-d591-410a-99b9-1d95c59d4e0f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878059673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.3878059673
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.3529032883
Short name T751
Test name
Test status
Simulation time 1437228800 ps
CPU time 135.61 seconds
Started Jun 06 01:33:54 PM PDT 24
Finished Jun 06 01:36:11 PM PDT 24
Peak memory 293984 kb
Host smart-1fd037f3-7ab2-4e11-971a-573e3fcec625
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529032883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.3529032883
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.3053809011
Short name T338
Test name
Test status
Simulation time 12435331500 ps
CPU time 168.62 seconds
Started Jun 06 01:33:57 PM PDT 24
Finished Jun 06 01:36:47 PM PDT 24
Peak memory 293876 kb
Host smart-ed74eb36-fc21-4719-a2f5-748d0a698055
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053809011 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.3053809011
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.3681910526
Short name T91
Test name
Test status
Simulation time 5168593300 ps
CPU time 93.07 seconds
Started Jun 06 01:33:53 PM PDT 24
Finished Jun 06 01:35:27 PM PDT 24
Peak memory 263144 kb
Host smart-aadc2cc3-90eb-4618-bf3b-0f8fa243997b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681910526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3
681910526
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.49216201
Short name T887
Test name
Test status
Simulation time 38934300 ps
CPU time 113.08 seconds
Started Jun 06 01:33:53 PM PDT 24
Finished Jun 06 01:35:47 PM PDT 24
Peak memory 259980 kb
Host smart-1475c33b-6151-4ffe-8997-d547e9be02e5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49216201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_otp
_reset.49216201
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.510150029
Short name T226
Test name
Test status
Simulation time 1350976200 ps
CPU time 258.87 seconds
Started Jun 06 01:34:02 PM PDT 24
Finished Jun 06 01:38:22 PM PDT 24
Peak memory 262988 kb
Host smart-648d0fba-8054-4156-a56d-7371db8bab80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=510150029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.510150029
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.3960219901
Short name T790
Test name
Test status
Simulation time 8914696000 ps
CPU time 190.88 seconds
Started Jun 06 01:33:56 PM PDT 24
Finished Jun 06 01:37:09 PM PDT 24
Peak memory 264968 kb
Host smart-8543a4e9-4e1e-492c-8e06-030ebe3a540e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960219901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.3960219901
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.896051223
Short name T57
Test name
Test status
Simulation time 2085377300 ps
CPU time 589.07 seconds
Started Jun 06 01:33:51 PM PDT 24
Finished Jun 06 01:43:41 PM PDT 24
Peak memory 285884 kb
Host smart-25b970c9-6093-42da-baf6-76cd0d0ff218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896051223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.896051223
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.3171999626
Short name T907
Test name
Test status
Simulation time 120234700 ps
CPU time 38.73 seconds
Started Jun 06 01:33:52 PM PDT 24
Finished Jun 06 01:34:31 PM PDT 24
Peak memory 275688 kb
Host smart-ed489d19-2726-4831-8429-8a4564247935
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171999626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.3171999626
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.710075890
Short name T514
Test name
Test status
Simulation time 3251607900 ps
CPU time 125.15 seconds
Started Jun 06 01:33:56 PM PDT 24
Finished Jun 06 01:36:02 PM PDT 24
Peak memory 291144 kb
Host smart-7780857b-4d56-4e34-a095-6266377dda0f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710075890 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.flash_ctrl_ro.710075890
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.1003306551
Short name T161
Test name
Test status
Simulation time 293044600 ps
CPU time 31.86 seconds
Started Jun 06 01:33:56 PM PDT 24
Finished Jun 06 01:34:29 PM PDT 24
Peak memory 275620 kb
Host smart-442bd669-e484-4d6e-97af-7097a25184f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003306551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.1003306551
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.2578795277
Short name T857
Test name
Test status
Simulation time 241962400 ps
CPU time 101.05 seconds
Started Jun 06 01:33:55 PM PDT 24
Finished Jun 06 01:35:37 PM PDT 24
Peak memory 277272 kb
Host smart-ff45f547-32c2-4d11-8045-fa0bd34600ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578795277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2578795277
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.44346274
Short name T116
Test name
Test status
Simulation time 2383205300 ps
CPU time 214.16 seconds
Started Jun 06 01:33:51 PM PDT 24
Finished Jun 06 01:37:26 PM PDT 24
Peak memory 265184 kb
Host smart-36858405-ee29-4bb9-b2a1-1bf45dfd0f25
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44346274 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_wo.44346274
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.3203041277
Short name T97
Test name
Test status
Simulation time 236789000 ps
CPU time 15.11 seconds
Started Jun 06 01:34:06 PM PDT 24
Finished Jun 06 01:34:22 PM PDT 24
Peak memory 257988 kb
Host smart-a7b32718-8f39-4a27-affb-41e173a55091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203041277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
3203041277
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.478628177
Short name T844
Test name
Test status
Simulation time 15876800 ps
CPU time 16.43 seconds
Started Jun 06 01:33:59 PM PDT 24
Finished Jun 06 01:34:16 PM PDT 24
Peak memory 274628 kb
Host smart-866f2b75-acae-4dfb-9205-73f9253d423e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478628177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.478628177
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2004424569
Short name T291
Test name
Test status
Simulation time 10034139300 ps
CPU time 100.46 seconds
Started Jun 06 01:34:02 PM PDT 24
Finished Jun 06 01:35:43 PM PDT 24
Peak memory 269612 kb
Host smart-9a4663b7-075e-481e-b55f-28de80e4c538
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004424569 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.2004424569
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.3924694813
Short name T285
Test name
Test status
Simulation time 46789600 ps
CPU time 13.63 seconds
Started Jun 06 01:33:57 PM PDT 24
Finished Jun 06 01:34:12 PM PDT 24
Peak memory 258260 kb
Host smart-7fd746df-54b8-4967-b874-e10ab1be1986
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924694813 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.3924694813
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.2741383256
Short name T594
Test name
Test status
Simulation time 380336844800 ps
CPU time 1037.27 seconds
Started Jun 06 01:33:59 PM PDT 24
Finished Jun 06 01:51:17 PM PDT 24
Peak memory 263584 kb
Host smart-de345e17-ac71-4be0-820d-29056fa02274
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741383256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.2741383256
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.615362559
Short name T310
Test name
Test status
Simulation time 12511258300 ps
CPU time 129.92 seconds
Started Jun 06 01:33:52 PM PDT 24
Finished Jun 06 01:36:02 PM PDT 24
Peak memory 260704 kb
Host smart-a3083845-6869-46dc-b501-d453f07d8a43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615362559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_h
w_sec_otp.615362559
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.1147478890
Short name T8
Test name
Test status
Simulation time 6638161800 ps
CPU time 228.03 seconds
Started Jun 06 01:33:53 PM PDT 24
Finished Jun 06 01:37:43 PM PDT 24
Peak memory 284696 kb
Host smart-7cda36d8-d7c6-4275-a871-ce7a2aa146ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147478890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.1147478890
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3522701550
Short name T938
Test name
Test status
Simulation time 23787513100 ps
CPU time 141.53 seconds
Started Jun 06 01:33:55 PM PDT 24
Finished Jun 06 01:36:17 PM PDT 24
Peak memory 292332 kb
Host smart-8f79c490-7727-4c56-9b34-ebefe6e83ee3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522701550 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.3522701550
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.1605206210
Short name T660
Test name
Test status
Simulation time 32760942500 ps
CPU time 84.51 seconds
Started Jun 06 01:33:58 PM PDT 24
Finished Jun 06 01:35:23 PM PDT 24
Peak memory 262772 kb
Host smart-45c04e96-a18d-4c19-b0fd-33a01448c737
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605206210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.1
605206210
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.3437069897
Short name T709
Test name
Test status
Simulation time 47050500 ps
CPU time 13.64 seconds
Started Jun 06 01:33:57 PM PDT 24
Finished Jun 06 01:34:11 PM PDT 24
Peak memory 260660 kb
Host smart-12e81505-8334-4f05-9c7b-ef90f77ce524
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437069897 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.3437069897
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.1900466100
Short name T806
Test name
Test status
Simulation time 5335775500 ps
CPU time 148.12 seconds
Started Jun 06 01:33:55 PM PDT 24
Finished Jun 06 01:36:24 PM PDT 24
Peak memory 263532 kb
Host smart-e2da2f3d-1867-4301-9f0f-2e2637d61d90
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900466100 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.1900466100
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.4270505549
Short name T1042
Test name
Test status
Simulation time 35346300 ps
CPU time 112.85 seconds
Started Jun 06 01:33:56 PM PDT 24
Finished Jun 06 01:35:50 PM PDT 24
Peak memory 259676 kb
Host smart-0c6ccefb-9edb-473c-9ac9-4bf6406be26d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270505549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.4270505549
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.1807088367
Short name T843
Test name
Test status
Simulation time 4127489200 ps
CPU time 518.09 seconds
Started Jun 06 01:33:57 PM PDT 24
Finished Jun 06 01:42:36 PM PDT 24
Peak memory 262968 kb
Host smart-b62e910b-5112-4269-85ba-958e61faae4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1807088367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.1807088367
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.558348989
Short name T416
Test name
Test status
Simulation time 103868500 ps
CPU time 13.71 seconds
Started Jun 06 01:33:58 PM PDT 24
Finished Jun 06 01:34:12 PM PDT 24
Peak memory 258456 kb
Host smart-5482b92e-4e1b-4421-923d-5ab4b8840b7f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558348989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_res
et.558348989
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.3117498826
Short name T104
Test name
Test status
Simulation time 300396300 ps
CPU time 650.67 seconds
Started Jun 06 01:33:56 PM PDT 24
Finished Jun 06 01:44:48 PM PDT 24
Peak memory 285260 kb
Host smart-25bc67e9-71c5-4a09-a1e3-f89a6a564049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117498826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3117498826
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.2968319701
Short name T719
Test name
Test status
Simulation time 922976700 ps
CPU time 122.36 seconds
Started Jun 06 01:33:59 PM PDT 24
Finished Jun 06 01:36:02 PM PDT 24
Peak memory 288792 kb
Host smart-7d77a0c0-a3d5-4ed0-8e67-90faf327bb36
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968319701 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.flash_ctrl_ro.2968319701
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.1905550837
Short name T697
Test name
Test status
Simulation time 7591437900 ps
CPU time 580.38 seconds
Started Jun 06 01:33:59 PM PDT 24
Finished Jun 06 01:43:40 PM PDT 24
Peak memory 314416 kb
Host smart-222248d1-80d5-4bbe-937c-16f6ad42f676
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905550837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.1905550837
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.763874960
Short name T966
Test name
Test status
Simulation time 128804400 ps
CPU time 31.03 seconds
Started Jun 06 01:33:55 PM PDT 24
Finished Jun 06 01:34:26 PM PDT 24
Peak memory 273528 kb
Host smart-cff4630c-05dd-4e6c-8489-813b3077efc7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763874960 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.763874960
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.532308224
Short name T868
Test name
Test status
Simulation time 1026795300 ps
CPU time 61.91 seconds
Started Jun 06 01:34:00 PM PDT 24
Finished Jun 06 01:35:03 PM PDT 24
Peak memory 263776 kb
Host smart-8ae12cff-4b3d-4fae-acf0-2e38a73058c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532308224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.532308224
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.906512258
Short name T618
Test name
Test status
Simulation time 90218200 ps
CPU time 76.57 seconds
Started Jun 06 01:33:59 PM PDT 24
Finished Jun 06 01:35:17 PM PDT 24
Peak memory 275312 kb
Host smart-96a46614-b3bc-4b61-a529-1051131a0c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906512258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.906512258
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.1351848660
Short name T640
Test name
Test status
Simulation time 2221445700 ps
CPU time 174.85 seconds
Started Jun 06 01:33:54 PM PDT 24
Finished Jun 06 01:36:49 PM PDT 24
Peak memory 265228 kb
Host smart-1b20ba7e-1230-4fae-912a-0eb4dae988f0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351848660 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.1351848660
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.1195697244
Short name T906
Test name
Test status
Simulation time 23538100 ps
CPU time 13.56 seconds
Started Jun 06 01:34:07 PM PDT 24
Finished Jun 06 01:34:22 PM PDT 24
Peak memory 264828 kb
Host smart-d9079d2d-dfcf-4580-98d0-fb8409aedcc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195697244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
1195697244
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.3160754145
Short name T944
Test name
Test status
Simulation time 28204200 ps
CPU time 16.16 seconds
Started Jun 06 01:34:03 PM PDT 24
Finished Jun 06 01:34:19 PM PDT 24
Peak memory 274636 kb
Host smart-d4a9fd74-44fe-4385-a4d9-7db73459ae86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160754145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.3160754145
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.2212396480
Short name T896
Test name
Test status
Simulation time 11227400 ps
CPU time 21.89 seconds
Started Jun 06 01:33:59 PM PDT 24
Finished Jun 06 01:34:22 PM PDT 24
Peak memory 273456 kb
Host smart-89c07389-0985-4e64-b438-26ebf2400c92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212396480 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.2212396480
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.445606993
Short name T1068
Test name
Test status
Simulation time 10032637300 ps
CPU time 95.4 seconds
Started Jun 06 01:34:04 PM PDT 24
Finished Jun 06 01:35:40 PM PDT 24
Peak memory 267540 kb
Host smart-31e26379-ef98-4cde-9d36-d647cae5eebf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445606993 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.445606993
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.1500345563
Short name T1081
Test name
Test status
Simulation time 25525000 ps
CPU time 13.33 seconds
Started Jun 06 01:34:08 PM PDT 24
Finished Jun 06 01:34:22 PM PDT 24
Peak memory 259052 kb
Host smart-4b40c685-0fa9-4b24-9d62-adb53deaadc9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500345563 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.1500345563
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.2791140931
Short name T816
Test name
Test status
Simulation time 40127918300 ps
CPU time 871.4 seconds
Started Jun 06 01:34:08 PM PDT 24
Finished Jun 06 01:48:40 PM PDT 24
Peak memory 264188 kb
Host smart-c05ca702-f834-4a99-acd3-4453b6e1aa52
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791140931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.2791140931
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.820690191
Short name T1040
Test name
Test status
Simulation time 25442098700 ps
CPU time 327.27 seconds
Started Jun 06 01:34:03 PM PDT 24
Finished Jun 06 01:39:31 PM PDT 24
Peak memory 284748 kb
Host smart-5b39b045-5af5-46a4-9e95-cf9a2feca7a3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820690191 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.820690191
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3298375794
Short name T698
Test name
Test status
Simulation time 25639400 ps
CPU time 13.53 seconds
Started Jun 06 01:34:01 PM PDT 24
Finished Jun 06 01:34:15 PM PDT 24
Peak memory 264672 kb
Host smart-3bf72337-e796-4565-a557-01faebe2bfb3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298375794 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3298375794
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.3345803971
Short name T111
Test name
Test status
Simulation time 13497157800 ps
CPU time 209.85 seconds
Started Jun 06 01:34:02 PM PDT 24
Finished Jun 06 01:37:32 PM PDT 24
Peak memory 272424 kb
Host smart-49e33af6-2dfb-4834-9ddb-71358018ac0e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345803971 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.3345803971
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.669776267
Short name T793
Test name
Test status
Simulation time 141408200 ps
CPU time 135.66 seconds
Started Jun 06 01:34:02 PM PDT 24
Finished Jun 06 01:36:19 PM PDT 24
Peak memory 262184 kb
Host smart-d86001c2-f0bd-49e6-8053-faafb859c2a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669776267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ot
p_reset.669776267
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.1773615155
Short name T798
Test name
Test status
Simulation time 747210800 ps
CPU time 376.31 seconds
Started Jun 06 01:34:03 PM PDT 24
Finished Jun 06 01:40:20 PM PDT 24
Peak memory 262940 kb
Host smart-4beb1df4-fcce-4e32-a7ee-2e8d8c096116
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1773615155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.1773615155
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.1726065694
Short name T610
Test name
Test status
Simulation time 38813100 ps
CPU time 13.73 seconds
Started Jun 06 01:34:04 PM PDT 24
Finished Jun 06 01:34:18 PM PDT 24
Peak memory 265244 kb
Host smart-3c7af549-814b-40d7-bac8-2fcde5cd5fdb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726065694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_re
set.1726065694
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.236391797
Short name T113
Test name
Test status
Simulation time 108796400 ps
CPU time 523.49 seconds
Started Jun 06 01:34:00 PM PDT 24
Finished Jun 06 01:42:44 PM PDT 24
Peak memory 281484 kb
Host smart-092c572f-5d1e-4b51-87bb-318d19333536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236391797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.236391797
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.2913135891
Short name T624
Test name
Test status
Simulation time 216964800 ps
CPU time 38.03 seconds
Started Jun 06 01:34:01 PM PDT 24
Finished Jun 06 01:34:40 PM PDT 24
Peak memory 275204 kb
Host smart-4a5fc22a-e97c-46ed-849d-bcb5c793ac28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913135891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.2913135891
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.4283201098
Short name T95
Test name
Test status
Simulation time 2069379300 ps
CPU time 113.21 seconds
Started Jun 06 01:34:01 PM PDT 24
Finished Jun 06 01:35:55 PM PDT 24
Peak memory 280664 kb
Host smart-03e4bb65-c330-4a48-8ebb-9b8db817cff1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283201098 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_ro.4283201098
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.4078368805
Short name T7
Test name
Test status
Simulation time 7062484400 ps
CPU time 556.83 seconds
Started Jun 06 01:34:02 PM PDT 24
Finished Jun 06 01:43:20 PM PDT 24
Peak memory 309600 kb
Host smart-06a69b46-9b37-408e-8b3b-cda5931922a7
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078368805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_rw.4078368805
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.404197445
Short name T1043
Test name
Test status
Simulation time 709064900 ps
CPU time 73.14 seconds
Started Jun 06 01:34:04 PM PDT 24
Finished Jun 06 01:35:18 PM PDT 24
Peak memory 262700 kb
Host smart-e65786b2-a9ec-4677-8811-2fae1ad3d48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404197445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.404197445
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.469950794
Short name T383
Test name
Test status
Simulation time 25674200 ps
CPU time 120.92 seconds
Started Jun 06 01:34:00 PM PDT 24
Finished Jun 06 01:36:01 PM PDT 24
Peak memory 276220 kb
Host smart-a66baceb-0490-40f4-bdba-7d0f93042cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469950794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.469950794
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.4038191083
Short name T777
Test name
Test status
Simulation time 2015704100 ps
CPU time 178.57 seconds
Started Jun 06 01:34:06 PM PDT 24
Finished Jun 06 01:37:06 PM PDT 24
Peak memory 265260 kb
Host smart-76056860-6aa4-4135-8b99-d655ecc631b6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038191083 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.flash_ctrl_wo.4038191083
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.3012401835
Short name T1082
Test name
Test status
Simulation time 316501600 ps
CPU time 14.56 seconds
Started Jun 06 01:34:08 PM PDT 24
Finished Jun 06 01:34:23 PM PDT 24
Peak memory 265196 kb
Host smart-6f196eff-985f-4bb0-accc-9af317a6dcaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012401835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
3012401835
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.760897826
Short name T622
Test name
Test status
Simulation time 51815100 ps
CPU time 16.22 seconds
Started Jun 06 01:34:07 PM PDT 24
Finished Jun 06 01:34:24 PM PDT 24
Peak memory 274552 kb
Host smart-0d4773f2-3915-4423-a413-7172371a072d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760897826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.760897826
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.2954155020
Short name T810
Test name
Test status
Simulation time 10582200 ps
CPU time 22.52 seconds
Started Jun 06 01:34:09 PM PDT 24
Finished Jun 06 01:34:32 PM PDT 24
Peak memory 273536 kb
Host smart-2720d2e0-75ea-4a18-9786-e72e1fb12eaf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954155020 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.2954155020
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2377760134
Short name T727
Test name
Test status
Simulation time 10019746300 ps
CPU time 98.8 seconds
Started Jun 06 01:34:08 PM PDT 24
Finished Jun 06 01:35:48 PM PDT 24
Peak memory 330528 kb
Host smart-9f70e6f7-09f2-428e-8bf8-04633704d595
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377760134 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.2377760134
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.2708671780
Short name T913
Test name
Test status
Simulation time 106191600 ps
CPU time 13.84 seconds
Started Jun 06 01:34:10 PM PDT 24
Finished Jun 06 01:34:24 PM PDT 24
Peak memory 259060 kb
Host smart-ac634d13-aa7b-4492-8dd3-b55b8fb03974
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708671780 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.2708671780
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.1578379069
Short name T625
Test name
Test status
Simulation time 160157689300 ps
CPU time 856.98 seconds
Started Jun 06 01:34:07 PM PDT 24
Finished Jun 06 01:48:25 PM PDT 24
Peak memory 264148 kb
Host smart-22f165cc-790d-46a9-9931-90a6ccaa7040
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578379069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.1578379069
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.2512334205
Short name T164
Test name
Test status
Simulation time 3089978900 ps
CPU time 176.49 seconds
Started Jun 06 01:34:06 PM PDT 24
Finished Jun 06 01:37:04 PM PDT 24
Peak memory 262416 kb
Host smart-fbfd54ca-2d96-45b7-bb5a-3a84b068ebe4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512334205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.2512334205
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.3363153158
Short name T335
Test name
Test status
Simulation time 2187087300 ps
CPU time 163.75 seconds
Started Jun 06 01:34:10 PM PDT 24
Finished Jun 06 01:36:54 PM PDT 24
Peak memory 294560 kb
Host smart-6e81543f-7463-46d3-b56f-b687a6819003
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363153158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.3363153158
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3761600904
Short name T779
Test name
Test status
Simulation time 23816796000 ps
CPU time 127.29 seconds
Started Jun 06 01:34:10 PM PDT 24
Finished Jun 06 01:36:18 PM PDT 24
Peak memory 292188 kb
Host smart-3aac0ece-759d-4c4b-8b97-0cacd702ad15
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761600904 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.3761600904
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.221791076
Short name T106
Test name
Test status
Simulation time 1629986900 ps
CPU time 75.21 seconds
Started Jun 06 01:34:06 PM PDT 24
Finished Jun 06 01:35:22 PM PDT 24
Peak memory 260368 kb
Host smart-19f0033c-32c3-4d48-b6c1-1eb25e812073
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221791076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.221791076
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2510995193
Short name T544
Test name
Test status
Simulation time 45762800 ps
CPU time 13.75 seconds
Started Jun 06 01:34:07 PM PDT 24
Finished Jun 06 01:34:22 PM PDT 24
Peak memory 264556 kb
Host smart-3a294ee7-3353-47e5-a0a0-c637b4827d30
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510995193 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.2510995193
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.3728244741
Short name T84
Test name
Test status
Simulation time 41275329300 ps
CPU time 336.87 seconds
Started Jun 06 01:34:07 PM PDT 24
Finished Jun 06 01:39:45 PM PDT 24
Peak memory 273576 kb
Host smart-be50240c-bfc1-4786-84d4-0743cb44de21
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728244741 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.3728244741
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.490931662
Short name T939
Test name
Test status
Simulation time 1898093500 ps
CPU time 377.85 seconds
Started Jun 06 01:34:07 PM PDT 24
Finished Jun 06 01:40:25 PM PDT 24
Peak memory 261944 kb
Host smart-02627b99-6335-4fa8-b945-6742c3f9ff68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=490931662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.490931662
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.1643812819
Short name T1047
Test name
Test status
Simulation time 62809200 ps
CPU time 14.1 seconds
Started Jun 06 01:34:07 PM PDT 24
Finished Jun 06 01:34:23 PM PDT 24
Peak memory 258396 kb
Host smart-14ba812b-f699-46bf-b443-0d01ef410167
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643812819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.1643812819
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.2589185069
Short name T99
Test name
Test status
Simulation time 163280500 ps
CPU time 258.97 seconds
Started Jun 06 01:34:09 PM PDT 24
Finished Jun 06 01:38:29 PM PDT 24
Peak memory 277956 kb
Host smart-20ac5d3e-126b-4940-aaaf-49e81051c76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589185069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2589185069
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.3666194701
Short name T517
Test name
Test status
Simulation time 176874000 ps
CPU time 37.65 seconds
Started Jun 06 01:34:09 PM PDT 24
Finished Jun 06 01:34:47 PM PDT 24
Peak memory 275540 kb
Host smart-73b00d78-a926-4c2d-8688-0a7474c02bf5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666194701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.3666194701
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.2533100515
Short name T1048
Test name
Test status
Simulation time 1074442800 ps
CPU time 129.49 seconds
Started Jun 06 01:34:10 PM PDT 24
Finished Jun 06 01:36:20 PM PDT 24
Peak memory 280808 kb
Host smart-efd48955-cb63-4055-b885-448dbe42ff6c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533100515 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.2533100515
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.3523145059
Short name T208
Test name
Test status
Simulation time 3560847300 ps
CPU time 562.39 seconds
Started Jun 06 01:34:11 PM PDT 24
Finished Jun 06 01:43:34 PM PDT 24
Peak memory 314316 kb
Host smart-7e8c0dc3-6607-45ae-a200-a5ddf4fae38e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523145059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_rw.3523145059
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.2546922233
Short name T163
Test name
Test status
Simulation time 48183600 ps
CPU time 31.82 seconds
Started Jun 06 01:34:09 PM PDT 24
Finished Jun 06 01:34:42 PM PDT 24
Peak memory 277428 kb
Host smart-1e0638c2-be43-43f9-b2e0-34707cfcd0da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546922233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.2546922233
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.2641402188
Short name T429
Test name
Test status
Simulation time 56703300 ps
CPU time 31.13 seconds
Started Jun 06 01:34:20 PM PDT 24
Finished Jun 06 01:34:51 PM PDT 24
Peak memory 267436 kb
Host smart-e5b794ca-27aa-4d03-abed-00dd3c923d87
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641402188 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.2641402188
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.26939297
Short name T1085
Test name
Test status
Simulation time 5374785900 ps
CPU time 70.07 seconds
Started Jun 06 01:34:11 PM PDT 24
Finished Jun 06 01:35:22 PM PDT 24
Peak memory 264412 kb
Host smart-dffa9a24-2cba-4935-82db-ab8facd53a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26939297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.26939297
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.547693769
Short name T548
Test name
Test status
Simulation time 36088700 ps
CPU time 125.29 seconds
Started Jun 06 01:34:07 PM PDT 24
Finished Jun 06 01:36:13 PM PDT 24
Peak memory 277020 kb
Host smart-2dd1fa22-2cfd-450c-b597-0949b9ae4f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547693769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.547693769
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.993016004
Short name T677
Test name
Test status
Simulation time 5089486600 ps
CPU time 201.51 seconds
Started Jun 06 01:34:07 PM PDT 24
Finished Jun 06 01:37:30 PM PDT 24
Peak memory 265004 kb
Host smart-3f16bdb7-f900-4560-a8c0-62fd4ba40826
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993016004 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.flash_ctrl_wo.993016004
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.517186306
Short name T554
Test name
Test status
Simulation time 126976100 ps
CPU time 13.94 seconds
Started Jun 06 01:34:32 PM PDT 24
Finished Jun 06 01:34:47 PM PDT 24
Peak memory 264764 kb
Host smart-c3ca833a-cdbc-4a2c-b74f-4bd016b08303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517186306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.517186306
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.389290936
Short name T832
Test name
Test status
Simulation time 81667100 ps
CPU time 15.82 seconds
Started Jun 06 01:34:26 PM PDT 24
Finished Jun 06 01:34:42 PM PDT 24
Peak memory 274832 kb
Host smart-b5327be0-aa2f-4b88-b4b6-0d7c51e66378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389290936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.389290936
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.1061179313
Short name T1033
Test name
Test status
Simulation time 29601400 ps
CPU time 22.08 seconds
Started Jun 06 01:34:27 PM PDT 24
Finished Jun 06 01:34:50 PM PDT 24
Peak memory 265628 kb
Host smart-e1bbb8c7-f822-450b-82f8-d8e40a1956d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061179313 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.1061179313
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.4056278142
Short name T193
Test name
Test status
Simulation time 10039426100 ps
CPU time 61.25 seconds
Started Jun 06 01:34:30 PM PDT 24
Finished Jun 06 01:35:32 PM PDT 24
Peak memory 288856 kb
Host smart-ded67213-a439-4c98-a6ca-226271520595
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056278142 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.4056278142
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.200455891
Short name T1091
Test name
Test status
Simulation time 15584600 ps
CPU time 13.42 seconds
Started Jun 06 01:34:29 PM PDT 24
Finished Jun 06 01:34:43 PM PDT 24
Peak memory 258220 kb
Host smart-5df1abe3-2e5b-4fa0-8b5a-52ae2016c6a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200455891 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.200455891
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.3970633275
Short name T157
Test name
Test status
Simulation time 120158584200 ps
CPU time 952.06 seconds
Started Jun 06 01:34:16 PM PDT 24
Finished Jun 06 01:50:08 PM PDT 24
Peak memory 261880 kb
Host smart-cc192c4e-118d-4657-8f42-ea91b59a6f40
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970633275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.3970633275
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.2574131018
Short name T995
Test name
Test status
Simulation time 2103473000 ps
CPU time 80.01 seconds
Started Jun 06 01:34:18 PM PDT 24
Finished Jun 06 01:35:38 PM PDT 24
Peak memory 262732 kb
Host smart-bb01c63f-9eff-4c44-bdef-d3a7b3f054aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574131018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.2574131018
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.1364598846
Short name T282
Test name
Test status
Simulation time 3644362100 ps
CPU time 209.17 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:40:32 PM PDT 24
Peak memory 290948 kb
Host smart-de7dee6c-cb3f-4906-9363-c2661d9c9b3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364598846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.1364598846
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2275652986
Short name T823
Test name
Test status
Simulation time 12212956000 ps
CPU time 259.32 seconds
Started Jun 06 01:34:27 PM PDT 24
Finished Jun 06 01:38:47 PM PDT 24
Peak memory 289812 kb
Host smart-4dc15179-f600-4562-91d2-de55d1052fa9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275652986 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.2275652986
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.689371647
Short name T799
Test name
Test status
Simulation time 3864308100 ps
CPU time 77.53 seconds
Started Jun 06 01:34:23 PM PDT 24
Finished Jun 06 01:35:41 PM PDT 24
Peak memory 263072 kb
Host smart-8cedb040-20e6-4ba5-89cf-f46064aa4e69
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689371647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.689371647
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.2170077336
Short name T428
Test name
Test status
Simulation time 94010900 ps
CPU time 13.46 seconds
Started Jun 06 01:34:31 PM PDT 24
Finished Jun 06 01:34:45 PM PDT 24
Peak memory 259504 kb
Host smart-ae5e9a16-5983-4dc1-83c9-38d111526bb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170077336 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.2170077336
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.904273143
Short name T1055
Test name
Test status
Simulation time 16791116600 ps
CPU time 431.44 seconds
Started Jun 06 01:34:17 PM PDT 24
Finished Jun 06 01:41:29 PM PDT 24
Peak memory 273072 kb
Host smart-47b21ef9-019e-4056-ae34-35819a695d62
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904273143 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_mp_regions.904273143
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.2435468747
Short name T818
Test name
Test status
Simulation time 39308500 ps
CPU time 132.14 seconds
Started Jun 06 01:34:15 PM PDT 24
Finished Jun 06 01:36:28 PM PDT 24
Peak memory 259912 kb
Host smart-a906f83f-bc16-4864-8f44-44d688420963
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435468747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.2435468747
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.1597684500
Short name T476
Test name
Test status
Simulation time 5604316300 ps
CPU time 132.29 seconds
Started Jun 06 01:34:16 PM PDT 24
Finished Jun 06 01:36:29 PM PDT 24
Peak memory 262864 kb
Host smart-769bd657-91df-4f2a-9fc8-dc960121362c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1597684500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1597684500
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.15561438
Short name T941
Test name
Test status
Simulation time 118213700 ps
CPU time 13.87 seconds
Started Jun 06 01:34:31 PM PDT 24
Finished Jun 06 01:34:45 PM PDT 24
Peak memory 258472 kb
Host smart-5bb0f407-7230-4ed7-8600-9bc2ace28c53
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15561438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_rese
t.15561438
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.2729390451
Short name T115
Test name
Test status
Simulation time 78793800 ps
CPU time 379.49 seconds
Started Jun 06 01:34:17 PM PDT 24
Finished Jun 06 01:40:37 PM PDT 24
Peak memory 281544 kb
Host smart-96b3203e-62d7-4254-ab58-84521d543a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729390451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2729390451
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.3727832462
Short name T605
Test name
Test status
Simulation time 782701400 ps
CPU time 125.37 seconds
Started Jun 06 01:34:22 PM PDT 24
Finished Jun 06 01:36:28 PM PDT 24
Peak memory 281720 kb
Host smart-a534654b-c43a-4af7-94f0-d07ca509d9e7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727832462 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.flash_ctrl_ro.3727832462
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.1578217033
Short name T50
Test name
Test status
Simulation time 4116042500 ps
CPU time 628.31 seconds
Started Jun 06 01:34:17 PM PDT 24
Finished Jun 06 01:44:46 PM PDT 24
Peak memory 309012 kb
Host smart-5fd660cc-62b8-4ef5-a788-ac7dc8a150f3
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578217033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.flash_ctrl_rw.1578217033
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.2020236411
Short name T190
Test name
Test status
Simulation time 51422200 ps
CPU time 31.72 seconds
Started Jun 06 01:34:27 PM PDT 24
Finished Jun 06 01:34:59 PM PDT 24
Peak memory 276340 kb
Host smart-047360d7-8da5-4e0e-96ed-2949091dbca5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020236411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_rw_evict.2020236411
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.2292552741
Short name T833
Test name
Test status
Simulation time 27666800 ps
CPU time 31.23 seconds
Started Jun 06 01:34:27 PM PDT 24
Finished Jun 06 01:34:59 PM PDT 24
Peak memory 273528 kb
Host smart-abb87c92-20d4-4cdd-813c-1e402b367e8b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292552741 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.2292552741
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.2043955181
Short name T984
Test name
Test status
Simulation time 8410649200 ps
CPU time 68.89 seconds
Started Jun 06 01:34:27 PM PDT 24
Finished Jun 06 01:35:37 PM PDT 24
Peak memory 262868 kb
Host smart-af528505-1a84-4b63-9e27-3ded46d75ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043955181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.2043955181
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.3513998141
Short name T457
Test name
Test status
Simulation time 25921500 ps
CPU time 76.81 seconds
Started Jun 06 01:34:15 PM PDT 24
Finished Jun 06 01:35:32 PM PDT 24
Peak memory 275412 kb
Host smart-a044f66f-eaeb-41b9-b7fd-23175afe5646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513998141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.3513998141
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.347194551
Short name T520
Test name
Test status
Simulation time 4614089700 ps
CPU time 159.35 seconds
Started Jun 06 01:34:18 PM PDT 24
Finished Jun 06 01:36:59 PM PDT 24
Peak memory 260828 kb
Host smart-7df550d7-64ea-43ba-8889-88eed6710d37
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347194551 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.flash_ctrl_wo.347194551
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.3372738090
Short name T989
Test name
Test status
Simulation time 51938500 ps
CPU time 13.68 seconds
Started Jun 06 01:34:43 PM PDT 24
Finished Jun 06 01:34:57 PM PDT 24
Peak memory 258012 kb
Host smart-18946752-cb90-41e5-9269-93a84065ceb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372738090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
3372738090
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.3817794635
Short name T692
Test name
Test status
Simulation time 14828800 ps
CPU time 16.17 seconds
Started Jun 06 01:34:37 PM PDT 24
Finished Jun 06 01:34:54 PM PDT 24
Peak memory 274692 kb
Host smart-f5a60ea6-92f8-4b5d-bc2e-968e0a65854d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817794635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.3817794635
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.2799945686
Short name T364
Test name
Test status
Simulation time 25261400 ps
CPU time 22.28 seconds
Started Jun 06 01:34:38 PM PDT 24
Finished Jun 06 01:35:01 PM PDT 24
Peak memory 273552 kb
Host smart-1440e01f-1a3d-4490-9839-a000ac6c0f89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799945686 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.2799945686
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1384483813
Short name T156
Test name
Test status
Simulation time 10012581400 ps
CPU time 154.81 seconds
Started Jun 06 01:34:46 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 398624 kb
Host smart-485d40b2-4713-41e1-b823-9be503ddba2e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384483813 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.1384483813
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.3351607352
Short name T1067
Test name
Test status
Simulation time 65167700 ps
CPU time 13.51 seconds
Started Jun 06 01:34:38 PM PDT 24
Finished Jun 06 01:34:52 PM PDT 24
Peak memory 259056 kb
Host smart-f2e2e5f4-7228-4a69-9ef7-1091d710c988
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351607352 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.3351607352
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.42667095
Short name T998
Test name
Test status
Simulation time 40126279800 ps
CPU time 888 seconds
Started Jun 06 01:34:36 PM PDT 24
Finished Jun 06 01:49:25 PM PDT 24
Peak memory 263940 kb
Host smart-8732c8c9-62a5-46b0-9ab8-62adffe10162
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42667095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 18.flash_ctrl_hw_rma_reset.42667095
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.4000095658
Short name T1062
Test name
Test status
Simulation time 5194677900 ps
CPU time 68.01 seconds
Started Jun 06 01:34:35 PM PDT 24
Finished Jun 06 01:35:44 PM PDT 24
Peak memory 262824 kb
Host smart-29e14600-3678-4f7b-96bc-24b9b560178c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000095658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.4000095658
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.1661448993
Short name T827
Test name
Test status
Simulation time 1999438400 ps
CPU time 230.11 seconds
Started Jun 06 01:34:36 PM PDT 24
Finished Jun 06 01:38:27 PM PDT 24
Peak memory 291064 kb
Host smart-4204a090-26b7-4c70-915b-040f663af14a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661448993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.1661448993
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1012934157
Short name T975
Test name
Test status
Simulation time 23754673700 ps
CPU time 169.55 seconds
Started Jun 06 01:34:38 PM PDT 24
Finished Jun 06 01:37:28 PM PDT 24
Peak memory 290892 kb
Host smart-dfba3d3c-b5e2-4853-ba4a-45f459ab7189
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012934157 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.1012934157
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.468390402
Short name T656
Test name
Test status
Simulation time 1708571700 ps
CPU time 69.93 seconds
Started Jun 06 01:34:36 PM PDT 24
Finished Jun 06 01:35:47 PM PDT 24
Peak memory 260136 kb
Host smart-6d3fa6f4-9851-4ecd-b2f9-767591c473ab
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468390402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.468390402
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.1890087592
Short name T681
Test name
Test status
Simulation time 15714300 ps
CPU time 13.4 seconds
Started Jun 06 01:34:37 PM PDT 24
Finished Jun 06 01:34:51 PM PDT 24
Peak memory 259540 kb
Host smart-212aac7f-0de2-456a-b982-e866d1fa8eef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890087592 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.1890087592
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.2678700759
Short name T109
Test name
Test status
Simulation time 70780189300 ps
CPU time 322.35 seconds
Started Jun 06 01:34:37 PM PDT 24
Finished Jun 06 01:40:00 PM PDT 24
Peak memory 274376 kb
Host smart-33b013bf-4e4d-464e-9def-a95497acade7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678700759 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.2678700759
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.2430127356
Short name T658
Test name
Test status
Simulation time 43518700 ps
CPU time 111.11 seconds
Started Jun 06 01:34:36 PM PDT 24
Finished Jun 06 01:36:28 PM PDT 24
Peak memory 260740 kb
Host smart-6b116014-c835-462b-951e-fb6295e5e3fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430127356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.2430127356
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.2352714685
Short name T413
Test name
Test status
Simulation time 595105800 ps
CPU time 437.85 seconds
Started Jun 06 01:34:26 PM PDT 24
Finished Jun 06 01:41:45 PM PDT 24
Peak memory 262996 kb
Host smart-b941e69c-9b05-41bc-b336-1d937a878f3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352714685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.2352714685
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.620519506
Short name T946
Test name
Test status
Simulation time 66716800 ps
CPU time 13.68 seconds
Started Jun 06 01:34:36 PM PDT 24
Finished Jun 06 01:34:51 PM PDT 24
Peak memory 258432 kb
Host smart-5e030e29-e620-45ce-a6bf-d80668929d76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620519506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_res
et.620519506
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.3064004480
Short name T1060
Test name
Test status
Simulation time 1477252000 ps
CPU time 777.65 seconds
Started Jun 06 01:34:27 PM PDT 24
Finished Jun 06 01:47:26 PM PDT 24
Peak memory 285700 kb
Host smart-b13ae50a-4a57-4441-90da-e5375f1d93ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064004480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.3064004480
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.1477434522
Short name T626
Test name
Test status
Simulation time 1198428800 ps
CPU time 111.4 seconds
Started Jun 06 01:34:35 PM PDT 24
Finished Jun 06 01:36:27 PM PDT 24
Peak memory 289872 kb
Host smart-b1821055-6174-4666-b466-ac419e015048
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477434522 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.1477434522
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.3475148862
Short name T522
Test name
Test status
Simulation time 65417300 ps
CPU time 30.89 seconds
Started Jun 06 01:34:37 PM PDT 24
Finished Jun 06 01:35:09 PM PDT 24
Peak memory 275176 kb
Host smart-1da7b68f-ee23-4ca2-88f8-41c7c9d5bf69
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475148862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_rw_evict.3475148862
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.3851535045
Short name T784
Test name
Test status
Simulation time 31029100 ps
CPU time 31.81 seconds
Started Jun 06 01:34:36 PM PDT 24
Finished Jun 06 01:35:08 PM PDT 24
Peak memory 273552 kb
Host smart-2630ae7d-bc51-442a-8dd1-7a6fc7abf963
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851535045 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.3851535045
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.1537136347
Short name T890
Test name
Test status
Simulation time 2754776100 ps
CPU time 70 seconds
Started Jun 06 01:34:36 PM PDT 24
Finished Jun 06 01:35:47 PM PDT 24
Peak memory 263392 kb
Host smart-581e41d0-a7cd-4029-b226-9cbeabe8b0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537136347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.1537136347
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.1970742325
Short name T572
Test name
Test status
Simulation time 105876700 ps
CPU time 124.57 seconds
Started Jun 06 01:34:32 PM PDT 24
Finished Jun 06 01:36:37 PM PDT 24
Peak memory 276468 kb
Host smart-afbfd4fa-65f9-4653-be18-b5b01327b251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970742325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.1970742325
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.2644602895
Short name T741
Test name
Test status
Simulation time 2531722000 ps
CPU time 165.51 seconds
Started Jun 06 01:34:35 PM PDT 24
Finished Jun 06 01:37:21 PM PDT 24
Peak memory 259648 kb
Host smart-62755474-2d6c-4a32-9202-bff49ec7d6bc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644602895 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.2644602895
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.1909712524
Short name T433
Test name
Test status
Simulation time 22935600 ps
CPU time 13.73 seconds
Started Jun 06 01:35:01 PM PDT 24
Finished Jun 06 01:35:15 PM PDT 24
Peak memory 265160 kb
Host smart-bc22df37-c6ee-4e9f-96a1-9e8984f5a6d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909712524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
1909712524
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.799197032
Short name T2
Test name
Test status
Simulation time 14080700 ps
CPU time 15.76 seconds
Started Jun 06 01:34:50 PM PDT 24
Finished Jun 06 01:35:06 PM PDT 24
Peak memory 274768 kb
Host smart-5c5b8f1b-cfa9-4382-b635-541478e225bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799197032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.799197032
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.4257137483
Short name T971
Test name
Test status
Simulation time 12520400 ps
CPU time 22.51 seconds
Started Jun 06 01:34:46 PM PDT 24
Finished Jun 06 01:35:09 PM PDT 24
Peak memory 273776 kb
Host smart-573129d0-34c4-401a-af0b-db2cc30bc40d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257137483 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.4257137483
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.239354223
Short name T289
Test name
Test status
Simulation time 10018442500 ps
CPU time 83.41 seconds
Started Jun 06 01:34:46 PM PDT 24
Finished Jun 06 01:36:11 PM PDT 24
Peak memory 291696 kb
Host smart-06da2905-99f0-4795-81d6-ca62d76452a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239354223 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.239354223
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.1356279263
Short name T963
Test name
Test status
Simulation time 15320000 ps
CPU time 13.94 seconds
Started Jun 06 01:34:46 PM PDT 24
Finished Jun 06 01:35:01 PM PDT 24
Peak memory 258256 kb
Host smart-1248a48d-2b13-4c1f-8eb5-54abeed7a6fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356279263 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.1356279263
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.1963179514
Short name T655
Test name
Test status
Simulation time 160176422100 ps
CPU time 932.36 seconds
Started Jun 06 01:34:48 PM PDT 24
Finished Jun 06 01:50:21 PM PDT 24
Peak memory 263916 kb
Host smart-2d02c473-445f-4d5e-bef9-924841105158
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963179514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.1963179514
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.212416214
Short name T688
Test name
Test status
Simulation time 643864900 ps
CPU time 64.74 seconds
Started Jun 06 01:34:46 PM PDT 24
Finished Jun 06 01:35:51 PM PDT 24
Peak memory 262976 kb
Host smart-44d91d07-6d88-41f7-98e0-806502e924eb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212416214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_h
w_sec_otp.212416214
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.944299274
Short name T582
Test name
Test status
Simulation time 655975500 ps
CPU time 138.91 seconds
Started Jun 06 01:34:47 PM PDT 24
Finished Jun 06 01:37:06 PM PDT 24
Peak memory 291084 kb
Host smart-6f3b9c03-3f5b-47d1-91ec-64838ee0d719
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944299274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flas
h_ctrl_intr_rd.944299274
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.446037927
Short name T1001
Test name
Test status
Simulation time 17417209900 ps
CPU time 496.85 seconds
Started Jun 06 01:34:47 PM PDT 24
Finished Jun 06 01:43:05 PM PDT 24
Peak memory 291124 kb
Host smart-f6b25302-fe06-488d-8075-5f86fd555ddd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446037927 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.446037927
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.2155417639
Short name T977
Test name
Test status
Simulation time 2134640800 ps
CPU time 67.67 seconds
Started Jun 06 01:34:44 PM PDT 24
Finished Jun 06 01:35:52 PM PDT 24
Peak memory 262896 kb
Host smart-31220847-5e84-43b1-b0e5-c373ae6b7fbd
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155417639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2
155417639
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.1826723376
Short name T667
Test name
Test status
Simulation time 26600700 ps
CPU time 13.49 seconds
Started Jun 06 01:34:49 PM PDT 24
Finished Jun 06 01:35:03 PM PDT 24
Peak memory 260396 kb
Host smart-dd17b8fd-9e35-407a-94dd-2ce3c8456b41
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826723376 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.1826723376
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.1524153215
Short name T716
Test name
Test status
Simulation time 8046402900 ps
CPU time 184.22 seconds
Started Jun 06 01:34:48 PM PDT 24
Finished Jun 06 01:37:53 PM PDT 24
Peak memory 265120 kb
Host smart-e6c638a2-d57d-41da-a3a9-1fc0aefd9542
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524153215 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.1524153215
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.530469198
Short name T968
Test name
Test status
Simulation time 88176800 ps
CPU time 137 seconds
Started Jun 06 01:34:46 PM PDT 24
Finished Jun 06 01:37:04 PM PDT 24
Peak memory 260844 kb
Host smart-1d4744d1-2541-4ae3-9ab8-c558cc9a6849
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530469198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ot
p_reset.530469198
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.3662233792
Short name T218
Test name
Test status
Simulation time 5564442700 ps
CPU time 573.38 seconds
Started Jun 06 01:34:44 PM PDT 24
Finished Jun 06 01:44:18 PM PDT 24
Peak memory 262920 kb
Host smart-7ad2f18a-e555-4377-a468-c4c1fdfde412
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3662233792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.3662233792
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.2877754875
Short name T829
Test name
Test status
Simulation time 59399000 ps
CPU time 13.97 seconds
Started Jun 06 01:34:44 PM PDT 24
Finished Jun 06 01:34:59 PM PDT 24
Peak memory 265072 kb
Host smart-b856cff0-38d6-4e96-87c1-2b5dbb7586a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877754875 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.2877754875
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.793328038
Short name T771
Test name
Test status
Simulation time 2110032300 ps
CPU time 961.34 seconds
Started Jun 06 01:34:48 PM PDT 24
Finished Jun 06 01:50:50 PM PDT 24
Peak memory 287072 kb
Host smart-c67abc52-96c4-4d23-a7eb-bb7d7796cb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793328038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.793328038
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.2594602109
Short name T527
Test name
Test status
Simulation time 215631900 ps
CPU time 39.13 seconds
Started Jun 06 01:34:47 PM PDT 24
Finished Jun 06 01:35:27 PM PDT 24
Peak memory 275184 kb
Host smart-d187fcff-711d-4a46-a7e3-a2515fab3c17
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594602109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.2594602109
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.2334014337
Short name T203
Test name
Test status
Simulation time 1701290400 ps
CPU time 108.93 seconds
Started Jun 06 01:34:45 PM PDT 24
Finished Jun 06 01:36:34 PM PDT 24
Peak memory 289876 kb
Host smart-c57719bb-4bd4-4bd9-b089-a75086f26ffa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334014337 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.flash_ctrl_ro.2334014337
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.3982335724
Short name T817
Test name
Test status
Simulation time 7876976900 ps
CPU time 523.3 seconds
Started Jun 06 01:34:45 PM PDT 24
Finished Jun 06 01:43:29 PM PDT 24
Peak memory 314044 kb
Host smart-0cb85ce6-798e-4358-881c-5ae52da55588
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982335724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.3982335724
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.2170617275
Short name T1070
Test name
Test status
Simulation time 52220700 ps
CPU time 32.68 seconds
Started Jun 06 01:34:46 PM PDT 24
Finished Jun 06 01:35:19 PM PDT 24
Peak memory 275924 kb
Host smart-9b92aa80-60b3-4073-b4f9-e36d4cdc5867
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170617275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.2170617275
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.2782903222
Short name T629
Test name
Test status
Simulation time 86714400 ps
CPU time 31.78 seconds
Started Jun 06 01:34:44 PM PDT 24
Finished Jun 06 01:35:17 PM PDT 24
Peak memory 273512 kb
Host smart-de29069a-b688-49c1-8634-b2c898861870
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782903222 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.2782903222
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.2722233594
Short name T615
Test name
Test status
Simulation time 1347670500 ps
CPU time 65.03 seconds
Started Jun 06 01:34:45 PM PDT 24
Finished Jun 06 01:35:50 PM PDT 24
Peak memory 263472 kb
Host smart-3544de50-b3e9-4624-98f4-841f8b4d043d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722233594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.2722233594
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.874853822
Short name T676
Test name
Test status
Simulation time 127582200 ps
CPU time 148.55 seconds
Started Jun 06 01:34:43 PM PDT 24
Finished Jun 06 01:37:13 PM PDT 24
Peak memory 281004 kb
Host smart-22ba32e6-7ddd-4062-b903-4b67fbf07405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874853822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.874853822
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.441571319
Short name T442
Test name
Test status
Simulation time 6317647500 ps
CPU time 148.55 seconds
Started Jun 06 01:34:45 PM PDT 24
Finished Jun 06 01:37:15 PM PDT 24
Peak memory 259620 kb
Host smart-cf292464-9e34-469c-972c-b670f173531b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441571319 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.flash_ctrl_wo.441571319
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.182233015
Short name T23
Test name
Test status
Simulation time 22656000 ps
CPU time 14.19 seconds
Started Jun 06 01:32:15 PM PDT 24
Finished Jun 06 01:32:30 PM PDT 24
Peak memory 260348 kb
Host smart-39e8d5c2-dce6-44fd-887d-a2e5bcc54be8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182233015 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.182233015
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.3024671938
Short name T965
Test name
Test status
Simulation time 32402200 ps
CPU time 13.72 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:32:39 PM PDT 24
Peak memory 265128 kb
Host smart-38d7e4e2-29a6-42f9-9004-3a7691079383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024671938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.3
024671938
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.3744656436
Short name T188
Test name
Test status
Simulation time 20078600 ps
CPU time 13.97 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:32:26 PM PDT 24
Peak memory 261340 kb
Host smart-4caca037-dbaa-4f0c-b1e2-1198a2fa8d80
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744656436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.3744656436
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.3767720494
Short name T370
Test name
Test status
Simulation time 21891100 ps
CPU time 15.87 seconds
Started Jun 06 01:32:09 PM PDT 24
Finished Jun 06 01:32:26 PM PDT 24
Peak memory 274664 kb
Host smart-3e024c2c-fae4-4f62-bf42-8cd3fc59908d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767720494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.3767720494
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.2766758180
Short name T489
Test name
Test status
Simulation time 327189100 ps
CPU time 110.61 seconds
Started Jun 06 01:32:06 PM PDT 24
Finished Jun 06 01:33:58 PM PDT 24
Peak memory 273524 kb
Host smart-630330ca-af83-4a93-ba09-919ca8cbe921
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766758180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.2766758180
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.3764466586
Short name T980
Test name
Test status
Simulation time 39900000 ps
CPU time 22.49 seconds
Started Jun 06 01:32:15 PM PDT 24
Finished Jun 06 01:32:39 PM PDT 24
Peak memory 272844 kb
Host smart-1c41fc5c-97c7-49ff-9c5d-ea8334fd8fad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764466586 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.3764466586
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.4219592004
Short name T129
Test name
Test status
Simulation time 4491460800 ps
CPU time 543.15 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:41:12 PM PDT 24
Peak memory 263212 kb
Host smart-d8e3ffac-b9d7-4683-a508-365c966bf9f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4219592004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.4219592004
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.2925615046
Short name T1063
Test name
Test status
Simulation time 4130533000 ps
CPU time 2185.93 seconds
Started Jun 06 01:32:09 PM PDT 24
Finished Jun 06 02:08:37 PM PDT 24
Peak memory 264644 kb
Host smart-7168c805-b3a1-4b07-b3c4-2d9e78818ea3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925615046 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.2925615046
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.575459570
Short name T173
Test name
Test status
Simulation time 1699675000 ps
CPU time 3109.29 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 02:24:02 PM PDT 24
Peak memory 263392 kb
Host smart-93cf1319-3d3d-4a27-877d-e933da9e0d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575459570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.575459570
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.1702372100
Short name T630
Test name
Test status
Simulation time 129480600 ps
CPU time 20.76 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:32:30 PM PDT 24
Peak memory 263412 kb
Host smart-971e3011-2ba9-4c45-a1a5-16825f90b602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702372100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.1702372100
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.2612813588
Short name T323
Test name
Test status
Simulation time 651444200 ps
CPU time 37.68 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:32:47 PM PDT 24
Peak memory 262380 kb
Host smart-63f3ea24-a858-46f5-98a7-905614c16ef9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612813588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.2612813588
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.4284879361
Short name T86
Test name
Test status
Simulation time 330936448100 ps
CPU time 2719.82 seconds
Started Jun 06 01:32:11 PM PDT 24
Finished Jun 06 02:17:33 PM PDT 24
Peak memory 265028 kb
Host smart-bb2d3f95-b46b-4814-a95f-608fb208716b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284879361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.4284879361
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.3360406063
Short name T462
Test name
Test status
Simulation time 148896100 ps
CPU time 70.16 seconds
Started Jun 06 01:32:09 PM PDT 24
Finished Jun 06 01:33:21 PM PDT 24
Peak memory 265200 kb
Host smart-80202d6c-e064-409c-8f69-0e858a149fc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360406063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.3360406063
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.2114088367
Short name T1044
Test name
Test status
Simulation time 10012412700 ps
CPU time 118.87 seconds
Started Jun 06 01:32:17 PM PDT 24
Finished Jun 06 01:34:16 PM PDT 24
Peak memory 291696 kb
Host smart-d5926bc6-a06d-4280-975e-a2de68e00cb7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114088367 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.2114088367
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.3644679016
Short name T1038
Test name
Test status
Simulation time 25306400 ps
CPU time 13.53 seconds
Started Jun 06 01:32:16 PM PDT 24
Finished Jun 06 01:32:31 PM PDT 24
Peak memory 259364 kb
Host smart-785d08cf-6b0e-4e09-9ed6-e92fac50fc4a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644679016 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.3644679016
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.1957794651
Short name T702
Test name
Test status
Simulation time 119658079000 ps
CPU time 2013.07 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 02:05:42 PM PDT 24
Peak memory 260340 kb
Host smart-56ba7356-211a-4964-97d7-b9b7e8ce9ffd
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957794651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.1957794651
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.1853359601
Short name T755
Test name
Test status
Simulation time 40121260700 ps
CPU time 803.48 seconds
Started Jun 06 01:32:07 PM PDT 24
Finished Jun 06 01:45:32 PM PDT 24
Peak memory 263896 kb
Host smart-607b85b7-6f4d-450a-99a3-3a542ec7fea7
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853359601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.1853359601
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.2204411224
Short name T189
Test name
Test status
Simulation time 18838631100 ps
CPU time 660.44 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:43:10 PM PDT 24
Peak memory 340116 kb
Host smart-05e7ac82-8ac5-4f06-bed1-d0cced1d1e3b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204411224 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.2204411224
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.1401353309
Short name T950
Test name
Test status
Simulation time 2959905500 ps
CPU time 216.44 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:35:46 PM PDT 24
Peak memory 292136 kb
Host smart-a5cc12d6-e7a8-4a32-9b1d-2d2af5cf65ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401353309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.1401353309
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.747655241
Short name T1027
Test name
Test status
Simulation time 16020077800 ps
CPU time 279.71 seconds
Started Jun 06 01:32:07 PM PDT 24
Finished Jun 06 01:36:49 PM PDT 24
Peak memory 284672 kb
Host smart-4f777550-78b3-4dcd-aeb4-05757f89e4be
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747655241 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.747655241
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.4282179581
Short name T1057
Test name
Test status
Simulation time 2493105400 ps
CPU time 74.2 seconds
Started Jun 06 01:32:12 PM PDT 24
Finished Jun 06 01:33:28 PM PDT 24
Peak memory 261404 kb
Host smart-50d94330-a508-45da-8cf9-9501f7d59401
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282179581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.4282179581
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.437694928
Short name T701
Test name
Test status
Simulation time 24724503900 ps
CPU time 218.66 seconds
Started Jun 06 01:32:11 PM PDT 24
Finished Jun 06 01:35:52 PM PDT 24
Peak memory 264928 kb
Host smart-d11c6151-0bdf-4782-9ce2-281871afdcb0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437
694928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.437694928
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.1089904807
Short name T81
Test name
Test status
Simulation time 1582388100 ps
CPU time 86.98 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:33:39 PM PDT 24
Peak memory 260476 kb
Host smart-1a2b63dc-32e3-400b-9f69-79fcb65fbc8a
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089904807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.1089904807
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.2250040956
Short name T125
Test name
Test status
Simulation time 908207800 ps
CPU time 70.65 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:33:22 PM PDT 24
Peak memory 260144 kb
Host smart-5e2ee811-35da-480f-8909-051c8fc6a0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250040956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.2250040956
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.4235786286
Short name T947
Test name
Test status
Simulation time 43144800 ps
CPU time 113.79 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:34:06 PM PDT 24
Peak memory 259704 kb
Host smart-3e71e79a-cedb-4461-8f38-4a958bd18e46
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235786286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.4235786286
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.2648028766
Short name T869
Test name
Test status
Simulation time 6464261400 ps
CPU time 233.09 seconds
Started Jun 06 01:32:11 PM PDT 24
Finished Jun 06 01:36:06 PM PDT 24
Peak memory 294560 kb
Host smart-cd56b34b-95f9-4afe-a032-f845c4a9555d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648028766 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.2648028766
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.3756515648
Short name T46
Test name
Test status
Simulation time 15880800 ps
CPU time 13.91 seconds
Started Jun 06 01:32:07 PM PDT 24
Finished Jun 06 01:32:22 PM PDT 24
Peak memory 278844 kb
Host smart-a4fbffe9-959a-4375-9642-c743a2230d51
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3756515648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.3756515648
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.3791121144
Short name T475
Test name
Test status
Simulation time 2743909100 ps
CPU time 211.1 seconds
Started Jun 06 01:32:11 PM PDT 24
Finished Jun 06 01:35:44 PM PDT 24
Peak memory 262868 kb
Host smart-57f4e2cc-046a-4d2c-8a8d-b3cd616bf551
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3791121144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.3791121144
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.3013960504
Short name T170
Test name
Test status
Simulation time 14928200 ps
CPU time 14.27 seconds
Started Jun 06 01:32:11 PM PDT 24
Finished Jun 06 01:32:27 PM PDT 24
Peak memory 265332 kb
Host smart-18914e44-fa6d-4b22-9cc8-72b0812267ec
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013960504 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.3013960504
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.1522674341
Short name T631
Test name
Test status
Simulation time 56536400 ps
CPU time 13.57 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:32:25 PM PDT 24
Peak memory 258564 kb
Host smart-a879853b-c5f8-4874-8a33-7be0a4089254
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522674341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.1522674341
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.3710373738
Short name T710
Test name
Test status
Simulation time 501314300 ps
CPU time 416.44 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:39:06 PM PDT 24
Peak memory 280660 kb
Host smart-2f06f6f8-3236-4031-925e-f081d2491de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710373738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.3710373738
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.1884975719
Short name T685
Test name
Test status
Simulation time 169284200 ps
CPU time 101.48 seconds
Started Jun 06 01:32:11 PM PDT 24
Finished Jun 06 01:33:54 PM PDT 24
Peak memory 262628 kb
Host smart-4085e7f3-d97c-4b46-87aa-0e6ab7728f93
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1884975719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1884975719
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.464411551
Short name T1003
Test name
Test status
Simulation time 64230600 ps
CPU time 32.89 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:32:45 PM PDT 24
Peak memory 279000 kb
Host smart-f532f4fa-6649-4d02-9a96-d6f49b646d94
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464411551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rd_intg.464411551
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.4261638252
Short name T322
Test name
Test status
Simulation time 339421000 ps
CPU time 37.21 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:32:49 PM PDT 24
Peak memory 275056 kb
Host smart-f77fd5f1-d1fc-4e62-8dad-a771a3e87deb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261638252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.4261638252
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.2600532563
Short name T912
Test name
Test status
Simulation time 18014900 ps
CPU time 22.69 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:32:32 PM PDT 24
Peak memory 265272 kb
Host smart-0730ce35-a6cb-4aa7-9e37-f270130ce8fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600532563 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.2600532563
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.4133461620
Short name T797
Test name
Test status
Simulation time 408656700 ps
CPU time 21.19 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:32:32 PM PDT 24
Peak memory 265164 kb
Host smart-6a704f69-8d79-4d84-9772-096c0c835472
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133461620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.4133461620
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.2160634314
Short name T712
Test name
Test status
Simulation time 447192400 ps
CPU time 98.6 seconds
Started Jun 06 01:32:11 PM PDT 24
Finished Jun 06 01:33:52 PM PDT 24
Peak memory 289844 kb
Host smart-45614b90-4e5f-4d62-8ec3-7289b461cb96
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160634314 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_ro.2160634314
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.466464606
Short name T1075
Test name
Test status
Simulation time 581612400 ps
CPU time 162.92 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:34:55 PM PDT 24
Peak memory 281704 kb
Host smart-d553b3be-abbc-49f1-a57c-17bcda8add4d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
466464606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.466464606
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.1547557764
Short name T1031
Test name
Test status
Simulation time 1315643200 ps
CPU time 126.61 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:34:16 PM PDT 24
Peak memory 294252 kb
Host smart-cf9d49d4-eabc-4a00-8747-c8681d919a79
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547557764 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.1547557764
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.722378924
Short name T206
Test name
Test status
Simulation time 12221797000 ps
CPU time 511.18 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:40:43 PM PDT 24
Peak memory 309500 kb
Host smart-84b70033-7b06-4b44-9c93-d2cde8994640
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722378924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.flash_ctrl_rw.722378924
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.1258441542
Short name T876
Test name
Test status
Simulation time 41496300 ps
CPU time 30.81 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:32:40 PM PDT 24
Peak memory 275192 kb
Host smart-7880925e-3c72-46dc-8ba3-14cff2c82e23
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258441542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.1258441542
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.1540213028
Short name T964
Test name
Test status
Simulation time 49665900 ps
CPU time 31.42 seconds
Started Jun 06 01:32:11 PM PDT 24
Finished Jun 06 01:32:45 PM PDT 24
Peak memory 267312 kb
Host smart-04243942-a9bc-4b98-bc03-2196591dcbf1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540213028 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.1540213028
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.3771249109
Short name T386
Test name
Test status
Simulation time 7969739500 ps
CPU time 678.12 seconds
Started Jun 06 01:32:07 PM PDT 24
Finished Jun 06 01:43:27 PM PDT 24
Peak memory 320520 kb
Host smart-6daebcca-65cb-4f98-9304-89528067bbcd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771249109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s
err.3771249109
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.2351350929
Short name T574
Test name
Test status
Simulation time 4061543000 ps
CPU time 75.32 seconds
Started Jun 06 01:32:09 PM PDT 24
Finished Jun 06 01:33:26 PM PDT 24
Peak memory 259648 kb
Host smart-07ab661e-11ea-48b9-8056-a0a00bc41a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351350929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.2351350929
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.1193136828
Short name T657
Test name
Test status
Simulation time 773533900 ps
CPU time 87.07 seconds
Started Jun 06 01:32:09 PM PDT 24
Finished Jun 06 01:33:38 PM PDT 24
Peak memory 265092 kb
Host smart-d51c12f5-b19e-48bb-88ff-edfcc317aba9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193136828 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.1193136828
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.613665384
Short name T794
Test name
Test status
Simulation time 85730400 ps
CPU time 76.79 seconds
Started Jun 06 01:32:09 PM PDT 24
Finished Jun 06 01:33:27 PM PDT 24
Peak memory 275352 kb
Host smart-729b6d4a-6335-41d3-b067-759a570d7f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613665384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.613665384
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.2239056876
Short name T1004
Test name
Test status
Simulation time 52964700 ps
CPU time 26.11 seconds
Started Jun 06 01:32:10 PM PDT 24
Finished Jun 06 01:32:38 PM PDT 24
Peak memory 259384 kb
Host smart-a430f3ea-4257-471c-9912-14cc0e101678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239056876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.2239056876
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.1804768418
Short name T607
Test name
Test status
Simulation time 810224300 ps
CPU time 540.04 seconds
Started Jun 06 01:32:11 PM PDT 24
Finished Jun 06 01:41:13 PM PDT 24
Peak memory 278900 kb
Host smart-e7b3386c-81ea-41c3-b6cf-dc31b621990a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804768418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.1804768418
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.1886130964
Short name T487
Test name
Test status
Simulation time 27534000 ps
CPU time 26.33 seconds
Started Jun 06 01:32:09 PM PDT 24
Finished Jun 06 01:32:37 PM PDT 24
Peak memory 261960 kb
Host smart-9e4b8ca8-22da-4d15-be21-f863573fd42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886130964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.1886130964
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.2611322281
Short name T101
Test name
Test status
Simulation time 2451398500 ps
CPU time 202.01 seconds
Started Jun 06 01:32:08 PM PDT 24
Finished Jun 06 01:35:31 PM PDT 24
Peak memory 265060 kb
Host smart-47073552-1222-492b-923c-777534afe1ac
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611322281 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_wo.2611322281
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.4101277928
Short name T179
Test name
Test status
Simulation time 78966100 ps
CPU time 15.19 seconds
Started Jun 06 01:32:11 PM PDT 24
Finished Jun 06 01:32:28 PM PDT 24
Peak memory 264668 kb
Host smart-5d9706fe-ed4e-48e5-b16a-7407a27b61a6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101277928 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.4101277928
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.1862016574
Short name T761
Test name
Test status
Simulation time 63186300 ps
CPU time 14.05 seconds
Started Jun 06 01:34:57 PM PDT 24
Finished Jun 06 01:35:12 PM PDT 24
Peak memory 265196 kb
Host smart-6bcc1bb8-a39a-42e6-843a-afd51b7ffd39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862016574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
1862016574
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.2280067452
Short name T118
Test name
Test status
Simulation time 14698600 ps
CPU time 13.76 seconds
Started Jun 06 01:34:59 PM PDT 24
Finished Jun 06 01:35:13 PM PDT 24
Peak memory 274660 kb
Host smart-565ed2db-3a99-4fd2-870c-f7305613dbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280067452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.2280067452
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.2694815803
Short name T721
Test name
Test status
Simulation time 20399400 ps
CPU time 21.94 seconds
Started Jun 06 01:34:56 PM PDT 24
Finished Jun 06 01:35:19 PM PDT 24
Peak memory 273468 kb
Host smart-eb766c1c-503c-4d78-abda-fd847c0b4e04
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694815803 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.2694815803
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2339203254
Short name T437
Test name
Test status
Simulation time 1557927600 ps
CPU time 63.2 seconds
Started Jun 06 01:34:57 PM PDT 24
Finished Jun 06 01:36:01 PM PDT 24
Peak memory 262928 kb
Host smart-1ebca8e8-c2c7-4393-a463-bda5840d6893
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339203254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.2339203254
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.2058829123
Short name T281
Test name
Test status
Simulation time 1311927800 ps
CPU time 134.3 seconds
Started Jun 06 01:34:57 PM PDT 24
Finished Jun 06 01:37:13 PM PDT 24
Peak memory 291004 kb
Host smart-aa82c0cb-3171-4cbe-8a2a-cf0c130546d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058829123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.2058829123
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.3815137910
Short name T1064
Test name
Test status
Simulation time 47644383000 ps
CPU time 234.16 seconds
Started Jun 06 01:34:53 PM PDT 24
Finished Jun 06 01:38:48 PM PDT 24
Peak memory 294244 kb
Host smart-965e8934-6661-4d44-9e3c-19e1aa6ea140
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815137910 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.3815137910
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.2752213005
Short name T531
Test name
Test status
Simulation time 38392200 ps
CPU time 133.14 seconds
Started Jun 06 01:34:56 PM PDT 24
Finished Jun 06 01:37:09 PM PDT 24
Peak memory 260820 kb
Host smart-90dfe27f-e22e-4ac2-9a00-727ce3aaeb75
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752213005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.2752213005
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.1344035361
Short name T586
Test name
Test status
Simulation time 12821412700 ps
CPU time 199.29 seconds
Started Jun 06 01:34:54 PM PDT 24
Finished Jun 06 01:38:14 PM PDT 24
Peak memory 265044 kb
Host smart-65a37529-9ea8-4bfb-bf63-419651a5dae5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344035361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.1344035361
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict.2677339264
Short name T325
Test name
Test status
Simulation time 33234900 ps
CPU time 31.8 seconds
Started Jun 06 01:34:59 PM PDT 24
Finished Jun 06 01:35:32 PM PDT 24
Peak memory 276564 kb
Host smart-06271394-4d17-4013-b3eb-31dee89b5871
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677339264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fl
ash_ctrl_rw_evict.2677339264
Directory /workspace/20.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.2796337425
Short name T451
Test name
Test status
Simulation time 54676000 ps
CPU time 30.46 seconds
Started Jun 06 01:34:56 PM PDT 24
Finished Jun 06 01:35:28 PM PDT 24
Peak memory 273528 kb
Host smart-c400bed5-1b83-46d1-891e-e8c0ce555930
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796337425 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.2796337425
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.4022422019
Short name T98
Test name
Test status
Simulation time 1440403300 ps
CPU time 78.06 seconds
Started Jun 06 01:34:58 PM PDT 24
Finished Jun 06 01:36:17 PM PDT 24
Peak memory 259340 kb
Host smart-fbb9fbe2-b64c-45b3-91d5-dbe2e955056a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022422019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.4022422019
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.3214294834
Short name T496
Test name
Test status
Simulation time 30389500 ps
CPU time 99.01 seconds
Started Jun 06 01:34:56 PM PDT 24
Finished Jun 06 01:36:36 PM PDT 24
Peak memory 275676 kb
Host smart-df2ce1d7-09b7-4a64-af90-4e35a9907624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214294834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.3214294834
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.2497966640
Short name T602
Test name
Test status
Simulation time 175036800 ps
CPU time 14.19 seconds
Started Jun 06 01:34:59 PM PDT 24
Finished Jun 06 01:35:14 PM PDT 24
Peak memory 264804 kb
Host smart-d1cb51db-ad72-4d67-adc7-e40cfac8e337
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497966640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
2497966640
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.3679480719
Short name T1071
Test name
Test status
Simulation time 37073200 ps
CPU time 16.65 seconds
Started Jun 06 01:34:56 PM PDT 24
Finished Jun 06 01:35:13 PM PDT 24
Peak memory 274608 kb
Host smart-770bef7a-ea20-4a11-afe5-c8f94131dc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679480719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.3679480719
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.2521562949
Short name T82
Test name
Test status
Simulation time 31101500 ps
CPU time 22.2 seconds
Started Jun 06 01:34:57 PM PDT 24
Finished Jun 06 01:35:20 PM PDT 24
Peak memory 273548 kb
Host smart-bdf22b4b-14ac-453d-8f3d-a08b929fe6fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521562949 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.2521562949
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.572951404
Short name T573
Test name
Test status
Simulation time 16474210900 ps
CPU time 118.54 seconds
Started Jun 06 01:34:57 PM PDT 24
Finished Jun 06 01:36:56 PM PDT 24
Peak memory 260644 kb
Host smart-da0dcec5-a2a7-4989-9123-91e1a8ea1790
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572951404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_h
w_sec_otp.572951404
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.1202215359
Short name T334
Test name
Test status
Simulation time 9384416000 ps
CPU time 223.82 seconds
Started Jun 06 01:34:56 PM PDT 24
Finished Jun 06 01:38:40 PM PDT 24
Peak memory 291988 kb
Host smart-4d61692c-e1f4-4a77-ae06-48dbfe823a56
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202215359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.1202215359
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.1299643387
Short name T509
Test name
Test status
Simulation time 23099797900 ps
CPU time 285.2 seconds
Started Jun 06 01:35:04 PM PDT 24
Finished Jun 06 01:39:51 PM PDT 24
Peak memory 290888 kb
Host smart-f0ae6e31-a4b1-4be0-ba3c-9d666796a408
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299643387 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.1299643387
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.635342028
Short name T845
Test name
Test status
Simulation time 154352000 ps
CPU time 134.04 seconds
Started Jun 06 01:34:57 PM PDT 24
Finished Jun 06 01:37:12 PM PDT 24
Peak memory 260036 kb
Host smart-0b3bf73f-eccb-4aa4-a0c5-7ed36c46a7c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635342028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ot
p_reset.635342028
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.1865540920
Short name T385
Test name
Test status
Simulation time 227875400 ps
CPU time 13.67 seconds
Started Jun 06 01:34:55 PM PDT 24
Finished Jun 06 01:35:09 PM PDT 24
Peak memory 265092 kb
Host smart-2fa7b617-a169-4949-9ef6-fa62343bc8fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865540920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_re
set.1865540920
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.2146027012
Short name T897
Test name
Test status
Simulation time 189905300 ps
CPU time 31.21 seconds
Started Jun 06 01:35:00 PM PDT 24
Finished Jun 06 01:35:32 PM PDT 24
Peak memory 275512 kb
Host smart-921674ac-d212-47fd-ba77-1ef681b27d18
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146027012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl
ash_ctrl_rw_evict.2146027012
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.4069208285
Short name T528
Test name
Test status
Simulation time 61481700 ps
CPU time 31.28 seconds
Started Jun 06 01:34:59 PM PDT 24
Finished Jun 06 01:35:31 PM PDT 24
Peak memory 273784 kb
Host smart-aa0edc25-cf3a-4040-bc2d-e676d8afa241
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069208285 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.4069208285
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.3438830489
Short name T403
Test name
Test status
Simulation time 7843674500 ps
CPU time 76.77 seconds
Started Jun 06 01:35:00 PM PDT 24
Finished Jun 06 01:36:18 PM PDT 24
Peak memory 259288 kb
Host smart-33df7db6-92af-49c3-9bb1-6b622d85f889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438830489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3438830489
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.3151357522
Short name T1030
Test name
Test status
Simulation time 27257400 ps
CPU time 127.18 seconds
Started Jun 06 01:35:03 PM PDT 24
Finished Jun 06 01:37:12 PM PDT 24
Peak memory 276072 kb
Host smart-72fd0bd8-9d12-4fc3-9e42-625e5de74897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151357522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.3151357522
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.891754465
Short name T679
Test name
Test status
Simulation time 74198700 ps
CPU time 13.61 seconds
Started Jun 06 01:35:09 PM PDT 24
Finished Jun 06 01:35:24 PM PDT 24
Peak memory 257972 kb
Host smart-c0690029-799d-4ca6-8d7f-2f0a1fe32eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891754465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.891754465
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.1102459207
Short name T733
Test name
Test status
Simulation time 51857600 ps
CPU time 13.46 seconds
Started Jun 06 01:35:05 PM PDT 24
Finished Jun 06 01:35:20 PM PDT 24
Peak memory 274748 kb
Host smart-54da8451-d038-42d0-a861-8c03be51934e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102459207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.1102459207
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.3131052424
Short name T647
Test name
Test status
Simulation time 11462433500 ps
CPU time 110.32 seconds
Started Jun 06 01:35:04 PM PDT 24
Finished Jun 06 01:36:56 PM PDT 24
Peak memory 262484 kb
Host smart-56945fd2-8c69-45d6-9f5a-0889e3b9260b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131052424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.3131052424
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.1988104971
Short name T962
Test name
Test status
Simulation time 4985665600 ps
CPU time 138.02 seconds
Started Jun 06 01:35:07 PM PDT 24
Finished Jun 06 01:37:26 PM PDT 24
Peak memory 293816 kb
Host smart-08d91cfc-d475-49f2-a36a-e2a5c798c923
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988104971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.1988104971
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1537666734
Short name T127
Test name
Test status
Simulation time 93898336800 ps
CPU time 316.86 seconds
Started Jun 06 01:35:07 PM PDT 24
Finished Jun 06 01:40:25 PM PDT 24
Peak memory 290904 kb
Host smart-c95b8beb-e0c9-4a05-ab58-38f5bc12ca1f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537666734 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.1537666734
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.1180589172
Short name T495
Test name
Test status
Simulation time 72687000 ps
CPU time 134.41 seconds
Started Jun 06 01:35:05 PM PDT 24
Finished Jun 06 01:37:21 PM PDT 24
Peak memory 263928 kb
Host smart-3757ecf5-8f3b-4519-ab50-5953dbfd9024
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180589172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.1180589172
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.4042169979
Short name T983
Test name
Test status
Simulation time 23094200 ps
CPU time 13.91 seconds
Started Jun 06 01:35:04 PM PDT 24
Finished Jun 06 01:35:19 PM PDT 24
Peak memory 265256 kb
Host smart-81629d12-3107-4e26-a974-c9f393c1a6ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042169979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.4042169979
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.505055287
Short name T64
Test name
Test status
Simulation time 31057500 ps
CPU time 31.58 seconds
Started Jun 06 01:35:04 PM PDT 24
Finished Jun 06 01:35:37 PM PDT 24
Peak memory 275212 kb
Host smart-9328be87-39d5-46f0-87b2-608c5d05741b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505055287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_rw_evict.505055287
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.1878273172
Short name T620
Test name
Test status
Simulation time 60436700 ps
CPU time 29.23 seconds
Started Jun 06 01:35:05 PM PDT 24
Finished Jun 06 01:35:36 PM PDT 24
Peak memory 267336 kb
Host smart-aea91532-d419-4d68-9946-4358eb3d1e12
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878273172 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.1878273172
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.1837501398
Short name T445
Test name
Test status
Simulation time 3395791100 ps
CPU time 79.75 seconds
Started Jun 06 01:35:04 PM PDT 24
Finished Jun 06 01:36:25 PM PDT 24
Peak memory 263984 kb
Host smart-2821297b-f1c4-4d9d-b842-2580804e55fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837501398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.1837501398
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.3167905625
Short name T708
Test name
Test status
Simulation time 75372500 ps
CPU time 51.94 seconds
Started Jun 06 01:34:56 PM PDT 24
Finished Jun 06 01:35:49 PM PDT 24
Peak memory 270972 kb
Host smart-232f5ee6-4ee5-4ee7-8393-547dbdd5d5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167905625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.3167905625
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.2795143839
Short name T447
Test name
Test status
Simulation time 80768400 ps
CPU time 14.03 seconds
Started Jun 06 01:35:07 PM PDT 24
Finished Jun 06 01:35:22 PM PDT 24
Peak memory 258000 kb
Host smart-8836eb19-abe0-44fb-91f3-ee0cd3a30ddc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795143839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
2795143839
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.3417917676
Short name T729
Test name
Test status
Simulation time 14944300 ps
CPU time 16.76 seconds
Started Jun 06 01:35:07 PM PDT 24
Finished Jun 06 01:35:25 PM PDT 24
Peak memory 274652 kb
Host smart-a4c5642d-90e5-4903-b0d2-2126c85916d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417917676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.3417917676
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.3649651875
Short name T955
Test name
Test status
Simulation time 68055200 ps
CPU time 20.89 seconds
Started Jun 06 01:35:08 PM PDT 24
Finished Jun 06 01:35:30 PM PDT 24
Peak memory 273488 kb
Host smart-e7375d75-94ec-4d21-a47c-ae2a948a7300
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649651875 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.3649651875
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.3279079352
Short name T420
Test name
Test status
Simulation time 5017239800 ps
CPU time 210.23 seconds
Started Jun 06 01:35:05 PM PDT 24
Finished Jun 06 01:38:36 PM PDT 24
Peak memory 262948 kb
Host smart-4e5504c6-0aa4-41f3-9d98-7bcffef2c382
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279079352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.3279079352
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.3431617961
Short name T342
Test name
Test status
Simulation time 24472938700 ps
CPU time 259.59 seconds
Started Jun 06 01:35:05 PM PDT 24
Finished Jun 06 01:39:26 PM PDT 24
Peak memory 284728 kb
Host smart-aec51cb3-73cf-4172-9309-da0ac4f8128b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431617961 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.3431617961
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.1340770432
Short name T960
Test name
Test status
Simulation time 40057500 ps
CPU time 132.85 seconds
Started Jun 06 01:35:09 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 259820 kb
Host smart-c6af8e39-4db9-4bc2-a5d9-d624ec7f6cee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340770432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.1340770432
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.675467649
Short name T824
Test name
Test status
Simulation time 71238800 ps
CPU time 13.81 seconds
Started Jun 06 01:35:06 PM PDT 24
Finished Jun 06 01:35:21 PM PDT 24
Peak memory 265004 kb
Host smart-d50403c8-4306-4201-a50f-e23985b630e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675467649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_res
et.675467649
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.318914092
Short name T743
Test name
Test status
Simulation time 4575480300 ps
CPU time 84.22 seconds
Started Jun 06 01:35:05 PM PDT 24
Finished Jun 06 01:36:30 PM PDT 24
Peak memory 263300 kb
Host smart-4db31c93-781a-4391-aa83-e8ce05ef6095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318914092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.318914092
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.3704218325
Short name T221
Test name
Test status
Simulation time 26647600 ps
CPU time 177.19 seconds
Started Jun 06 01:35:04 PM PDT 24
Finished Jun 06 01:38:02 PM PDT 24
Peak memory 278356 kb
Host smart-45bce4f9-a68d-446b-ac1b-068c9a398ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704218325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.3704218325
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.2457512729
Short name T883
Test name
Test status
Simulation time 39107400 ps
CPU time 13.96 seconds
Started Jun 06 01:35:08 PM PDT 24
Finished Jun 06 01:35:23 PM PDT 24
Peak memory 264880 kb
Host smart-0642fd9b-21fb-4cc3-a386-1ced3f45cb8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457512729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
2457512729
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.3601257975
Short name T1014
Test name
Test status
Simulation time 26310000 ps
CPU time 13.7 seconds
Started Jun 06 01:35:06 PM PDT 24
Finished Jun 06 01:35:21 PM PDT 24
Peak memory 284056 kb
Host smart-e729bf81-aa5f-4f90-8d0c-65f0a278073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601257975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.3601257975
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.146645475
Short name T612
Test name
Test status
Simulation time 50793000 ps
CPU time 21.84 seconds
Started Jun 06 01:35:06 PM PDT 24
Finished Jun 06 01:35:29 PM PDT 24
Peak memory 264720 kb
Host smart-45d4c303-f6ba-4066-a541-07a237e559a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146645475 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.146645475
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.2788638469
Short name T804
Test name
Test status
Simulation time 10407225900 ps
CPU time 168.52 seconds
Started Jun 06 01:35:04 PM PDT 24
Finished Jun 06 01:37:54 PM PDT 24
Peak memory 262848 kb
Host smart-58d802b2-a50a-458d-be47-66cfcbaa71db
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788638469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.2788638469
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.1016056653
Short name T865
Test name
Test status
Simulation time 1142634300 ps
CPU time 170.94 seconds
Started Jun 06 01:35:07 PM PDT 24
Finished Jun 06 01:37:59 PM PDT 24
Peak memory 294128 kb
Host smart-3d0d9f1e-2378-448b-b921-6e7bbb823136
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016056653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.1016056653
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.1181199195
Short name T39
Test name
Test status
Simulation time 11654528000 ps
CPU time 178.38 seconds
Started Jun 06 01:35:04 PM PDT 24
Finished Jun 06 01:38:04 PM PDT 24
Peak memory 294092 kb
Host smart-18be0954-effc-479a-8ea0-e9ed64e4811b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181199195 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.1181199195
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.2086496657
Short name T649
Test name
Test status
Simulation time 156493900 ps
CPU time 133.74 seconds
Started Jun 06 01:35:07 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 259788 kb
Host smart-c446ca7f-35ad-490d-830d-d06e4f034c9c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086496657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o
tp_reset.2086496657
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.1431485341
Short name T94
Test name
Test status
Simulation time 23958600 ps
CPU time 13.69 seconds
Started Jun 06 01:35:08 PM PDT 24
Finished Jun 06 01:35:23 PM PDT 24
Peak memory 264960 kb
Host smart-18ad40e3-7e2f-438f-88b8-fbbcb44f1e6d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431485341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.1431485341
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.1958997629
Short name T695
Test name
Test status
Simulation time 49575800 ps
CPU time 31.23 seconds
Started Jun 06 01:35:08 PM PDT 24
Finished Jun 06 01:35:40 PM PDT 24
Peak memory 267316 kb
Host smart-b14d7be9-57e9-4f91-b66f-3297a73c06eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958997629 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.1958997629
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.2849483434
Short name T893
Test name
Test status
Simulation time 2808257000 ps
CPU time 70.94 seconds
Started Jun 06 01:35:03 PM PDT 24
Finished Jun 06 01:36:16 PM PDT 24
Peak memory 263892 kb
Host smart-4dd9d60f-270c-478c-9a1e-902d89b884ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849483434 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.2849483434
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.3351285618
Short name T219
Test name
Test status
Simulation time 72596200 ps
CPU time 147.87 seconds
Started Jun 06 01:35:05 PM PDT 24
Finished Jun 06 01:37:34 PM PDT 24
Peak memory 278072 kb
Host smart-44aa39da-5e61-4226-a1a0-ad3bf389949b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351285618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.3351285618
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.977259685
Short name T485
Test name
Test status
Simulation time 39643300 ps
CPU time 13.69 seconds
Started Jun 06 01:35:17 PM PDT 24
Finished Jun 06 01:35:32 PM PDT 24
Peak memory 258052 kb
Host smart-3e363eff-881d-4f13-82cd-6edf3268e96e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977259685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.977259685
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.1284547531
Short name T880
Test name
Test status
Simulation time 13279400 ps
CPU time 15.92 seconds
Started Jun 06 01:35:18 PM PDT 24
Finished Jun 06 01:35:34 PM PDT 24
Peak memory 274580 kb
Host smart-4cdd5273-c16b-4a19-b575-aec9f0901810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284547531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1284547531
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.3440918095
Short name T948
Test name
Test status
Simulation time 12625800 ps
CPU time 20.59 seconds
Started Jun 06 01:35:18 PM PDT 24
Finished Jun 06 01:35:39 PM PDT 24
Peak memory 273532 kb
Host smart-bc5af75d-2f66-4881-b28b-6e2c482d55d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440918095 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.3440918095
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.234873234
Short name T707
Test name
Test status
Simulation time 11790523500 ps
CPU time 102.34 seconds
Started Jun 06 01:35:06 PM PDT 24
Finished Jun 06 01:36:50 PM PDT 24
Peak memory 263044 kb
Host smart-4e016c0d-a69a-417d-b74b-6b7af99d8cdc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234873234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_h
w_sec_otp.234873234
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.509232615
Short name T717
Test name
Test status
Simulation time 735146400 ps
CPU time 126.33 seconds
Started Jun 06 01:35:18 PM PDT 24
Finished Jun 06 01:37:25 PM PDT 24
Peak memory 293644 kb
Host smart-7cf05766-b4ff-4e2a-aaae-923b91ee4898
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509232615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flas
h_ctrl_intr_rd.509232615
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.2409765168
Short name T508
Test name
Test status
Simulation time 39805100 ps
CPU time 132.42 seconds
Started Jun 06 01:35:09 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 259984 kb
Host smart-61f18a6f-54da-4dc3-9d56-e21f813ef3da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409765168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.2409765168
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.2353410153
Short name T238
Test name
Test status
Simulation time 17518237400 ps
CPU time 249.05 seconds
Started Jun 06 01:35:16 PM PDT 24
Finished Jun 06 01:39:26 PM PDT 24
Peak memory 265016 kb
Host smart-f5c4ac26-833b-4b14-a653-ec72d5ace53c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353410153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.2353410153
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.2874408746
Short name T313
Test name
Test status
Simulation time 63246800 ps
CPU time 28.47 seconds
Started Jun 06 01:35:17 PM PDT 24
Finished Jun 06 01:35:47 PM PDT 24
Peak memory 276372 kb
Host smart-04c208ac-fd2f-46a5-976e-0fdde365dcaa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874408746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.2874408746
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.2484778301
Short name T1046
Test name
Test status
Simulation time 568202300 ps
CPU time 70.06 seconds
Started Jun 06 01:35:19 PM PDT 24
Finished Jun 06 01:36:30 PM PDT 24
Peak memory 263740 kb
Host smart-33972c96-892a-461e-958a-9762874fb282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484778301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.2484778301
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.1220466902
Short name T687
Test name
Test status
Simulation time 21892000 ps
CPU time 52.99 seconds
Started Jun 06 01:35:06 PM PDT 24
Finished Jun 06 01:36:00 PM PDT 24
Peak memory 270980 kb
Host smart-16cdd814-a60e-49c8-afea-2a414b683c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220466902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.1220466902
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.1999235136
Short name T503
Test name
Test status
Simulation time 39516300 ps
CPU time 14.21 seconds
Started Jun 06 01:35:19 PM PDT 24
Finished Jun 06 01:35:34 PM PDT 24
Peak memory 258004 kb
Host smart-4cf802ba-389e-4998-aae8-1cb18598de0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999235136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.
1999235136
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.3947695548
Short name T653
Test name
Test status
Simulation time 14207600 ps
CPU time 13.54 seconds
Started Jun 06 01:35:18 PM PDT 24
Finished Jun 06 01:35:33 PM PDT 24
Peak memory 274812 kb
Host smart-cde0029d-cde9-4de2-adbe-262fdc9ad145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947695548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.3947695548
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.8720384
Short name T456
Test name
Test status
Simulation time 5384099100 ps
CPU time 179.89 seconds
Started Jun 06 01:35:28 PM PDT 24
Finished Jun 06 01:38:29 PM PDT 24
Peak memory 262300 kb
Host smart-037a2db4-d8e9-4c16-8476-8515469b3cda
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8720384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_hw_
sec_otp.8720384
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.2869199941
Short name T41
Test name
Test status
Simulation time 1842476900 ps
CPU time 209.99 seconds
Started Jun 06 01:35:18 PM PDT 24
Finished Jun 06 01:38:49 PM PDT 24
Peak memory 292268 kb
Host smart-3873dcc6-ffa1-49ae-8b87-d3301101f630
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869199941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.2869199941
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1120360315
Short name T840
Test name
Test status
Simulation time 6054872600 ps
CPU time 135.34 seconds
Started Jun 06 01:35:17 PM PDT 24
Finished Jun 06 01:37:33 PM PDT 24
Peak memory 292072 kb
Host smart-7a602471-cf7e-4433-9f50-bc7f0c039ec0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120360315 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1120360315
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.162559820
Short name T397
Test name
Test status
Simulation time 41509800 ps
CPU time 131.93 seconds
Started Jun 06 01:35:19 PM PDT 24
Finished Jun 06 01:37:31 PM PDT 24
Peak memory 264648 kb
Host smart-138473b9-9d35-4593-8c55-c3e860708975
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162559820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ot
p_reset.162559820
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.1434607567
Short name T613
Test name
Test status
Simulation time 42499300 ps
CPU time 13.78 seconds
Started Jun 06 01:35:18 PM PDT 24
Finished Jun 06 01:35:32 PM PDT 24
Peak memory 258852 kb
Host smart-a8fca3e2-e16f-4869-9312-d5f3878c05bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434607567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_re
set.1434607567
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.2092442859
Short name T44
Test name
Test status
Simulation time 73910500 ps
CPU time 31.86 seconds
Started Jun 06 01:35:18 PM PDT 24
Finished Jun 06 01:35:51 PM PDT 24
Peak memory 276384 kb
Host smart-cb6d2e0c-7592-4612-9c58-4164122f9a18
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092442859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.2092442859
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.914407664
Short name T506
Test name
Test status
Simulation time 66974100 ps
CPU time 31.73 seconds
Started Jun 06 01:35:16 PM PDT 24
Finished Jun 06 01:35:49 PM PDT 24
Peak memory 267448 kb
Host smart-723d41b3-e943-4870-9cc0-558a0b1feeff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914407664 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.914407664
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.102852263
Short name T1051
Test name
Test status
Simulation time 1837691200 ps
CPU time 72.35 seconds
Started Jun 06 01:35:19 PM PDT 24
Finished Jun 06 01:36:32 PM PDT 24
Peak memory 264460 kb
Host smart-9f2c3a49-285d-4f13-833f-e2836d184f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102852263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.102852263
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.2780843370
Short name T380
Test name
Test status
Simulation time 2787852000 ps
CPU time 213.65 seconds
Started Jun 06 01:35:18 PM PDT 24
Finished Jun 06 01:38:52 PM PDT 24
Peak memory 281528 kb
Host smart-d6772152-4ed4-48bc-87bd-5eee0d68a0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780843370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.2780843370
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.1551550306
Short name T899
Test name
Test status
Simulation time 63747600 ps
CPU time 13.86 seconds
Started Jun 06 01:35:27 PM PDT 24
Finished Jun 06 01:35:42 PM PDT 24
Peak memory 258216 kb
Host smart-29f13ff1-dc86-4cde-8f5c-3615702304a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551550306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
1551550306
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.3278980903
Short name T432
Test name
Test status
Simulation time 23451300 ps
CPU time 15.54 seconds
Started Jun 06 01:35:28 PM PDT 24
Finished Jun 06 01:35:44 PM PDT 24
Peak memory 274752 kb
Host smart-3a556271-a5a2-4205-981c-138e4c16973b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278980903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3278980903
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.3307041942
Short name T362
Test name
Test status
Simulation time 36880300 ps
CPU time 20.75 seconds
Started Jun 06 01:35:31 PM PDT 24
Finished Jun 06 01:35:53 PM PDT 24
Peak memory 273508 kb
Host smart-3a34e5f3-c161-4de9-8637-5bc2a8763807
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307041942 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.3307041942
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.3446429402
Short name T421
Test name
Test status
Simulation time 2217966500 ps
CPU time 38.21 seconds
Started Jun 06 01:35:19 PM PDT 24
Finished Jun 06 01:35:58 PM PDT 24
Peak memory 261844 kb
Host smart-3d3803c3-5c99-40ec-80d4-2bdfee5fa485
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446429402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.3446429402
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.3151109149
Short name T347
Test name
Test status
Simulation time 2171244700 ps
CPU time 209.21 seconds
Started Jun 06 01:35:30 PM PDT 24
Finished Jun 06 01:39:01 PM PDT 24
Peak memory 291048 kb
Host smart-14343878-742b-4c90-a8a0-88caba9f16c5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151109149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.3151109149
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.712391064
Short name T477
Test name
Test status
Simulation time 11248947600 ps
CPU time 145.3 seconds
Started Jun 06 01:35:29 PM PDT 24
Finished Jun 06 01:37:55 PM PDT 24
Peak memory 292444 kb
Host smart-fc916f50-b7a8-4066-b7c2-45001ca8f740
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712391064 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.712391064
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.4037517596
Short name T149
Test name
Test status
Simulation time 42273600 ps
CPU time 133.45 seconds
Started Jun 06 01:35:19 PM PDT 24
Finished Jun 06 01:37:33 PM PDT 24
Peak memory 260744 kb
Host smart-bec3d340-9e8a-42b5-b8fd-49e2778f3784
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037517596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.4037517596
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.2162373131
Short name T768
Test name
Test status
Simulation time 87234200 ps
CPU time 14.44 seconds
Started Jun 06 01:35:27 PM PDT 24
Finished Jun 06 01:35:42 PM PDT 24
Peak memory 265140 kb
Host smart-dbe79551-81f3-4cc0-bd85-236046cfd7b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162373131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_re
set.2162373131
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.3512329758
Short name T1011
Test name
Test status
Simulation time 29876100 ps
CPU time 29.27 seconds
Started Jun 06 01:35:30 PM PDT 24
Finished Jun 06 01:36:00 PM PDT 24
Peak memory 276412 kb
Host smart-ee289305-2cc5-4067-a4d3-134b15766fc1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512329758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl
ash_ctrl_rw_evict.3512329758
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.3338246562
Short name T515
Test name
Test status
Simulation time 30759500 ps
CPU time 29.19 seconds
Started Jun 06 01:35:27 PM PDT 24
Finished Jun 06 01:35:57 PM PDT 24
Peak memory 267396 kb
Host smart-ba493c01-9e99-4eb9-b8c6-327195c23148
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338246562 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.3338246562
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.1728710050
Short name T387
Test name
Test status
Simulation time 92860600 ps
CPU time 98.28 seconds
Started Jun 06 01:35:20 PM PDT 24
Finished Jun 06 01:36:59 PM PDT 24
Peak memory 276964 kb
Host smart-108da527-d303-4d3b-a396-52ddc1506a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728710050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.1728710050
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.1901680522
Short name T450
Test name
Test status
Simulation time 39236200 ps
CPU time 13.78 seconds
Started Jun 06 01:35:31 PM PDT 24
Finished Jun 06 01:35:46 PM PDT 24
Peak memory 257968 kb
Host smart-ae9df032-8ba5-4696-9628-084568bfba35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901680522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
1901680522
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.2645077216
Short name T635
Test name
Test status
Simulation time 20053700 ps
CPU time 16.2 seconds
Started Jun 06 01:35:30 PM PDT 24
Finished Jun 06 01:35:47 PM PDT 24
Peak memory 274832 kb
Host smart-5b1a629c-5116-419f-a132-069bbb1ea723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645077216 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.2645077216
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.3504961065
Short name T365
Test name
Test status
Simulation time 27283500 ps
CPU time 22.33 seconds
Started Jun 06 01:35:29 PM PDT 24
Finished Jun 06 01:35:53 PM PDT 24
Peak memory 273552 kb
Host smart-ca7f315f-32b3-442f-850d-48da1845c810
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504961065 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.3504961065
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.2692546890
Short name T1080
Test name
Test status
Simulation time 5865716400 ps
CPU time 222.42 seconds
Started Jun 06 01:35:30 PM PDT 24
Finished Jun 06 01:39:14 PM PDT 24
Peak memory 262428 kb
Host smart-e1153ca1-afb5-4d02-bda7-f0b4f59bfa14
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692546890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.2692546890
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.2383097996
Short name T336
Test name
Test status
Simulation time 14368089800 ps
CPU time 220.72 seconds
Started Jun 06 01:35:26 PM PDT 24
Finished Jun 06 01:39:07 PM PDT 24
Peak memory 284576 kb
Host smart-aa0129fe-0de2-4f99-910a-d3ab9470cf81
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383097996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_intr_rd.2383097996
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3068376285
Short name T38
Test name
Test status
Simulation time 26169838800 ps
CPU time 312.54 seconds
Started Jun 06 01:35:31 PM PDT 24
Finished Jun 06 01:40:45 PM PDT 24
Peak memory 289824 kb
Host smart-db138aa2-7e43-4263-b2c0-55f4fc4a08db
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068376285 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.3068376285
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.1929825896
Short name T861
Test name
Test status
Simulation time 40148000 ps
CPU time 129.87 seconds
Started Jun 06 01:35:28 PM PDT 24
Finished Jun 06 01:37:39 PM PDT 24
Peak memory 259804 kb
Host smart-b2400054-4a85-443e-971e-36e8b09ef67f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929825896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.1929825896
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.151104552
Short name T961
Test name
Test status
Simulation time 40579300 ps
CPU time 13.84 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:35:53 PM PDT 24
Peak memory 265204 kb
Host smart-65be7aaf-f71e-4c7b-a0f2-6805a1af5662
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151104552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_res
et.151104552
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.3835962749
Short name T1019
Test name
Test status
Simulation time 47901200 ps
CPU time 31.36 seconds
Started Jun 06 01:35:30 PM PDT 24
Finished Jun 06 01:36:03 PM PDT 24
Peak memory 267412 kb
Host smart-295c6ef6-85da-4a8f-b8eb-8a59f4bbc24f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835962749 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.3835962749
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.2270580274
Short name T378
Test name
Test status
Simulation time 1466815600 ps
CPU time 62.96 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:36:42 PM PDT 24
Peak memory 264964 kb
Host smart-5dda3820-fec4-429a-8df3-08f0e706629c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270580274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.2270580274
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.2064243302
Short name T551
Test name
Test status
Simulation time 25747700 ps
CPU time 77.89 seconds
Started Jun 06 01:35:28 PM PDT 24
Finished Jun 06 01:36:47 PM PDT 24
Peak memory 269668 kb
Host smart-b3bc66b5-4d8f-4d9a-a819-1d8233e96f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064243302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.2064243302
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.2994536721
Short name T453
Test name
Test status
Simulation time 65405600 ps
CPU time 14.23 seconds
Started Jun 06 01:35:27 PM PDT 24
Finished Jun 06 01:35:42 PM PDT 24
Peak memory 264920 kb
Host smart-e41be4f5-ae4a-4ff3-9b83-78164c5ecaa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994536721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
2994536721
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.178742418
Short name T1053
Test name
Test status
Simulation time 29305800 ps
CPU time 16.54 seconds
Started Jun 06 01:35:28 PM PDT 24
Finished Jun 06 01:35:45 PM PDT 24
Peak memory 274608 kb
Host smart-3e0909bf-11bd-4842-9153-a9fa50f4ee92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178742418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.178742418
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.516208609
Short name T49
Test name
Test status
Simulation time 22606800 ps
CPU time 21.57 seconds
Started Jun 06 01:35:28 PM PDT 24
Finished Jun 06 01:35:50 PM PDT 24
Peak memory 273576 kb
Host smart-6085218d-0ff4-4974-8106-518ea437f37b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516208609 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.516208609
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.3620561528
Short name T448
Test name
Test status
Simulation time 5714712200 ps
CPU time 158.23 seconds
Started Jun 06 01:35:29 PM PDT 24
Finished Jun 06 01:38:08 PM PDT 24
Peak memory 262964 kb
Host smart-cc462f31-6509-4767-8559-71ed34c6d6e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620561528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.3620561528
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.3758261232
Short name T1009
Test name
Test status
Simulation time 1730647700 ps
CPU time 203.48 seconds
Started Jun 06 01:35:29 PM PDT 24
Finished Jun 06 01:38:53 PM PDT 24
Peak memory 291076 kb
Host smart-a6b5615a-f96c-4922-bf3d-551f78b18f04
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758261232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.3758261232
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.1530222218
Short name T723
Test name
Test status
Simulation time 37527200 ps
CPU time 110.72 seconds
Started Jun 06 01:35:31 PM PDT 24
Finished Jun 06 01:37:23 PM PDT 24
Peak memory 259720 kb
Host smart-409cc65b-ae3d-44ac-8ea0-56f2a586afa5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530222218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.1530222218
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.3641362430
Short name T666
Test name
Test status
Simulation time 3733858800 ps
CPU time 192.41 seconds
Started Jun 06 01:35:28 PM PDT 24
Finished Jun 06 01:38:42 PM PDT 24
Peak memory 265072 kb
Host smart-abb0a3bb-b217-4eb1-93ee-aee7b34de639
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641362430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.3641362430
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.2128984350
Short name T937
Test name
Test status
Simulation time 28801100 ps
CPU time 31.26 seconds
Started Jun 06 01:35:28 PM PDT 24
Finished Jun 06 01:36:00 PM PDT 24
Peak memory 275228 kb
Host smart-c7e9bf41-f46b-4e85-a806-2efaf859385c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128984350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.2128984350
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.3844731465
Short name T33
Test name
Test status
Simulation time 31763600 ps
CPU time 31.22 seconds
Started Jun 06 01:35:30 PM PDT 24
Finished Jun 06 01:36:02 PM PDT 24
Peak memory 273536 kb
Host smart-cb84c3a3-ee41-473f-9e9d-a9e612eb4513
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844731465 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.3844731465
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.606867109
Short name T220
Test name
Test status
Simulation time 135601200 ps
CPU time 53.05 seconds
Started Jun 06 01:35:29 PM PDT 24
Finished Jun 06 01:36:23 PM PDT 24
Peak memory 270908 kb
Host smart-675851f8-1f9c-4aca-87b5-e0e93353bc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606867109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.606867109
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.1104663133
Short name T1093
Test name
Test status
Simulation time 82478800 ps
CPU time 14.09 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:32:36 PM PDT 24
Peak memory 258196 kb
Host smart-eb9ae228-3cf7-4b25-85de-f348683dfbdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104663133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.1
104663133
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.4179149674
Short name T1076
Test name
Test status
Simulation time 21920000 ps
CPU time 13.9 seconds
Started Jun 06 01:32:18 PM PDT 24
Finished Jun 06 01:32:33 PM PDT 24
Peak memory 261312 kb
Host smart-d5977cc8-a8e9-436f-9d56-c4fd54539591
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179149674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.4179149674
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.1857025323
Short name T680
Test name
Test status
Simulation time 15980600 ps
CPU time 13.2 seconds
Started Jun 06 01:32:17 PM PDT 24
Finished Jun 06 01:32:31 PM PDT 24
Peak memory 274844 kb
Host smart-5deaa375-667b-43e4-97fb-f8239fe69389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857025323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.1857025323
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.2254936611
Short name T418
Test name
Test status
Simulation time 184688200 ps
CPU time 104.76 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 01:34:09 PM PDT 24
Peak memory 281712 kb
Host smart-ad1f1b57-cd13-42c6-b294-4d8bd521e652
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254936611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_derr_detect.2254936611
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.3388056373
Short name T367
Test name
Test status
Simulation time 41557900 ps
CPU time 20.76 seconds
Started Jun 06 01:32:30 PM PDT 24
Finished Jun 06 01:32:52 PM PDT 24
Peak memory 265292 kb
Host smart-06bf7a5b-a007-4c3f-a91d-517cf5a8d184
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388056373 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.3388056373
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.4036303154
Short name T543
Test name
Test status
Simulation time 7396116100 ps
CPU time 2301.53 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 02:10:45 PM PDT 24
Peak memory 264752 kb
Host smart-18ffea42-4a0f-4088-a32d-f809d138b537
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036303154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.4036303154
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.2700651140
Short name T534
Test name
Test status
Simulation time 3240675900 ps
CPU time 3446.61 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 02:29:52 PM PDT 24
Peak memory 262096 kb
Host smart-409b5592-df7d-4bd2-9477-558b67010058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700651140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.2700651140
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.158481507
Short name T562
Test name
Test status
Simulation time 5135849200 ps
CPU time 773.47 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 01:45:17 PM PDT 24
Peak memory 264524 kb
Host smart-ec6de2e1-8cd5-420d-a2de-6500162dd1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158481507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.158481507
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.481625006
Short name T60
Test name
Test status
Simulation time 566192300 ps
CPU time 20.08 seconds
Started Jun 06 01:32:21 PM PDT 24
Finished Jun 06 01:32:43 PM PDT 24
Peak memory 263404 kb
Host smart-d02faead-4ce0-4e78-baa6-c8477883cae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481625006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.481625006
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.1088478939
Short name T651
Test name
Test status
Simulation time 741071600 ps
CPU time 34.83 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:32:59 PM PDT 24
Peak memory 262576 kb
Host smart-683d28a0-110b-4a7c-ae4f-79192de33fb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088478939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.1088478939
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.2828047581
Short name T25
Test name
Test status
Simulation time 243327220400 ps
CPU time 2739.45 seconds
Started Jun 06 01:32:25 PM PDT 24
Finished Jun 06 02:18:06 PM PDT 24
Peak memory 263900 kb
Host smart-c4772002-ddac-4f20-b1e8-1375e83023aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828047581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.2828047581
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.2269786106
Short name T207
Test name
Test status
Simulation time 162088700 ps
CPU time 82.91 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 01:33:46 PM PDT 24
Peak memory 262292 kb
Host smart-88f7cc6a-1a78-4c4d-bcb9-524ed03dfb7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2269786106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.2269786106
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2912725960
Short name T753
Test name
Test status
Simulation time 10016701800 ps
CPU time 85.78 seconds
Started Jun 06 01:32:21 PM PDT 24
Finished Jun 06 01:33:48 PM PDT 24
Peak memory 291764 kb
Host smart-82a89a31-2d16-4ca8-80ed-6a8ca399f905
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912725960 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.2912725960
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.1186056603
Short name T789
Test name
Test status
Simulation time 45517200 ps
CPU time 13.69 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:32:35 PM PDT 24
Peak memory 264596 kb
Host smart-0f49c375-b507-4051-a47d-c11236915f73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186056603 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.1186056603
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.3974239447
Short name T27
Test name
Test status
Simulation time 40121213800 ps
CPU time 812.99 seconds
Started Jun 06 01:32:19 PM PDT 24
Finished Jun 06 01:45:53 PM PDT 24
Peak memory 264324 kb
Host smart-26947218-a707-4469-8cda-50f4d19c8f41
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974239447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_hw_rma_reset.3974239447
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.1278026201
Short name T311
Test name
Test status
Simulation time 3815810300 ps
CPU time 143.68 seconds
Started Jun 06 01:32:19 PM PDT 24
Finished Jun 06 01:34:44 PM PDT 24
Peak memory 262964 kb
Host smart-57c12f56-bd6c-408f-92f5-01601cb935bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278026201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.1278026201
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_integrity.282893111
Short name T240
Test name
Test status
Simulation time 5809045700 ps
CPU time 508.51 seconds
Started Jun 06 01:32:29 PM PDT 24
Finished Jun 06 01:40:59 PM PDT 24
Peak memory 327816 kb
Host smart-6d6476e3-94a8-4012-8b24-f816b8fd6b59
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282893111 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.flash_ctrl_integrity.282893111
Directory /workspace/3.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.3819663805
Short name T1008
Test name
Test status
Simulation time 2737788100 ps
CPU time 179.77 seconds
Started Jun 06 01:32:21 PM PDT 24
Finished Jun 06 01:35:22 PM PDT 24
Peak memory 293948 kb
Host smart-270028a5-fddb-454c-93cc-04462604e55b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819663805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.3819663805
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.3275935616
Short name T466
Test name
Test status
Simulation time 7343714900 ps
CPU time 124.52 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 01:34:29 PM PDT 24
Peak memory 292416 kb
Host smart-7a33c795-45b4-4901-951d-11577ba1696e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275935616 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.3275935616
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.3728389277
Short name T1016
Test name
Test status
Simulation time 5699322900 ps
CPU time 83.33 seconds
Started Jun 06 01:32:21 PM PDT 24
Finished Jun 06 01:33:45 PM PDT 24
Peak memory 265268 kb
Host smart-2b10bb31-e146-4b8e-bad4-6e6dd138c308
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728389277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.3728389277
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.132036401
Short name T835
Test name
Test status
Simulation time 26672167600 ps
CPU time 208.58 seconds
Started Jun 06 01:32:19 PM PDT 24
Finished Jun 06 01:35:49 PM PDT 24
Peak memory 259640 kb
Host smart-1f8fc163-64a7-4672-aae4-30ec62595bd6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132
036401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.132036401
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.726644934
Short name T482
Test name
Test status
Simulation time 4290318100 ps
CPU time 68.04 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:33:37 PM PDT 24
Peak memory 260504 kb
Host smart-ee301d20-0f4b-482e-97f2-28bdaef040b6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726644934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.726644934
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.3062391210
Short name T637
Test name
Test status
Simulation time 15015200 ps
CPU time 13.62 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 01:32:37 PM PDT 24
Peak memory 259412 kb
Host smart-c72a2997-3b0c-44a0-87d1-aac449564e1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062391210 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.3062391210
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.1098932853
Short name T820
Test name
Test status
Simulation time 42762631600 ps
CPU time 299.53 seconds
Started Jun 06 01:32:21 PM PDT 24
Finished Jun 06 01:37:21 PM PDT 24
Peak memory 274384 kb
Host smart-9aecedb2-5f3f-4ff8-9dd5-7854f37d0d3b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098932853 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.1098932853
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.594522126
Short name T75
Test name
Test status
Simulation time 70265700 ps
CPU time 133.53 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:34:42 PM PDT 24
Peak memory 259604 kb
Host smart-7b9577f6-fcfd-4e35-8907-a159771faa97
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594522126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp
_reset.594522126
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.1009699252
Short name T1002
Test name
Test status
Simulation time 25988759800 ps
CPU time 202.17 seconds
Started Jun 06 01:32:29 PM PDT 24
Finished Jun 06 01:35:53 PM PDT 24
Peak memory 294856 kb
Host smart-2f0b251b-8668-4b33-ad6b-053f5490e6d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009699252 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.1009699252
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.3178102745
Short name T135
Test name
Test status
Simulation time 78875600 ps
CPU time 14.27 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:32:35 PM PDT 24
Peak memory 279052 kb
Host smart-250c110a-1cf0-43fe-a392-b901b060dead
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3178102745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.3178102745
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.1177843194
Short name T505
Test name
Test status
Simulation time 693211000 ps
CPU time 207.4 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 01:35:51 PM PDT 24
Peak memory 262800 kb
Host smart-7ba97d45-e548-4a10-b43e-c0d3ab5df226
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1177843194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1177843194
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.3306309714
Short name T171
Test name
Test status
Simulation time 46067800 ps
CPU time 14.28 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:32:36 PM PDT 24
Peak memory 262384 kb
Host smart-f2fdfb01-e0a4-4034-aee3-9ca4be5b5557
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306309714 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.3306309714
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.3228405059
Short name T641
Test name
Test status
Simulation time 21744100 ps
CPU time 13.45 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:32:42 PM PDT 24
Peak memory 265204 kb
Host smart-348f16ac-2978-4d11-be6f-fc2ed54e2dc1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228405059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.3228405059
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.30607394
Short name T114
Test name
Test status
Simulation time 312895300 ps
CPU time 301.87 seconds
Started Jun 06 01:32:19 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 281556 kb
Host smart-0a4a6506-9202-4d58-b3eb-6695f5e98d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30607394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.30607394
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.2285303176
Short name T1090
Test name
Test status
Simulation time 92906500 ps
CPU time 34.89 seconds
Started Jun 06 01:32:28 PM PDT 24
Finished Jun 06 01:33:05 PM PDT 24
Peak memory 275560 kb
Host smart-36ddfe3c-7c85-4490-a6cb-0c47d0ad1ab4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285303176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.2285303176
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.1302885535
Short name T736
Test name
Test status
Simulation time 27128700 ps
CPU time 23.19 seconds
Started Jun 06 01:32:26 PM PDT 24
Finished Jun 06 01:32:51 PM PDT 24
Peak memory 264764 kb
Host smart-c1291deb-df01-450d-a081-48c432641887
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302885535 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.1302885535
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.1778931644
Short name T851
Test name
Test status
Simulation time 2067163300 ps
CPU time 102.56 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:34:08 PM PDT 24
Peak memory 280716 kb
Host smart-30f6f7a4-e929-48b7-b20a-cfd9a254293a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778931644 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.1778931644
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.2614653254
Short name T200
Test name
Test status
Simulation time 514755500 ps
CPU time 157.08 seconds
Started Jun 06 01:32:26 PM PDT 24
Finished Jun 06 01:35:04 PM PDT 24
Peak memory 281736 kb
Host smart-aa780f54-33c1-4494-a95b-7e75e81e7c20
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2614653254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.2614653254
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.1638349263
Short name T588
Test name
Test status
Simulation time 1954140700 ps
CPU time 138.14 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:34:46 PM PDT 24
Peak memory 294680 kb
Host smart-c5aeaca6-f261-4056-92f6-f09c2e52e7a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638349263 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.1638349263
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.1026875664
Short name T599
Test name
Test status
Simulation time 27690767100 ps
CPU time 597.19 seconds
Started Jun 06 01:32:28 PM PDT 24
Finished Jun 06 01:42:27 PM PDT 24
Peak memory 314412 kb
Host smart-bf11ead7-04dc-4ce3-9ba5-a23472323012
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026875664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_rw.1026875664
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.426225727
Short name T587
Test name
Test status
Simulation time 98580400 ps
CPU time 30.74 seconds
Started Jun 06 01:32:29 PM PDT 24
Finished Jun 06 01:33:01 PM PDT 24
Peak memory 277272 kb
Host smart-650cd07b-7178-48a9-9595-5a1a0920651c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426225727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_rw_evict.426225727
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.3760434142
Short name T194
Test name
Test status
Simulation time 123132400 ps
CPU time 31.05 seconds
Started Jun 06 01:32:28 PM PDT 24
Finished Jun 06 01:33:00 PM PDT 24
Peak memory 275556 kb
Host smart-6e08c2c1-5fcb-41ca-aa24-4884832a4d05
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760434142 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.3760434142
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.78048479
Short name T811
Test name
Test status
Simulation time 609382500 ps
CPU time 51.12 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:33:16 PM PDT 24
Peak memory 264788 kb
Host smart-0e7f98c6-24b6-472f-ba2a-26fd707b678c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78048479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_serr_address.78048479
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.4118924150
Short name T809
Test name
Test status
Simulation time 2080889900 ps
CPU time 62.27 seconds
Started Jun 06 01:32:24 PM PDT 24
Finished Jun 06 01:33:28 PM PDT 24
Peak memory 273528 kb
Host smart-691387c7-81ce-4ca3-8f9c-15bbcc67f9ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118924150 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.4118924150
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.3660105679
Short name T973
Test name
Test status
Simulation time 16425600 ps
CPU time 77.12 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:33:39 PM PDT 24
Peak memory 276432 kb
Host smart-201821bc-0755-4dd1-929b-8959c5a83475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660105679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.3660105679
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.2940999237
Short name T1021
Test name
Test status
Simulation time 57354000 ps
CPU time 26.44 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:32:48 PM PDT 24
Peak memory 259140 kb
Host smart-ccbee10b-e3f2-41a5-9e95-f969a24c1dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940999237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.2940999237
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.1459160522
Short name T1089
Test name
Test status
Simulation time 263585700 ps
CPU time 672.48 seconds
Started Jun 06 01:32:18 PM PDT 24
Finished Jun 06 01:43:32 PM PDT 24
Peak memory 280960 kb
Host smart-96cec7e6-46e5-4e64-a8d0-d694b516de9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459160522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.1459160522
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.966613193
Short name T614
Test name
Test status
Simulation time 399644100 ps
CPU time 26.59 seconds
Started Jun 06 01:32:17 PM PDT 24
Finished Jun 06 01:32:44 PM PDT 24
Peak memory 261952 kb
Host smart-b9797913-01f2-4d80-9fbc-0383ccd3ac10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966613193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.966613193
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.391000106
Short name T792
Test name
Test status
Simulation time 2480889100 ps
CPU time 177.24 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:35:22 PM PDT 24
Peak memory 265240 kb
Host smart-21038ab9-8241-4040-a762-995ec15eb191
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391000106 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.flash_ctrl_wo.391000106
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.1184747582
Short name T773
Test name
Test status
Simulation time 44746800 ps
CPU time 13.63 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:35:53 PM PDT 24
Peak memory 257984 kb
Host smart-97c8a5fc-7e35-4a3d-aec3-c0e755bafef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184747582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
1184747582
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.3732660542
Short name T636
Test name
Test status
Simulation time 24453600 ps
CPU time 13.61 seconds
Started Jun 06 01:35:36 PM PDT 24
Finished Jun 06 01:35:50 PM PDT 24
Peak memory 274848 kb
Host smart-f11bde47-a523-49f7-a440-2fed0ae3f656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732660542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.3732660542
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.3037786743
Short name T976
Test name
Test status
Simulation time 70020400 ps
CPU time 20.86 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:36:00 PM PDT 24
Peak memory 264700 kb
Host smart-75cb7574-c6bb-4914-b0f0-8a3b5f1e5482
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037786743 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.3037786743
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.1847981334
Short name T309
Test name
Test status
Simulation time 5720636600 ps
CPU time 170.56 seconds
Started Jun 06 01:35:40 PM PDT 24
Finished Jun 06 01:38:31 PM PDT 24
Peak memory 260652 kb
Host smart-65e34e80-059e-4297-bd80-78ff47730c0f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847981334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.1847981334
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3674009523
Short name T705
Test name
Test status
Simulation time 5489638000 ps
CPU time 158.59 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:38:18 PM PDT 24
Peak memory 294056 kb
Host smart-001b08d6-180c-417b-b6ab-ac7155e3b9d9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674009523 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.3674009523
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.3915325944
Short name T578
Test name
Test status
Simulation time 156818300 ps
CPU time 133.41 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:37:52 PM PDT 24
Peak memory 260824 kb
Host smart-511d22b1-5315-4932-92c8-5ca246ac7765
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915325944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.3915325944
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.2486599068
Short name T945
Test name
Test status
Simulation time 67151500 ps
CPU time 31.25 seconds
Started Jun 06 01:35:39 PM PDT 24
Finished Jun 06 01:36:11 PM PDT 24
Peak memory 275620 kb
Host smart-973cd56e-516f-4817-9736-022658a7fa9b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486599068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fl
ash_ctrl_rw_evict.2486599068
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.1772578049
Short name T978
Test name
Test status
Simulation time 70217300 ps
CPU time 32.08 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:36:12 PM PDT 24
Peak memory 273540 kb
Host smart-cc56ecda-5373-45d4-b23d-cca52ffedb16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772578049 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.1772578049
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.1455107331
Short name T703
Test name
Test status
Simulation time 3063593700 ps
CPU time 80.99 seconds
Started Jun 06 01:35:37 PM PDT 24
Finished Jun 06 01:36:59 PM PDT 24
Peak memory 262756 kb
Host smart-1411994f-eb26-4ef8-a1bb-52a8b8e22560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455107331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.1455107331
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.459910384
Short name T192
Test name
Test status
Simulation time 18495900 ps
CPU time 50.23 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:36:30 PM PDT 24
Peak memory 270912 kb
Host smart-d210502e-6d29-4c65-96f6-7ba14906ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459910384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.459910384
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.2643269302
Short name T598
Test name
Test status
Simulation time 62183400 ps
CPU time 14.63 seconds
Started Jun 06 01:35:42 PM PDT 24
Finished Jun 06 01:35:57 PM PDT 24
Peak memory 264920 kb
Host smart-230dbcc4-19c5-4884-8e08-3dfa17599ab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643269302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
2643269302
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.2105905764
Short name T1039
Test name
Test status
Simulation time 18400900 ps
CPU time 16.2 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:35:56 PM PDT 24
Peak memory 274720 kb
Host smart-c6e67e53-96a1-480b-8ea4-35ae5ef733a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105905764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.2105905764
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.266336499
Short name T828
Test name
Test status
Simulation time 12680400 ps
CPU time 22.75 seconds
Started Jun 06 01:35:39 PM PDT 24
Finished Jun 06 01:36:03 PM PDT 24
Peak memory 264676 kb
Host smart-ccec6a2f-0fbd-4a97-88e7-ebf97627c149
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266336499 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.266336499
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.1579125907
Short name T836
Test name
Test status
Simulation time 8873420000 ps
CPU time 151.22 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:38:11 PM PDT 24
Peak memory 262920 kb
Host smart-30403d3e-b914-48db-895b-65d2e0f44102
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579125907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.1579125907
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.397529818
Short name T40
Test name
Test status
Simulation time 2550030800 ps
CPU time 152.52 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:38:12 PM PDT 24
Peak memory 291724 kb
Host smart-2f54d48c-1ee6-4b83-817b-724f4a8082ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397529818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flas
h_ctrl_intr_rd.397529818
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.486073874
Short name T930
Test name
Test status
Simulation time 47059653000 ps
CPU time 159.49 seconds
Started Jun 06 01:35:39 PM PDT 24
Finished Jun 06 01:38:20 PM PDT 24
Peak memory 292192 kb
Host smart-62d1f0fc-cabd-4dd1-9814-5b65f46cbfa4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486073874 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.486073874
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.3480414758
Short name T1065
Test name
Test status
Simulation time 33988200 ps
CPU time 112.45 seconds
Started Jun 06 01:35:37 PM PDT 24
Finished Jun 06 01:37:30 PM PDT 24
Peak memory 259996 kb
Host smart-5b575614-b20e-49e2-a12d-aceb592d1ead
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480414758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.3480414758
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.3768521619
Short name T886
Test name
Test status
Simulation time 77755700 ps
CPU time 31.26 seconds
Started Jun 06 01:35:37 PM PDT 24
Finished Jun 06 01:36:10 PM PDT 24
Peak memory 275596 kb
Host smart-86ecb609-842b-44b2-9954-80172af62a0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768521619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.3768521619
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.604104071
Short name T31
Test name
Test status
Simulation time 52992200 ps
CPU time 28.66 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:36:08 PM PDT 24
Peak memory 275540 kb
Host smart-d7f96bbe-45f0-4acc-a617-8175cac399d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604104071 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.604104071
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.1982436217
Short name T499
Test name
Test status
Simulation time 13748054300 ps
CPU time 64.63 seconds
Started Jun 06 01:35:38 PM PDT 24
Finished Jun 06 01:36:44 PM PDT 24
Peak memory 263436 kb
Host smart-c9140711-1243-43e0-87a5-0bd40b95b8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982436217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.1982436217
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.2729294353
Short name T516
Test name
Test status
Simulation time 29664000 ps
CPU time 103.86 seconds
Started Jun 06 01:35:37 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 276384 kb
Host smart-4ccfa525-f271-4a14-a562-aca097f773a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729294353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.2729294353
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.3976882576
Short name T470
Test name
Test status
Simulation time 77108100 ps
CPU time 14.02 seconds
Started Jun 06 01:35:47 PM PDT 24
Finished Jun 06 01:36:02 PM PDT 24
Peak memory 264848 kb
Host smart-deb3d6a0-61a3-4256-a881-0c8a778ac9c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976882576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
3976882576
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.1568998384
Short name T802
Test name
Test status
Simulation time 39621300 ps
CPU time 15.87 seconds
Started Jun 06 01:35:47 PM PDT 24
Finished Jun 06 01:36:04 PM PDT 24
Peak memory 274724 kb
Host smart-cf4a8ef4-a11e-40d5-a827-708798ee4056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568998384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.1568998384
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.3421730563
Short name T396
Test name
Test status
Simulation time 10153700 ps
CPU time 22.16 seconds
Started Jun 06 01:35:49 PM PDT 24
Finished Jun 06 01:36:12 PM PDT 24
Peak memory 273568 kb
Host smart-c95b5d84-08b5-493c-b574-5309660cb48b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421730563 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.3421730563
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.695093250
Short name T760
Test name
Test status
Simulation time 1074916900 ps
CPU time 34.45 seconds
Started Jun 06 01:35:47 PM PDT 24
Finished Jun 06 01:36:22 PM PDT 24
Peak memory 262940 kb
Host smart-4ad170a7-7f5f-47d8-accc-c0f9be9906ce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695093250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_h
w_sec_otp.695093250
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.55624863
Short name T519
Test name
Test status
Simulation time 5707947700 ps
CPU time 153.74 seconds
Started Jun 06 01:35:46 PM PDT 24
Finished Jun 06 01:38:21 PM PDT 24
Peak memory 292144 kb
Host smart-259d9933-2619-41ef-b95b-f13d9075681e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55624863 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.55624863
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.3317467997
Short name T315
Test name
Test status
Simulation time 33707000 ps
CPU time 31.24 seconds
Started Jun 06 01:35:47 PM PDT 24
Finished Jun 06 01:36:19 PM PDT 24
Peak memory 275200 kb
Host smart-387a2016-8326-4b6c-a407-5011ab705d3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317467997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl
ash_ctrl_rw_evict.3317467997
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.3710924775
Short name T596
Test name
Test status
Simulation time 185269500 ps
CPU time 31.45 seconds
Started Jun 06 01:35:46 PM PDT 24
Finished Jun 06 01:36:19 PM PDT 24
Peak memory 275556 kb
Host smart-cc1e9b84-8f31-4da4-9896-32c020376bdc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710924775 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.3710924775
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.883412590
Short name T379
Test name
Test status
Simulation time 5739081600 ps
CPU time 71.35 seconds
Started Jun 06 01:35:49 PM PDT 24
Finished Jun 06 01:37:01 PM PDT 24
Peak memory 263316 kb
Host smart-9a953d5a-538b-4031-b31a-8b7c3d543168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883412590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.883412590
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.3840518593
Short name T863
Test name
Test status
Simulation time 73564700 ps
CPU time 126.32 seconds
Started Jun 06 01:35:51 PM PDT 24
Finished Jun 06 01:37:57 PM PDT 24
Peak memory 276084 kb
Host smart-00b3ca4a-5c53-48f1-9b19-63f2405454ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840518593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.3840518593
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.2703833271
Short name T497
Test name
Test status
Simulation time 108825100 ps
CPU time 13.88 seconds
Started Jun 06 01:35:51 PM PDT 24
Finished Jun 06 01:36:05 PM PDT 24
Peak memory 258048 kb
Host smart-f3bd944e-9881-4ee1-9ddd-e38b205d2a9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703833271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
2703833271
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.2585927924
Short name T461
Test name
Test status
Simulation time 16912400 ps
CPU time 14.35 seconds
Started Jun 06 01:35:47 PM PDT 24
Finished Jun 06 01:36:02 PM PDT 24
Peak memory 274520 kb
Host smart-3b153915-34e8-4374-a9c1-2890b3e6763b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585927924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2585927924
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.3981824632
Short name T395
Test name
Test status
Simulation time 27785900 ps
CPU time 22.01 seconds
Started Jun 06 01:35:50 PM PDT 24
Finished Jun 06 01:36:12 PM PDT 24
Peak memory 264660 kb
Host smart-3b324ed2-0272-42c8-bfc4-9139dc93d8ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981824632 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.3981824632
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.3633274592
Short name T608
Test name
Test status
Simulation time 1544036700 ps
CPU time 70.96 seconds
Started Jun 06 01:35:48 PM PDT 24
Finished Jun 06 01:37:00 PM PDT 24
Peak memory 262888 kb
Host smart-a1ecea99-ea9f-4f3e-a688-2a02433ac0bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633274592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.3633274592
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.2708051995
Short name T561
Test name
Test status
Simulation time 6741313300 ps
CPU time 219.19 seconds
Started Jun 06 01:35:57 PM PDT 24
Finished Jun 06 01:39:37 PM PDT 24
Peak memory 292148 kb
Host smart-1dd0f75b-0028-414c-9ee6-bdf45b60fb09
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708051995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.2708051995
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3168555118
Short name T337
Test name
Test status
Simulation time 23418938200 ps
CPU time 151.61 seconds
Started Jun 06 01:35:47 PM PDT 24
Finished Jun 06 01:38:19 PM PDT 24
Peak memory 289848 kb
Host smart-0238d9ae-9daf-4eab-884e-3194a75ce5ff
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168555118 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.3168555118
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.1405065894
Short name T918
Test name
Test status
Simulation time 87938700 ps
CPU time 135.17 seconds
Started Jun 06 01:35:44 PM PDT 24
Finished Jun 06 01:38:00 PM PDT 24
Peak memory 261112 kb
Host smart-9620ad45-c953-4499-aa05-781697cb2dd4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405065894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.1405065894
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.14527112
Short name T321
Test name
Test status
Simulation time 27394800 ps
CPU time 31.88 seconds
Started Jun 06 01:35:49 PM PDT 24
Finished Jun 06 01:36:21 PM PDT 24
Peak memory 273528 kb
Host smart-9b3fb536-07a9-4480-b44e-5cb584b38b1e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14527112 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.14527112
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.1254451327
Short name T373
Test name
Test status
Simulation time 1749043000 ps
CPU time 66.08 seconds
Started Jun 06 01:35:47 PM PDT 24
Finished Jun 06 01:36:53 PM PDT 24
Peak memory 263444 kb
Host smart-9e7856ee-6852-4758-a579-6493a98dc8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254451327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1254451327
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.86359242
Short name T473
Test name
Test status
Simulation time 108288800 ps
CPU time 153.36 seconds
Started Jun 06 01:35:48 PM PDT 24
Finished Jun 06 01:38:22 PM PDT 24
Peak memory 278964 kb
Host smart-1d7d06d6-a74c-4713-986c-332c03e284a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86359242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.86359242
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.2466919976
Short name T427
Test name
Test status
Simulation time 102965300 ps
CPU time 13.82 seconds
Started Jun 06 01:35:56 PM PDT 24
Finished Jun 06 01:36:11 PM PDT 24
Peak memory 257972 kb
Host smart-5f519bdd-98ee-4b74-9f99-3c0418c28e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466919976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
2466919976
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.71004658
Short name T472
Test name
Test status
Simulation time 14872000 ps
CPU time 15.91 seconds
Started Jun 06 01:35:56 PM PDT 24
Finished Jun 06 01:36:12 PM PDT 24
Peak memory 274708 kb
Host smart-f2145d58-fe04-48d2-95ec-ae29addb5d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71004658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.71004658
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.1989645169
Short name T431
Test name
Test status
Simulation time 59804625600 ps
CPU time 167.91 seconds
Started Jun 06 01:35:57 PM PDT 24
Finished Jun 06 01:38:46 PM PDT 24
Peak memory 260592 kb
Host smart-bee9cf89-1b8f-4889-ada0-d3ef88a474d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989645169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.1989645169
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.1105499268
Short name T724
Test name
Test status
Simulation time 2919350500 ps
CPU time 224.09 seconds
Started Jun 06 01:35:50 PM PDT 24
Finished Jun 06 01:39:35 PM PDT 24
Peak memory 292132 kb
Host smart-40db0dee-9915-416a-b771-6fef65577ab4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105499268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_intr_rd.1105499268
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.2504969120
Short name T923
Test name
Test status
Simulation time 173262197800 ps
CPU time 427.11 seconds
Started Jun 06 01:35:57 PM PDT 24
Finished Jun 06 01:43:05 PM PDT 24
Peak memory 284792 kb
Host smart-cd60bcb3-11e3-44e7-9707-0b92e9bf72f4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504969120 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.2504969120
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.3366286677
Short name T988
Test name
Test status
Simulation time 45680800 ps
CPU time 111.47 seconds
Started Jun 06 01:35:49 PM PDT 24
Finished Jun 06 01:37:41 PM PDT 24
Peak memory 259796 kb
Host smart-7e0f7daa-568e-43a4-9126-7e61c5b0be0c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366286677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.3366286677
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.1789786631
Short name T854
Test name
Test status
Simulation time 46695800 ps
CPU time 31.07 seconds
Started Jun 06 01:35:48 PM PDT 24
Finished Jun 06 01:36:19 PM PDT 24
Peak memory 275184 kb
Host smart-8bbb46d2-fec5-4254-8a27-bd4b136bcfcc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789786631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.1789786631
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.4174415578
Short name T283
Test name
Test status
Simulation time 68981500 ps
CPU time 28.32 seconds
Started Jun 06 01:35:57 PM PDT 24
Finished Jun 06 01:36:26 PM PDT 24
Peak memory 275592 kb
Host smart-0180dbcf-9256-4a79-8822-c109760c5a0b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174415578 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.4174415578
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.1690821483
Short name T669
Test name
Test status
Simulation time 642710200 ps
CPU time 68.48 seconds
Started Jun 06 01:36:00 PM PDT 24
Finished Jun 06 01:37:09 PM PDT 24
Peak memory 263936 kb
Host smart-58f58ffe-ff91-4008-9628-83c3518d6fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690821483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.1690821483
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.2549599334
Short name T471
Test name
Test status
Simulation time 16935700 ps
CPU time 50.28 seconds
Started Jun 06 01:35:57 PM PDT 24
Finished Jun 06 01:36:48 PM PDT 24
Peak memory 270832 kb
Host smart-b46fb7fb-9e3c-44af-a6fb-a7b89752be17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549599334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.2549599334
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.4268264561
Short name T959
Test name
Test status
Simulation time 53287200 ps
CPU time 14.13 seconds
Started Jun 06 01:35:56 PM PDT 24
Finished Jun 06 01:36:10 PM PDT 24
Peak memory 264812 kb
Host smart-f82edbff-0350-485c-8800-f80ca0773f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268264561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
4268264561
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.2751978993
Short name T731
Test name
Test status
Simulation time 20181800 ps
CPU time 15.81 seconds
Started Jun 06 01:35:56 PM PDT 24
Finished Jun 06 01:36:13 PM PDT 24
Peak memory 274744 kb
Host smart-6bf0ed92-d941-4ac4-b443-d7e1751a5954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751978993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2751978993
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.2106857144
Short name T866
Test name
Test status
Simulation time 18488100 ps
CPU time 21.83 seconds
Started Jun 06 01:35:57 PM PDT 24
Finished Jun 06 01:36:20 PM PDT 24
Peak memory 273548 kb
Host smart-35da3c19-af6f-4333-aa15-d821030c3584
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106857144 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.2106857144
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.2029576476
Short name T481
Test name
Test status
Simulation time 9717372000 ps
CPU time 142.07 seconds
Started Jun 06 01:35:56 PM PDT 24
Finished Jun 06 01:38:19 PM PDT 24
Peak memory 262472 kb
Host smart-6be36855-f91a-47af-80ec-0fd209afaabf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029576476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.2029576476
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.109284534
Short name T343
Test name
Test status
Simulation time 543881900 ps
CPU time 128.73 seconds
Started Jun 06 01:35:55 PM PDT 24
Finished Jun 06 01:38:04 PM PDT 24
Peak memory 293692 kb
Host smart-f3823676-00c7-441c-8770-c2a2d645fca8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109284534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flas
h_ctrl_intr_rd.109284534
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.517380360
Short name T341
Test name
Test status
Simulation time 26014356500 ps
CPU time 308.49 seconds
Started Jun 06 01:35:56 PM PDT 24
Finished Jun 06 01:41:05 PM PDT 24
Peak memory 291600 kb
Host smart-8ccf01f7-5db5-4286-86de-afba5726df21
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517380360 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.517380360
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.852715369
Short name T540
Test name
Test status
Simulation time 211222700 ps
CPU time 135.05 seconds
Started Jun 06 01:35:56 PM PDT 24
Finished Jun 06 01:38:12 PM PDT 24
Peak memory 263948 kb
Host smart-d083d3f3-2944-48b7-9e41-bcea0fc27cc0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852715369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ot
p_reset.852715369
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.3692148745
Short name T891
Test name
Test status
Simulation time 133403100 ps
CPU time 30.76 seconds
Started Jun 06 01:35:59 PM PDT 24
Finished Jun 06 01:36:30 PM PDT 24
Peak memory 275664 kb
Host smart-af97d7c3-b284-4245-84c1-f5a87ef91718
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692148745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.3692148745
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.1441628502
Short name T537
Test name
Test status
Simulation time 104884200 ps
CPU time 30.92 seconds
Started Jun 06 01:36:00 PM PDT 24
Finished Jun 06 01:36:31 PM PDT 24
Peak memory 273488 kb
Host smart-705ef2cf-07c4-4966-a399-95f8dcec60e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441628502 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.1441628502
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.1401028615
Short name T525
Test name
Test status
Simulation time 3917315600 ps
CPU time 69.22 seconds
Started Jun 06 01:35:56 PM PDT 24
Finished Jun 06 01:37:06 PM PDT 24
Peak memory 263724 kb
Host smart-cf75779e-7fdf-4a80-ab0f-fddee3bc28e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401028615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.1401028615
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.586044374
Short name T460
Test name
Test status
Simulation time 33841600 ps
CPU time 76.99 seconds
Started Jun 06 01:35:57 PM PDT 24
Finished Jun 06 01:37:15 PM PDT 24
Peak memory 276644 kb
Host smart-7d89759d-fd86-4e1d-927a-b8d912ff9d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586044374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.586044374
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.2613652309
Short name T177
Test name
Test status
Simulation time 38636800 ps
CPU time 13.63 seconds
Started Jun 06 01:36:07 PM PDT 24
Finished Jun 06 01:36:22 PM PDT 24
Peak memory 264892 kb
Host smart-a342f8c1-f427-489f-ae3c-a53c75e1858d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613652309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
2613652309
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.3248077761
Short name T990
Test name
Test status
Simulation time 13157900 ps
CPU time 15.55 seconds
Started Jun 06 01:36:09 PM PDT 24
Finished Jun 06 01:36:25 PM PDT 24
Peak memory 274720 kb
Host smart-47514596-74a5-4328-ac7b-02001b8befad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248077761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3248077761
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.2681535167
Short name T730
Test name
Test status
Simulation time 11628557200 ps
CPU time 183.39 seconds
Started Jun 06 01:35:56 PM PDT 24
Finished Jun 06 01:39:00 PM PDT 24
Peak memory 262772 kb
Host smart-f35ebf31-fa7d-41d8-b987-ec6d6ed62c91
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681535167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.2681535167
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.3567989911
Short name T846
Test name
Test status
Simulation time 1317225200 ps
CPU time 117.66 seconds
Started Jun 06 01:36:08 PM PDT 24
Finished Jun 06 01:38:07 PM PDT 24
Peak memory 293776 kb
Host smart-b24bee22-b01b-4acc-831c-226a7ddeaff7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567989911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.3567989911
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3120853800
Short name T1095
Test name
Test status
Simulation time 11186953000 ps
CPU time 269.83 seconds
Started Jun 06 01:36:08 PM PDT 24
Finished Jun 06 01:40:39 PM PDT 24
Peak memory 284532 kb
Host smart-44784903-77b9-45f1-b011-0adc401bc068
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120853800 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.3120853800
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.1918859336
Short name T469
Test name
Test status
Simulation time 37417400 ps
CPU time 111.04 seconds
Started Jun 06 01:35:57 PM PDT 24
Finished Jun 06 01:37:49 PM PDT 24
Peak memory 264904 kb
Host smart-4cdf2c68-79c4-48d9-aa03-6a99b5f20d62
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918859336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.1918859336
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.2680639432
Short name T314
Test name
Test status
Simulation time 33182100 ps
CPU time 28.76 seconds
Started Jun 06 01:36:06 PM PDT 24
Finished Jun 06 01:36:35 PM PDT 24
Peak memory 275616 kb
Host smart-ba8e414c-f173-48c0-a5ec-7bb594146d25
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680639432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.2680639432
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.366227527
Short name T270
Test name
Test status
Simulation time 32585300 ps
CPU time 32.1 seconds
Started Jun 06 01:36:08 PM PDT 24
Finished Jun 06 01:36:41 PM PDT 24
Peak memory 267416 kb
Host smart-bb3fd09b-3c75-4040-92f9-d721af4d4432
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366227527 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.366227527
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.1336126823
Short name T372
Test name
Test status
Simulation time 1303105200 ps
CPU time 49.62 seconds
Started Jun 06 01:36:09 PM PDT 24
Finished Jun 06 01:36:59 PM PDT 24
Peak memory 263648 kb
Host smart-9478602d-9743-43ad-aa05-49e1877ffdfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336126823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.1336126823
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.2608630206
Short name T1054
Test name
Test status
Simulation time 80237600 ps
CPU time 74.72 seconds
Started Jun 06 01:35:56 PM PDT 24
Finished Jun 06 01:37:11 PM PDT 24
Peak memory 276548 kb
Host smart-dd92813f-4820-48e4-af65-ea6cc110845c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608630206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2608630206
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.870245214
Short name T1045
Test name
Test status
Simulation time 42164300 ps
CPU time 14.04 seconds
Started Jun 06 01:36:08 PM PDT 24
Finished Jun 06 01:36:23 PM PDT 24
Peak memory 258028 kb
Host smart-f9e6c2ad-7006-47aa-afa6-8ef430ece0cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870245214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.870245214
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.1467188016
Short name T48
Test name
Test status
Simulation time 83841500 ps
CPU time 16.37 seconds
Started Jun 06 01:36:09 PM PDT 24
Finished Jun 06 01:36:26 PM PDT 24
Peak memory 274680 kb
Host smart-49cf97a6-d214-443c-accd-3fef16836262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467188016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.1467188016
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.2929694968
Short name T393
Test name
Test status
Simulation time 15916800 ps
CPU time 22.04 seconds
Started Jun 06 01:36:08 PM PDT 24
Finished Jun 06 01:36:31 PM PDT 24
Peak memory 273516 kb
Host smart-042e2503-6613-4460-97bd-a872b7d13a74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929694968 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.2929694968
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.4031808970
Short name T619
Test name
Test status
Simulation time 19762627100 ps
CPU time 243.45 seconds
Started Jun 06 01:36:08 PM PDT 24
Finished Jun 06 01:40:12 PM PDT 24
Peak memory 262380 kb
Host smart-e1859e58-efef-49b7-bed8-c118710643c6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031808970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.4031808970
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.4076160253
Short name T639
Test name
Test status
Simulation time 1773658800 ps
CPU time 210.89 seconds
Started Jun 06 01:36:07 PM PDT 24
Finished Jun 06 01:39:39 PM PDT 24
Peak memory 284556 kb
Host smart-ce8f141d-6eb8-471d-baca-737572af3e92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076160253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.4076160253
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.1305872031
Short name T542
Test name
Test status
Simulation time 8765178000 ps
CPU time 224.54 seconds
Started Jun 06 01:36:07 PM PDT 24
Finished Jun 06 01:39:52 PM PDT 24
Peak memory 291736 kb
Host smart-2a60892f-e55b-4105-b616-ed8fa5319b84
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305872031 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.1305872031
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.3015777114
Short name T136
Test name
Test status
Simulation time 215869700 ps
CPU time 132.5 seconds
Started Jun 06 01:36:07 PM PDT 24
Finished Jun 06 01:38:21 PM PDT 24
Peak memory 260824 kb
Host smart-d8ac646f-4ee1-47fa-9b80-2768fd0d6ddf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015777114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.3015777114
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.2022857257
Short name T439
Test name
Test status
Simulation time 68310100 ps
CPU time 30.98 seconds
Started Jun 06 01:36:08 PM PDT 24
Finished Jun 06 01:36:39 PM PDT 24
Peak memory 275344 kb
Host smart-2b4e107e-387b-4e66-ad57-b2c84bc78a37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022857257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.2022857257
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.634022695
Short name T1061
Test name
Test status
Simulation time 74390200 ps
CPU time 31.35 seconds
Started Jun 06 01:36:06 PM PDT 24
Finished Jun 06 01:36:38 PM PDT 24
Peak memory 275588 kb
Host smart-1db3b81a-5305-4566-9b9e-9341b12d1a35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634022695 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.634022695
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.142058907
Short name T821
Test name
Test status
Simulation time 2453769200 ps
CPU time 84.35 seconds
Started Jun 06 01:36:09 PM PDT 24
Finished Jun 06 01:37:34 PM PDT 24
Peak memory 259320 kb
Host smart-bc27fb00-fde6-4e21-9bab-4ccc2f2e8948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142058907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.142058907
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.1190031090
Short name T813
Test name
Test status
Simulation time 26558400 ps
CPU time 50.55 seconds
Started Jun 06 01:36:09 PM PDT 24
Finished Jun 06 01:37:00 PM PDT 24
Peak memory 269524 kb
Host smart-21a72de1-31f3-46ad-9608-7cab2a194867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190031090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.1190031090
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.2197296048
Short name T593
Test name
Test status
Simulation time 20361700 ps
CPU time 13.54 seconds
Started Jun 06 01:36:14 PM PDT 24
Finished Jun 06 01:36:28 PM PDT 24
Peak memory 257964 kb
Host smart-cea179e7-81df-43ab-8705-28e089079d8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197296048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
2197296048
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.310432681
Short name T1010
Test name
Test status
Simulation time 26415700 ps
CPU time 15.86 seconds
Started Jun 06 01:36:09 PM PDT 24
Finished Jun 06 01:36:25 PM PDT 24
Peak memory 274740 kb
Host smart-1bc1bca8-482e-4320-a2c2-f4ad09bcbc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310432681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.310432681
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.331525731
Short name T155
Test name
Test status
Simulation time 19983600 ps
CPU time 22.51 seconds
Started Jun 06 01:36:06 PM PDT 24
Finished Jun 06 01:36:29 PM PDT 24
Peak memory 265200 kb
Host smart-08c5ffab-4511-4fef-9b29-35b8957b858c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331525731 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.331525731
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.4042217003
Short name T985
Test name
Test status
Simulation time 12977991700 ps
CPU time 262.94 seconds
Started Jun 06 01:36:10 PM PDT 24
Finished Jun 06 01:40:33 PM PDT 24
Peak memory 262432 kb
Host smart-48aba7bd-4328-40d3-b612-bf6083cecd43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042217003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.4042217003
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.3786523458
Short name T333
Test name
Test status
Simulation time 3744604700 ps
CPU time 183.87 seconds
Started Jun 06 01:36:07 PM PDT 24
Finished Jun 06 01:39:12 PM PDT 24
Peak memory 293512 kb
Host smart-b849da42-887d-41aa-a0a6-7e31a820344c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786523458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.3786523458
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.1855041547
Short name T659
Test name
Test status
Simulation time 30491204000 ps
CPU time 164.43 seconds
Started Jun 06 01:36:07 PM PDT 24
Finished Jun 06 01:38:52 PM PDT 24
Peak memory 293544 kb
Host smart-3619ad12-4e65-4d28-9108-7cd6661506cd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855041547 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.1855041547
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.378410561
Short name T1024
Test name
Test status
Simulation time 47934000 ps
CPU time 134.03 seconds
Started Jun 06 01:36:10 PM PDT 24
Finished Jun 06 01:38:25 PM PDT 24
Peak memory 260792 kb
Host smart-5fb27e33-0de6-4177-a312-982c18c7ea7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378410561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ot
p_reset.378410561
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.319207755
Short name T796
Test name
Test status
Simulation time 44137900 ps
CPU time 32.55 seconds
Started Jun 06 01:36:08 PM PDT 24
Finished Jun 06 01:36:42 PM PDT 24
Peak memory 275576 kb
Host smart-fe281f54-58fb-4743-adc5-d14a7cfd9ca6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319207755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_rw_evict.319207755
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.2786994445
Short name T644
Test name
Test status
Simulation time 49845800 ps
CPU time 29.81 seconds
Started Jun 06 01:36:07 PM PDT 24
Finished Jun 06 01:36:38 PM PDT 24
Peak memory 275552 kb
Host smart-5847eed2-2d94-438f-bae9-1ab78ed82e1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786994445 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.2786994445
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.103794705
Short name T37
Test name
Test status
Simulation time 7875276100 ps
CPU time 69.61 seconds
Started Jun 06 01:36:09 PM PDT 24
Finished Jun 06 01:37:19 PM PDT 24
Peak memory 261820 kb
Host smart-bb7bfad6-5fc0-4513-afc2-4e4c97743f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103794705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.103794705
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.1652193639
Short name T1066
Test name
Test status
Simulation time 102907900 ps
CPU time 149.95 seconds
Started Jun 06 01:36:07 PM PDT 24
Finished Jun 06 01:38:38 PM PDT 24
Peak memory 276832 kb
Host smart-74728b4e-2b3d-43f0-9e5f-26b4f394beae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652193639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.1652193639
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.2013584362
Short name T1056
Test name
Test status
Simulation time 44152500 ps
CPU time 13.89 seconds
Started Jun 06 01:36:18 PM PDT 24
Finished Jun 06 01:36:33 PM PDT 24
Peak memory 257964 kb
Host smart-2819ec3c-5dba-4168-add0-1e0acc993f6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013584362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
2013584362
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.576472174
Short name T864
Test name
Test status
Simulation time 27107500 ps
CPU time 16.09 seconds
Started Jun 06 01:36:14 PM PDT 24
Finished Jun 06 01:36:31 PM PDT 24
Peak memory 274648 kb
Host smart-64c8e9b3-65f4-417a-9992-66650eb5e0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576472174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.576472174
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.2242917327
Short name T590
Test name
Test status
Simulation time 34336100 ps
CPU time 20.6 seconds
Started Jun 06 01:36:14 PM PDT 24
Finished Jun 06 01:36:36 PM PDT 24
Peak memory 273548 kb
Host smart-63de62f0-f635-4af9-842d-d041b6adf8e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242917327 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.2242917327
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.2174008544
Short name T734
Test name
Test status
Simulation time 3473418800 ps
CPU time 135.09 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:38:31 PM PDT 24
Peak memory 262860 kb
Host smart-eb358514-2059-4845-a62b-7561e49bc5ae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174008544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.2174008544
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3360990903
Short name T175
Test name
Test status
Simulation time 12640004700 ps
CPU time 297.86 seconds
Started Jun 06 01:36:13 PM PDT 24
Finished Jun 06 01:41:12 PM PDT 24
Peak memory 289780 kb
Host smart-88bbd77c-8a52-4154-abe5-9e38eb8d5698
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360990903 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.3360990903
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.2737060165
Short name T740
Test name
Test status
Simulation time 39436100 ps
CPU time 133.21 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:38:29 PM PDT 24
Peak memory 259796 kb
Host smart-ab1ab92d-c81f-45e8-bfbe-e30dbff7c09d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737060165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o
tp_reset.2737060165
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.2025890225
Short name T459
Test name
Test status
Simulation time 45245800 ps
CPU time 31.74 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:36:48 PM PDT 24
Peak memory 275160 kb
Host smart-0bfc268e-dce2-490c-a4bb-717bd39de2cf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025890225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.2025890225
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.678185087
Short name T536
Test name
Test status
Simulation time 32820600 ps
CPU time 30.85 seconds
Started Jun 06 01:36:16 PM PDT 24
Finished Jun 06 01:36:48 PM PDT 24
Peak memory 273576 kb
Host smart-06f7c2c5-6b1d-4a56-8890-3442414e1678
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678185087 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.678185087
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.4276510182
Short name T371
Test name
Test status
Simulation time 1307942800 ps
CPU time 62.37 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:37:19 PM PDT 24
Peak memory 264688 kb
Host smart-3971277f-15f3-417b-b6cb-f75eb9a8e4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276510182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.4276510182
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.1854708777
Short name T533
Test name
Test status
Simulation time 19820100 ps
CPU time 102.14 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:37:58 PM PDT 24
Peak memory 276728 kb
Host smart-eb7fbe34-926c-4fcd-b981-8cf139eb7883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854708777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1854708777
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.3981982672
Short name T927
Test name
Test status
Simulation time 78619800 ps
CPU time 13.68 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:32:38 PM PDT 24
Peak memory 264760 kb
Host smart-44403132-b538-4ec8-a573-f03420c49021
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981982672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.3
981982672
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.3644183967
Short name T359
Test name
Test status
Simulation time 20304100 ps
CPU time 14.29 seconds
Started Jun 06 01:32:21 PM PDT 24
Finished Jun 06 01:32:37 PM PDT 24
Peak memory 261524 kb
Host smart-deb47a52-e2e1-4751-b3ff-fcd15b4fee3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644183967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.3644183967
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.3132382687
Short name T546
Test name
Test status
Simulation time 27562400 ps
CPU time 15.83 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:32:37 PM PDT 24
Peak memory 274700 kb
Host smart-9423cb84-a2ab-4ca7-98e7-e689f5b664ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132382687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.3132382687
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.211758175
Short name T911
Test name
Test status
Simulation time 317826000 ps
CPU time 104.72 seconds
Started Jun 06 01:32:21 PM PDT 24
Finished Jun 06 01:34:07 PM PDT 24
Peak memory 280688 kb
Host smart-0473dfb3-a77c-44a0-9b18-488d285c2012
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211758175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.flash_ctrl_derr_detect.211758175
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.2036018192
Short name T1078
Test name
Test status
Simulation time 1250424800 ps
CPU time 238.96 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:36:20 PM PDT 24
Peak memory 263192 kb
Host smart-12572b97-a75c-4ee7-b95e-4b039a9f3142
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2036018192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2036018192
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.3971283551
Short name T585
Test name
Test status
Simulation time 17377294500 ps
CPU time 2430.19 seconds
Started Jun 06 01:32:24 PM PDT 24
Finished Jun 06 02:12:56 PM PDT 24
Peak memory 265016 kb
Host smart-aadc2beb-0fa2-4ba8-a2e5-50ffb451ab2b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971283551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.3971283551
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.966735976
Short name T493
Test name
Test status
Simulation time 644412600 ps
CPU time 902.03 seconds
Started Jun 06 01:32:21 PM PDT 24
Finished Jun 06 01:47:25 PM PDT 24
Peak memory 273140 kb
Host smart-3cd207b0-a705-44cc-9c56-6a793d197885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966735976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.966735976
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.1821222311
Short name T53
Test name
Test status
Simulation time 1243061400 ps
CPU time 27.76 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:32:52 PM PDT 24
Peak memory 262316 kb
Host smart-375ee5c7-f5c1-452b-83f5-30bdc13310f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821222311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.1821222311
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.1857957343
Short name T969
Test name
Test status
Simulation time 720328700 ps
CPU time 35.4 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:32:56 PM PDT 24
Peak memory 262700 kb
Host smart-222043f2-88f0-4204-9c46-e9d142bc6d6d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857957343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.1857957343
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.1572443337
Short name T110
Test name
Test status
Simulation time 717156348000 ps
CPU time 2993.27 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 02:22:22 PM PDT 24
Peak memory 265136 kb
Host smart-376020e5-6c30-417c-aa6c-9750f49ee294
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572443337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.1572443337
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.2566005318
Short name T494
Test name
Test status
Simulation time 66441400 ps
CPU time 24.15 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 01:32:48 PM PDT 24
Peak memory 265084 kb
Host smart-aa116eac-e0bf-49cb-88ea-e70cf1ded5a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2566005318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.2566005318
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.3254983793
Short name T747
Test name
Test status
Simulation time 10019325700 ps
CPU time 185.33 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:35:34 PM PDT 24
Peak memory 299052 kb
Host smart-e6939c3d-2ba5-4e76-a57b-903df9d5d187
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254983793 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.3254983793
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.971587779
Short name T668
Test name
Test status
Simulation time 178128700 ps
CPU time 13.51 seconds
Started Jun 06 01:32:19 PM PDT 24
Finished Jun 06 01:32:33 PM PDT 24
Peak memory 264596 kb
Host smart-b245555a-97c1-4489-a234-abcebc45e229
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971587779 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.971587779
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.3561197536
Short name T815
Test name
Test status
Simulation time 160192411700 ps
CPU time 880.67 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 01:47:04 PM PDT 24
Peak memory 260624 kb
Host smart-18791902-d06b-4dd9-89f4-4f0806d08f54
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561197536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.3561197536
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.1706125777
Short name T424
Test name
Test status
Simulation time 2765268300 ps
CPU time 59.43 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:33:29 PM PDT 24
Peak memory 262944 kb
Host smart-59aac0d4-7449-407a-bbd8-ece48bad1273
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706125777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.1706125777
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.3052927567
Short name T879
Test name
Test status
Simulation time 2990713100 ps
CPU time 141.33 seconds
Started Jun 06 01:32:30 PM PDT 24
Finished Jun 06 01:34:52 PM PDT 24
Peak memory 294032 kb
Host smart-68946bd5-a6e4-4757-b87d-5aec4c3a18fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052927567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.3052927567
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.3616911242
Short name T903
Test name
Test status
Simulation time 28285087900 ps
CPU time 288.57 seconds
Started Jun 06 01:32:28 PM PDT 24
Finished Jun 06 01:37:18 PM PDT 24
Peak memory 284384 kb
Host smart-4656450f-a9dd-4ace-9904-2440128059fe
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616911242 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.3616911242
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.2987708838
Short name T822
Test name
Test status
Simulation time 7471257300 ps
CPU time 70.04 seconds
Started Jun 06 01:32:30 PM PDT 24
Finished Jun 06 01:33:41 PM PDT 24
Peak memory 259748 kb
Host smart-28ad18e3-277e-4397-a19c-1ba170749963
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987708838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.2987708838
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1575785728
Short name T1035
Test name
Test status
Simulation time 22735705000 ps
CPU time 190.64 seconds
Started Jun 06 01:32:28 PM PDT 24
Finished Jun 06 01:35:40 PM PDT 24
Peak memory 260036 kb
Host smart-8cc64802-884c-4ef5-b95b-5bec0216b874
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157
5785728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.1575785728
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.1117430876
Short name T102
Test name
Test status
Simulation time 3946137300 ps
CPU time 60.72 seconds
Started Jun 06 01:32:24 PM PDT 24
Finished Jun 06 01:33:26 PM PDT 24
Peak memory 263276 kb
Host smart-d3458ac9-f21f-4b9c-8f85-0f1f4ad7e923
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117430876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.1117430876
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.2048820503
Short name T96
Test name
Test status
Simulation time 49566200 ps
CPU time 13.52 seconds
Started Jun 06 01:32:19 PM PDT 24
Finished Jun 06 01:32:34 PM PDT 24
Peak memory 259616 kb
Host smart-bfed5dc0-d296-476c-ad2f-626899cd64b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048820503 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.2048820503
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.2418479555
Short name T124
Test name
Test status
Simulation time 12786426400 ps
CPU time 81.05 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:33:46 PM PDT 24
Peak memory 260184 kb
Host smart-cb2b0a51-c9af-49e8-91d5-3fc09fbc5722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418479555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.2418479555
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.4145524483
Short name T112
Test name
Test status
Simulation time 12044400800 ps
CPU time 317.94 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 01:37:42 PM PDT 24
Peak memory 274368 kb
Host smart-b446fcf2-f9e6-48c1-90fb-149af85ba7ea
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145524483 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_mp_regions.4145524483
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.2407991332
Short name T987
Test name
Test status
Simulation time 79995000 ps
CPU time 134.5 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 01:34:38 PM PDT 24
Peak memory 260676 kb
Host smart-cd791c4c-3858-4cb7-bd5b-2f6d6a343681
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407991332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.2407991332
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.2989916020
Short name T882
Test name
Test status
Simulation time 7465966800 ps
CPU time 236.69 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:36:18 PM PDT 24
Peak memory 289944 kb
Host smart-31b18ff5-82b0-439b-8c5a-5d37b958c427
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989916020 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.2989916020
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.1525189429
Short name T45
Test name
Test status
Simulation time 28888600 ps
CPU time 14.19 seconds
Started Jun 06 01:32:20 PM PDT 24
Finished Jun 06 01:32:35 PM PDT 24
Peak memory 279196 kb
Host smart-f5600570-263e-4560-85a7-fcde4d0a5c77
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1525189429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.1525189429
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.3835693674
Short name T884
Test name
Test status
Simulation time 767175300 ps
CPU time 423.12 seconds
Started Jun 06 01:32:28 PM PDT 24
Finished Jun 06 01:39:32 PM PDT 24
Peak memory 262936 kb
Host smart-e27f0c14-cf78-472e-a0df-6bcafaf91742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3835693674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.3835693674
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.673860780
Short name T1069
Test name
Test status
Simulation time 15715000 ps
CPU time 14.03 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:32:39 PM PDT 24
Peak memory 262308 kb
Host smart-43d28a22-6868-4a4c-90a4-a2b5f41c9fc1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673860780 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.673860780
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.2215311687
Short name T381
Test name
Test status
Simulation time 26661200 ps
CPU time 13.58 seconds
Started Jun 06 01:32:28 PM PDT 24
Finished Jun 06 01:32:43 PM PDT 24
Peak memory 265240 kb
Host smart-56bfee9b-f214-461d-bce8-e461bef54d95
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215311687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_res
et.2215311687
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.598188788
Short name T689
Test name
Test status
Simulation time 2090182700 ps
CPU time 214.54 seconds
Started Jun 06 01:32:19 PM PDT 24
Finished Jun 06 01:35:55 PM PDT 24
Peak memory 280840 kb
Host smart-f132e923-a1f9-47c5-9955-85d3fc6ba302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598188788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.598188788
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.3496678249
Short name T275
Test name
Test status
Simulation time 144613500 ps
CPU time 99.26 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:34:05 PM PDT 24
Peak memory 262448 kb
Host smart-076b6363-aa8d-4b28-bac2-5e994916e326
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3496678249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.3496678249
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.1833057184
Short name T51
Test name
Test status
Simulation time 88678400 ps
CPU time 36.3 seconds
Started Jun 06 01:32:18 PM PDT 24
Finished Jun 06 01:32:55 PM PDT 24
Peak memory 275576 kb
Host smart-ca08fe39-2b2e-4e73-9613-f7b04355b560
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833057184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.1833057184
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.3181165486
Short name T725
Test name
Test status
Simulation time 2273438000 ps
CPU time 129.18 seconds
Started Jun 06 01:32:24 PM PDT 24
Finished Jun 06 01:34:35 PM PDT 24
Peak memory 289964 kb
Host smart-3021ce41-ebcd-4fd4-b4f5-cef35b3d112a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181165486 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_ro.3181165486
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.3909069702
Short name T180
Test name
Test status
Simulation time 3819884700 ps
CPU time 136.29 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:34:41 PM PDT 24
Peak memory 281812 kb
Host smart-78b19d6d-d9b1-46e0-828a-906e665000c1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3909069702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.3909069702
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.2982579312
Short name T577
Test name
Test status
Simulation time 4013171500 ps
CPU time 167.03 seconds
Started Jun 06 01:32:26 PM PDT 24
Finished Jun 06 01:35:15 PM PDT 24
Peak memory 294844 kb
Host smart-84f3db95-5961-4582-88be-d87e53fc77ec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982579312 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.2982579312
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.1891518690
Short name T929
Test name
Test status
Simulation time 8168858600 ps
CPU time 677.91 seconds
Started Jun 06 01:32:26 PM PDT 24
Finished Jun 06 01:43:45 PM PDT 24
Peak memory 313816 kb
Host smart-edd3d554-d411-4e30-977c-58c13018e1c8
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891518690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_rw.1891518690
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_derr.1010833846
Short name T814
Test name
Test status
Simulation time 8733260200 ps
CPU time 590.77 seconds
Started Jun 06 01:32:29 PM PDT 24
Finished Jun 06 01:42:21 PM PDT 24
Peak memory 312248 kb
Host smart-40e19633-e147-491c-924d-85f9ab2e029a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010833846 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_rw_derr.1010833846
Directory /workspace/4.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.254989762
Short name T271
Test name
Test status
Simulation time 74301600 ps
CPU time 29.37 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:32:54 PM PDT 24
Peak memory 275608 kb
Host smart-e182815d-ab10-4a76-bea7-ccd88e353c07
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254989762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_rw_evict.254989762
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.3680059911
Short name T775
Test name
Test status
Simulation time 32221900 ps
CPU time 30.54 seconds
Started Jun 06 01:32:24 PM PDT 24
Finished Jun 06 01:32:56 PM PDT 24
Peak memory 267384 kb
Host smart-386b8828-a6e0-4e2e-b82b-ea13ec5b3e16
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680059911 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.3680059911
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.726515009
Short name T492
Test name
Test status
Simulation time 16208395600 ps
CPU time 481.4 seconds
Started Jun 06 01:32:24 PM PDT 24
Finished Jun 06 01:40:27 PM PDT 24
Peak memory 312748 kb
Host smart-f0ffb516-af78-4263-bd6d-f6c0822410e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726515009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_se
rr.726515009
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.1287411409
Short name T672
Test name
Test status
Simulation time 1885601600 ps
CPU time 55.89 seconds
Started Jun 06 01:32:24 PM PDT 24
Finished Jun 06 01:33:22 PM PDT 24
Peak memory 265356 kb
Host smart-3d157a72-00d1-4c09-aa87-183b8cdd805c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287411409 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.1287411409
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.69380272
Short name T390
Test name
Test status
Simulation time 12071697200 ps
CPU time 111.58 seconds
Started Jun 06 01:32:26 PM PDT 24
Finished Jun 06 01:34:19 PM PDT 24
Peak memory 265320 kb
Host smart-2ac08617-38e4-4711-a058-3cbcb4cb3ed4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69380272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_serr_counter.69380272
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.4034732170
Short name T1015
Test name
Test status
Simulation time 4217552800 ps
CPU time 109.83 seconds
Started Jun 06 01:32:24 PM PDT 24
Finished Jun 06 01:34:16 PM PDT 24
Peak memory 281032 kb
Host smart-58fa4335-e25f-4148-85b7-4659f3fe0626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034732170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.4034732170
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.3825565435
Short name T500
Test name
Test status
Simulation time 17694500 ps
CPU time 26.04 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:32:51 PM PDT 24
Peak memory 259352 kb
Host smart-dc3bde14-0575-4ff6-92bc-5adbf9f01d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825565435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.3825565435
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.1668774454
Short name T812
Test name
Test status
Simulation time 3536208700 ps
CPU time 1491.28 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 01:57:15 PM PDT 24
Peak memory 296800 kb
Host smart-9cc3cbbd-205d-4c38-917a-23aea8988aff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668774454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.1668774454
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.4027598067
Short name T571
Test name
Test status
Simulation time 85539600 ps
CPU time 23.84 seconds
Started Jun 06 01:32:21 PM PDT 24
Finished Jun 06 01:32:46 PM PDT 24
Peak memory 261928 kb
Host smart-0ccb4780-40e4-4228-8aac-fd9f74f2392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027598067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.4027598067
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.792338650
Short name T100
Test name
Test status
Simulation time 1827561100 ps
CPU time 159.12 seconds
Started Jun 06 01:32:26 PM PDT 24
Finished Jun 06 01:35:06 PM PDT 24
Peak memory 259116 kb
Host smart-4d1e6e67-d366-423f-b59c-2c3f027976a7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792338650 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.flash_ctrl_wo.792338650
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.2126743680
Short name T423
Test name
Test status
Simulation time 44637300 ps
CPU time 13.96 seconds
Started Jun 06 01:36:14 PM PDT 24
Finished Jun 06 01:36:29 PM PDT 24
Peak memory 264752 kb
Host smart-07c0f06b-0e3c-4205-a6da-9af061f241cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126743680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.
2126743680
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.870788078
Short name T841
Test name
Test status
Simulation time 94979900 ps
CPU time 15.82 seconds
Started Jun 06 01:36:17 PM PDT 24
Finished Jun 06 01:36:34 PM PDT 24
Peak memory 284020 kb
Host smart-980ffd21-e967-4a12-8adf-8b7ac87ab5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870788078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.870788078
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.3299181177
Short name T70
Test name
Test status
Simulation time 29880300 ps
CPU time 20.82 seconds
Started Jun 06 01:36:14 PM PDT 24
Finished Jun 06 01:36:36 PM PDT 24
Peak memory 265400 kb
Host smart-3f1c0375-4854-4062-8314-301703f8f5b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299181177 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.3299181177
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.3995425347
Short name T780
Test name
Test status
Simulation time 1560334700 ps
CPU time 64.95 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:37:21 PM PDT 24
Peak memory 262520 kb
Host smart-e2249299-3d82-4123-9b0a-f5bd4b206f7a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995425347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.3995425347
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.3680837379
Short name T142
Test name
Test status
Simulation time 82982200 ps
CPU time 132.18 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:38:28 PM PDT 24
Peak memory 259996 kb
Host smart-beca24c5-6455-48ea-8093-f405256199b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680837379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.3680837379
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.2340493859
Short name T752
Test name
Test status
Simulation time 1691364400 ps
CPU time 65.82 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:37:22 PM PDT 24
Peak memory 259344 kb
Host smart-0373b13a-8dfc-44f5-86fd-361f9e6e4f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340493859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2340493859
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.3246393235
Short name T915
Test name
Test status
Simulation time 38074100 ps
CPU time 124.61 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:38:20 PM PDT 24
Peak memory 276304 kb
Host smart-a73037d5-0374-47a4-992a-34811436e6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246393235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.3246393235
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.1440334539
Short name T763
Test name
Test status
Simulation time 70687300 ps
CPU time 14.6 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:36:31 PM PDT 24
Peak memory 257940 kb
Host smart-dbe384b2-1d8d-4b21-b8f5-a250c5335926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440334539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
1440334539
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.2265265636
Short name T807
Test name
Test status
Simulation time 32450800 ps
CPU time 15.99 seconds
Started Jun 06 01:36:14 PM PDT 24
Finished Jun 06 01:36:30 PM PDT 24
Peak memory 274580 kb
Host smart-99dc9a4c-b541-4fa9-8af7-8c2fa30b531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265265636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2265265636
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.2023751951
Short name T1041
Test name
Test status
Simulation time 89053900 ps
CPU time 21.6 seconds
Started Jun 06 01:36:17 PM PDT 24
Finished Jun 06 01:36:39 PM PDT 24
Peak memory 273500 kb
Host smart-d52fc134-a337-4a9c-bc7c-56db5acfbdc4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023751951 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.2023751951
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3492623513
Short name T758
Test name
Test status
Simulation time 1762967000 ps
CPU time 62.28 seconds
Started Jun 06 01:36:13 PM PDT 24
Finished Jun 06 01:37:16 PM PDT 24
Peak memory 262904 kb
Host smart-9837a570-68d6-4c7e-a897-977e82feb71e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492623513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.3492623513
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.140113697
Short name T967
Test name
Test status
Simulation time 138644500 ps
CPU time 111.67 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:38:08 PM PDT 24
Peak memory 260044 kb
Host smart-adbc732e-4f01-4470-a508-ad303a79cd2f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140113697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ot
p_reset.140113697
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.1934748472
Short name T592
Test name
Test status
Simulation time 2130290100 ps
CPU time 60.12 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:37:16 PM PDT 24
Peak memory 263660 kb
Host smart-62c226ea-8864-4822-9efc-ed2be5fd9cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934748472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.1934748472
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.2347912303
Short name T611
Test name
Test status
Simulation time 28813800 ps
CPU time 125.95 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:38:22 PM PDT 24
Peak memory 275968 kb
Host smart-59efb45a-b7a4-4057-9866-c50a5e18ca07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347912303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2347912303
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.2028835524
Short name T512
Test name
Test status
Simulation time 61519100 ps
CPU time 13.77 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:36:30 PM PDT 24
Peak memory 258004 kb
Host smart-acfa2516-0473-423c-95fc-0e700aa11071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028835524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
2028835524
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.4103789635
Short name T165
Test name
Test status
Simulation time 22470400 ps
CPU time 13.42 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:36:30 PM PDT 24
Peak memory 284064 kb
Host smart-50cc8640-2baa-4aec-a002-d10fce4fbd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103789635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.4103789635
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.3649047685
Short name T570
Test name
Test status
Simulation time 11663200 ps
CPU time 22.06 seconds
Started Jun 06 01:36:16 PM PDT 24
Finished Jun 06 01:36:39 PM PDT 24
Peak memory 265312 kb
Host smart-a7b10c39-168e-4102-8cb0-d95f84dc76bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649047685 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.3649047685
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.3491579736
Short name T1036
Test name
Test status
Simulation time 1552450500 ps
CPU time 66.56 seconds
Started Jun 06 01:36:18 PM PDT 24
Finished Jun 06 01:37:25 PM PDT 24
Peak memory 262860 kb
Host smart-a49a12d5-1d92-44f5-9dd4-1bcb71cfa561
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491579736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.3491579736
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.4103737187
Short name T580
Test name
Test status
Simulation time 40838000 ps
CPU time 135.41 seconds
Started Jun 06 01:36:14 PM PDT 24
Finished Jun 06 01:38:30 PM PDT 24
Peak memory 260852 kb
Host smart-e8dce33d-0a8c-4a02-b952-645ac7042d3e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103737187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.4103737187
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.4160242149
Short name T831
Test name
Test status
Simulation time 8065016600 ps
CPU time 62.22 seconds
Started Jun 06 01:36:15 PM PDT 24
Finished Jun 06 01:37:18 PM PDT 24
Peak memory 263896 kb
Host smart-30ba9537-3c4b-4bb0-81c9-aeee565fe62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160242149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.4160242149
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.3503895759
Short name T953
Test name
Test status
Simulation time 95335200 ps
CPU time 226.59 seconds
Started Jun 06 01:36:14 PM PDT 24
Finished Jun 06 01:40:01 PM PDT 24
Peak memory 277760 kb
Host smart-934ee7aa-f320-49bb-bb67-b27dff2053cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503895759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.3503895759
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.2565603264
Short name T584
Test name
Test status
Simulation time 135447700 ps
CPU time 14.11 seconds
Started Jun 06 01:36:46 PM PDT 24
Finished Jun 06 01:37:01 PM PDT 24
Peak memory 257992 kb
Host smart-f83b5ae2-01e8-4882-8f77-cd525b47de48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565603264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
2565603264
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.3331742675
Short name T532
Test name
Test status
Simulation time 15156700 ps
CPU time 15.86 seconds
Started Jun 06 01:36:48 PM PDT 24
Finished Jun 06 01:37:04 PM PDT 24
Peak memory 274676 kb
Host smart-64d6b2aa-d595-42fc-8e2b-527357b19c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331742675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3331742675
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.2063408978
Short name T368
Test name
Test status
Simulation time 17171000 ps
CPU time 21.2 seconds
Started Jun 06 01:36:46 PM PDT 24
Finished Jun 06 01:37:08 PM PDT 24
Peak memory 265228 kb
Host smart-bf349f6b-3317-478c-a074-5dca4ed966b5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063408978 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.2063408978
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.1449860299
Short name T994
Test name
Test status
Simulation time 4952554400 ps
CPU time 54.53 seconds
Started Jun 06 01:36:47 PM PDT 24
Finished Jun 06 01:37:43 PM PDT 24
Peak memory 260620 kb
Host smart-52243b79-4b83-480d-af23-6b0e4e17c032
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449860299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.1449860299
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.4259883525
Short name T74
Test name
Test status
Simulation time 138023500 ps
CPU time 135.29 seconds
Started Jun 06 01:36:51 PM PDT 24
Finished Jun 06 01:39:07 PM PDT 24
Peak memory 260680 kb
Host smart-b9047bdb-6530-4ccc-a04a-2939ee188540
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259883525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.4259883525
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.1682811865
Short name T757
Test name
Test status
Simulation time 7528793700 ps
CPU time 80.92 seconds
Started Jun 06 01:36:46 PM PDT 24
Finished Jun 06 01:38:09 PM PDT 24
Peak memory 259364 kb
Host smart-c5acb3c7-02e5-4ce2-9a9e-efefa16e7741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682811865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.1682811865
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.1635057703
Short name T567
Test name
Test status
Simulation time 19308300 ps
CPU time 123.52 seconds
Started Jun 06 01:36:48 PM PDT 24
Finished Jun 06 01:38:52 PM PDT 24
Peak memory 277124 kb
Host smart-ab9cb85d-a0ca-43c0-94a2-39d5d08bba0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635057703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.1635057703
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.38811017
Short name T870
Test name
Test status
Simulation time 89899100 ps
CPU time 13.81 seconds
Started Jun 06 01:36:49 PM PDT 24
Finished Jun 06 01:37:03 PM PDT 24
Peak memory 258048 kb
Host smart-eb4fd649-e1a8-496b-8aa0-784e6da5d9a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38811017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.38811017
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.3939798956
Short name T894
Test name
Test status
Simulation time 43712800 ps
CPU time 16.33 seconds
Started Jun 06 01:36:45 PM PDT 24
Finished Jun 06 01:37:02 PM PDT 24
Peak memory 274692 kb
Host smart-b88e04d3-1acc-4140-adab-168ed5baecb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939798956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.3939798956
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.3861808429
Short name T921
Test name
Test status
Simulation time 10524800 ps
CPU time 22.07 seconds
Started Jun 06 01:36:46 PM PDT 24
Finished Jun 06 01:37:09 PM PDT 24
Peak memory 273448 kb
Host smart-a5f304bc-021a-4bb4-9780-2f4b0a633e8d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861808429 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.3861808429
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.2312037705
Short name T711
Test name
Test status
Simulation time 8251986800 ps
CPU time 152.26 seconds
Started Jun 06 01:36:48 PM PDT 24
Finished Jun 06 01:39:21 PM PDT 24
Peak memory 261784 kb
Host smart-44da41db-2ab5-4070-845f-107cf7fc5e82
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312037705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.2312037705
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.2449717563
Short name T147
Test name
Test status
Simulation time 119118000 ps
CPU time 110.95 seconds
Started Jun 06 01:36:46 PM PDT 24
Finished Jun 06 01:38:38 PM PDT 24
Peak memory 264928 kb
Host smart-9fb941c2-adbe-46a2-a3f8-22c0a467c863
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449717563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.2449717563
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.3352134615
Short name T1028
Test name
Test status
Simulation time 2614307700 ps
CPU time 74.03 seconds
Started Jun 06 01:36:46 PM PDT 24
Finished Jun 06 01:38:00 PM PDT 24
Peak memory 263344 kb
Host smart-6b5dffb5-50ee-4adf-b946-9e76142920e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352134615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.3352134615
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.1870757221
Short name T970
Test name
Test status
Simulation time 17963200 ps
CPU time 98.02 seconds
Started Jun 06 01:36:46 PM PDT 24
Finished Jun 06 01:38:25 PM PDT 24
Peak memory 276624 kb
Host smart-4b812e66-704a-4940-8abb-7e11d5a71719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870757221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.1870757221
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.2123285973
Short name T486
Test name
Test status
Simulation time 227058600 ps
CPU time 13.68 seconds
Started Jun 06 01:36:47 PM PDT 24
Finished Jun 06 01:37:01 PM PDT 24
Peak memory 257940 kb
Host smart-9f44a4df-a5e1-4ba1-8fec-81326de659dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123285973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
2123285973
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.1900294781
Short name T1006
Test name
Test status
Simulation time 13510400 ps
CPU time 16.11 seconds
Started Jun 06 01:36:46 PM PDT 24
Finished Jun 06 01:37:03 PM PDT 24
Peak memory 274704 kb
Host smart-6e45984e-036e-4748-a358-46bb01b10b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900294781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.1900294781
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.427068058
Short name T366
Test name
Test status
Simulation time 10105200 ps
CPU time 21.14 seconds
Started Jun 06 01:36:44 PM PDT 24
Finished Jun 06 01:37:06 PM PDT 24
Peak memory 265164 kb
Host smart-0befdd97-b3b5-4b75-a2d1-8fff4cb02c40
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427068058 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.427068058
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.2408214623
Short name T748
Test name
Test status
Simulation time 2556691600 ps
CPU time 86.22 seconds
Started Jun 06 01:36:49 PM PDT 24
Finished Jun 06 01:38:16 PM PDT 24
Peak memory 260648 kb
Host smart-bb21662b-6477-4eb2-a5f3-21962e2b6476
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408214623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.2408214623
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.2889550717
Short name T153
Test name
Test status
Simulation time 77777700 ps
CPU time 111.76 seconds
Started Jun 06 01:36:46 PM PDT 24
Finished Jun 06 01:38:39 PM PDT 24
Peak memory 264536 kb
Host smart-56cd89ad-937d-471f-a1ab-92a68fc02bf0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889550717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.2889550717
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.4276703591
Short name T401
Test name
Test status
Simulation time 2145348600 ps
CPU time 73.31 seconds
Started Jun 06 01:36:45 PM PDT 24
Finished Jun 06 01:37:59 PM PDT 24
Peak memory 259584 kb
Host smart-3e1b251e-6c9f-498a-80eb-ffbe6011767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276703591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.4276703591
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.3540233335
Short name T501
Test name
Test status
Simulation time 23391600 ps
CPU time 124.34 seconds
Started Jun 06 01:36:47 PM PDT 24
Finished Jun 06 01:38:52 PM PDT 24
Peak memory 277568 kb
Host smart-154039f8-6fba-40b6-b56f-6d6ea9fb8532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540233335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.3540233335
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.1914715106
Short name T555
Test name
Test status
Simulation time 45321600 ps
CPU time 13.87 seconds
Started Jun 06 01:36:53 PM PDT 24
Finished Jun 06 01:37:08 PM PDT 24
Peak memory 257936 kb
Host smart-7483aa37-faaf-44d8-b49d-1a6bb9eccac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914715106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
1914715106
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.2226972866
Short name T700
Test name
Test status
Simulation time 22926000 ps
CPU time 15.9 seconds
Started Jun 06 01:36:56 PM PDT 24
Finished Jun 06 01:37:13 PM PDT 24
Peak memory 284148 kb
Host smart-a91e0a69-0bb5-4fa8-91f5-978a762d58f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226972866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.2226972866
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.1020023426
Short name T363
Test name
Test status
Simulation time 27146800 ps
CPU time 21.32 seconds
Started Jun 06 01:36:53 PM PDT 24
Finished Jun 06 01:37:16 PM PDT 24
Peak memory 273548 kb
Host smart-86a67098-a0fc-448c-b900-0dbe119313c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020023426 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.1020023426
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.4013255413
Short name T774
Test name
Test status
Simulation time 16196167300 ps
CPU time 157.89 seconds
Started Jun 06 01:36:54 PM PDT 24
Finished Jun 06 01:39:33 PM PDT 24
Peak memory 262900 kb
Host smart-e3305f21-78b3-458e-bd66-258064b3d3c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013255413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_
hw_sec_otp.4013255413
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.3936188463
Short name T726
Test name
Test status
Simulation time 76230100 ps
CPU time 135.56 seconds
Started Jun 06 01:36:52 PM PDT 24
Finished Jun 06 01:39:08 PM PDT 24
Peak memory 260760 kb
Host smart-f9318006-f3a6-4b20-9779-f3fca52bfe35
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936188463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.3936188463
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.3785658569
Short name T402
Test name
Test status
Simulation time 3771751600 ps
CPU time 73.78 seconds
Started Jun 06 01:36:50 PM PDT 24
Finished Jun 06 01:38:04 PM PDT 24
Peak memory 263316 kb
Host smart-54d5cc4c-723f-4051-9164-bdd50849ef42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785658569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.3785658569
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.3684907625
Short name T195
Test name
Test status
Simulation time 35337700 ps
CPU time 99.3 seconds
Started Jun 06 01:36:53 PM PDT 24
Finished Jun 06 01:38:33 PM PDT 24
Peak memory 276836 kb
Host smart-1ba84e3f-f926-4d7f-a83c-ba02b324c321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684907625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3684907625
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.2087388881
Short name T877
Test name
Test status
Simulation time 87444500 ps
CPU time 13.9 seconds
Started Jun 06 01:36:53 PM PDT 24
Finished Jun 06 01:37:08 PM PDT 24
Peak memory 257948 kb
Host smart-be0278d5-e253-4e8d-b77d-90aa536778e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087388881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
2087388881
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.480440169
Short name T803
Test name
Test status
Simulation time 32528800 ps
CPU time 15.81 seconds
Started Jun 06 01:36:54 PM PDT 24
Finished Jun 06 01:37:11 PM PDT 24
Peak memory 274752 kb
Host smart-50263997-3634-407b-bb0e-27812e5a70fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480440169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.480440169
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.1331144754
Short name T847
Test name
Test status
Simulation time 13725100 ps
CPU time 22.03 seconds
Started Jun 06 01:36:51 PM PDT 24
Finished Jun 06 01:37:14 PM PDT 24
Peak memory 273440 kb
Host smart-d8e6f2e0-b1b0-4eeb-b388-7c534618c991
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331144754 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.1331144754
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.986146986
Short name T181
Test name
Test status
Simulation time 15532448500 ps
CPU time 144.08 seconds
Started Jun 06 01:36:51 PM PDT 24
Finished Jun 06 01:39:16 PM PDT 24
Peak memory 260652 kb
Host smart-c843da8b-250b-48c7-879e-30723f7e8675
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986146986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_h
w_sec_otp.986146986
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.890209547
Short name T467
Test name
Test status
Simulation time 147918900 ps
CPU time 135.4 seconds
Started Jun 06 01:36:53 PM PDT 24
Finished Jun 06 01:39:10 PM PDT 24
Peak memory 260820 kb
Host smart-c016ea62-3685-4c22-b0ac-2f087ffa4413
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890209547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ot
p_reset.890209547
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.949908123
Short name T406
Test name
Test status
Simulation time 13853901900 ps
CPU time 84.49 seconds
Started Jun 06 01:36:51 PM PDT 24
Finished Jun 06 01:38:16 PM PDT 24
Peak memory 263288 kb
Host smart-09b074c8-a336-4258-808c-e64841d45866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949908123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.949908123
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.3653255923
Short name T20
Test name
Test status
Simulation time 226692800 ps
CPU time 76.82 seconds
Started Jun 06 01:36:52 PM PDT 24
Finished Jun 06 01:38:10 PM PDT 24
Peak memory 275464 kb
Host smart-075c8247-b8cb-4a20-979a-a5f69a33788c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653255923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3653255923
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.321842991
Short name T444
Test name
Test status
Simulation time 176464600 ps
CPU time 14.24 seconds
Started Jun 06 01:36:53 PM PDT 24
Finished Jun 06 01:37:08 PM PDT 24
Peak memory 264916 kb
Host smart-5f9df9e5-0f02-4252-b6f1-e02336fb254c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321842991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.321842991
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.2729198264
Short name T71
Test name
Test status
Simulation time 32860200 ps
CPU time 21.93 seconds
Started Jun 06 01:36:54 PM PDT 24
Finished Jun 06 01:37:16 PM PDT 24
Peak memory 264704 kb
Host smart-1045aed3-a1df-4763-b714-839e506d5b97
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729198264 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.2729198264
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.3937827047
Short name T935
Test name
Test status
Simulation time 3731819400 ps
CPU time 139.26 seconds
Started Jun 06 01:36:55 PM PDT 24
Finished Jun 06 01:39:15 PM PDT 24
Peak memory 262900 kb
Host smart-33add107-273f-49ee-9dd3-71659a046ba3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937827047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.3937827047
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.3626144780
Short name T830
Test name
Test status
Simulation time 34803800 ps
CPU time 133.05 seconds
Started Jun 06 01:36:52 PM PDT 24
Finished Jun 06 01:39:06 PM PDT 24
Peak memory 260724 kb
Host smart-94382c6d-f09a-4a49-ad99-20e452672468
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626144780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.3626144780
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.2605639448
Short name T1005
Test name
Test status
Simulation time 6938826200 ps
CPU time 74.48 seconds
Started Jun 06 01:36:53 PM PDT 24
Finished Jun 06 01:38:08 PM PDT 24
Peak memory 263128 kb
Host smart-5076f7c6-3382-460f-9c24-c79267f0f7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605639448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.2605639448
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.3322305677
Short name T901
Test name
Test status
Simulation time 34665800 ps
CPU time 148.37 seconds
Started Jun 06 01:36:53 PM PDT 24
Finished Jun 06 01:39:22 PM PDT 24
Peak memory 276584 kb
Host smart-fa970860-2c66-4292-b559-f8edcd24cc36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322305677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.3322305677
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.983756240
Short name T463
Test name
Test status
Simulation time 66654600 ps
CPU time 14 seconds
Started Jun 06 01:36:52 PM PDT 24
Finished Jun 06 01:37:07 PM PDT 24
Peak memory 265408 kb
Host smart-0e13c3e8-cc6e-4df6-b7e4-f9ff42a02569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983756240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.983756240
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.3296898186
Short name T529
Test name
Test status
Simulation time 17457200 ps
CPU time 13.57 seconds
Started Jun 06 01:36:53 PM PDT 24
Finished Jun 06 01:37:07 PM PDT 24
Peak memory 274572 kb
Host smart-fabbcfe3-152e-4b3a-9603-604f27980e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296898186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.3296898186
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.375663018
Short name T400
Test name
Test status
Simulation time 17962200 ps
CPU time 21.86 seconds
Started Jun 06 01:36:53 PM PDT 24
Finished Jun 06 01:37:15 PM PDT 24
Peak memory 273540 kb
Host smart-bcaaea15-69db-4e4e-b241-7c0ca8313757
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375663018 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.375663018
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.1750380171
Short name T850
Test name
Test status
Simulation time 5261285900 ps
CPU time 64.95 seconds
Started Jun 06 01:36:56 PM PDT 24
Finished Jun 06 01:38:02 PM PDT 24
Peak memory 262488 kb
Host smart-2ccf8284-da35-4d73-b73a-c5097fe34b0f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750380171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.1750380171
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.3843070844
Short name T993
Test name
Test status
Simulation time 51879600 ps
CPU time 133.85 seconds
Started Jun 06 01:36:54 PM PDT 24
Finished Jun 06 01:39:09 PM PDT 24
Peak memory 259980 kb
Host smart-750ced71-991e-4cc8-8871-2151aa29099c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843070844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.3843070844
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.3312679224
Short name T374
Test name
Test status
Simulation time 2058495200 ps
CPU time 74.81 seconds
Started Jun 06 01:36:54 PM PDT 24
Finished Jun 06 01:38:10 PM PDT 24
Peak memory 264544 kb
Host smart-741a89de-c4f3-4a90-a0a4-2ec091950be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312679224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.3312679224
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.292962831
Short name T765
Test name
Test status
Simulation time 23038300 ps
CPU time 154.9 seconds
Started Jun 06 01:36:54 PM PDT 24
Finished Jun 06 01:39:29 PM PDT 24
Peak memory 277748 kb
Host smart-43ae9f07-00c1-46ad-a9bf-2ea204a5d898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292962831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.292962831
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.1179009868
Short name T1034
Test name
Test status
Simulation time 124621800 ps
CPU time 13.5 seconds
Started Jun 06 01:32:35 PM PDT 24
Finished Jun 06 01:32:49 PM PDT 24
Peak memory 264812 kb
Host smart-c8c62c8e-3070-49de-a13e-3486679108a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179009868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.1
179009868
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.1883928341
Short name T795
Test name
Test status
Simulation time 23197100 ps
CPU time 15.52 seconds
Started Jun 06 01:32:32 PM PDT 24
Finished Jun 06 01:32:49 PM PDT 24
Peak memory 274744 kb
Host smart-ba907dc7-ee2f-42e5-8c95-75a5ad5d15f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883928341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.1883928341
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.3072872734
Short name T1050
Test name
Test status
Simulation time 11359100 ps
CPU time 21.84 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:32:59 PM PDT 24
Peak memory 273472 kb
Host smart-36d42d59-f4db-4b16-afd6-692340597535
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072872734 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.3072872734
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.1498235305
Short name T293
Test name
Test status
Simulation time 8396269100 ps
CPU time 2527.79 seconds
Started Jun 06 01:32:28 PM PDT 24
Finished Jun 06 02:14:38 PM PDT 24
Peak memory 262436 kb
Host smart-51392b96-71bb-41ad-808c-b68158255802
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498235305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.1498235305
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.2848249048
Short name T904
Test name
Test status
Simulation time 4364423300 ps
CPU time 910.63 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:47:39 PM PDT 24
Peak memory 270212 kb
Host smart-dcc75e26-f1b8-48ee-a485-e1cc102ff18c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848249048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2848249048
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.3158291188
Short name T997
Test name
Test status
Simulation time 1089411600 ps
CPU time 26.53 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:32:51 PM PDT 24
Peak memory 262308 kb
Host smart-2d5f8a80-02cc-492e-977c-dc0e7ecc4f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158291188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.3158291188
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3584141047
Short name T521
Test name
Test status
Simulation time 10029274500 ps
CPU time 124.87 seconds
Started Jun 06 01:32:26 PM PDT 24
Finished Jun 06 01:34:32 PM PDT 24
Peak memory 280216 kb
Host smart-9b3c48a5-2f58-43ce-8239-64868713543e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584141047 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.3584141047
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.2788574886
Short name T346
Test name
Test status
Simulation time 25429900 ps
CPU time 13.45 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:32:51 PM PDT 24
Peak memory 258912 kb
Host smart-addedf31-60dd-4470-b221-ecc72399352d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788574886 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.2788574886
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.443554579
Short name T949
Test name
Test status
Simulation time 80148720000 ps
CPU time 900.42 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:47:29 PM PDT 24
Peak memory 260652 kb
Host smart-44887337-4b07-4123-87f2-a58842c1b92f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443554579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.flash_ctrl_hw_rma_reset.443554579
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.4066391868
Short name T900
Test name
Test status
Simulation time 4795060700 ps
CPU time 73.07 seconds
Started Jun 06 01:32:22 PM PDT 24
Finished Jun 06 01:33:37 PM PDT 24
Peak memory 263016 kb
Host smart-4203b019-33c6-4f46-9f22-604342f29a70
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066391868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_h
w_sec_otp.4066391868
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.1798966712
Short name T279
Test name
Test status
Simulation time 1257469100 ps
CPU time 150.24 seconds
Started Jun 06 01:32:40 PM PDT 24
Finished Jun 06 01:35:11 PM PDT 24
Peak memory 290988 kb
Host smart-d46bb453-d27a-4ae9-95bd-9b3522ff0bf1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798966712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.1798966712
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3999536858
Short name T749
Test name
Test status
Simulation time 25712979900 ps
CPU time 558.24 seconds
Started Jun 06 01:32:28 PM PDT 24
Finished Jun 06 01:41:48 PM PDT 24
Peak memory 284556 kb
Host smart-d0df5ca6-8e23-4e6f-b41c-c57a7d0d8a2f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999536858 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.3999536858
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.2256427454
Short name T535
Test name
Test status
Simulation time 12363151100 ps
CPU time 76.67 seconds
Started Jun 06 01:32:31 PM PDT 24
Finished Jun 06 01:33:49 PM PDT 24
Peak memory 264976 kb
Host smart-a253839f-ae77-4dc4-8841-274ad960e5f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256427454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.2256427454
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3394679860
Short name T1074
Test name
Test status
Simulation time 343127382000 ps
CPU time 386.65 seconds
Started Jun 06 01:32:30 PM PDT 24
Finished Jun 06 01:38:58 PM PDT 24
Peak memory 265280 kb
Host smart-08bd82b4-6002-4fa0-93a8-18dcdcae09e4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339
4679860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.3394679860
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.3063978373
Short name T805
Test name
Test status
Simulation time 2015139300 ps
CPU time 90.9 seconds
Started Jun 06 01:32:24 PM PDT 24
Finished Jun 06 01:33:57 PM PDT 24
Peak memory 260588 kb
Host smart-ead994f6-6d89-4b74-bd6c-c433b8561f7e
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063978373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.3063978373
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.559057003
Short name T137
Test name
Test status
Simulation time 47761400 ps
CPU time 13.7 seconds
Started Jun 06 01:32:25 PM PDT 24
Finished Jun 06 01:32:40 PM PDT 24
Peak memory 259596 kb
Host smart-30970943-8cf8-467b-b229-4ebe1b1c58ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559057003 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.559057003
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.2550966219
Short name T787
Test name
Test status
Simulation time 26582369300 ps
CPU time 325.66 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:37:54 PM PDT 24
Peak memory 273324 kb
Host smart-5076999c-5c86-48f4-8495-fd151ef39149
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550966219 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.2550966219
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.4288333704
Short name T742
Test name
Test status
Simulation time 43981500 ps
CPU time 134.05 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:34:43 PM PDT 24
Peak memory 259680 kb
Host smart-82d1fc94-68d6-4e83-9f76-e4c771ee8913
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288333704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.4288333704
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.3414437238
Short name T225
Test name
Test status
Simulation time 27410120500 ps
CPU time 480.82 seconds
Started Jun 06 01:32:21 PM PDT 24
Finished Jun 06 01:40:24 PM PDT 24
Peak memory 262852 kb
Host smart-55aed1f1-1074-4d8e-ad42-ae14ba544e04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3414437238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.3414437238
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.1941412556
Short name T564
Test name
Test status
Simulation time 20457300 ps
CPU time 13.41 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:32:51 PM PDT 24
Peak memory 265048 kb
Host smart-e6c4c424-8fdd-4a1b-9b97-3fd4f9a1a2b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941412556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.1941412556
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.2327475169
Short name T526
Test name
Test status
Simulation time 296940200 ps
CPU time 1179.98 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:52:05 PM PDT 24
Peak memory 287552 kb
Host smart-ecefaa4a-dda1-4f95-93f3-21caed46992c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327475169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.2327475169
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.2294496100
Short name T783
Test name
Test status
Simulation time 2344087000 ps
CPU time 121.3 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:34:30 PM PDT 24
Peak memory 289916 kb
Host smart-5608f8f8-6e0a-4dde-a47e-666b28ccb6c4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294496100 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_ro.2294496100
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.1799110394
Short name T199
Test name
Test status
Simulation time 534920700 ps
CPU time 118.63 seconds
Started Jun 06 01:32:35 PM PDT 24
Finished Jun 06 01:34:35 PM PDT 24
Peak memory 281656 kb
Host smart-00358c8d-6d11-468b-bccc-b4eecbda7bf5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1799110394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.1799110394
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.3004668077
Short name T277
Test name
Test status
Simulation time 9991248000 ps
CPU time 160.62 seconds
Started Jun 06 01:32:32 PM PDT 24
Finished Jun 06 01:35:14 PM PDT 24
Peak memory 281768 kb
Host smart-7fc3d263-87b4-466e-920c-7c7062d17040
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004668077 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.3004668077
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.3165185529
Short name T1072
Test name
Test status
Simulation time 6560935800 ps
CPU time 506.57 seconds
Started Jun 06 01:32:23 PM PDT 24
Finished Jun 06 01:40:52 PM PDT 24
Peak memory 309396 kb
Host smart-2683f690-4615-42be-8f90-fc2b1e5f3bdc
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165185529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.flash_ctrl_rw.3165185529
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.536126122
Short name T1058
Test name
Test status
Simulation time 14179443400 ps
CPU time 505.03 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:41:02 PM PDT 24
Peak memory 334392 kb
Host smart-ba7b0a02-f00a-4f64-b838-7243e3a5e3d1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536126122 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.flash_ctrl_rw_derr.536126122
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.1816840285
Short name T776
Test name
Test status
Simulation time 4206609600 ps
CPU time 700.2 seconds
Started Jun 06 01:32:37 PM PDT 24
Finished Jun 06 01:44:19 PM PDT 24
Peak memory 313012 kb
Host smart-aaafea86-d770-49b0-a9c1-85a1b9b86c15
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816840285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.1816840285
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.2498710416
Short name T168
Test name
Test status
Simulation time 4007308500 ps
CPU time 71.92 seconds
Started Jun 06 01:32:38 PM PDT 24
Finished Jun 06 01:33:51 PM PDT 24
Peak memory 262412 kb
Host smart-24617902-ecf0-4210-9c3c-2de3f0be59a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498710416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.2498710416
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.2644180356
Short name T699
Test name
Test status
Simulation time 17688500 ps
CPU time 76.55 seconds
Started Jun 06 01:32:19 PM PDT 24
Finished Jun 06 01:33:37 PM PDT 24
Peak memory 276388 kb
Host smart-890287e7-14a3-4da2-b61d-7856beaff5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644180356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2644180356
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.3858769719
Short name T547
Test name
Test status
Simulation time 4888881400 ps
CPU time 205.09 seconds
Started Jun 06 01:32:26 PM PDT 24
Finished Jun 06 01:35:52 PM PDT 24
Peak memory 264932 kb
Host smart-5457e7bc-48ac-41bd-b84b-e8088f7be0d4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858769719 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.flash_ctrl_wo.3858769719
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.3333707353
Short name T565
Test name
Test status
Simulation time 36306300 ps
CPU time 15.91 seconds
Started Jun 06 01:36:54 PM PDT 24
Finished Jun 06 01:37:10 PM PDT 24
Peak memory 274728 kb
Host smart-6c7102d8-8631-4aa7-ac3e-bbd75eeb39fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333707353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.3333707353
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.3559429807
Short name T394
Test name
Test status
Simulation time 110099000 ps
CPU time 110.88 seconds
Started Jun 06 01:36:50 PM PDT 24
Finished Jun 06 01:38:42 PM PDT 24
Peak memory 259552 kb
Host smart-d53cbc17-071f-4cda-85ea-2100c1d89e36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559429807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.3559429807
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.981710565
Short name T1086
Test name
Test status
Simulation time 53357100 ps
CPU time 15.68 seconds
Started Jun 06 01:36:51 PM PDT 24
Finished Jun 06 01:37:07 PM PDT 24
Peak memory 274544 kb
Host smart-553906fc-ac20-4fbf-874d-cf07b64e98b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981710565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.981710565
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.534290619
Short name T934
Test name
Test status
Simulation time 133090800 ps
CPU time 133.78 seconds
Started Jun 06 01:36:55 PM PDT 24
Finished Jun 06 01:39:09 PM PDT 24
Peak memory 264840 kb
Host smart-ed5b0778-db8d-4cd7-aed7-08bbeb66a4d0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534290619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_ot
p_reset.534290619
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.1362141136
Short name T478
Test name
Test status
Simulation time 16761000 ps
CPU time 15.84 seconds
Started Jun 06 01:36:55 PM PDT 24
Finished Jun 06 01:37:12 PM PDT 24
Peak memory 274824 kb
Host smart-3df088f8-750a-4cd5-8577-6c16feedaf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362141136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1362141136
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.931221007
Short name T1094
Test name
Test status
Simulation time 77209900 ps
CPU time 133.38 seconds
Started Jun 06 01:36:52 PM PDT 24
Finished Jun 06 01:39:06 PM PDT 24
Peak memory 260804 kb
Host smart-84132cff-7ddc-4cc0-a17b-fa3158b78d92
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931221007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_ot
p_reset.931221007
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.2525364435
Short name T704
Test name
Test status
Simulation time 16279800 ps
CPU time 15.92 seconds
Started Jun 06 01:36:54 PM PDT 24
Finished Jun 06 01:37:11 PM PDT 24
Peak memory 274676 kb
Host smart-71b7a156-1255-4919-8ddc-5eea8648f894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525364435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.2525364435
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.2713972266
Short name T560
Test name
Test status
Simulation time 38239600 ps
CPU time 136.49 seconds
Started Jun 06 01:36:54 PM PDT 24
Finished Jun 06 01:39:11 PM PDT 24
Peak memory 260780 kb
Host smart-9fc34eec-6eef-4b15-a97a-03442f3e88f1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713972266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o
tp_reset.2713972266
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.705520336
Short name T479
Test name
Test status
Simulation time 99339600 ps
CPU time 13.51 seconds
Started Jun 06 01:36:52 PM PDT 24
Finished Jun 06 01:37:07 PM PDT 24
Peak memory 274776 kb
Host smart-9bdc9a9f-a63b-43a2-b349-e54436d9cb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705520336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.705520336
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.839210816
Short name T693
Test name
Test status
Simulation time 101901100 ps
CPU time 135.35 seconds
Started Jun 06 01:36:51 PM PDT 24
Finished Jun 06 01:39:07 PM PDT 24
Peak memory 264572 kb
Host smart-9a2bba19-6efd-4862-bb06-05884baf99b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839210816 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_ot
p_reset.839210816
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.4156486344
Short name T550
Test name
Test status
Simulation time 24285300 ps
CPU time 16.05 seconds
Started Jun 06 01:36:56 PM PDT 24
Finished Jun 06 01:37:13 PM PDT 24
Peak memory 274536 kb
Host smart-ef12dced-6120-4e2e-aff2-ae1a905c7ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156486344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.4156486344
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.221359240
Short name T606
Test name
Test status
Simulation time 53146000 ps
CPU time 131.5 seconds
Started Jun 06 01:36:52 PM PDT 24
Finished Jun 06 01:39:04 PM PDT 24
Peak memory 259760 kb
Host smart-cda194cf-2453-4ebc-934c-eba48fa143b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221359240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_ot
p_reset.221359240
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.1320548065
Short name T186
Test name
Test status
Simulation time 13294600 ps
CPU time 15.9 seconds
Started Jun 06 01:36:59 PM PDT 24
Finished Jun 06 01:37:16 PM PDT 24
Peak memory 274596 kb
Host smart-0fa0a16f-623b-4581-94b1-a29dab0150fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320548065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.1320548065
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.2820830164
Short name T502
Test name
Test status
Simulation time 133112800 ps
CPU time 113.55 seconds
Started Jun 06 01:36:59 PM PDT 24
Finished Jun 06 01:38:54 PM PDT 24
Peak memory 260784 kb
Host smart-f201e5e3-22d1-401c-a3b0-519f1c2b8d4a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820830164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o
tp_reset.2820830164
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.4072124776
Short name T690
Test name
Test status
Simulation time 17533200 ps
CPU time 15.84 seconds
Started Jun 06 01:36:57 PM PDT 24
Finished Jun 06 01:37:13 PM PDT 24
Peak memory 274656 kb
Host smart-79c6c3ac-fa2a-4fe3-8146-c6ea47811fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072124776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.4072124776
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.1133794110
Short name T1026
Test name
Test status
Simulation time 40732200 ps
CPU time 132.23 seconds
Started Jun 06 01:36:58 PM PDT 24
Finished Jun 06 01:39:11 PM PDT 24
Peak memory 259848 kb
Host smart-907a3855-ebe9-45c5-aaf5-401c0e0f804e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133794110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.1133794110
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.464769437
Short name T956
Test name
Test status
Simulation time 30201800 ps
CPU time 13.37 seconds
Started Jun 06 01:37:02 PM PDT 24
Finished Jun 06 01:37:16 PM PDT 24
Peak memory 274592 kb
Host smart-5becdab3-f6fc-4a6a-b06b-c6bf22ff0f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464769437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.464769437
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.1201042044
Short name T30
Test name
Test status
Simulation time 480986500 ps
CPU time 132.64 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:39:15 PM PDT 24
Peak memory 260812 kb
Host smart-beadcf8e-c983-476d-ba6c-b10ccd23b79f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201042044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.1201042044
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.69312730
Short name T549
Test name
Test status
Simulation time 38288200 ps
CPU time 15.84 seconds
Started Jun 06 01:36:57 PM PDT 24
Finished Jun 06 01:37:14 PM PDT 24
Peak memory 274664 kb
Host smart-696e143d-025f-4ed5-a704-113ea26aef59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69312730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.69312730
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.3486312741
Short name T1098
Test name
Test status
Simulation time 67974800 ps
CPU time 13.57 seconds
Started Jun 06 01:32:37 PM PDT 24
Finished Jun 06 01:32:51 PM PDT 24
Peak memory 264840 kb
Host smart-fc6fe9e3-1d19-4a9f-9cc8-c3db8e51dada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486312741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3
486312741
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.3437489422
Short name T539
Test name
Test status
Simulation time 15055600 ps
CPU time 15.65 seconds
Started Jun 06 01:32:41 PM PDT 24
Finished Jun 06 01:32:57 PM PDT 24
Peak memory 274428 kb
Host smart-5ba4305c-99e4-4534-87b6-3f87de3c4a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437489422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.3437489422
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.3966532650
Short name T925
Test name
Test status
Simulation time 11434000 ps
CPU time 21.88 seconds
Started Jun 06 01:32:37 PM PDT 24
Finished Jun 06 01:33:00 PM PDT 24
Peak memory 273452 kb
Host smart-37348f4a-d372-4e42-8a2b-def5d15aca3d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966532650 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.3966532650
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.2295305483
Short name T224
Test name
Test status
Simulation time 11418116500 ps
CPU time 2169.67 seconds
Started Jun 06 01:32:38 PM PDT 24
Finished Jun 06 02:08:49 PM PDT 24
Peak memory 264584 kb
Host smart-5151abcd-54f4-476b-9609-260241ea1e5f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295305483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.2295305483
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.836398318
Short name T737
Test name
Test status
Simulation time 602548700 ps
CPU time 781.19 seconds
Started Jun 06 01:32:35 PM PDT 24
Finished Jun 06 01:45:38 PM PDT 24
Peak memory 273616 kb
Host smart-d73a62ee-53cd-472f-a912-a4d82f7d005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836398318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.836398318
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.3277477880
Short name T61
Test name
Test status
Simulation time 410892100 ps
CPU time 20.12 seconds
Started Jun 06 01:32:38 PM PDT 24
Finished Jun 06 01:32:59 PM PDT 24
Peak memory 263228 kb
Host smart-ac3e45d0-2542-4d8d-8711-103c05717a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277477880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.3277477880
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.737844844
Short name T889
Test name
Test status
Simulation time 10035419100 ps
CPU time 43.47 seconds
Started Jun 06 01:32:37 PM PDT 24
Finished Jun 06 01:33:21 PM PDT 24
Peak memory 265204 kb
Host smart-dbc5e1c9-c39b-4dd5-a6ce-7dd614a272ee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737844844 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.737844844
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.1818069621
Short name T848
Test name
Test status
Simulation time 46907400 ps
CPU time 13.52 seconds
Started Jun 06 01:32:35 PM PDT 24
Finished Jun 06 01:32:49 PM PDT 24
Peak memory 258184 kb
Host smart-64b7ff45-48fc-40e2-94ba-88d2a5ba35d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818069621 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.1818069621
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.201244040
Short name T855
Test name
Test status
Simulation time 80128936200 ps
CPU time 844.07 seconds
Started Jun 06 01:32:28 PM PDT 24
Finished Jun 06 01:46:34 PM PDT 24
Peak memory 260672 kb
Host smart-d7ca5966-da06-4f96-9591-8bb28ae1d107
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201244040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.flash_ctrl_hw_rma_reset.201244040
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.3355908129
Short name T458
Test name
Test status
Simulation time 2834488000 ps
CPU time 190.09 seconds
Started Jun 06 01:32:37 PM PDT 24
Finished Jun 06 01:35:48 PM PDT 24
Peak memory 262484 kb
Host smart-dc1694b5-ac1c-419e-8ab0-cc23eca4f396
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355908129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.3355908129
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.4192722085
Short name T715
Test name
Test status
Simulation time 3091779800 ps
CPU time 203.43 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:36:01 PM PDT 24
Peak memory 284712 kb
Host smart-a073e93a-dfb9-4600-b609-41a8c2575c7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192722085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.4192722085
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.265679693
Short name T646
Test name
Test status
Simulation time 37327756200 ps
CPU time 299.99 seconds
Started Jun 06 01:32:33 PM PDT 24
Finished Jun 06 01:37:34 PM PDT 24
Peak memory 290812 kb
Host smart-1f4be151-914a-401e-982f-9ab0b842678b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265679693 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.265679693
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.3896388258
Short name T35
Test name
Test status
Simulation time 4171819500 ps
CPU time 66.83 seconds
Started Jun 06 01:32:37 PM PDT 24
Finished Jun 06 01:33:45 PM PDT 24
Peak memory 260244 kb
Host smart-a388f6ca-1ac8-4a18-9437-f5f83e76c08a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896388258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.3896388258
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2068686512
Short name T32
Test name
Test status
Simulation time 45646600100 ps
CPU time 199.01 seconds
Started Jun 06 01:32:32 PM PDT 24
Finished Jun 06 01:35:52 PM PDT 24
Peak memory 264936 kb
Host smart-6b014e92-403d-4fde-8eb9-4a30f007628f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206
8686512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.2068686512
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.4088695795
Short name T664
Test name
Test status
Simulation time 1021875600 ps
CPU time 83.58 seconds
Started Jun 06 01:32:31 PM PDT 24
Finished Jun 06 01:33:56 PM PDT 24
Peak memory 260424 kb
Host smart-da23e30e-3882-436a-8ae2-37dca7968b37
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088695795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.4088695795
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.3746927423
Short name T713
Test name
Test status
Simulation time 63431300 ps
CPU time 13.49 seconds
Started Jun 06 01:32:35 PM PDT 24
Finished Jun 06 01:32:49 PM PDT 24
Peak memory 259580 kb
Host smart-833ca88a-1d14-4ce4-8e48-725047e48e6f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746927423 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.3746927423
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.993595636
Short name T90
Test name
Test status
Simulation time 37807747600 ps
CPU time 448.97 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:40:06 PM PDT 24
Peak memory 274316 kb
Host smart-da35f836-3558-4fda-8207-1e321ea529a3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993595636 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_mp_regions.993595636
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.2897165438
Short name T28
Test name
Test status
Simulation time 144529000 ps
CPU time 134.08 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:34:51 PM PDT 24
Peak memory 264448 kb
Host smart-247b0c30-6744-47b4-b7c5-19a7c084e29c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897165438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.2897165438
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.674838560
Short name T162
Test name
Test status
Simulation time 4284630100 ps
CPU time 213.46 seconds
Started Jun 06 01:32:32 PM PDT 24
Finished Jun 06 01:36:06 PM PDT 24
Peak memory 262912 kb
Host smart-3029c16a-d8c4-49fb-b9c8-43e78d072e53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=674838560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.674838560
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.2547581027
Short name T800
Test name
Test status
Simulation time 18641100 ps
CPU time 13.45 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:32:51 PM PDT 24
Peak memory 258324 kb
Host smart-e45e146d-26a1-4924-9424-bbc6c3e877c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547581027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.2547581027
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.597397375
Short name T759
Test name
Test status
Simulation time 59883600 ps
CPU time 379.02 seconds
Started Jun 06 01:32:27 PM PDT 24
Finished Jun 06 01:38:48 PM PDT 24
Peak memory 281552 kb
Host smart-3046513f-1b44-4a0c-badc-7a6df95447f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597397375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.597397375
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.3248948598
Short name T675
Test name
Test status
Simulation time 294126400 ps
CPU time 32.76 seconds
Started Jun 06 01:32:35 PM PDT 24
Finished Jun 06 01:33:09 PM PDT 24
Peak memory 277412 kb
Host smart-2e4a8364-857d-4e57-a82a-59ce34287eb8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248948598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.3248948598
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.3435193104
Short name T746
Test name
Test status
Simulation time 2523347500 ps
CPU time 128.98 seconds
Started Jun 06 01:32:38 PM PDT 24
Finished Jun 06 01:34:48 PM PDT 24
Peak memory 280680 kb
Host smart-4dca3e88-ff3e-49c4-977a-14ae02e40313
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435193104 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_ro.3435193104
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.2620417607
Short name T682
Test name
Test status
Simulation time 3246611200 ps
CPU time 144.78 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:35:02 PM PDT 24
Peak memory 281704 kb
Host smart-bed4776f-cd55-49d4-b671-a69e33dc4b2f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2620417607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.2620417607
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.463391676
Short name T766
Test name
Test status
Simulation time 5250909900 ps
CPU time 150.45 seconds
Started Jun 06 01:32:32 PM PDT 24
Finished Jun 06 01:35:04 PM PDT 24
Peak memory 281736 kb
Host smart-c0f2460d-562f-4741-8079-6906c2257f01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463391676 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.463391676
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.157658136
Short name T842
Test name
Test status
Simulation time 6193965400 ps
CPU time 555.04 seconds
Started Jun 06 01:32:33 PM PDT 24
Finished Jun 06 01:41:49 PM PDT 24
Peak memory 314380 kb
Host smart-e01ddeb1-2a15-4ce2-ae50-e68ed88955b2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157658136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.flash_ctrl_rw.157658136
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.495612799
Short name T209
Test name
Test status
Simulation time 16950613200 ps
CPU time 657.45 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:43:34 PM PDT 24
Peak memory 339000 kb
Host smart-0a8eb501-cc05-4002-84dc-60a46157bf60
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495612799 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_rw_derr.495612799
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.3090592925
Short name T454
Test name
Test status
Simulation time 66790000 ps
CPU time 27.94 seconds
Started Jun 06 01:32:32 PM PDT 24
Finished Jun 06 01:33:01 PM PDT 24
Peak memory 275664 kb
Host smart-e7bc225d-9a3e-4fa7-abc8-592f16545e7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090592925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.3090592925
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.3206306629
Short name T319
Test name
Test status
Simulation time 48124500 ps
CPU time 30.57 seconds
Started Jun 06 01:32:31 PM PDT 24
Finished Jun 06 01:33:03 PM PDT 24
Peak memory 273484 kb
Host smart-5f4c656b-f3f8-49c1-a4a1-3777de873cb7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206306629 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.3206306629
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.428619934
Short name T407
Test name
Test status
Simulation time 1964585500 ps
CPU time 60.19 seconds
Started Jun 06 01:32:41 PM PDT 24
Finished Jun 06 01:33:41 PM PDT 24
Peak memory 262868 kb
Host smart-576aef48-b4f5-43d5-a061-ba1e895c3c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428619934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.428619934
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.1701660126
Short name T722
Test name
Test status
Simulation time 40820600 ps
CPU time 52.17 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:33:29 PM PDT 24
Peak memory 270752 kb
Host smart-4a35ad96-6c95-4391-bd7b-501b6c8e803f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701660126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.1701660126
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.1376465322
Short name T237
Test name
Test status
Simulation time 39206297700 ps
CPU time 190.25 seconds
Started Jun 06 01:32:31 PM PDT 24
Finished Jun 06 01:35:43 PM PDT 24
Peak memory 265028 kb
Host smart-9589d7a8-25a3-452f-bc3b-07ef8b3f39c6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376465322 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.flash_ctrl_wo.1376465322
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.4215708324
Short name T419
Test name
Test status
Simulation time 18605900 ps
CPU time 15.98 seconds
Started Jun 06 01:36:57 PM PDT 24
Finished Jun 06 01:37:13 PM PDT 24
Peak memory 284196 kb
Host smart-74c6d809-4ae5-4c88-bb31-7db4920ff9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215708324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.4215708324
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.2630498908
Short name T750
Test name
Test status
Simulation time 76455600 ps
CPU time 134.56 seconds
Started Jun 06 01:36:56 PM PDT 24
Finished Jun 06 01:39:12 PM PDT 24
Peak memory 259624 kb
Host smart-aa72e021-9ed9-448b-b563-dc8da647dfee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630498908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.2630498908
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.4096698904
Short name T187
Test name
Test status
Simulation time 47415600 ps
CPU time 15.83 seconds
Started Jun 06 01:37:02 PM PDT 24
Finished Jun 06 01:37:19 PM PDT 24
Peak memory 274776 kb
Host smart-f2749e3b-ed0a-4139-844d-e45b72099325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096698904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.4096698904
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.3481684482
Short name T440
Test name
Test status
Simulation time 276774200 ps
CPU time 137.49 seconds
Started Jun 06 01:36:56 PM PDT 24
Finished Jun 06 01:39:14 PM PDT 24
Peak memory 259712 kb
Host smart-004bf099-8477-43ed-b73b-ef2c7e76375f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481684482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.3481684482
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.534063058
Short name T511
Test name
Test status
Simulation time 13521200 ps
CPU time 13.73 seconds
Started Jun 06 01:36:56 PM PDT 24
Finished Jun 06 01:37:10 PM PDT 24
Peak memory 274464 kb
Host smart-0aa8f344-e9a9-4acb-838d-81efb209ff50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534063058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.534063058
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.3176068080
Short name T1088
Test name
Test status
Simulation time 77780300 ps
CPU time 132.94 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:39:15 PM PDT 24
Peak memory 259836 kb
Host smart-b8e1f922-afa0-4e85-8728-2d6a142af65b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176068080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.3176068080
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.3137038823
Short name T791
Test name
Test status
Simulation time 14507300 ps
CPU time 16.02 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:37:18 PM PDT 24
Peak memory 274752 kb
Host smart-dcbb64c8-5eec-4f57-97d2-c219901b4656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137038823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.3137038823
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.813544066
Short name T648
Test name
Test status
Simulation time 74449800 ps
CPU time 111.81 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:38:54 PM PDT 24
Peak memory 260748 kb
Host smart-602f53bd-749e-404e-866f-b17ea6bb5320
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813544066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_ot
p_reset.813544066
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.1053306884
Short name T974
Test name
Test status
Simulation time 42534800 ps
CPU time 13.45 seconds
Started Jun 06 01:36:57 PM PDT 24
Finished Jun 06 01:37:11 PM PDT 24
Peak memory 284068 kb
Host smart-6ae4548e-9fdc-4d05-b734-8f8c16e34e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053306884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.1053306884
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.2649218472
Short name T764
Test name
Test status
Simulation time 43407400 ps
CPU time 111.42 seconds
Started Jun 06 01:36:56 PM PDT 24
Finished Jun 06 01:38:48 PM PDT 24
Peak memory 259764 kb
Host smart-527d8a95-e378-4144-8566-1bc906c5583a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649218472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.2649218472
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.1598770035
Short name T559
Test name
Test status
Simulation time 27051800 ps
CPU time 15.82 seconds
Started Jun 06 01:37:00 PM PDT 24
Finished Jun 06 01:37:18 PM PDT 24
Peak memory 274800 kb
Host smart-fb6f8ff9-24d8-4a57-a9d7-6193a8849bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598770035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.1598770035
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.3248306971
Short name T483
Test name
Test status
Simulation time 399463100 ps
CPU time 133.27 seconds
Started Jun 06 01:37:00 PM PDT 24
Finished Jun 06 01:39:15 PM PDT 24
Peak memory 259708 kb
Host smart-cd54d8a6-1b44-4c80-bfc8-7158c6520b44
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248306971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.3248306971
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.2907335825
Short name T922
Test name
Test status
Simulation time 49774400 ps
CPU time 15.58 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:37:18 PM PDT 24
Peak memory 274624 kb
Host smart-9afbe7c9-4cad-42ff-bcb1-8424ebed2400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907335825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2907335825
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.2781513008
Short name T145
Test name
Test status
Simulation time 127176100 ps
CPU time 113.75 seconds
Started Jun 06 01:36:57 PM PDT 24
Finished Jun 06 01:38:51 PM PDT 24
Peak memory 260108 kb
Host smart-5cc13edf-9292-4fb0-91b9-4f0d58965e82
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781513008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.2781513008
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.4245139454
Short name T1079
Test name
Test status
Simulation time 17429800 ps
CPU time 16.07 seconds
Started Jun 06 01:36:56 PM PDT 24
Finished Jun 06 01:37:13 PM PDT 24
Peak memory 274656 kb
Host smart-5e331d4d-a421-4e4c-bd6a-14a7602fbb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245139454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.4245139454
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.3556775968
Short name T452
Test name
Test status
Simulation time 137706200 ps
CPU time 133.75 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:39:16 PM PDT 24
Peak memory 260660 kb
Host smart-ba306c75-2079-49e9-a0f7-fd53cbd53786
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556775968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.3556775968
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.23586716
Short name T103
Test name
Test status
Simulation time 184054100 ps
CPU time 16.65 seconds
Started Jun 06 01:36:57 PM PDT 24
Finished Jun 06 01:37:14 PM PDT 24
Peak memory 274064 kb
Host smart-1511354d-f766-4e9e-b03d-d0a374e37d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23586716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.23586716
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.565893268
Short name T1087
Test name
Test status
Simulation time 34171300 ps
CPU time 133.35 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:39:16 PM PDT 24
Peak memory 260640 kb
Host smart-16487811-22ba-4525-a642-0b8319d32a66
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565893268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_ot
p_reset.565893268
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.199358114
Short name T714
Test name
Test status
Simulation time 55718800 ps
CPU time 15.95 seconds
Started Jun 06 01:36:56 PM PDT 24
Finished Jun 06 01:37:13 PM PDT 24
Peak memory 274848 kb
Host smart-46983b6e-7bdb-4800-bba8-f96d43be5fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199358114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.199358114
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.535739561
Short name T77
Test name
Test status
Simulation time 38228600 ps
CPU time 132.43 seconds
Started Jun 06 01:37:00 PM PDT 24
Finished Jun 06 01:39:14 PM PDT 24
Peak memory 259716 kb
Host smart-c1850508-b23e-4c55-8c2f-7b758e1cb7dd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535739561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_ot
p_reset.535739561
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.140207365
Short name T782
Test name
Test status
Simulation time 85804200 ps
CPU time 13.74 seconds
Started Jun 06 01:32:48 PM PDT 24
Finished Jun 06 01:33:04 PM PDT 24
Peak memory 258000 kb
Host smart-74f40230-d2a4-4572-be2c-501d7c02e515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140207365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.140207365
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.2112543612
Short name T808
Test name
Test status
Simulation time 22588600 ps
CPU time 16.04 seconds
Started Jun 06 01:32:45 PM PDT 24
Finished Jun 06 01:33:03 PM PDT 24
Peak memory 274680 kb
Host smart-8429b9ac-27c7-463d-9661-7ea2397676b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112543612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.2112543612
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.3070612465
Short name T399
Test name
Test status
Simulation time 16401900 ps
CPU time 20.69 seconds
Started Jun 06 01:32:48 PM PDT 24
Finished Jun 06 01:33:11 PM PDT 24
Peak memory 273464 kb
Host smart-17d653f0-be20-4548-91f9-cdab8d4358a5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070612465 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.3070612465
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.4093037228
Short name T770
Test name
Test status
Simulation time 1279926000 ps
CPU time 886.95 seconds
Started Jun 06 01:32:40 PM PDT 24
Finished Jun 06 01:47:28 PM PDT 24
Peak memory 270224 kb
Host smart-30b46ace-3509-4fa2-b5eb-734f5e6da194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093037228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.4093037228
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.1331264593
Short name T52
Test name
Test status
Simulation time 400270700 ps
CPU time 23.78 seconds
Started Jun 06 01:32:37 PM PDT 24
Finished Jun 06 01:33:02 PM PDT 24
Peak memory 262240 kb
Host smart-c7284b45-ab6c-4a34-a45a-a65be98bcbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331264593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.1331264593
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.1022049462
Short name T287
Test name
Test status
Simulation time 10011708700 ps
CPU time 104.15 seconds
Started Jun 06 01:32:48 PM PDT 24
Finished Jun 06 01:34:34 PM PDT 24
Peak memory 306720 kb
Host smart-f33e132d-2aed-4d2e-9448-1ebc33e82457
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022049462 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.1022049462
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.2864174942
Short name T133
Test name
Test status
Simulation time 15310200 ps
CPU time 13.66 seconds
Started Jun 06 01:32:45 PM PDT 24
Finished Jun 06 01:33:01 PM PDT 24
Peak memory 258060 kb
Host smart-45422bdb-6a9a-402b-b9f2-0bff00a76509
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864174942 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.2864174942
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.2406870325
Short name T160
Test name
Test status
Simulation time 40125514500 ps
CPU time 881.14 seconds
Started Jun 06 01:32:41 PM PDT 24
Finished Jun 06 01:47:23 PM PDT 24
Peak memory 263724 kb
Host smart-5d113db5-eb94-42a5-b901-ac9c976a35b4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406870325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.2406870325
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1981200400
Short name T914
Test name
Test status
Simulation time 4136174700 ps
CPU time 96.15 seconds
Started Jun 06 01:32:42 PM PDT 24
Finished Jun 06 01:34:19 PM PDT 24
Peak memory 263024 kb
Host smart-001860f8-cbed-4645-9c96-93d6c7336952
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981200400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.1981200400
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.372261357
Short name T621
Test name
Test status
Simulation time 2780125100 ps
CPU time 135.41 seconds
Started Jun 06 01:32:38 PM PDT 24
Finished Jun 06 01:34:54 PM PDT 24
Peak memory 293580 kb
Host smart-a07719ef-586a-41cd-a2d0-d8e56b11a42a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372261357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash
_ctrl_intr_rd.372261357
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3921184502
Short name T853
Test name
Test status
Simulation time 82971397900 ps
CPU time 284.63 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:37:21 PM PDT 24
Peak memory 284696 kb
Host smart-7ec57b16-fbb8-4bb8-982e-18979e8d1d4a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921184502 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.3921184502
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.1703668020
Short name T917
Test name
Test status
Simulation time 10442826900 ps
CPU time 82.61 seconds
Started Jun 06 01:32:39 PM PDT 24
Finished Jun 06 01:34:02 PM PDT 24
Peak memory 265268 kb
Host smart-fef976c3-5aec-4d0c-9534-fd883bfe61bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703668020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.1703668020
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3332254325
Short name T767
Test name
Test status
Simulation time 29730020200 ps
CPU time 211.95 seconds
Started Jun 06 01:32:45 PM PDT 24
Finished Jun 06 01:36:19 PM PDT 24
Peak memory 264868 kb
Host smart-3e3cb300-13d3-4d47-bf4f-c0c04c16cd97
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333
2254325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.3332254325
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.2721075858
Short name T982
Test name
Test status
Simulation time 3876177100 ps
CPU time 60.63 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:33:38 PM PDT 24
Peak memory 260456 kb
Host smart-b8ebafa9-5d78-4e40-848b-bd326b801814
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721075858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2721075858
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.4014901089
Short name T292
Test name
Test status
Simulation time 26828300 ps
CPU time 13.84 seconds
Started Jun 06 01:32:47 PM PDT 24
Finished Jun 06 01:33:02 PM PDT 24
Peak memory 264576 kb
Host smart-04dc2133-abce-4b96-8500-eb9892970ff9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014901089 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.4014901089
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.454705887
Short name T88
Test name
Test status
Simulation time 62345732000 ps
CPU time 343.66 seconds
Started Jun 06 01:32:38 PM PDT 24
Finished Jun 06 01:38:22 PM PDT 24
Peak memory 274116 kb
Host smart-84a9d5b6-fc53-431b-a846-428e5361cf31
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454705887 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_mp_regions.454705887
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.1908201465
Short name T650
Test name
Test status
Simulation time 125220700 ps
CPU time 111.39 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:34:29 PM PDT 24
Peak memory 263028 kb
Host smart-6f9d4c6e-f9c6-42e6-a416-1bc715cdfaa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1908201465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1908201465
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.2864291212
Short name T490
Test name
Test status
Simulation time 53316800 ps
CPU time 13.54 seconds
Started Jun 06 01:32:48 PM PDT 24
Finished Jun 06 01:33:03 PM PDT 24
Peak memory 265264 kb
Host smart-77c401b7-b793-4cc0-81b5-921b7c1d85e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864291212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_res
et.2864291212
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.426586969
Short name T601
Test name
Test status
Simulation time 302337500 ps
CPU time 128.78 seconds
Started Jun 06 01:32:35 PM PDT 24
Finished Jun 06 01:34:45 PM PDT 24
Peak memory 277740 kb
Host smart-3d1fdbec-93b5-4176-8a63-181eb282ea4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426586969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.426586969
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.3801789910
Short name T278
Test name
Test status
Simulation time 285196600 ps
CPU time 33.14 seconds
Started Jun 06 01:32:48 PM PDT 24
Finished Jun 06 01:33:22 PM PDT 24
Peak memory 275112 kb
Host smart-f6e54983-f670-417c-a542-b958a35de762
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801789910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.3801789910
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.1263164933
Short name T575
Test name
Test status
Simulation time 1053653400 ps
CPU time 131.9 seconds
Started Jun 06 01:32:37 PM PDT 24
Finished Jun 06 01:34:50 PM PDT 24
Peak memory 289912 kb
Host smart-7ce24b52-6b36-4e68-b98f-f10fd73669ce
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263164933 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.1263164933
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.3643565090
Short name T247
Test name
Test status
Simulation time 1132198700 ps
CPU time 148.82 seconds
Started Jun 06 01:32:42 PM PDT 24
Finished Jun 06 01:35:11 PM PDT 24
Peak memory 281772 kb
Host smart-f7ab2bc0-9230-47dd-bf54-c7c99820a499
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3643565090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.3643565090
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.229659607
Short name T786
Test name
Test status
Simulation time 552465300 ps
CPU time 128.06 seconds
Started Jun 06 01:32:40 PM PDT 24
Finished Jun 06 01:34:49 PM PDT 24
Peak memory 281684 kb
Host smart-00530805-2777-48e6-9938-4fa22ae75431
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229659607 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.229659607
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.1212814016
Short name T979
Test name
Test status
Simulation time 9303787100 ps
CPU time 628.95 seconds
Started Jun 06 01:32:40 PM PDT 24
Finished Jun 06 01:43:09 PM PDT 24
Peak memory 309584 kb
Host smart-c6427bc8-482d-484f-9e32-f2e4fc9ad16e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212814016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.flash_ctrl_rw.1212814016
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.307991609
Short name T92
Test name
Test status
Simulation time 34845300 ps
CPU time 31.39 seconds
Started Jun 06 01:32:48 PM PDT 24
Finished Jun 06 01:33:22 PM PDT 24
Peak memory 267340 kb
Host smart-b9acb413-743a-46b3-b93c-687d24437897
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307991609 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.307991609
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_serr.1509697805
Short name T781
Test name
Test status
Simulation time 8853564600 ps
CPU time 543.97 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:41:41 PM PDT 24
Peak memory 312204 kb
Host smart-07f871a0-097b-4601-8c65-4648572488f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509697805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_s
err.1509697805
Directory /workspace/7.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.3532820584
Short name T623
Test name
Test status
Simulation time 9029275900 ps
CPU time 69.72 seconds
Started Jun 06 01:32:43 PM PDT 24
Finished Jun 06 01:33:54 PM PDT 24
Peak memory 259416 kb
Host smart-1c68cdf8-7003-4076-b06b-b2a56944a339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532820584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.3532820584
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.3816964048
Short name T384
Test name
Test status
Simulation time 25568600 ps
CPU time 100.05 seconds
Started Jun 06 01:32:31 PM PDT 24
Finished Jun 06 01:34:13 PM PDT 24
Peak memory 276760 kb
Host smart-9f47e269-d45c-4d3f-8215-89af8de4c240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816964048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.3816964048
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.3788613426
Short name T227
Test name
Test status
Simulation time 2400656600 ps
CPU time 200.39 seconds
Started Jun 06 01:32:36 PM PDT 24
Finished Jun 06 01:35:58 PM PDT 24
Peak memory 264668 kb
Host smart-319760d1-bab4-470d-ba9d-50c3dd81f338
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788613426 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.flash_ctrl_wo.3788613426
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.3611526321
Short name T926
Test name
Test status
Simulation time 38804600 ps
CPU time 16.06 seconds
Started Jun 06 01:37:04 PM PDT 24
Finished Jun 06 01:37:21 PM PDT 24
Peak memory 274728 kb
Host smart-a4a23cd4-2d79-4877-95e9-962e3ad65ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611526321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.3611526321
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.623637988
Short name T138
Test name
Test status
Simulation time 466009800 ps
CPU time 133.38 seconds
Started Jun 06 01:36:59 PM PDT 24
Finished Jun 06 01:39:13 PM PDT 24
Peak memory 259640 kb
Host smart-4ff86c41-0d89-4f96-801f-1b444c9dba78
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623637988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_ot
p_reset.623637988
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.1030251717
Short name T1083
Test name
Test status
Simulation time 13829400 ps
CPU time 13.44 seconds
Started Jun 06 01:37:04 PM PDT 24
Finished Jun 06 01:37:18 PM PDT 24
Peak memory 274784 kb
Host smart-5358eced-007c-4655-90f5-2ef7650469c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030251717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.1030251717
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.2839544697
Short name T732
Test name
Test status
Simulation time 74357400 ps
CPU time 135.34 seconds
Started Jun 06 01:37:00 PM PDT 24
Finished Jun 06 01:39:17 PM PDT 24
Peak memory 260728 kb
Host smart-fa2fa38b-c5d4-475b-a628-51f0f1541e8e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839544697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.2839544697
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.1191339922
Short name T632
Test name
Test status
Simulation time 50330000 ps
CPU time 15.95 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:37:19 PM PDT 24
Peak memory 274752 kb
Host smart-8cfe4b9d-5fee-4505-b083-b6be1e94335d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191339922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.1191339922
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.1348355415
Short name T662
Test name
Test status
Simulation time 40951000 ps
CPU time 112.45 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:38:55 PM PDT 24
Peak memory 264824 kb
Host smart-d3461abe-8b22-4ff6-8f9a-0bd1a3a9ee31
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348355415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.1348355415
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.3828536540
Short name T369
Test name
Test status
Simulation time 74258500 ps
CPU time 13.51 seconds
Started Jun 06 01:37:03 PM PDT 24
Finished Jun 06 01:37:18 PM PDT 24
Peak memory 274712 kb
Host smart-a42bb03d-eaf9-487e-912d-7c3783644c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828536540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.3828536540
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.1565433440
Short name T3
Test name
Test status
Simulation time 74940300 ps
CPU time 133.47 seconds
Started Jun 06 01:37:00 PM PDT 24
Finished Jun 06 01:39:14 PM PDT 24
Peak memory 260760 kb
Host smart-e6d987dc-57ce-43ca-8091-7342362e1ccd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565433440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.1565433440
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.1023673458
Short name T617
Test name
Test status
Simulation time 30725800 ps
CPU time 15.8 seconds
Started Jun 06 01:37:00 PM PDT 24
Finished Jun 06 01:37:17 PM PDT 24
Peak memory 274668 kb
Host smart-87539a60-83af-445e-ad69-b8ebdd72e2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023673458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.1023673458
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.1212654193
Short name T881
Test name
Test status
Simulation time 38595400 ps
CPU time 133.21 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:39:16 PM PDT 24
Peak memory 260800 kb
Host smart-23777309-b6f6-4ba2-a151-aa11611aa4d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212654193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.1212654193
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.3616902301
Short name T1037
Test name
Test status
Simulation time 53354200 ps
CPU time 13.63 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:37:16 PM PDT 24
Peak memory 283904 kb
Host smart-6d9ce1ff-544f-415c-89be-eb9afda1bbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616902301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.3616902301
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.2179591479
Short name T150
Test name
Test status
Simulation time 41007600 ps
CPU time 132.57 seconds
Started Jun 06 01:37:02 PM PDT 24
Finished Jun 06 01:39:16 PM PDT 24
Peak memory 259980 kb
Host smart-8e67673d-f6e0-4e53-b6d6-cd57bc1504b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179591479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.2179591479
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.3867983374
Short name T932
Test name
Test status
Simulation time 51173200 ps
CPU time 13.5 seconds
Started Jun 06 01:37:00 PM PDT 24
Finished Jun 06 01:37:15 PM PDT 24
Peak memory 283896 kb
Host smart-21eaa04a-5a64-478b-9cb4-8cb052d98162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867983374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.3867983374
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.2710002475
Short name T954
Test name
Test status
Simulation time 121508600 ps
CPU time 134.99 seconds
Started Jun 06 01:37:05 PM PDT 24
Finished Jun 06 01:39:21 PM PDT 24
Peak memory 259796 kb
Host smart-a107e058-f942-4809-9188-1bb0de6deeeb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710002475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.2710002475
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.4067449199
Short name T958
Test name
Test status
Simulation time 97087800 ps
CPU time 13.52 seconds
Started Jun 06 01:37:04 PM PDT 24
Finished Jun 06 01:37:18 PM PDT 24
Peak memory 274796 kb
Host smart-8c5af3c0-262a-4844-936c-ee2144fae6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067449199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.4067449199
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.978011399
Short name T576
Test name
Test status
Simulation time 139494400 ps
CPU time 131.74 seconds
Started Jun 06 01:37:01 PM PDT 24
Finished Jun 06 01:39:14 PM PDT 24
Peak memory 265260 kb
Host smart-45750659-b305-4161-aae0-29f0e32f1451
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978011399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_ot
p_reset.978011399
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.629812977
Short name T999
Test name
Test status
Simulation time 62451800 ps
CPU time 16 seconds
Started Jun 06 01:37:00 PM PDT 24
Finished Jun 06 01:37:18 PM PDT 24
Peak memory 274772 kb
Host smart-13d2e992-42ff-44f1-9c94-f08a11dde154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629812977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.629812977
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.519320274
Short name T144
Test name
Test status
Simulation time 39642500 ps
CPU time 112.53 seconds
Started Jun 06 01:37:02 PM PDT 24
Finished Jun 06 01:38:56 PM PDT 24
Peak memory 260764 kb
Host smart-459dca36-c593-4e1d-a337-e5ad428b11ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519320274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_ot
p_reset.519320274
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.1093511801
Short name T541
Test name
Test status
Simulation time 22597500 ps
CPU time 15.97 seconds
Started Jun 06 01:37:02 PM PDT 24
Finished Jun 06 01:37:19 PM PDT 24
Peak memory 274744 kb
Host smart-97a7ff79-8605-4ab4-bb9d-eb2c8bdb1369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093511801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.1093511801
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.639171967
Short name T860
Test name
Test status
Simulation time 41282400 ps
CPU time 131.69 seconds
Started Jun 06 01:37:03 PM PDT 24
Finished Jun 06 01:39:15 PM PDT 24
Peak memory 260016 kb
Host smart-1ae76ffe-4c10-4029-9a2b-31d1c067d067
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639171967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_ot
p_reset.639171967
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.3759722923
Short name T434
Test name
Test status
Simulation time 72378600 ps
CPU time 13.82 seconds
Started Jun 06 01:33:07 PM PDT 24
Finished Jun 06 01:33:21 PM PDT 24
Peak memory 257944 kb
Host smart-af715cc0-5b76-45d2-82b8-c33bd3b5ab4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759722923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3
759722923
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.4264924497
Short name T1096
Test name
Test status
Simulation time 24971200 ps
CPU time 15.64 seconds
Started Jun 06 01:32:53 PM PDT 24
Finished Jun 06 01:33:10 PM PDT 24
Peak memory 274844 kb
Host smart-b0ebab50-b8fd-4ca7-9e21-d6cdc9345675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264924497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.4264924497
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.3708923936
Short name T852
Test name
Test status
Simulation time 16508900 ps
CPU time 21.88 seconds
Started Jun 06 01:32:54 PM PDT 24
Finished Jun 06 01:33:17 PM PDT 24
Peak memory 265244 kb
Host smart-5e33b50f-2dc9-4921-a865-c405b41f1c9d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708923936 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.3708923936
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.4137656167
Short name T838
Test name
Test status
Simulation time 87110425000 ps
CPU time 2446.11 seconds
Started Jun 06 01:32:48 PM PDT 24
Finished Jun 06 02:13:36 PM PDT 24
Peak memory 262576 kb
Host smart-48c0582b-f547-4c1d-8a77-b04a51b7a57d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137656167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.4137656167
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.2985280264
Short name T905
Test name
Test status
Simulation time 1315120200 ps
CPU time 876.19 seconds
Started Jun 06 01:32:47 PM PDT 24
Finished Jun 06 01:47:25 PM PDT 24
Peak memory 273256 kb
Host smart-e4088a2e-327a-4a8f-a77f-3de8edde9707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985280264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.2985280264
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.575914361
Short name T62
Test name
Test status
Simulation time 135456300 ps
CPU time 23.83 seconds
Started Jun 06 01:32:47 PM PDT 24
Finished Jun 06 01:33:13 PM PDT 24
Peak memory 263404 kb
Host smart-63d1dc15-cd3f-44b0-adea-150bd0eca432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575914361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.575914361
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3198886208
Short name T290
Test name
Test status
Simulation time 10038419900 ps
CPU time 55.81 seconds
Started Jun 06 01:32:53 PM PDT 24
Finished Jun 06 01:33:50 PM PDT 24
Peak memory 269556 kb
Host smart-ae84935d-c300-429f-b5a2-bf47bc6d307f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198886208 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3198886208
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.4289533187
Short name T344
Test name
Test status
Simulation time 107457000 ps
CPU time 13.37 seconds
Started Jun 06 01:32:56 PM PDT 24
Finished Jun 06 01:33:10 PM PDT 24
Peak memory 259104 kb
Host smart-69814479-ee4d-45cb-8c0c-f25770aae38f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289533187 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.4289533187
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.586894255
Short name T159
Test name
Test status
Simulation time 160187538700 ps
CPU time 941.92 seconds
Started Jun 06 01:32:46 PM PDT 24
Finished Jun 06 01:48:29 PM PDT 24
Peak memory 263452 kb
Host smart-a39903c6-ff66-4ea9-bc40-5ac5611206f3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586894255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 8.flash_ctrl_hw_rma_reset.586894255
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.1301353823
Short name T441
Test name
Test status
Simulation time 3193951100 ps
CPU time 207.86 seconds
Started Jun 06 01:32:49 PM PDT 24
Finished Jun 06 01:36:18 PM PDT 24
Peak memory 262908 kb
Host smart-d22b4601-a86f-4e85-8d55-60e9b4d6fe06
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301353823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.1301353823
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.672626308
Short name T268
Test name
Test status
Simulation time 1697632000 ps
CPU time 276.24 seconds
Started Jun 06 01:32:53 PM PDT 24
Finished Jun 06 01:37:31 PM PDT 24
Peak memory 290984 kb
Host smart-48b6b3cf-fb1d-4fdd-a20a-4300351b26be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672626308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_intr_rd.672626308
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.2781951436
Short name T919
Test name
Test status
Simulation time 37699020400 ps
CPU time 213.64 seconds
Started Jun 06 01:32:54 PM PDT 24
Finished Jun 06 01:36:29 PM PDT 24
Peak memory 292948 kb
Host smart-548e023e-6f22-46e1-9d0a-63c6d103e9e5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781951436 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.2781951436
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.1927342866
Short name T36
Test name
Test status
Simulation time 10702391000 ps
CPU time 76.41 seconds
Started Jun 06 01:32:54 PM PDT 24
Finished Jun 06 01:34:12 PM PDT 24
Peak memory 265264 kb
Host smart-8c34122e-b5db-4a74-8e2d-35a3d2026a86
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927342866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.1927342866
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.59160390
Short name T1022
Test name
Test status
Simulation time 67926480400 ps
CPU time 245.98 seconds
Started Jun 06 01:32:53 PM PDT 24
Finished Jun 06 01:37:01 PM PDT 24
Peak memory 260032 kb
Host smart-99dc9669-2cc8-439c-a6ae-b702af071a93
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591
60390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.59160390
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.3208866663
Short name T410
Test name
Test status
Simulation time 8639252000 ps
CPU time 68.41 seconds
Started Jun 06 01:32:55 PM PDT 24
Finished Jun 06 01:34:04 PM PDT 24
Peak memory 260328 kb
Host smart-22fa9a73-3625-4a64-9e21-4223a35647bb
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208866663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3208866663
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.680505815
Short name T530
Test name
Test status
Simulation time 48630900 ps
CPU time 13.57 seconds
Started Jun 06 01:32:55 PM PDT 24
Finished Jun 06 01:33:10 PM PDT 24
Peak memory 259536 kb
Host smart-3561240f-f77f-4be9-92e7-5f47b37808a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680505815 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.680505815
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.3926199349
Short name T589
Test name
Test status
Simulation time 6584246900 ps
CPU time 160.11 seconds
Started Jun 06 01:32:44 PM PDT 24
Finished Jun 06 01:35:26 PM PDT 24
Peak memory 265148 kb
Host smart-1b612391-6baa-4998-87f3-0dda95b01398
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926199349 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.3926199349
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.2360968139
Short name T146
Test name
Test status
Simulation time 480197200 ps
CPU time 111.73 seconds
Started Jun 06 01:32:49 PM PDT 24
Finished Jun 06 01:34:42 PM PDT 24
Peak memory 259704 kb
Host smart-70bd8168-0bb8-4e0a-83d2-41cdb14a23cd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360968139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.2360968139
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.1657782265
Short name T488
Test name
Test status
Simulation time 3563084500 ps
CPU time 355.42 seconds
Started Jun 06 01:32:45 PM PDT 24
Finished Jun 06 01:38:42 PM PDT 24
Peak memory 262776 kb
Host smart-d04a9bd1-292f-49a9-a196-cd118e3fef97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1657782265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.1657782265
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.348485641
Short name T849
Test name
Test status
Simulation time 22368400 ps
CPU time 13.71 seconds
Started Jun 06 01:32:56 PM PDT 24
Finished Jun 06 01:33:11 PM PDT 24
Peak memory 264988 kb
Host smart-635af278-5468-4d5b-9c33-1ef441a17482
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348485641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_rese
t.348485641
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.4224140872
Short name T1018
Test name
Test status
Simulation time 1483144100 ps
CPU time 532.45 seconds
Started Jun 06 01:32:47 PM PDT 24
Finished Jun 06 01:41:41 PM PDT 24
Peak memory 282852 kb
Host smart-60b4d1d3-5777-4eeb-ad2f-57858a9c3de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224140872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.4224140872
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.18037681
Short name T1049
Test name
Test status
Simulation time 523877600 ps
CPU time 36.13 seconds
Started Jun 06 01:32:53 PM PDT 24
Finished Jun 06 01:33:31 PM PDT 24
Peak memory 270060 kb
Host smart-58047dc7-14c7-4026-8b14-4916898b707c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18037681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_re_evict.18037681
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.1736889945
Short name T645
Test name
Test status
Simulation time 1055269300 ps
CPU time 109.08 seconds
Started Jun 06 01:32:56 PM PDT 24
Finished Jun 06 01:34:46 PM PDT 24
Peak memory 289888 kb
Host smart-8dc7acbd-17b1-46a4-89b4-371431e6cb90
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736889945 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_ro.1736889945
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.2944655147
Short name T718
Test name
Test status
Simulation time 7277535800 ps
CPU time 159.5 seconds
Started Jun 06 01:32:54 PM PDT 24
Finished Jun 06 01:35:35 PM PDT 24
Peak memory 282696 kb
Host smart-aeaeb36e-5e3b-4fca-ac1f-0fd2ae129331
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2944655147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2944655147
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.847563730
Short name T609
Test name
Test status
Simulation time 621639300 ps
CPU time 158.84 seconds
Started Jun 06 01:32:54 PM PDT 24
Finished Jun 06 01:35:34 PM PDT 24
Peak memory 281636 kb
Host smart-171d889a-6ea1-4ae9-beac-d9b204b536bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847563730 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.847563730
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.1348069884
Short name T778
Test name
Test status
Simulation time 6305012200 ps
CPU time 566.11 seconds
Started Jun 06 01:32:53 PM PDT 24
Finished Jun 06 01:42:20 PM PDT 24
Peak memory 314028 kb
Host smart-06eb4b96-fc6a-4213-bb72-4c787add1fcd
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348069884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.flash_ctrl_rw.1348069884
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.3701048667
Short name T205
Test name
Test status
Simulation time 4743993900 ps
CPU time 760.95 seconds
Started Jun 06 01:32:53 PM PDT 24
Finished Jun 06 01:45:35 PM PDT 24
Peak memory 334444 kb
Host smart-ac739dd8-32ca-4060-94e0-1a20c1ef6a6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701048667 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_rw_derr.3701048667
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.87011365
Short name T579
Test name
Test status
Simulation time 40708800 ps
CPU time 31.39 seconds
Started Jun 06 01:32:55 PM PDT 24
Finished Jun 06 01:33:27 PM PDT 24
Peak memory 275040 kb
Host smart-ecf1f772-96fd-4a9a-ba0c-5f7bfe79f8bb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87011365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_rw_evict.87011365
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.1089008608
Short name T885
Test name
Test status
Simulation time 153700200 ps
CPU time 31.77 seconds
Started Jun 06 01:32:54 PM PDT 24
Finished Jun 06 01:33:27 PM PDT 24
Peak memory 267356 kb
Host smart-5aae575b-efe8-4446-a545-0b270c2b8050
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089008608 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.1089008608
Directory /workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.168060583
Short name T405
Test name
Test status
Simulation time 1156844000 ps
CPU time 66.69 seconds
Started Jun 06 01:32:53 PM PDT 24
Finished Jun 06 01:34:01 PM PDT 24
Peak memory 263716 kb
Host smart-bd1d867c-0a38-42cb-8b6e-8418eb3770c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168060583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.168060583
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.2805692226
Short name T388
Test name
Test status
Simulation time 563889000 ps
CPU time 99.91 seconds
Started Jun 06 01:32:51 PM PDT 24
Finished Jun 06 01:34:32 PM PDT 24
Peak memory 276052 kb
Host smart-bbc7b96c-5217-4db5-ab7c-d7eb8be66f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805692226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.2805692226
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.1590368973
Short name T928
Test name
Test status
Simulation time 4766561100 ps
CPU time 196.96 seconds
Started Jun 06 01:32:54 PM PDT 24
Finished Jun 06 01:36:12 PM PDT 24
Peak memory 265272 kb
Host smart-499dcf33-0918-4511-b1a2-023926cbd5f9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590368973 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.flash_ctrl_wo.1590368973
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.564421429
Short name T1059
Test name
Test status
Simulation time 21363900 ps
CPU time 14.16 seconds
Started Jun 06 01:33:42 PM PDT 24
Finished Jun 06 01:33:57 PM PDT 24
Peak memory 264748 kb
Host smart-790ff9f2-3ef4-45ae-85d0-408a2197ab61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564421429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.564421429
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.1573090574
Short name T674
Test name
Test status
Simulation time 29662400 ps
CPU time 15.8 seconds
Started Jun 06 01:33:41 PM PDT 24
Finished Jun 06 01:33:58 PM PDT 24
Peak memory 274796 kb
Host smart-43d17c61-70c6-4e82-984d-cf3d30fcb2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573090574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.1573090574
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.1209009714
Short name T834
Test name
Test status
Simulation time 11481300 ps
CPU time 21.8 seconds
Started Jun 06 01:33:43 PM PDT 24
Finished Jun 06 01:34:06 PM PDT 24
Peak memory 265352 kb
Host smart-376de4fa-42f9-41a0-804e-340171c80596
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209009714 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.1209009714
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.3365330736
Short name T735
Test name
Test status
Simulation time 17131697200 ps
CPU time 2401.69 seconds
Started Jun 06 01:33:09 PM PDT 24
Finished Jun 06 02:13:12 PM PDT 24
Peak memory 262400 kb
Host smart-7644d735-81de-41ac-9a6d-a3dca195ece4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365330736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.3365330736
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.2681854101
Short name T294
Test name
Test status
Simulation time 2154386500 ps
CPU time 1005.07 seconds
Started Jun 06 01:33:06 PM PDT 24
Finished Jun 06 01:49:52 PM PDT 24
Peak memory 273400 kb
Host smart-4f4ea4f3-13e5-4412-8212-c0d3f2660a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681854101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.2681854101
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.14020620
Short name T634
Test name
Test status
Simulation time 112437700 ps
CPU time 22.99 seconds
Started Jun 06 01:33:07 PM PDT 24
Finished Jun 06 01:33:31 PM PDT 24
Peak memory 263296 kb
Host smart-e921fe8e-a31c-44db-bb72-b164186eb8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14020620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.14020620
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.4273439446
Short name T131
Test name
Test status
Simulation time 10093612700 ps
CPU time 58.01 seconds
Started Jun 06 01:33:41 PM PDT 24
Finished Jun 06 01:34:40 PM PDT 24
Peak memory 265152 kb
Host smart-950adfb0-5de0-42be-83bd-4eab1c636c4c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273439446 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.4273439446
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.1957131354
Short name T345
Test name
Test status
Simulation time 16048600 ps
CPU time 13.79 seconds
Started Jun 06 01:33:41 PM PDT 24
Finished Jun 06 01:33:56 PM PDT 24
Peak memory 264584 kb
Host smart-1869b8cf-a26a-42c0-9941-b794394d43d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957131354 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.1957131354
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.2532614557
Short name T1029
Test name
Test status
Simulation time 40121466700 ps
CPU time 842.18 seconds
Started Jun 06 01:33:09 PM PDT 24
Finished Jun 06 01:47:12 PM PDT 24
Peak memory 263716 kb
Host smart-da393edf-6062-4cfb-912d-65543871fec9
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532614557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.2532614557
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.3099946806
Short name T683
Test name
Test status
Simulation time 5421315100 ps
CPU time 205.68 seconds
Started Jun 06 01:33:07 PM PDT 24
Finished Jun 06 01:36:34 PM PDT 24
Peak memory 291116 kb
Host smart-a82852d7-1fe5-4959-aebb-2d6791dc6b2d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099946806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.3099946806
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3315908562
Short name T910
Test name
Test status
Simulation time 12838670300 ps
CPU time 427.27 seconds
Started Jun 06 01:33:08 PM PDT 24
Finished Jun 06 01:40:16 PM PDT 24
Peak memory 284480 kb
Host smart-74f9b27d-98b3-4ec7-b489-51a7a612f4d1
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315908562 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.3315908562
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.3377042403
Short name T908
Test name
Test status
Simulation time 6014578800 ps
CPU time 70.98 seconds
Started Jun 06 01:33:09 PM PDT 24
Finished Jun 06 01:34:21 PM PDT 24
Peak memory 260224 kb
Host smart-29e4c443-6b16-4b36-8a6f-70f3b2658e4e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377042403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.3377042403
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1190261552
Short name T1007
Test name
Test status
Simulation time 68005236800 ps
CPU time 161.22 seconds
Started Jun 06 01:33:09 PM PDT 24
Finished Jun 06 01:35:51 PM PDT 24
Peak memory 259640 kb
Host smart-6ae2aa36-beb3-4ef7-a10d-1be9126514b6
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119
0261552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.1190261552
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.2216763876
Short name T411
Test name
Test status
Simulation time 7580892400 ps
CPU time 64.31 seconds
Started Jun 06 01:33:08 PM PDT 24
Finished Jun 06 01:34:13 PM PDT 24
Peak memory 263200 kb
Host smart-b2b27ffe-a720-44e1-900e-e974a6c91e11
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216763876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2216763876
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.2173153518
Short name T513
Test name
Test status
Simulation time 15932000 ps
CPU time 14.06 seconds
Started Jun 06 01:33:40 PM PDT 24
Finished Jun 06 01:33:55 PM PDT 24
Peak memory 264532 kb
Host smart-9f12527b-245e-4cf4-bd97-abd7d1d0c0b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173153518 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.2173153518
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.762462247
Short name T892
Test name
Test status
Simulation time 26336172100 ps
CPU time 233.78 seconds
Started Jun 06 01:33:08 PM PDT 24
Finished Jun 06 01:37:03 PM PDT 24
Peak memory 265100 kb
Host smart-944d99c4-1e8e-4252-9694-6d016931d066
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762462247 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 9.flash_ctrl_mp_regions.762462247
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.2434807611
Short name T556
Test name
Test status
Simulation time 233210500 ps
CPU time 131.96 seconds
Started Jun 06 01:33:08 PM PDT 24
Finished Jun 06 01:35:21 PM PDT 24
Peak memory 260008 kb
Host smart-11c92eaa-65a1-4892-a1de-d9587e873041
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434807611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot
p_reset.2434807611
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.2303101869
Short name T566
Test name
Test status
Simulation time 2740244400 ps
CPU time 473.12 seconds
Started Jun 06 01:33:08 PM PDT 24
Finished Jun 06 01:41:02 PM PDT 24
Peak memory 262832 kb
Host smart-523b6e77-1ddd-4760-82df-aa7c9ac34951
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2303101869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2303101869
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.18814872
Short name T132
Test name
Test status
Simulation time 20911200 ps
CPU time 13.6 seconds
Started Jun 06 01:33:08 PM PDT 24
Finished Jun 06 01:33:23 PM PDT 24
Peak memory 265016 kb
Host smart-90dac4a9-8c9e-4ba2-972c-ea974e919355
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18814872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_r
eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset
.18814872
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.1503852949
Short name T858
Test name
Test status
Simulation time 125799200 ps
CPU time 1046.19 seconds
Started Jun 06 01:33:08 PM PDT 24
Finished Jun 06 01:50:35 PM PDT 24
Peak memory 287156 kb
Host smart-d8b1d1d8-22f3-4299-acee-94dc9c5681ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503852949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.1503852949
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.700942183
Short name T274
Test name
Test status
Simulation time 301392400 ps
CPU time 36.71 seconds
Started Jun 06 01:33:43 PM PDT 24
Finished Jun 06 01:34:21 PM PDT 24
Peak memory 275660 kb
Host smart-9af33f9d-49fc-4b2c-9c00-56689b0a68ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700942183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_re_evict.700942183
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.2712032544
Short name T772
Test name
Test status
Simulation time 4293132800 ps
CPU time 122.73 seconds
Started Jun 06 01:33:06 PM PDT 24
Finished Jun 06 01:35:09 PM PDT 24
Peak memory 280744 kb
Host smart-d8c08c5d-b935-460f-a813-b25761068fc7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712032544 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_ro.2712032544
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.3199831237
Short name T600
Test name
Test status
Simulation time 12074067100 ps
CPU time 137.89 seconds
Started Jun 06 01:33:07 PM PDT 24
Finished Jun 06 01:35:25 PM PDT 24
Peak memory 294852 kb
Host smart-16cafc75-5e9a-45e6-9596-101089cd6685
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199831237 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.3199831237
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.1003379828
Short name T524
Test name
Test status
Simulation time 7757969400 ps
CPU time 581.08 seconds
Started Jun 06 01:33:07 PM PDT 24
Finished Jun 06 01:42:48 PM PDT 24
Peak memory 314096 kb
Host smart-8527e618-94ca-45cc-8fea-bd261686998d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003379828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.flash_ctrl_rw.1003379828
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.2000189867
Short name T638
Test name
Test status
Simulation time 41237300 ps
CPU time 30.91 seconds
Started Jun 06 01:33:08 PM PDT 24
Finished Jun 06 01:33:39 PM PDT 24
Peak memory 275272 kb
Host smart-e8a0ebfd-f1b7-44e9-8123-9d967d8a766a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000189867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.2000189867
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.3058218726
Short name T826
Test name
Test status
Simulation time 47648300 ps
CPU time 28.63 seconds
Started Jun 06 01:33:43 PM PDT 24
Finished Jun 06 01:34:13 PM PDT 24
Peak memory 275564 kb
Host smart-43e0ab80-4ac2-4efc-b50b-3019cc907311
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058218726 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.3058218726
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.1663864764
Short name T56
Test name
Test status
Simulation time 32987100 ps
CPU time 99.33 seconds
Started Jun 06 01:33:13 PM PDT 24
Finished Jun 06 01:34:53 PM PDT 24
Peak memory 276964 kb
Host smart-21419181-bc5c-4a5c-b656-bbffb868f27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663864764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.1663864764
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.1923014632
Short name T671
Test name
Test status
Simulation time 7759489000 ps
CPU time 191.02 seconds
Started Jun 06 01:33:08 PM PDT 24
Finished Jun 06 01:36:20 PM PDT 24
Peak memory 259056 kb
Host smart-a86c95c6-eac0-4aaf-96e3-74658f3a26dc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923014632 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.flash_ctrl_wo.1923014632
Directory /workspace/9.flash_ctrl_wo/latest
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