Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	213447	1		T1	2		T2	2		T3	1
all_values[1]	213447	1		T1	2		T2	2		T3	1
all_values[2]	213447	1		T1	2		T2	2		T3	1
all_values[3]	213447	1		T1	2		T2	2		T3	1
all_values[4]	213447	1		T1	2		T2	2		T3	1
all_values[5]	213447	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	433175	1		T1	12		T2	12		T3	6
auto[1]	847507	1		T25	43056		T28	4688		T29	4336

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	627802	1		T1	7		T2	6		T3	4
auto[1]	652880	1		T1	5		T2	6		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	213290	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	157	1		T291	5		T364	6		T365	4
all_values[1]	auto[0]	auto[1]	213300	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	147	1		T364	3		T365	3		T366	6
all_values[2]	auto[0]	auto[0]	1583	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	46	1		T291	1		T364	1		T368	1
all_values[2]	auto[1]	auto[0]	211749	1		T25	10764		T28	1172		T29	1084
all_values[2]	auto[1]	auto[1]	69	1		T364	2		T365	2		T366	3
all_values[3]	auto[0]	auto[0]	1595	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	52	1		T291	2		T364	3		T365	3
all_values[3]	auto[1]	auto[0]	85413	1		T25	1794		T28	586		T29	542
all_values[3]	auto[1]	auto[1]	126387	1		T25	8970		T28	586		T29	542
all_values[4]	auto[0]	auto[0]	1124	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	521	1		T1	1		T2	1		T5	1
all_values[4]	auto[1]	auto[0]	113083	1		T25	8970		T28	586		T29	542
all_values[4]	auto[1]	auto[1]	98719	1		T25	1794		T28	586		T29	542
all_values[5]	auto[0]	auto[0]	1518	1		T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	146	1		T2	1		T5	1		T6	1
all_values[5]	auto[1]	auto[0]	211737	1		T25	10764		T28	1172		T29	1084
all_values[5]	auto[1]	auto[1]	46	1		T291	3		T364	3		T368	1