Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
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Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv



Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00
Crosses 16 0 16 100.00


Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
erase_cp 2 0 2 100.00 100 1 1 0
op_cp 4 0 4 100.00 100 1 1 0
op_evict_cp 5 0 5 100.00 100 1 1 0
part_cp 4 0 4 100.00 100 1 1 0


Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
op_part_cross 16 0 16 100.00 100 1 1 0


Summary for Variable erase_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for erase_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashErasePage] 236054 1 T1 791 T2 552 T5 1319
auto[FlashEraseBank] 264801 1 T1 734 T2 467 T4 5



Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for op_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashOpRead] 247442 1 T2 1019 T5 1450 T15 2
auto[FlashOpProgram] 233177 1 T1 1525 T4 5 T5 1615
auto[FlashOpErase] 16236 1 T15 1 T49 100 T17 184
auto[FlashOpInvalid] 4000 1 T49 200 T115 200 T53 200



Summary for Variable op_evict_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for op_evict_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
op[FlashOpRead] 247442 1 T2 1019 T5 1450 T15 2
op[FlashOpProgram] 233177 1 T1 1525 T4 5 T5 1615
op[FlashOpErase] 16236 1 T15 1 T49 100 T17 184
read_erase_read 632 1 T41 2 T31 35 T39 5
read_prog_read 790 1 T5 10 T42 6 T40 1



Summary for Variable part_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for part_cp

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashPartData] 362481 1 T1 1352 T2 776 T4 1
auto[FlashPartInfo] 134655 1 T1 168 T2 240 T4 4
auto[FlashPartInfo1] 928 1 T2 2 T5 5 T6 3
auto[FlashPartInfo2] 2791 1 T1 5 T2 1 T5 6



Summary for Cross op_part_cross

Samples crossed: part_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for op_part_cross

Bins
part_cpop_cpCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashPartData] auto[FlashOpRead] 178817 1 T2 776 T5 1085 T15 2
auto[FlashPartData] auto[FlashOpProgram] 175927 1 T1 1352 T4 1 T5 1469
auto[FlashPartData] auto[FlashOpErase] 3817 1 T15 1 T49 97 T41 2
auto[FlashPartData] auto[FlashOpInvalid] 3920 1 T49 194 T115 192 T53 200
auto[FlashPartInfo] auto[FlashOpRead] 65988 1 T2 240 T5 358 T6 194
auto[FlashPartInfo] auto[FlashOpProgram] 56223 1 T1 168 T4 4 T5 142
auto[FlashPartInfo] auto[FlashOpErase] 12372 1 T49 3 T17 184 T47 363
auto[FlashPartInfo] auto[FlashOpInvalid] 72 1 T49 6 T115 8 T117 8
auto[FlashPartInfo1] auto[FlashOpRead] 758 1 T2 2 T5 5 T6 3
auto[FlashPartInfo1] auto[FlashOpProgram] 163 1 T118 1 T56 32 T87 1
auto[FlashPartInfo1] auto[FlashOpErase] 5 1 T87 1 T460 1 T461 3
auto[FlashPartInfo1] auto[FlashOpInvalid] 2 1 T87 2 - - - -
auto[FlashPartInfo2] auto[FlashOpRead] 1879 1 T2 1 T5 2 T6 8
auto[FlashPartInfo2] auto[FlashOpProgram] 864 1 T1 5 T5 4 T42 11
auto[FlashPartInfo2] auto[FlashOpErase] 42 1 T41 1 T462 1 T136 1
auto[FlashPartInfo2] auto[FlashOpInvalid] 6 1 T462 2 T463 2 T464 2

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