Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.10	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	5	27	84.38

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	5	27	84.38	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31151	1		T15	4		T49	400		T17	372
auto[1]	16	1		T372	2		T313	1		T228	2
auto[2]	47	1		T373	1		T176	8		T96	1
auto[3]	52	1		T26	1		T27	2		T223	2

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7812	1		T15	1		T49	100		T17	93
evic_idx[1]	7818	1		T15	1		T49	100		T17	93
evic_idx[2]	7821	1		T15	1		T49	100		T17	93
evic_idx[3]	7815	1		T15	1		T49	100		T17	93

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30237	1		T15	4		T49	400		T17	372
evic_op[2]	349	1		T26	1		T35	4		T27	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	5	27	84.38	5

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[1]]	[auto[1]]	0	1	1
[evic_idx[0]]	[evic_op[2]]	[auto[2]]	0	1	1
[evic_idx[1] , evic_idx[2]]	[evic_op[1]]	[auto[1]]	--	--	2
[evic_idx[3]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7551	1		T15	1		T49	100		T17	93
evic_idx[0]	evic_op[1]	auto[2]	5	1		T374	5		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	2	1		T375	2		-	-		-	-
evic_idx[0]	evic_op[2]	auto[0]	72	1		T35	1		T55	4		T78	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T376	1		T377	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	10	1		T26	1		T27	1		T223	1
evic_idx[1]	evic_op[1]	auto[0]	7550	1		T15	1		T49	100		T17	93
evic_idx[1]	evic_op[1]	auto[2]	5	1		T374	5		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	4	1		T378	1		T379	1		T375	2
evic_idx[1]	evic_op[2]	auto[0]	74	1		T35	1		T55	4		T118	1
evic_idx[1]	evic_op[2]	auto[1]	5	1		T120	1		T319	1		T376	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T373	1		T96	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	8	1		T27	1		T380	1		T381	1
evic_idx[2]	evic_op[1]	auto[0]	7552	1		T15	1		T49	100		T17	93
evic_idx[2]	evic_op[1]	auto[2]	5	1		T374	5		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	3	1		T379	1		T375	2		-	-
evic_idx[2]	evic_op[2]	auto[0]	71	1		T35	1		T55	4		T197	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T372	1		T228	1		T382	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T383	1		T384	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	14	1		T309	1		T385	1		T380	1
evic_idx[3]	evic_op[1]	auto[0]	7552	1		T15	1		T49	100		T17	93
evic_idx[3]	evic_op[1]	auto[1]	1	1		T226	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	4	1		T374	4		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	3	1		T379	1		T375	2		-	-
evic_idx[3]	evic_op[2]	auto[0]	73	1		T35	1		T55	4		T118	1
evic_idx[3]	evic_op[2]	auto[1]	4	1		T372	1		T313	1		T228	1
evic_idx[3]	evic_op[2]	auto[3]	8	1		T223	1		T225	1		T386	1