Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	4	14	77.78

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	1	14	93.33	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	1	14	93.33

User Defined Bins for rd_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
rd_lvl[1]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[2]	2576	1		T312	2576		-	-		-	-
rd_lvl[3]	7409	1		T25	4658		T312	2082		T355	669
rd_lvl[4]	25937	1		T25	4312		T356	260		T312	1120
rd_lvl[5]	8953	1		T357	179		T358	1054		T356	56
rd_lvl[6]	9573	1		T128	616		T357	55		T358	290
rd_lvl[7]	12345	1		T239	481		T128	286		T359	1836
rd_lvl[8]	15776	1		T239	215		T240	2982		T128	70
rd_lvl[9]	4727	1		T29	339		T239	221		T240	518
rd_lvl[10]	4537	1		T29	193		T239	203		T360	898
rd_lvl[11]	3574	1		T357	1		T98	498		T358	4
rd_lvl[12]	10138	1		T29	10		T230	27		T98	1046
rd_lvl[13]	2742	1		T244	748		T361	97		T362	314
rd_lvl[14]	4038	1		T28	336		T244	958		T363	1225
rd_lvl[15]	4597	1		T28	233		T38	297		T363	322