Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	213447	1		T1	2		T2	2		T3	1
all_pins[1]	213447	1		T1	2		T2	2		T3	1
all_pins[2]	213447	1		T1	2		T2	2		T3	1
all_pins[3]	213447	1		T1	2		T2	2		T3	1
all_pins[4]	213447	1		T1	2		T2	2		T3	1
all_pins[5]	213447	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1037456	1		T1	12		T2	12		T3	6
values[0x1]	243226	1		T25	11932		T28	1206		T29	1084
transitions[0x0=>0x1]	210405	1		T25	10764		T28	1172		T29	1084
transitions[0x1=>0x0]	210381	1		T25	10764		T28	1172		T29	1084

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	213290	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	157	1		T291	5		T364	6		T365	4
all_pins[0]	transitions[0x0=>0x1]	88	1		T291	5		T364	5		T365	4
all_pins[0]	transitions[0x1=>0x0]	78	1		T364	2		T365	3		T366	4
all_pins[1]	values[0x0]	213300	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	147	1		T364	3		T365	3		T366	6
all_pins[1]	transitions[0x0=>0x1]	107	1		T364	1		T365	1		T366	4
all_pins[1]	transitions[0x1=>0x0]	7685	1		T28	17		T38	278		T391	1129
all_pins[2]	values[0x0]	205722	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	7725	1		T28	17		T38	278		T391	1129
all_pins[2]	transitions[0x0=>0x1]	48	1		T364	1		T365	2		T366	2
all_pins[2]	transitions[0x1=>0x0]	117005	1		T25	8970		T28	569		T29	542
all_pins[3]	values[0x0]	88765	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	124682	1		T25	8970		T28	586		T29	542
all_pins[3]	transitions[0x0=>0x1]	99686	1		T25	7802		T28	569		T29	542
all_pins[3]	transitions[0x1=>0x0]	85473	1		T25	1794		T28	586		T29	542
all_pins[4]	values[0x0]	102978	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	110469	1		T25	2962		T28	603		T29	542
all_pins[4]	transitions[0x0=>0x1]	110457	1		T25	2962		T28	603		T29	542
all_pins[4]	transitions[0x1=>0x0]	34	1		T291	3		T364	3		T369	3
all_pins[5]	values[0x0]	213401	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	46	1		T291	3		T364	3		T368	1
all_pins[5]	transitions[0x0=>0x1]	19	1		T364	1		T369	2		T392	1
all_pins[5]	transitions[0x1=>0x0]	106	1		T291	2		T364	3		T365	3