Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	260	1		T291	4		T364	7		T365	7
all_values[1]	260	1		T291	4		T364	7		T365	7
all_values[2]	260	1		T291	4		T364	7		T365	7
all_values[3]	260	1		T291	4		T364	7		T365	7
all_values[4]	260	1		T291	4		T364	7		T365	7
all_values[5]	260	1		T291	4		T364	7		T365	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	848	1		T291	12		T364	18		T365	24
auto[1]	712	1		T291	12		T364	24		T365	18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	506	1		T291	8		T364	12		T365	13
auto[1]	1054	1		T291	16		T364	30		T365	29

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	919	1		T291	15		T364	25		T365	23
auto[1]	641	1		T291	9		T364	17		T365	19

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	85	1		T364	2		T365	2		T366	3
all_values[0]	auto[0]	auto[1]	auto[1]	78	1		T291	3		T364	4		T365	2
all_values[0]	auto[1]	auto[0]	auto[1]	65	1		T365	2		T366	2		T367	2
all_values[0]	auto[1]	auto[1]	auto[1]	32	1		T291	1		T364	1		T365	1
all_values[1]	auto[0]	auto[0]	auto[1]	76	1		T291	3		T364	2		T365	2
all_values[1]	auto[0]	auto[1]	auto[1]	73	1		T364	1		T365	1		T366	4
all_values[1]	auto[1]	auto[0]	auto[1]	60	1		T291	1		T364	1		T365	2
all_values[1]	auto[1]	auto[1]	auto[1]	51	1		T364	3		T365	2		T366	2
all_values[2]	auto[0]	auto[0]	auto[0]	74	1		T291	2		T364	2		T366	3
all_values[2]	auto[0]	auto[1]	auto[0]	71	1		T291	1		T364	2		T365	5
all_values[2]	auto[1]	auto[0]	auto[1]	51	1		T366	1		T368	2		T369	1
all_values[2]	auto[1]	auto[1]	auto[1]	64	1		T291	1		T364	3		T365	2
all_values[3]	auto[0]	auto[0]	auto[0]	85	1		T291	2		T364	2		T365	3
all_values[3]	auto[0]	auto[1]	auto[0]	63	1		T365	1		T367	2		T368	1
all_values[3]	auto[1]	auto[0]	auto[1]	55	1		T291	2		T364	2		T365	3
all_values[3]	auto[1]	auto[1]	auto[1]	57	1		T364	3		T366	1		T367	1
all_values[4]	auto[0]	auto[0]	auto[0]	55	1		T291	2		T364	2		T365	2
all_values[4]	auto[0]	auto[0]	auto[1]	32	1		T365	1		T366	3		T369	1
all_values[4]	auto[0]	auto[1]	auto[0]	49	1		T291	1		T364	3		T367	1
all_values[4]	auto[0]	auto[1]	auto[1]	27	1		T364	1		T368	2		T370	1
all_values[4]	auto[1]	auto[0]	auto[1]	55	1		T365	3		T366	4		T368	1
all_values[4]	auto[1]	auto[1]	auto[1]	42	1		T291	1		T364	1		T365	1
all_values[5]	auto[0]	auto[0]	auto[0]	60	1		T364	1		T366	1		T367	1
all_values[5]	auto[0]	auto[0]	auto[1]	27	1		T364	1		T365	2		T368	1
all_values[5]	auto[0]	auto[1]	auto[0]	49	1		T365	2		T366	2		T367	3
all_values[5]	auto[0]	auto[1]	auto[1]	15	1		T291	1		T364	2		T371	1
all_values[5]	auto[1]	auto[0]	auto[1]	68	1		T364	3		T365	2		T366	3
all_values[5]	auto[1]	auto[1]	auto[1]	41	1		T291	3		T365	1		T366	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal