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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.28 95.71 93.87 97.54 92.52 98.14 98.16 98.00


Total test records in report: 1245
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T1077 /workspace/coverage/default/36.flash_ctrl_intr_rd.3626913347 Jun 07 07:06:30 PM PDT 24 Jun 07 07:09:45 PM PDT 24 5761149700 ps
T1078 /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.3199197973 Jun 07 07:02:51 PM PDT 24 Jun 07 07:04:08 PM PDT 24 1369279000 ps
T1079 /workspace/coverage/default/47.flash_ctrl_sec_info_access.600382884 Jun 07 07:07:11 PM PDT 24 Jun 07 07:08:25 PM PDT 24 1907773400 ps
T1080 /workspace/coverage/default/22.flash_ctrl_rw_evict.105597227 Jun 07 07:05:10 PM PDT 24 Jun 07 07:05:42 PM PDT 24 30352800 ps
T1081 /workspace/coverage/default/0.flash_ctrl_derr_detect.282498430 Jun 07 06:58:45 PM PDT 24 Jun 07 07:00:28 PM PDT 24 141053100 ps
T1082 /workspace/coverage/default/6.flash_ctrl_alert_test.2177109542 Jun 07 07:01:40 PM PDT 24 Jun 07 07:01:55 PM PDT 24 116391400 ps
T1083 /workspace/coverage/default/34.flash_ctrl_alert_test.1508036482 Jun 07 07:06:20 PM PDT 24 Jun 07 07:06:35 PM PDT 24 174925500 ps
T1084 /workspace/coverage/default/18.flash_ctrl_otp_reset.3555231343 Jun 07 07:04:33 PM PDT 24 Jun 07 07:06:45 PM PDT 24 45013900 ps
T1085 /workspace/coverage/default/4.flash_ctrl_error_prog_win.3951236294 Jun 07 07:00:49 PM PDT 24 Jun 07 07:13:43 PM PDT 24 2776309800 ps
T1086 /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.3830357601 Jun 07 07:04:54 PM PDT 24 Jun 07 07:06:39 PM PDT 24 25358478500 ps
T1087 /workspace/coverage/default/4.flash_ctrl_fs_sup.168763286 Jun 07 07:00:55 PM PDT 24 Jun 07 07:01:36 PM PDT 24 330892200 ps
T355 /workspace/coverage/default/23.flash_ctrl_intr_rd.1020713602 Jun 07 07:05:12 PM PDT 24 Jun 07 07:08:59 PM PDT 24 2863059800 ps
T1088 /workspace/coverage/default/76.flash_ctrl_otp_reset.1858872125 Jun 07 07:07:46 PM PDT 24 Jun 07 07:10:01 PM PDT 24 256428600 ps
T1089 /workspace/coverage/default/74.flash_ctrl_otp_reset.60836676 Jun 07 07:07:41 PM PDT 24 Jun 07 07:09:30 PM PDT 24 132283800 ps
T1090 /workspace/coverage/default/31.flash_ctrl_connect.1942481715 Jun 07 07:06:05 PM PDT 24 Jun 07 07:06:23 PM PDT 24 27668500 ps
T1091 /workspace/coverage/default/27.flash_ctrl_connect.1638289596 Jun 07 07:05:38 PM PDT 24 Jun 07 07:05:54 PM PDT 24 39890800 ps
T1092 /workspace/coverage/default/17.flash_ctrl_alert_test.3924305563 Jun 07 07:04:24 PM PDT 24 Jun 07 07:04:39 PM PDT 24 110010300 ps
T1093 /workspace/coverage/default/29.flash_ctrl_otp_reset.3197914790 Jun 07 07:05:52 PM PDT 24 Jun 07 07:08:07 PM PDT 24 163848800 ps
T1094 /workspace/coverage/default/26.flash_ctrl_smoke.1231253008 Jun 07 07:05:22 PM PDT 24 Jun 07 07:08:36 PM PDT 24 101227100 ps
T1095 /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.3278039424 Jun 07 07:07:05 PM PDT 24 Jun 07 07:08:17 PM PDT 24 2069666500 ps
T1096 /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2047475205 Jun 07 07:04:01 PM PDT 24 Jun 07 07:06:05 PM PDT 24 10012072700 ps
T1097 /workspace/coverage/default/22.flash_ctrl_intr_rd.2571320006 Jun 07 07:05:10 PM PDT 24 Jun 07 07:07:54 PM PDT 24 2386094500 ps
T1098 /workspace/coverage/default/44.flash_ctrl_smoke.635144196 Jun 07 07:06:57 PM PDT 24 Jun 07 07:09:24 PM PDT 24 698197500 ps
T1099 /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.2006008185 Jun 07 07:05:22 PM PDT 24 Jun 07 07:05:54 PM PDT 24 29763100 ps
T1100 /workspace/coverage/default/33.flash_ctrl_intr_rd.682885082 Jun 07 07:06:11 PM PDT 24 Jun 07 07:08:16 PM PDT 24 6170012500 ps
T1101 /workspace/coverage/default/14.flash_ctrl_sec_info_access.1754605742 Jun 07 07:03:45 PM PDT 24 Jun 07 07:04:54 PM PDT 24 16412338200 ps
T1102 /workspace/coverage/default/14.flash_ctrl_phy_arb.3506336377 Jun 07 07:03:31 PM PDT 24 Jun 07 07:09:32 PM PDT 24 389450900 ps
T1103 /workspace/coverage/default/22.flash_ctrl_disable.19284070 Jun 07 07:05:08 PM PDT 24 Jun 07 07:05:31 PM PDT 24 38262900 ps
T1104 /workspace/coverage/default/17.flash_ctrl_invalid_op.3085018461 Jun 07 07:04:16 PM PDT 24 Jun 07 07:05:44 PM PDT 24 2155457200 ps
T1105 /workspace/coverage/default/16.flash_ctrl_phy_arb.3406734094 Jun 07 07:04:01 PM PDT 24 Jun 07 07:13:42 PM PDT 24 5533082400 ps
T69 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3546956487 Jun 07 07:43:37 PM PDT 24 Jun 07 07:58:46 PM PDT 24 1024226900 ps
T70 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2175148730 Jun 07 07:42:47 PM PDT 24 Jun 07 07:43:34 PM PDT 24 47463500 ps
T1106 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.4009798094 Jun 07 07:43:17 PM PDT 24 Jun 07 07:43:35 PM PDT 24 15865000 ps
T1107 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2360469475 Jun 07 07:42:39 PM PDT 24 Jun 07 07:42:56 PM PDT 24 22508700 ps
T291 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1428157278 Jun 07 07:43:35 PM PDT 24 Jun 07 07:43:50 PM PDT 24 25107300 ps
T71 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.14769581 Jun 07 07:43:17 PM PDT 24 Jun 07 07:43:36 PM PDT 24 165284800 ps
T1108 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.55126743 Jun 07 07:42:29 PM PDT 24 Jun 07 07:42:44 PM PDT 24 16843400 ps
T249 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2105170132 Jun 07 07:42:42 PM PDT 24 Jun 07 07:43:30 PM PDT 24 89128800 ps
T217 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3620041333 Jun 07 07:43:31 PM PDT 24 Jun 07 07:43:49 PM PDT 24 168605300 ps
T216 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2567268942 Jun 07 07:43:09 PM PDT 24 Jun 07 07:50:50 PM PDT 24 1645406700 ps
T1109 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1753934744 Jun 07 07:43:17 PM PDT 24 Jun 07 07:43:35 PM PDT 24 94296500 ps
T245 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.626521183 Jun 07 07:43:09 PM PDT 24 Jun 07 07:43:30 PM PDT 24 197195300 ps
T286 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2555742339 Jun 07 07:43:07 PM PDT 24 Jun 07 07:49:31 PM PDT 24 1471629200 ps
T364 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1007086406 Jun 07 07:43:35 PM PDT 24 Jun 07 07:43:51 PM PDT 24 27892100 ps
T246 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4178536524 Jun 07 07:42:54 PM PDT 24 Jun 07 07:43:14 PM PDT 24 41633500 ps
T275 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1287999051 Jun 07 07:43:28 PM PDT 24 Jun 07 07:43:47 PM PDT 24 32413300 ps
T252 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2796012846 Jun 07 07:42:56 PM PDT 24 Jun 07 07:43:14 PM PDT 24 36654800 ps
T365 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.663069117 Jun 07 07:43:06 PM PDT 24 Jun 07 07:43:21 PM PDT 24 52187700 ps
T1110 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2154605556 Jun 07 07:43:37 PM PDT 24 Jun 07 07:43:55 PM PDT 24 19565400 ps
T247 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1090328014 Jun 07 07:43:18 PM PDT 24 Jun 07 07:51:01 PM PDT 24 197339900 ps
T248 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2159634281 Jun 07 07:42:29 PM PDT 24 Jun 07 07:42:47 PM PDT 24 172492200 ps
T366 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3381239035 Jun 07 07:42:33 PM PDT 24 Jun 07 07:42:47 PM PDT 24 16335100 ps
T253 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.4282838055 Jun 07 07:43:09 PM PDT 24 Jun 07 07:43:26 PM PDT 24 67274900 ps
T254 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2234372209 Jun 07 07:42:46 PM PDT 24 Jun 07 07:43:06 PM PDT 24 205588800 ps
T1111 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.127020821 Jun 07 07:43:09 PM PDT 24 Jun 07 07:43:23 PM PDT 24 26835500 ps
T1112 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.4033262087 Jun 07 07:42:38 PM PDT 24 Jun 07 07:42:55 PM PDT 24 94795400 ps
T1113 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1877304135 Jun 07 07:43:05 PM PDT 24 Jun 07 07:43:19 PM PDT 24 20020900 ps
T367 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2991199648 Jun 07 07:43:44 PM PDT 24 Jun 07 07:43:59 PM PDT 24 14681100 ps
T1114 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2212058929 Jun 07 07:42:38 PM PDT 24 Jun 07 07:42:53 PM PDT 24 28953800 ps
T276 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.204323570 Jun 07 07:42:44 PM PDT 24 Jun 07 07:43:02 PM PDT 24 37321100 ps
T1115 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.238619697 Jun 07 07:42:31 PM PDT 24 Jun 07 07:42:49 PM PDT 24 12140000 ps
T1116 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3389699425 Jun 07 07:42:38 PM PDT 24 Jun 07 07:42:53 PM PDT 24 26041500 ps
T368 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.560855054 Jun 07 07:43:35 PM PDT 24 Jun 07 07:43:51 PM PDT 24 31019900 ps
T1117 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1239055391 Jun 07 07:42:39 PM PDT 24 Jun 07 07:42:55 PM PDT 24 15429400 ps
T370 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3826551732 Jun 07 07:43:06 PM PDT 24 Jun 07 07:43:21 PM PDT 24 109084100 ps
T371 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3858895747 Jun 07 07:43:38 PM PDT 24 Jun 07 07:43:54 PM PDT 24 15911000 ps
T258 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1634134607 Jun 07 07:42:28 PM PDT 24 Jun 07 07:42:43 PM PDT 24 40896200 ps
T1118 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1391827272 Jun 07 07:42:39 PM PDT 24 Jun 07 07:43:17 PM PDT 24 339584600 ps
T1119 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2707021593 Jun 07 07:43:19 PM PDT 24 Jun 07 07:43:36 PM PDT 24 39900100 ps
T259 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2383551430 Jun 07 07:42:48 PM PDT 24 Jun 07 07:43:02 PM PDT 24 24156400 ps
T1120 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.4178326826 Jun 07 07:42:30 PM PDT 24 Jun 07 07:42:44 PM PDT 24 23024600 ps
T277 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3985617791 Jun 07 07:43:16 PM PDT 24 Jun 07 07:43:37 PM PDT 24 61343700 ps
T255 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3692529985 Jun 07 07:43:06 PM PDT 24 Jun 07 07:43:24 PM PDT 24 34461100 ps
T256 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.241001040 Jun 07 07:42:57 PM PDT 24 Jun 07 07:43:19 PM PDT 24 753007300 ps
T257 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2841106395 Jun 07 07:42:36 PM PDT 24 Jun 07 07:42:56 PM PDT 24 424761300 ps
T369 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.59846629 Jun 07 07:43:48 PM PDT 24 Jun 07 07:44:03 PM PDT 24 31971200 ps
T297 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2670097664 Jun 07 07:42:57 PM PDT 24 Jun 07 07:57:52 PM PDT 24 713720800 ps
T332 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.4149897346 Jun 07 07:42:55 PM PDT 24 Jun 07 07:43:36 PM PDT 24 1631159800 ps
T392 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2967113860 Jun 07 07:43:34 PM PDT 24 Jun 07 07:43:48 PM PDT 24 17564800 ps
T278 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3613910980 Jun 07 07:42:38 PM PDT 24 Jun 07 07:42:57 PM PDT 24 1338215500 ps
T1121 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.132228405 Jun 07 07:43:17 PM PDT 24 Jun 07 07:43:36 PM PDT 24 47393000 ps
T279 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.83298849 Jun 07 07:43:18 PM PDT 24 Jun 07 07:43:36 PM PDT 24 40746600 ps
T333 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3707558091 Jun 07 07:43:21 PM PDT 24 Jun 07 07:43:40 PM PDT 24 132372600 ps
T394 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3028907960 Jun 07 07:42:56 PM PDT 24 Jun 07 07:49:20 PM PDT 24 1265842300 ps
T334 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.585229346 Jun 07 07:42:31 PM PDT 24 Jun 07 07:42:53 PM PDT 24 224648300 ps
T1122 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.164637192 Jun 07 07:42:56 PM PDT 24 Jun 07 07:43:11 PM PDT 24 40505800 ps
T1123 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.130476916 Jun 07 07:42:28 PM PDT 24 Jun 07 07:43:15 PM PDT 24 186498900 ps
T302 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3823291229 Jun 07 07:43:21 PM PDT 24 Jun 07 07:51:07 PM PDT 24 1587378900 ps
T290 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1146716176 Jun 07 07:43:17 PM PDT 24 Jun 07 07:43:35 PM PDT 24 75865600 ps
T1124 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1186081698 Jun 07 07:43:09 PM PDT 24 Jun 07 07:43:23 PM PDT 24 51894400 ps
T1125 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.384532379 Jun 07 07:43:27 PM PDT 24 Jun 07 07:43:42 PM PDT 24 80835600 ps
T1126 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3381341267 Jun 07 07:42:40 PM PDT 24 Jun 07 07:43:01 PM PDT 24 118174800 ps
T301 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1266309325 Jun 07 07:42:45 PM PDT 24 Jun 07 07:57:56 PM PDT 24 8560801900 ps
T1127 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1673689265 Jun 07 07:42:56 PM PDT 24 Jun 07 07:43:12 PM PDT 24 21605700 ps
T335 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1563383949 Jun 07 07:42:31 PM PDT 24 Jun 07 07:42:50 PM PDT 24 451774000 ps
T1128 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.129745956 Jun 07 07:42:47 PM PDT 24 Jun 07 07:43:02 PM PDT 24 17188400 ps
T336 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.289180930 Jun 07 07:42:27 PM PDT 24 Jun 07 07:43:30 PM PDT 24 1597063500 ps
T1129 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.122395807 Jun 07 07:42:28 PM PDT 24 Jun 07 07:42:47 PM PDT 24 358457600 ps
T1130 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.451772706 Jun 07 07:43:39 PM PDT 24 Jun 07 07:43:57 PM PDT 24 17983400 ps
T299 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1968861857 Jun 07 07:42:57 PM PDT 24 Jun 07 07:43:17 PM PDT 24 205441700 ps
T296 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2008672587 Jun 07 07:43:37 PM PDT 24 Jun 07 07:43:56 PM PDT 24 54339900 ps
T1131 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.400126444 Jun 07 07:43:34 PM PDT 24 Jun 07 07:43:49 PM PDT 24 17164200 ps
T337 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1202665047 Jun 07 07:43:38 PM PDT 24 Jun 07 07:44:15 PM PDT 24 191270700 ps
T1132 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.161851212 Jun 07 07:43:07 PM PDT 24 Jun 07 07:43:22 PM PDT 24 170977500 ps
T1133 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3587779412 Jun 07 07:43:07 PM PDT 24 Jun 07 07:43:41 PM PDT 24 122005300 ps
T293 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3592155576 Jun 07 07:43:07 PM PDT 24 Jun 07 07:43:25 PM PDT 24 61904700 ps
T1134 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1197719840 Jun 07 07:43:47 PM PDT 24 Jun 07 07:44:02 PM PDT 24 15647100 ps
T338 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3603909752 Jun 07 07:42:45 PM PDT 24 Jun 07 07:43:07 PM PDT 24 205704200 ps
T1135 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1488045123 Jun 07 07:43:06 PM PDT 24 Jun 07 07:43:23 PM PDT 24 127783500 ps
T1136 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3267372039 Jun 07 07:42:47 PM PDT 24 Jun 07 07:43:55 PM PDT 24 9323969400 ps
T298 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4251143085 Jun 07 07:43:29 PM PDT 24 Jun 07 07:43:48 PM PDT 24 71328400 ps
T288 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4218058567 Jun 07 07:43:18 PM PDT 24 Jun 07 07:43:38 PM PDT 24 100087200 ps
T1137 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3157248454 Jun 07 07:43:25 PM PDT 24 Jun 07 07:43:44 PM PDT 24 28725400 ps
T1138 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3516175935 Jun 07 07:43:15 PM PDT 24 Jun 07 07:43:30 PM PDT 24 20700600 ps
T1139 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1329524081 Jun 07 07:43:28 PM PDT 24 Jun 07 07:43:45 PM PDT 24 61270500 ps
T1140 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3728105347 Jun 07 07:43:21 PM PDT 24 Jun 07 07:43:43 PM PDT 24 124771000 ps
T1141 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.980592818 Jun 07 07:43:25 PM PDT 24 Jun 07 07:43:40 PM PDT 24 22407500 ps
T1142 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1552000306 Jun 07 07:43:05 PM PDT 24 Jun 07 07:43:20 PM PDT 24 28838300 ps
T1143 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.380658463 Jun 07 07:43:09 PM PDT 24 Jun 07 07:43:26 PM PDT 24 25495300 ps
T400 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2034092753 Jun 07 07:42:36 PM PDT 24 Jun 07 07:57:39 PM PDT 24 2697366400 ps
T1144 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4089331860 Jun 07 07:43:25 PM PDT 24 Jun 07 07:43:41 PM PDT 24 30642000 ps
T1145 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1350410977 Jun 07 07:43:35 PM PDT 24 Jun 07 07:43:51 PM PDT 24 14460300 ps
T1146 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3910914823 Jun 07 07:43:50 PM PDT 24 Jun 07 07:44:06 PM PDT 24 32074900 ps
T1147 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.769965221 Jun 07 07:43:16 PM PDT 24 Jun 07 07:43:32 PM PDT 24 83293500 ps
T295 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2530273794 Jun 07 07:43:08 PM PDT 24 Jun 07 07:43:29 PM PDT 24 56960700 ps
T1148 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1860559879 Jun 07 07:42:31 PM PDT 24 Jun 07 07:43:14 PM PDT 24 659218200 ps
T1149 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1804137891 Jun 07 07:43:07 PM PDT 24 Jun 07 07:43:22 PM PDT 24 105262800 ps
T1150 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1028308536 Jun 07 07:42:57 PM PDT 24 Jun 07 07:43:27 PM PDT 24 228641400 ps
T399 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.4281404835 Jun 07 07:43:09 PM PDT 24 Jun 07 07:50:51 PM PDT 24 1151168000 ps
T1151 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1462097596 Jun 07 07:43:16 PM PDT 24 Jun 07 07:43:31 PM PDT 24 12186400 ps
T1152 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3079420651 Jun 07 07:42:31 PM PDT 24 Jun 07 07:42:45 PM PDT 24 51458400 ps
T1153 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.865747283 Jun 07 07:43:27 PM PDT 24 Jun 07 07:43:46 PM PDT 24 50457400 ps
T1154 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3672035635 Jun 07 07:42:47 PM PDT 24 Jun 07 07:44:00 PM PDT 24 2772279800 ps
T1155 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1658092496 Jun 07 07:43:49 PM PDT 24 Jun 07 07:44:04 PM PDT 24 54867000 ps
T294 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.949970712 Jun 07 07:42:58 PM PDT 24 Jun 07 07:58:07 PM PDT 24 852043600 ps
T339 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3028409692 Jun 07 07:42:29 PM PDT 24 Jun 07 07:43:17 PM PDT 24 104002800 ps
T1156 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2939121523 Jun 07 07:43:07 PM PDT 24 Jun 07 07:43:43 PM PDT 24 514389800 ps
T1157 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.345570831 Jun 07 07:43:27 PM PDT 24 Jun 07 07:43:45 PM PDT 24 151423900 ps
T303 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3940964895 Jun 07 07:43:06 PM PDT 24 Jun 07 07:43:22 PM PDT 24 32494900 ps
T1158 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3521511586 Jun 07 07:43:08 PM PDT 24 Jun 07 07:43:25 PM PDT 24 11995500 ps
T289 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.89153634 Jun 07 07:42:29 PM PDT 24 Jun 07 07:42:49 PM PDT 24 53512400 ps
T1159 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2888474997 Jun 07 07:43:45 PM PDT 24 Jun 07 07:44:00 PM PDT 24 46155900 ps
T1160 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3303617376 Jun 07 07:43:16 PM PDT 24 Jun 07 07:43:31 PM PDT 24 43650400 ps
T1161 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2084843036 Jun 07 07:42:37 PM PDT 24 Jun 07 07:42:55 PM PDT 24 33303200 ps
T398 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3421444922 Jun 07 07:43:32 PM PDT 24 Jun 07 07:56:05 PM PDT 24 882456400 ps
T1162 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3849544968 Jun 07 07:42:47 PM PDT 24 Jun 07 07:43:01 PM PDT 24 16513700 ps
T1163 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2788367113 Jun 07 07:43:06 PM PDT 24 Jun 07 07:43:25 PM PDT 24 29516700 ps
T1164 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3370619237 Jun 07 07:42:56 PM PDT 24 Jun 07 07:43:11 PM PDT 24 53835200 ps
T1165 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2384401554 Jun 07 07:43:18 PM PDT 24 Jun 07 07:43:37 PM PDT 24 397097400 ps
T1166 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.507598406 Jun 07 07:43:35 PM PDT 24 Jun 07 07:43:55 PM PDT 24 27385900 ps
T1167 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.4161168547 Jun 07 07:43:10 PM PDT 24 Jun 07 07:43:26 PM PDT 24 37282200 ps
T1168 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.4173044283 Jun 07 07:42:58 PM PDT 24 Jun 07 07:44:03 PM PDT 24 1316948300 ps
T1169 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.4156010621 Jun 07 07:43:41 PM PDT 24 Jun 07 07:43:56 PM PDT 24 17097100 ps
T340 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1003341870 Jun 07 07:42:37 PM PDT 24 Jun 07 07:42:54 PM PDT 24 321309200 ps
T1170 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2733352348 Jun 07 07:43:41 PM PDT 24 Jun 07 07:43:56 PM PDT 24 43382300 ps
T1171 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.476552651 Jun 07 07:43:36 PM PDT 24 Jun 07 07:43:52 PM PDT 24 17263600 ps
T1172 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1905498400 Jun 07 07:43:35 PM PDT 24 Jun 07 07:43:51 PM PDT 24 44719200 ps
T1173 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1197075989 Jun 07 07:43:35 PM PDT 24 Jun 07 07:43:54 PM PDT 24 48317100 ps
T1174 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2149167624 Jun 07 07:42:58 PM PDT 24 Jun 07 07:43:13 PM PDT 24 48111500 ps
T1175 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2396889097 Jun 07 07:43:35 PM PDT 24 Jun 07 07:43:49 PM PDT 24 49128500 ps
T1176 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2279960112 Jun 07 07:43:20 PM PDT 24 Jun 07 07:43:39 PM PDT 24 242278000 ps
T1177 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1013255906 Jun 07 07:43:20 PM PDT 24 Jun 07 07:43:41 PM PDT 24 87504800 ps
T341 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.451648559 Jun 07 07:43:27 PM PDT 24 Jun 07 07:44:05 PM PDT 24 203983300 ps
T1178 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.869768000 Jun 07 07:42:57 PM PDT 24 Jun 07 07:43:16 PM PDT 24 81830600 ps
T1179 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2527565865 Jun 07 07:42:54 PM PDT 24 Jun 07 07:43:22 PM PDT 24 35802800 ps
T1180 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3100541287 Jun 07 07:42:39 PM PDT 24 Jun 07 07:43:20 PM PDT 24 7970062000 ps
T260 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.131245676 Jun 07 07:42:40 PM PDT 24 Jun 07 07:42:57 PM PDT 24 20436400 ps
T1181 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.4008994286 Jun 07 07:43:35 PM PDT 24 Jun 07 07:43:51 PM PDT 24 50744400 ps
T1182 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.531561282 Jun 07 07:43:49 PM PDT 24 Jun 07 07:44:05 PM PDT 24 47979200 ps
T1183 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2683133965 Jun 07 07:43:10 PM PDT 24 Jun 07 07:43:26 PM PDT 24 11646400 ps
T1184 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.242262535 Jun 07 07:43:07 PM PDT 24 Jun 07 07:43:42 PM PDT 24 58445600 ps
T1185 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3792696255 Jun 07 07:43:50 PM PDT 24 Jun 07 07:44:06 PM PDT 24 25708600 ps
T1186 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.317830560 Jun 07 07:43:36 PM PDT 24 Jun 07 07:43:52 PM PDT 24 14728100 ps
T1187 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2811356741 Jun 07 07:42:58 PM PDT 24 Jun 07 07:43:13 PM PDT 24 15033500 ps
T1188 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1482230107 Jun 07 07:43:44 PM PDT 24 Jun 07 07:43:59 PM PDT 24 56521300 ps
T1189 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2270664340 Jun 07 07:43:07 PM PDT 24 Jun 07 07:43:23 PM PDT 24 193501900 ps
T1190 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.753806389 Jun 07 07:43:21 PM PDT 24 Jun 07 07:43:41 PM PDT 24 95780400 ps
T402 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.30435192 Jun 07 07:43:18 PM PDT 24 Jun 07 07:56:04 PM PDT 24 854442600 ps
T292 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.356195302 Jun 07 07:43:39 PM PDT 24 Jun 07 07:44:00 PM PDT 24 108415700 ps
T1191 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3833766808 Jun 07 07:42:55 PM PDT 24 Jun 07 07:43:14 PM PDT 24 36981300 ps
T304 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.592794745 Jun 07 07:43:21 PM PDT 24 Jun 07 07:58:16 PM PDT 24 589176500 ps
T1192 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3137731568 Jun 07 07:43:19 PM PDT 24 Jun 07 07:43:40 PM PDT 24 98337800 ps
T1193 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3677567540 Jun 07 07:43:45 PM PDT 24 Jun 07 07:44:00 PM PDT 24 112258100 ps
T1194 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1325738124 Jun 07 07:42:36 PM PDT 24 Jun 07 07:43:20 PM PDT 24 655314100 ps
T1195 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3321639551 Jun 07 07:43:36 PM PDT 24 Jun 07 07:43:52 PM PDT 24 17302800 ps
T1196 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4030078773 Jun 07 07:43:40 PM PDT 24 Jun 07 07:43:57 PM PDT 24 66849700 ps
T1197 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2898848795 Jun 07 07:43:37 PM PDT 24 Jun 07 07:43:53 PM PDT 24 26861200 ps
T1198 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1049710070 Jun 07 07:42:37 PM PDT 24 Jun 07 07:42:52 PM PDT 24 17986800 ps
T1199 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3003506966 Jun 07 07:42:42 PM PDT 24 Jun 07 07:43:49 PM PDT 24 4910637600 ps
T1200 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1688495604 Jun 07 07:43:06 PM PDT 24 Jun 07 07:43:24 PM PDT 24 24351400 ps
T393 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4129079160 Jun 07 07:42:55 PM PDT 24 Jun 07 07:43:15 PM PDT 24 397338600 ps
T1201 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1726517509 Jun 07 07:42:55 PM PDT 24 Jun 07 07:43:09 PM PDT 24 70166700 ps
T1202 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1683611778 Jun 07 07:42:59 PM PDT 24 Jun 07 07:43:16 PM PDT 24 42132500 ps
T1203 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.917423870 Jun 07 07:43:08 PM PDT 24 Jun 07 07:43:31 PM PDT 24 2647127900 ps
T342 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.339212175 Jun 07 07:43:06 PM PDT 24 Jun 07 07:43:46 PM PDT 24 3511886600 ps
T1204 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2281505270 Jun 07 07:42:30 PM PDT 24 Jun 07 07:42:47 PM PDT 24 12071300 ps
T1205 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.950025432 Jun 07 07:43:45 PM PDT 24 Jun 07 07:44:00 PM PDT 24 112098500 ps
T396 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3591531680 Jun 07 07:43:07 PM PDT 24 Jun 07 07:50:47 PM PDT 24 3432777100 ps
T1206 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2904749259 Jun 07 07:42:57 PM PDT 24 Jun 07 07:43:12 PM PDT 24 13569500 ps
T1207 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3128870809 Jun 07 07:42:37 PM PDT 24 Jun 07 07:42:52 PM PDT 24 55174500 ps
T1208 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1474742170 Jun 07 07:43:40 PM PDT 24 Jun 07 07:43:56 PM PDT 24 57418700 ps
T1209 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.348155654 Jun 07 07:43:16 PM PDT 24 Jun 07 07:43:31 PM PDT 24 56485900 ps
T1210 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.575704159 Jun 07 07:42:37 PM PDT 24 Jun 07 07:42:57 PM PDT 24 55333200 ps
T1211 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2983024016 Jun 07 07:42:56 PM PDT 24 Jun 07 07:43:16 PM PDT 24 529977300 ps
T397 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2481002037 Jun 07 07:43:31 PM PDT 24 Jun 07 07:58:29 PM PDT 24 1372421000 ps
T300 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3212714504 Jun 07 07:42:41 PM PDT 24 Jun 07 07:43:03 PM PDT 24 157193100 ps
T1212 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3269936153 Jun 07 07:43:06 PM PDT 24 Jun 07 07:43:20 PM PDT 24 24947000 ps
T1213 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2246923460 Jun 07 07:42:28 PM PDT 24 Jun 07 07:42:43 PM PDT 24 55322800 ps
T403 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.910198946 Jun 07 07:42:31 PM PDT 24 Jun 07 07:50:13 PM PDT 24 536191800 ps
T261 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.23788972 Jun 07 07:42:32 PM PDT 24 Jun 07 07:42:47 PM PDT 24 17909500 ps
T1214 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.673266174 Jun 07 07:43:09 PM PDT 24 Jun 07 07:43:31 PM PDT 24 108042000 ps
T1215 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1369173043 Jun 07 07:42:29 PM PDT 24 Jun 07 07:42:47 PM PDT 24 59958200 ps
T1216 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1711960130 Jun 07 07:43:07 PM PDT 24 Jun 07 07:43:25 PM PDT 24 27945000 ps
T1217 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.902490719 Jun 07 07:43:07 PM PDT 24 Jun 07 07:43:24 PM PDT 24 36701200 ps
T1218 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1419116570 Jun 07 07:43:15 PM PDT 24 Jun 07 07:43:33 PM PDT 24 94560700 ps
T1219 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.950169462 Jun 07 07:42:37 PM PDT 24 Jun 07 07:42:59 PM PDT 24 65583400 ps
T401 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3657312244 Jun 07 07:42:38 PM PDT 24 Jun 07 07:49:05 PM PDT 24 176933400 ps
T1220 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3264913235 Jun 07 07:42:46 PM PDT 24 Jun 07 07:43:05 PM PDT 24 129969200 ps
T1221 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1077092871 Jun 07 07:43:07 PM PDT 24 Jun 07 07:43:25 PM PDT 24 21534900 ps
T1222 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3733886293 Jun 07 07:42:56 PM PDT 24 Jun 07 07:43:13 PM PDT 24 24260000 ps
T1223 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1889222825 Jun 07 07:42:57 PM PDT 24 Jun 07 07:43:14 PM PDT 24 15775100 ps
T1224 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3655487179 Jun 07 07:42:56 PM PDT 24 Jun 07 07:43:15 PM PDT 24 25729900 ps
T1225 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2083303590 Jun 07 07:42:30 PM PDT 24 Jun 07 07:42:48 PM PDT 24 30350000 ps
T1226 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1541334589 Jun 07 07:43:28 PM PDT 24 Jun 07 07:43:43 PM PDT 24 15578400 ps
T1227 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2657891856 Jun 07 07:43:17 PM PDT 24 Jun 07 07:43:35 PM PDT 24 23997700 ps
T1228 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.4155608942 Jun 07 07:43:35 PM PDT 24 Jun 07 07:43:54 PM PDT 24 115674600 ps
T1229 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3523690772 Jun 07 07:42:56 PM PDT 24 Jun 07 07:43:14 PM PDT 24 30977400 ps
T1230 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3334669003 Jun 07 07:43:05 PM PDT 24 Jun 07 07:43:22 PM PDT 24 15127100 ps
T1231 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.29475517 Jun 07 07:42:29 PM PDT 24 Jun 07 07:48:54 PM PDT 24 685328100 ps
T1232 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2212146255 Jun 07 07:43:38 PM PDT 24 Jun 07 07:43:56 PM PDT 24 95415100 ps
T1233 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.718642271 Jun 07 07:42:45 PM PDT 24 Jun 07 07:43:02 PM PDT 24 13342200 ps
T262 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2536900248 Jun 07 07:42:47 PM PDT 24 Jun 07 07:43:02 PM PDT 24 42171500 ps
T1234 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3798561916 Jun 07 07:43:50 PM PDT 24 Jun 07 07:44:06 PM PDT 24 80746900 ps
T1235 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1563911069 Jun 07 07:43:26 PM PDT 24 Jun 07 07:43:46 PM PDT 24 349463300 ps
T1236 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4000674172 Jun 07 07:42:59 PM PDT 24 Jun 07 07:43:20 PM PDT 24 106539400 ps
T1237 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3793742224 Jun 07 07:43:16 PM PDT 24 Jun 07 07:43:37 PM PDT 24 109776300 ps
T395 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2069185432 Jun 07 07:43:11 PM PDT 24 Jun 07 07:49:37 PM PDT 24 340345600 ps
T1238 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1006176854 Jun 07 07:43:47 PM PDT 24 Jun 07 07:44:03 PM PDT 24 54479500 ps
T1239 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1566505716 Jun 07 07:43:35 PM PDT 24 Jun 07 07:43:50 PM PDT 24 31743400 ps
T1240 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.246928007 Jun 07 07:43:15 PM PDT 24 Jun 07 07:43:32 PM PDT 24 12974000 ps
T1241 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3103312521 Jun 07 07:42:58 PM PDT 24 Jun 07 07:43:15 PM PDT 24 109144400 ps
T1242 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1555299519 Jun 07 07:43:16 PM PDT 24 Jun 07 07:43:30 PM PDT 24 20734600 ps
T1243 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2171268989 Jun 07 07:43:36 PM PDT 24 Jun 07 07:43:52 PM PDT 24 12875400 ps
T1244 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2438550118 Jun 07 07:42:47 PM PDT 24 Jun 07 07:43:04 PM PDT 24 14159600 ps
T1245 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1289927114 Jun 07 07:43:50 PM PDT 24 Jun 07 07:44:05 PM PDT 24 17624200 ps

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.1800506041
Short name T5
Test name
Test status
Simulation time 21123403700 ps
CPU time 597.6 seconds
Started Jun 07 07:00:48 PM PDT 24
Finished Jun 07 07:10:47 PM PDT 24
Peak memory 313684 kb
Host smart-269758b0-2fec-4488-9c0f-c65d816450b7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800506041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_s
err.1800506041
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3546956487
Short name T69
Test name
Test status
Simulation time 1024226900 ps
CPU time 906.61 seconds
Started Jun 07 07:43:37 PM PDT 24
Finished Jun 07 07:58:46 PM PDT 24
Peak memory 263744 kb
Host smart-34b3bb8a-6a94-474b-bd86-4c05ab7affea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546956487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.3546956487
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.135634941
Short name T21
Test name
Test status
Simulation time 40129586400 ps
CPU time 883.94 seconds
Started Jun 07 07:01:02 PM PDT 24
Finished Jun 07 07:15:47 PM PDT 24
Peak memory 264580 kb
Host smart-b89bdbf7-4208-4c10-94b9-02ce114c6d35
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135634941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 5.flash_ctrl_hw_rma_reset.135634941
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.3163252098
Short name T40
Test name
Test status
Simulation time 64416400 ps
CPU time 214.45 seconds
Started Jun 07 07:05:37 PM PDT 24
Finished Jun 07 07:09:12 PM PDT 24
Peak memory 270228 kb
Host smart-3d5fcc7a-574a-4ab2-88fc-39de74111423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163252098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.3163252098
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.3684612352
Short name T118
Test name
Test status
Simulation time 3715684700 ps
CPU time 128.56 seconds
Started Jun 07 07:01:25 PM PDT 24
Finished Jun 07 07:03:35 PM PDT 24
Peak memory 265488 kb
Host smart-88f7ca7b-e489-49c4-9f70-20d594a3980b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684612352 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.3684612352
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.2635388201
Short name T11
Test name
Test status
Simulation time 73640000 ps
CPU time 130.88 seconds
Started Jun 07 07:06:02 PM PDT 24
Finished Jun 07 07:08:14 PM PDT 24
Peak memory 260368 kb
Host smart-e1b803e9-e2bd-415e-80c3-6651ea02a451
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635388201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.2635388201
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_cm.3260151692
Short name T12
Test name
Test status
Simulation time 8322504300 ps
CPU time 6188.34 seconds
Started Jun 07 07:00:56 PM PDT 24
Finished Jun 07 08:44:06 PM PDT 24
Peak memory 286812 kb
Host smart-ab8f5e11-2e1e-41ec-8374-6b728a5b8209
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260151692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3260151692
Directory /workspace/4.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.2223219164
Short name T49
Test name
Test status
Simulation time 4303081800 ps
CPU time 68.69 seconds
Started Jun 07 07:04:08 PM PDT 24
Finished Jun 07 07:05:17 PM PDT 24
Peak memory 261068 kb
Host smart-86421248-474b-437b-b80c-d0ed3d96f906
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223219164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.2
223219164
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.3589349245
Short name T176
Test name
Test status
Simulation time 3844697900 ps
CPU time 426.89 seconds
Started Jun 07 07:00:40 PM PDT 24
Finished Jun 07 07:07:47 PM PDT 24
Peak memory 263708 kb
Host smart-53405888-0702-4425-bf7f-0e1f49bdeaae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589349245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.3589349245
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.4180193777
Short name T175
Test name
Test status
Simulation time 895637700 ps
CPU time 69.65 seconds
Started Jun 07 06:58:35 PM PDT 24
Finished Jun 07 06:59:46 PM PDT 24
Peak memory 260740 kb
Host smart-c4ae2dbe-2f13-4d2d-a6b1-b953e90569a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180193777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.4180193777
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3456509894
Short name T25
Test name
Test status
Simulation time 32877287900 ps
CPU time 354.93 seconds
Started Jun 07 07:05:45 PM PDT 24
Finished Jun 07 07:11:42 PM PDT 24
Peak memory 285236 kb
Host smart-97de0698-ef56-415b-ad08-6f7da4d88320
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456509894 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.3456509894
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.1179240890
Short name T8
Test name
Test status
Simulation time 24252700 ps
CPU time 14.19 seconds
Started Jun 07 07:01:02 PM PDT 24
Finished Jun 07 07:01:17 PM PDT 24
Peak memory 263200 kb
Host smart-0c7d9a8f-7c4f-4fd3-a0bd-c6be4eca07c4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179240890 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.1179240890
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.2218042089
Short name T662
Test name
Test status
Simulation time 72533900 ps
CPU time 132.56 seconds
Started Jun 07 07:06:36 PM PDT 24
Finished Jun 07 07:08:50 PM PDT 24
Peak memory 265276 kb
Host smart-c246f4c2-1ca6-4cc5-b069-1eb00c27b30c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218042089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.2218042089
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2159634281
Short name T248
Test name
Test status
Simulation time 172492200 ps
CPU time 16.29 seconds
Started Jun 07 07:42:29 PM PDT 24
Finished Jun 07 07:42:47 PM PDT 24
Peak memory 263764 kb
Host smart-7d8d620c-a952-4d9b-8577-3acc1687f640
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159634281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.2
159634281
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.970652443
Short name T17
Test name
Test status
Simulation time 13935213100 ps
CPU time 123.1 seconds
Started Jun 07 07:06:52 PM PDT 24
Finished Jun 07 07:08:55 PM PDT 24
Peak memory 263324 kb
Host smart-60ef8e60-81d7-4152-819c-32f9d7797342
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970652443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_h
w_sec_otp.970652443
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.3176446630
Short name T52
Test name
Test status
Simulation time 559441600 ps
CPU time 22.62 seconds
Started Jun 07 07:00:19 PM PDT 24
Finished Jun 07 07:00:43 PM PDT 24
Peak memory 263948 kb
Host smart-15246990-23ee-46aa-a3aa-943b1eb5c899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176446630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.3176446630
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.560855054
Short name T368
Test name
Test status
Simulation time 31019900 ps
CPU time 13.39 seconds
Started Jun 07 07:43:35 PM PDT 24
Finished Jun 07 07:43:51 PM PDT 24
Peak memory 261040 kb
Host smart-f0469721-756d-43fd-9556-9808a751cf12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560855054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.560855054
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.2869146134
Short name T157
Test name
Test status
Simulation time 150197300 ps
CPU time 132.03 seconds
Started Jun 07 07:07:39 PM PDT 24
Finished Jun 07 07:09:53 PM PDT 24
Peak memory 260240 kb
Host smart-0f89a432-b703-4e1d-ba25-70261781a1c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869146134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.2869146134
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.3132728761
Short name T23
Test name
Test status
Simulation time 266079099500 ps
CPU time 2395.27 seconds
Started Jun 07 06:59:44 PM PDT 24
Finished Jun 07 07:39:40 PM PDT 24
Peak memory 265440 kb
Host smart-33467d06-79aa-4e94-9482-4d53d7b21c0f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132728761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 2.flash_ctrl_host_ctrl_arb.3132728761
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.3695827452
Short name T16
Test name
Test status
Simulation time 85307200 ps
CPU time 13.76 seconds
Started Jun 07 07:05:17 PM PDT 24
Finished Jun 07 07:05:32 PM PDT 24
Peak memory 258592 kb
Host smart-d66802a5-cff4-43e3-ab3c-159568b93ff1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695827452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.
3695827452
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.2777936923
Short name T2
Test name
Test status
Simulation time 1365185600 ps
CPU time 136.97 seconds
Started Jun 07 06:59:43 PM PDT 24
Finished Jun 07 07:02:01 PM PDT 24
Peak memory 282360 kb
Host smart-a3359551-6221-4e17-9911-63320ecb44eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2777936923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.2777936923
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2753978150
Short name T146
Test name
Test status
Simulation time 10019775800 ps
CPU time 164.87 seconds
Started Jun 07 07:04:14 PM PDT 24
Finished Jun 07 07:07:00 PM PDT 24
Peak memory 272428 kb
Host smart-f66c2b78-b787-4a7f-8a40-6a5eef1e6180
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753978150 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.2753978150
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.143186984
Short name T140
Test name
Test status
Simulation time 209523100 ps
CPU time 13.41 seconds
Started Jun 07 07:01:18 PM PDT 24
Finished Jun 07 07:01:32 PM PDT 24
Peak memory 261100 kb
Host smart-20f65955-d0f4-4bab-806c-291d8f340694
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143186984 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.143186984
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.4103274155
Short name T417
Test name
Test status
Simulation time 4782253500 ps
CPU time 83.88 seconds
Started Jun 07 07:07:12 PM PDT 24
Finished Jun 07 07:08:37 PM PDT 24
Peak memory 264936 kb
Host smart-bb8a907d-4fbd-49f5-89b8-87db280ee728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103274155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.4103274155
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.2367546272
Short name T7
Test name
Test status
Simulation time 53028300 ps
CPU time 15.17 seconds
Started Jun 07 06:59:16 PM PDT 24
Finished Jun 07 06:59:32 PM PDT 24
Peak memory 264836 kb
Host smart-869f1b4d-4dcf-4323-9d2e-98fd44b2714f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367546272 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.2367546272
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.3665538443
Short name T244
Test name
Test status
Simulation time 2845715500 ps
CPU time 227.87 seconds
Started Jun 07 07:03:08 PM PDT 24
Finished Jun 07 07:06:57 PM PDT 24
Peak memory 291468 kb
Host smart-10128403-e48f-4c89-ae94-e872b1da7fca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665538443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.3665538443
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.2914563909
Short name T180
Test name
Test status
Simulation time 86574600 ps
CPU time 13.38 seconds
Started Jun 07 07:05:03 PM PDT 24
Finished Jun 07 07:05:17 PM PDT 24
Peak memory 265464 kb
Host smart-867e72d5-4e57-46b2-bd10-a0510c316a71
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914563909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.2914563909
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.1399304566
Short name T147
Test name
Test status
Simulation time 92484804800 ps
CPU time 1033.71 seconds
Started Jun 07 06:58:52 PM PDT 24
Finished Jun 07 07:16:07 PM PDT 24
Peak memory 303728 kb
Host smart-768b9a9f-accc-4277-be2d-f596d84796cc
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399304566 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.1399304566
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.254546090
Short name T173
Test name
Test status
Simulation time 886087100 ps
CPU time 70.75 seconds
Started Jun 07 07:00:48 PM PDT 24
Finished Jun 07 07:02:01 PM PDT 24
Peak memory 260752 kb
Host smart-faea8728-31a7-4ba8-a4bc-42cfe65fb37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254546090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.254546090
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.3799854962
Short name T86
Test name
Test status
Simulation time 13137643600 ps
CPU time 983.81 seconds
Started Jun 07 07:04:33 PM PDT 24
Finished Jun 07 07:20:58 PM PDT 24
Peak memory 275568 kb
Host smart-20102f61-b06f-4398-9115-1ba3eb173294
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799854962 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_mp_regions.3799854962
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1634134607
Short name T258
Test name
Test status
Simulation time 40896200 ps
CPU time 13.56 seconds
Started Jun 07 07:42:28 PM PDT 24
Finished Jun 07 07:42:43 PM PDT 24
Peak memory 262716 kb
Host smart-4343fa6b-c528-4a02-bab5-ffb7d65af231
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634134607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.1634134607
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.1824508252
Short name T63
Test name
Test status
Simulation time 1152941500 ps
CPU time 201.17 seconds
Started Jun 07 07:00:20 PM PDT 24
Finished Jun 07 07:03:42 PM PDT 24
Peak memory 282228 kb
Host smart-37a6a3df-6312-415e-8bf1-3c9df58a5dbd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824508252 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.1824508252
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3212714504
Short name T300
Test name
Test status
Simulation time 157193100 ps
CPU time 19.31 seconds
Started Jun 07 07:42:41 PM PDT 24
Finished Jun 07 07:43:03 PM PDT 24
Peak memory 263672 kb
Host smart-a215f1a8-caa6-4752-a767-c4049d172e25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212714504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3
212714504
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.1260363435
Short name T27
Test name
Test status
Simulation time 49257200 ps
CPU time 30.85 seconds
Started Jun 07 07:05:59 PM PDT 24
Finished Jun 07 07:06:31 PM PDT 24
Peak memory 276068 kb
Host smart-9dcca2cd-7b5d-4b8c-a830-262f33ab2d28
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260363435 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.1260363435
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.468983546
Short name T60
Test name
Test status
Simulation time 8672104500 ps
CPU time 70.79 seconds
Started Jun 07 07:00:45 PM PDT 24
Finished Jun 07 07:01:57 PM PDT 24
Peak memory 273976 kb
Host smart-56b6fa08-b40e-4cba-a7a5-3b588f12f388
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468983546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_serr_address.468983546
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.2452007957
Short name T22
Test name
Test status
Simulation time 80148089700 ps
CPU time 909.11 seconds
Started Jun 07 07:00:41 PM PDT 24
Finished Jun 07 07:15:51 PM PDT 24
Peak memory 264596 kb
Host smart-1f5365f4-b93f-438b-95d3-890efdaf4324
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452007957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.2452007957
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.949970712
Short name T294
Test name
Test status
Simulation time 852043600 ps
CPU time 907.31 seconds
Started Jun 07 07:42:58 PM PDT 24
Finished Jun 07 07:58:07 PM PDT 24
Peak memory 263732 kb
Host smart-78afe7bc-edcb-4dbd-8a08-e2ee3a48ef18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949970712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_
tl_intg_err.949970712
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.1746726450
Short name T38
Test name
Test status
Simulation time 1047453500 ps
CPU time 143.38 seconds
Started Jun 07 07:05:38 PM PDT 24
Finished Jun 07 07:08:02 PM PDT 24
Peak memory 294440 kb
Host smart-95fd721a-065e-4249-b330-4b636fd4479e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746726450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.1746726450
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1021235920
Short name T281
Test name
Test status
Simulation time 10036177000 ps
CPU time 53.79 seconds
Started Jun 07 06:58:56 PM PDT 24
Finished Jun 07 06:59:51 PM PDT 24
Peak memory 282564 kb
Host smart-fd4fa698-fd6e-4896-a6c1-874e79959391
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021235920 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.1021235920
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.2519616152
Short name T761
Test name
Test status
Simulation time 2500284800 ps
CPU time 170.07 seconds
Started Jun 07 07:04:07 PM PDT 24
Finished Jun 07 07:06:58 PM PDT 24
Peak memory 293488 kb
Host smart-595414c7-36e0-4390-92a9-dface17f6260
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519616152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.2519616152
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.4108688425
Short name T138
Test name
Test status
Simulation time 877900900 ps
CPU time 17.79 seconds
Started Jun 07 06:58:54 PM PDT 24
Finished Jun 07 06:59:13 PM PDT 24
Peak memory 263388 kb
Host smart-24395e2f-2048-4568-af58-98dc47441acb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108688425 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.4108688425
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.1165204605
Short name T352
Test name
Test status
Simulation time 21586616600 ps
CPU time 174.21 seconds
Started Jun 07 07:06:36 PM PDT 24
Finished Jun 07 07:09:31 PM PDT 24
Peak memory 263472 kb
Host smart-a02738d3-5c3a-47ea-b661-f0f8fa3dd808
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165204605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.1165204605
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2841106395
Short name T257
Test name
Test status
Simulation time 424761300 ps
CPU time 19.39 seconds
Started Jun 07 07:42:36 PM PDT 24
Finished Jun 07 07:42:56 PM PDT 24
Peak memory 272012 kb
Host smart-7a162168-4aa8-48d0-b623-b775ce7f1d72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841106395 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.2841106395
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.2951468043
Short name T377
Test name
Test status
Simulation time 375086000 ps
CPU time 39.64 seconds
Started Jun 07 06:58:56 PM PDT 24
Finished Jun 07 06:59:36 PM PDT 24
Peak memory 263176 kb
Host smart-fae71a51-bea4-44dc-ade4-b7035ecc1c6b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951468043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.2951468043
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_cm.1138546012
Short name T13
Test name
Test status
Simulation time 1442231400 ps
CPU time 6148.69 seconds
Started Jun 07 06:58:45 PM PDT 24
Finished Jun 07 08:41:15 PM PDT 24
Peak memory 287496 kb
Host smart-0fcf558c-6e04-49ce-a7f2-bb0dfcb3ff19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138546012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.1138546012
Directory /workspace/0.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1186081698
Short name T1124
Test name
Test status
Simulation time 51894400 ps
CPU time 13.36 seconds
Started Jun 07 07:43:09 PM PDT 24
Finished Jun 07 07:43:23 PM PDT 24
Peak memory 261120 kb
Host smart-c4e0abdc-ece8-4916-bedd-fa3e97c7810a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186081698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
1186081698
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.1783424467
Short name T96
Test name
Test status
Simulation time 7169007700 ps
CPU time 635.92 seconds
Started Jun 07 07:04:27 PM PDT 24
Finished Jun 07 07:15:03 PM PDT 24
Peak memory 312440 kb
Host smart-b10da5aa-f13e-4643-a315-11192362ef7a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783424467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.flash_ctrl_rw.1783424467
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.902255418
Short name T375
Test name
Test status
Simulation time 88029600 ps
CPU time 33.38 seconds
Started Jun 07 07:02:37 PM PDT 24
Finished Jun 07 07:03:11 PM PDT 24
Peak memory 275788 kb
Host smart-7f24bc37-9956-46a0-ac75-8924ec0865c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902255418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_re_evict.902255418
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.1292680180
Short name T46
Test name
Test status
Simulation time 249228700 ps
CPU time 20.43 seconds
Started Jun 07 06:58:39 PM PDT 24
Finished Jun 07 06:59:01 PM PDT 24
Peak memory 262712 kb
Host smart-a59a2ca6-8645-49ad-807e-54e79218b7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292680180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.1292680180
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4218058567
Short name T288
Test name
Test status
Simulation time 100087200 ps
CPU time 18.52 seconds
Started Jun 07 07:43:18 PM PDT 24
Finished Jun 07 07:43:38 PM PDT 24
Peak memory 263768 kb
Host smart-f7a3156b-1bcf-4384-8e2e-a2fb4d9c460b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218058567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.
4218058567
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.4126063232
Short name T374
Test name
Test status
Simulation time 151548200 ps
CPU time 34.97 seconds
Started Jun 07 07:03:00 PM PDT 24
Finished Jun 07 07:03:36 PM PDT 24
Peak memory 274964 kb
Host smart-210f6567-536d-4490-8447-2ca1279d9f41
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126063232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.4126063232
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.2015451969
Short name T360
Test name
Test status
Simulation time 49138624800 ps
CPU time 278.16 seconds
Started Jun 07 07:03:07 PM PDT 24
Finished Jun 07 07:07:46 PM PDT 24
Peak memory 285160 kb
Host smart-785a718c-39d2-4689-aeb0-99cb197471a3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015451969 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.2015451969
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.2487101209
Short name T43
Test name
Test status
Simulation time 37955900 ps
CPU time 14.46 seconds
Started Jun 07 06:58:54 PM PDT 24
Finished Jun 07 06:59:09 PM PDT 24
Peak memory 279720 kb
Host smart-81dc2244-f860-4f77-a88e-30ab31918fe3
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=2487101209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.2487101209
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.2605414045
Short name T771
Test name
Test status
Simulation time 10257100 ps
CPU time 20.22 seconds
Started Jun 07 07:05:18 PM PDT 24
Finished Jun 07 07:05:39 PM PDT 24
Peak memory 265840 kb
Host smart-e3894761-ead7-4011-afc8-e664b8c2dda8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605414045 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.2605414045
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2618162023
Short name T390
Test name
Test status
Simulation time 15264800 ps
CPU time 13.6 seconds
Started Jun 07 06:59:23 PM PDT 24
Finished Jun 07 06:59:38 PM PDT 24
Peak memory 265172 kb
Host smart-442d0487-0a3b-4ca1-afac-b877f8e6b6ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618162023 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.2618162023
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.1045901915
Short name T218
Test name
Test status
Simulation time 16878200 ps
CPU time 15.71 seconds
Started Jun 07 07:02:43 PM PDT 24
Finished Jun 07 07:03:00 PM PDT 24
Peak memory 275104 kb
Host smart-165f7f27-bcbe-4da4-aa34-243b73a0c346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045901915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1045901915
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.472713241
Short name T226
Test name
Test status
Simulation time 307530600 ps
CPU time 34.26 seconds
Started Jun 07 07:03:08 PM PDT 24
Finished Jun 07 07:03:44 PM PDT 24
Peak memory 275660 kb
Host smart-44e37966-3f1c-44ef-bf6f-f74a2e864ed4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472713241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_re_evict.472713241
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.300082495
Short name T155
Test name
Test status
Simulation time 38514700 ps
CPU time 133.94 seconds
Started Jun 07 07:06:05 PM PDT 24
Finished Jun 07 07:08:20 PM PDT 24
Peak memory 260152 kb
Host smart-07606f68-387b-4467-ac46-ebbd074e064e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300082495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_ot
p_reset.300082495
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.481640670
Short name T10
Test name
Test status
Simulation time 15261400 ps
CPU time 13.83 seconds
Started Jun 07 07:00:32 PM PDT 24
Finished Jun 07 07:00:47 PM PDT 24
Peak memory 265244 kb
Host smart-71682f33-1977-4af9-afaa-d913a0ff1c37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481640670 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.481640670
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.3087032145
Short name T1005
Test name
Test status
Simulation time 3307306900 ps
CPU time 2413.12 seconds
Started Jun 07 06:58:39 PM PDT 24
Finished Jun 07 07:38:53 PM PDT 24
Peak memory 265216 kb
Host smart-91966b12-f36d-4d70-8ac6-8fc27c6c7734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087032145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.3087032145
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.2590436627
Short name T224
Test name
Test status
Simulation time 6309252600 ps
CPU time 172.94 seconds
Started Jun 07 07:00:20 PM PDT 24
Finished Jun 07 07:03:14 PM PDT 24
Peak memory 282944 kb
Host smart-13a81374-d0bf-4538-b8bd-e1a947963873
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2590436627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.2590436627
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.174774167
Short name T331
Test name
Test status
Simulation time 372980500 ps
CPU time 862.59 seconds
Started Jun 07 06:58:37 PM PDT 24
Finished Jun 07 07:13:01 PM PDT 24
Peak memory 270944 kb
Host smart-aead2c38-f7bb-4715-b0b7-cea16d7957e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174774167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.174774167
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.592794745
Short name T304
Test name
Test status
Simulation time 589176500 ps
CPU time 892.22 seconds
Started Jun 07 07:43:21 PM PDT 24
Finished Jun 07 07:58:16 PM PDT 24
Peak memory 263696 kb
Host smart-120e982e-6f75-4afc-85a2-dfff3ea2f3e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592794745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl
_tl_intg_err.592794745
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2670097664
Short name T297
Test name
Test status
Simulation time 713720800 ps
CPU time 892.96 seconds
Started Jun 07 07:42:57 PM PDT 24
Finished Jun 07 07:57:52 PM PDT 24
Peak memory 263752 kb
Host smart-c6d79996-361f-4436-a07d-c1554591ccd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670097664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.2670097664
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.584892374
Short name T913
Test name
Test status
Simulation time 25989600 ps
CPU time 13.83 seconds
Started Jun 07 06:58:55 PM PDT 24
Finished Jun 07 06:59:10 PM PDT 24
Peak memory 258784 kb
Host smart-7966346a-ccbf-41d1-8d64-652e599cf595
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584892374 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.584892374
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.2817313877
Short name T24
Test name
Test status
Simulation time 10057439000 ps
CPU time 43.19 seconds
Started Jun 07 07:02:57 PM PDT 24
Finished Jun 07 07:03:41 PM PDT 24
Peak memory 265916 kb
Host smart-b4a22e3a-1bf8-4608-b270-1e7c36c78588
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817313877 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.2817313877
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3421444922
Short name T398
Test name
Test status
Simulation time 882456400 ps
CPU time 752.08 seconds
Started Jun 07 07:43:32 PM PDT 24
Finished Jun 07 07:56:05 PM PDT 24
Peak memory 263764 kb
Host smart-aa14afd1-5ebe-4444-8119-f77e9138a876
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421444922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.3421444922
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.534021419
Short name T328
Test name
Test status
Simulation time 35359800 ps
CPU time 13.87 seconds
Started Jun 07 07:03:07 PM PDT 24
Finished Jun 07 07:03:22 PM PDT 24
Peak memory 259052 kb
Host smart-1fe05fd1-68ab-46b3-b208-28206bb09ec1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534021419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_res
et.534021419
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.3701142266
Short name T358
Test name
Test status
Simulation time 765257000 ps
CPU time 157.99 seconds
Started Jun 07 07:03:52 PM PDT 24
Finished Jun 07 07:06:31 PM PDT 24
Peak memory 293480 kb
Host smart-b4e9abcd-4213-4d3b-9e76-ab9973f2c2db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701142266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.3701142266
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.192100860
Short name T462
Test name
Test status
Simulation time 3873913700 ps
CPU time 89.92 seconds
Started Jun 07 07:03:51 PM PDT 24
Finished Jun 07 07:05:21 PM PDT 24
Peak memory 263576 kb
Host smart-71dea038-4cff-4f2a-bca4-436b253bfa91
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192100860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.192100860
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.3607210991
Short name T446
Test name
Test status
Simulation time 4992267700 ps
CPU time 67.66 seconds
Started Jun 07 07:05:51 PM PDT 24
Finished Jun 07 07:07:00 PM PDT 24
Peak memory 263812 kb
Host smart-2a589b73-6de0-4988-a9db-4fe14d09e259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607210991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.3607210991
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.1429725448
Short name T415
Test name
Test status
Simulation time 6500563600 ps
CPU time 77.8 seconds
Started Jun 07 07:05:58 PM PDT 24
Finished Jun 07 07:07:16 PM PDT 24
Peak memory 264408 kb
Host smart-bb9b9f8e-220a-4288-95db-6081fb76032b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429725448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.1429725448
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.1033161512
Short name T380
Test name
Test status
Simulation time 30174700 ps
CPU time 31.55 seconds
Started Jun 07 07:06:06 PM PDT 24
Finished Jun 07 07:06:39 PM PDT 24
Peak memory 276072 kb
Host smart-13c698b9-6c88-4340-bc96-2e16e4020c46
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033161512 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.1033161512
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.3901243268
Short name T439
Test name
Test status
Simulation time 149198400 ps
CPU time 132.02 seconds
Started Jun 07 07:07:41 PM PDT 24
Finished Jun 07 07:09:54 PM PDT 24
Peak memory 265164 kb
Host smart-99be61e7-d1e0-42c7-b51b-61d11b3043a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901243268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.3901243268
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.1919919628
Short name T87
Test name
Test status
Simulation time 1642610500 ps
CPU time 64.76 seconds
Started Jun 07 07:02:04 PM PDT 24
Finished Jun 07 07:03:10 PM PDT 24
Peak memory 263572 kb
Host smart-b77f8861-081e-4d8b-9746-ff09ac8837d1
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919919628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.1919919628
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.1381907389
Short name T238
Test name
Test status
Simulation time 19687900 ps
CPU time 13.68 seconds
Started Jun 07 06:58:54 PM PDT 24
Finished Jun 07 06:59:09 PM PDT 24
Peak memory 265024 kb
Host smart-fc04033a-660b-4e00-8c7a-16d4becaf0cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381907389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.flash_ctrl_config_regwen.1381907389
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.3737287226
Short name T59
Test name
Test status
Simulation time 780178900 ps
CPU time 17.56 seconds
Started Jun 07 06:59:21 PM PDT 24
Finished Jun 07 06:59:39 PM PDT 24
Peak memory 266008 kb
Host smart-5753ef8d-5f0e-47d9-9f30-c74e38c011cc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737287226 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.3737287226
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.3263658808
Short name T170
Test name
Test status
Simulation time 258471576500 ps
CPU time 2310.95 seconds
Started Jun 07 06:58:39 PM PDT 24
Finished Jun 07 07:37:11 PM PDT 24
Peak memory 264220 kb
Host smart-6b7f4f65-76e3-4483-b14d-c7ea900a8bbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263658808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.3263658808
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.89153634
Short name T289
Test name
Test status
Simulation time 53512400 ps
CPU time 18.64 seconds
Started Jun 07 07:42:29 PM PDT 24
Finished Jun 07 07:42:49 PM PDT 24
Peak memory 262752 kb
Host smart-32ec09ae-26d6-4730-a0df-18ac4414ec42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89153634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.89153634
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.4120533598
Short name T236
Test name
Test status
Simulation time 1400584900 ps
CPU time 131.06 seconds
Started Jun 07 06:58:36 PM PDT 24
Finished Jun 07 07:00:48 PM PDT 24
Peak memory 290976 kb
Host smart-3d2f45f6-e6e3-4352-8e0f-ef5e3239bf0f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120533598 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.4120533598
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.2507198828
Short name T33
Test name
Test status
Simulation time 2939286600 ps
CPU time 81.64 seconds
Started Jun 07 07:00:58 PM PDT 24
Finished Jun 07 07:02:20 PM PDT 24
Peak memory 260888 kb
Host smart-e896ac0e-d50e-4c64-a0e0-b88310bcbda3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507198828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.flash_ctrl_intr_wr.2507198828
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3516175935
Short name T1138
Test name
Test status
Simulation time 20700600 ps
CPU time 13.45 seconds
Started Jun 07 07:43:15 PM PDT 24
Finished Jun 07 07:43:30 PM PDT 24
Peak memory 261064 kb
Host smart-4f762239-e2d9-4f4f-86d6-5adff899c393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516175935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
3516175935
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1090328014
Short name T247
Test name
Test status
Simulation time 197339900 ps
CPU time 461.71 seconds
Started Jun 07 07:43:18 PM PDT 24
Finished Jun 07 07:51:01 PM PDT 24
Peak memory 263688 kb
Host smart-b98059fe-c4d5-424c-86ee-959f954b353e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090328014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.1090328014
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.30435192
Short name T402
Test name
Test status
Simulation time 854442600 ps
CPU time 763.51 seconds
Started Jun 07 07:43:18 PM PDT 24
Finished Jun 07 07:56:04 PM PDT 24
Peak memory 263748 kb
Host smart-4abbc78e-cd65-45b0-bc07-22fdae5ff43b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30435192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
tl_intg_err.30435192
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.1478273864
Short name T906
Test name
Test status
Simulation time 10474300 ps
CPU time 20.63 seconds
Started Jun 07 06:58:49 PM PDT 24
Finished Jun 07 06:59:10 PM PDT 24
Peak memory 274028 kb
Host smart-ebda5cf5-8750-4bce-9e6d-5149455712ab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478273864 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.1478273864
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.3783635222
Short name T383
Test name
Test status
Simulation time 46686400 ps
CPU time 30.47 seconds
Started Jun 07 06:58:47 PM PDT 24
Finished Jun 07 06:59:18 PM PDT 24
Peak memory 276076 kb
Host smart-f5384318-de9f-4018-81e3-203c16d14065
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783635222 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.3783635222
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.3699504657
Short name T846
Test name
Test status
Simulation time 21573800 ps
CPU time 20.29 seconds
Started Jun 07 07:02:44 PM PDT 24
Finished Jun 07 07:03:06 PM PDT 24
Peak memory 274052 kb
Host smart-6d15b93e-c7e3-485f-8255-a08ebeae020a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699504657 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.3699504657
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.2799288530
Short name T215
Test name
Test status
Simulation time 20789800 ps
CPU time 21.68 seconds
Started Jun 07 07:03:02 PM PDT 24
Finished Jun 07 07:03:25 PM PDT 24
Peak memory 265808 kb
Host smart-cfcc2c2d-c5ed-49ce-9dc4-4d4b978b90bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799288530 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.2799288530
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.2984751861
Short name T769
Test name
Test status
Simulation time 566457100 ps
CPU time 65.02 seconds
Started Jun 07 07:02:59 PM PDT 24
Finished Jun 07 07:04:05 PM PDT 24
Peak memory 264860 kb
Host smart-e5c3eee4-66c1-4c3b-9734-8b9ce46894d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984751861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.2984751861
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.49971905
Short name T76
Test name
Test status
Simulation time 13783500 ps
CPU time 21.48 seconds
Started Jun 07 07:03:46 PM PDT 24
Finished Jun 07 07:04:08 PM PDT 24
Peak memory 274052 kb
Host smart-bd63a2f1-1150-4d17-ba01-04f0f3e903fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49971905 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.flash_ctrl_disable.49971905
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.3460085739
Short name T163
Test name
Test status
Simulation time 41375700 ps
CPU time 20.68 seconds
Started Jun 07 07:04:59 PM PDT 24
Finished Jun 07 07:05:20 PM PDT 24
Peak memory 273992 kb
Host smart-44957b80-366c-4f64-a9b2-6764b18e45f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460085739 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.3460085739
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.3535704829
Short name T452
Test name
Test status
Simulation time 1894743300 ps
CPU time 59.6 seconds
Started Jun 07 07:05:10 PM PDT 24
Finished Jun 07 07:06:11 PM PDT 24
Peak memory 264920 kb
Host smart-a8b1455c-f764-4c23-a9b0-f39da5f92d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535704829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.3535704829
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.1502088515
Short name T451
Test name
Test status
Simulation time 2358128600 ps
CPU time 78.58 seconds
Started Jun 07 07:05:14 PM PDT 24
Finished Jun 07 07:06:34 PM PDT 24
Peak memory 265488 kb
Host smart-194cbd75-e8e3-4ad0-8b1e-f25a4fb72e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502088515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.1502088515
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.3868145924
Short name T312
Test name
Test status
Simulation time 6952642200 ps
CPU time 239.56 seconds
Started Jun 07 07:05:50 PM PDT 24
Finished Jun 07 07:09:51 PM PDT 24
Peak memory 291708 kb
Host smart-f4565935-2042-4e8f-a8af-c1548b7a1fca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868145924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.3868145924
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.971772590
Short name T414
Test name
Test status
Simulation time 1713084900 ps
CPU time 60.3 seconds
Started Jun 07 07:06:35 PM PDT 24
Finished Jun 07 07:07:36 PM PDT 24
Peak memory 265464 kb
Host smart-9b636ad8-cece-470b-9fea-a90f01e0c3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971772590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.971772590
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3592155576
Short name T293
Test name
Test status
Simulation time 61904700 ps
CPU time 16.03 seconds
Started Jun 07 07:43:07 PM PDT 24
Finished Jun 07 07:43:25 PM PDT 24
Peak memory 263736 kb
Host smart-956b5b6f-04bd-4a30-94d0-249fcce6050a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592155576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
3592155576
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.2320919153
Short name T20
Test name
Test status
Simulation time 45198100 ps
CPU time 13.87 seconds
Started Jun 07 06:58:45 PM PDT 24
Finished Jun 07 06:59:00 PM PDT 24
Peak memory 265820 kb
Host smart-f583ebe9-108e-4a46-927f-17b0f3d5c806
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320919153 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.2320919153
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_derr.1293744600
Short name T459
Test name
Test status
Simulation time 5119148500 ps
CPU time 740.96 seconds
Started Jun 07 06:59:17 PM PDT 24
Finished Jun 07 07:11:39 PM PDT 24
Peak memory 334080 kb
Host smart-032f9693-3006-4f07-b5fa-367ca8280c14
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293744600 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_rw_derr.1293744600
Directory /workspace/1.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.3199330755
Short name T241
Test name
Test status
Simulation time 44749300 ps
CPU time 13.8 seconds
Started Jun 07 06:59:22 PM PDT 24
Finished Jun 07 06:59:37 PM PDT 24
Peak memory 262040 kb
Host smart-3261e931-bdfe-44e5-a7b8-50677dc5b88d
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3199330755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.3199330755
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.115109359
Short name T210
Test name
Test status
Simulation time 11871251800 ps
CPU time 244.66 seconds
Started Jun 07 07:05:52 PM PDT 24
Finished Jun 07 07:09:58 PM PDT 24
Peak memory 295304 kb
Host smart-94ddc33b-e0f8-4430-b3ef-8029de10221d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115109359 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.115109359
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.409455734
Short name T988
Test name
Test status
Simulation time 28139700 ps
CPU time 28.07 seconds
Started Jun 07 07:06:05 PM PDT 24
Finished Jun 07 07:06:34 PM PDT 24
Peak memory 275728 kb
Host smart-45705607-207c-4046-aed4-b181e771a3a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409455734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_rw_evict.409455734
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.3516874851
Short name T639
Test name
Test status
Simulation time 4806612000 ps
CPU time 2239.77 seconds
Started Jun 07 06:58:39 PM PDT 24
Finished Jun 07 07:36:00 PM PDT 24
Peak memory 265540 kb
Host smart-7056080e-22d6-4673-8de5-9337df71219e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516874851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_err
or_mp.3516874851
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.2735626891
Short name T1001
Test name
Test status
Simulation time 489110225300 ps
CPU time 4527.96 seconds
Started Jun 07 06:58:36 PM PDT 24
Finished Jun 07 08:14:06 PM PDT 24
Peak memory 265780 kb
Host smart-cbb1a017-d39b-4205-9165-342c574bb1dc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735626891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.2735626891
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.3146990220
Short name T282
Test name
Test status
Simulation time 84340600 ps
CPU time 14.91 seconds
Started Jun 07 06:58:45 PM PDT 24
Finished Jun 07 06:59:01 PM PDT 24
Peak memory 261044 kb
Host smart-273eff0a-2f91-4583-857b-f717087c6a39
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146990220 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.3146990220
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.3742918707
Short name T517
Test name
Test status
Simulation time 218593700 ps
CPU time 100.52 seconds
Started Jun 07 06:58:59 PM PDT 24
Finished Jun 07 07:00:40 PM PDT 24
Peak memory 263112 kb
Host smart-8012f528-ce02-4aeb-85d7-4cd29740b1af
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3742918707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.3742918707
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.1105056732
Short name T131
Test name
Test status
Simulation time 5565844500 ps
CPU time 118.7 seconds
Started Jun 07 06:59:11 PM PDT 24
Finished Jun 07 07:01:11 PM PDT 24
Peak memory 289312 kb
Host smart-4f7f9392-b5b3-4233-9783-301ba801bf6c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105056732 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_ro.1105056732
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.2687809686
Short name T116
Test name
Test status
Simulation time 65861100 ps
CPU time 27.9 seconds
Started Jun 07 07:02:44 PM PDT 24
Finished Jun 07 07:03:12 PM PDT 24
Peak memory 276932 kb
Host smart-ceb90c39-2bfd-4a1d-af1a-f12db0e0aee7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687809686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_rw_evict.2687809686
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.1858413112
Short name T81
Test name
Test status
Simulation time 710623200 ps
CPU time 17.87 seconds
Started Jun 07 07:00:24 PM PDT 24
Finished Jun 07 07:00:42 PM PDT 24
Peak memory 264508 kb
Host smart-5c02acb5-5d9c-4b27-8332-7b7f36cd9118
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858413112 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.1858413112
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.2564929092
Short name T305
Test name
Test status
Simulation time 70529200 ps
CPU time 28.54 seconds
Started Jun 07 07:00:25 PM PDT 24
Finished Jun 07 07:00:55 PM PDT 24
Peak memory 270176 kb
Host smart-972c910f-59c8-4f24-a133-0806ac15888a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564929092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.2564929092
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.289180930
Short name T336
Test name
Test status
Simulation time 1597063500 ps
CPU time 62.28 seconds
Started Jun 07 07:42:27 PM PDT 24
Finished Jun 07 07:43:30 PM PDT 24
Peak memory 261132 kb
Host smart-5520c447-d3ea-4c90-a017-420a220cc97b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289180930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_aliasing.289180930
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1860559879
Short name T1148
Test name
Test status
Simulation time 659218200 ps
CPU time 41.22 seconds
Started Jun 07 07:42:31 PM PDT 24
Finished Jun 07 07:43:14 PM PDT 24
Peak memory 260972 kb
Host smart-33ba8b29-2b09-4aca-b714-ccf2871babc7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860559879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.1860559879
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.130476916
Short name T1123
Test name
Test status
Simulation time 186498900 ps
CPU time 46.14 seconds
Started Jun 07 07:42:28 PM PDT 24
Finished Jun 07 07:43:15 PM PDT 24
Peak memory 261184 kb
Host smart-80e95191-16b1-4784-87b8-a4a7ad906bf4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130476916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.flash_ctrl_csr_hw_reset.130476916
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.585229346
Short name T334
Test name
Test status
Simulation time 224648300 ps
CPU time 19.78 seconds
Started Jun 07 07:42:31 PM PDT 24
Finished Jun 07 07:42:53 PM PDT 24
Peak memory 271992 kb
Host smart-51ddc039-3cd1-4ce5-aea5-97f8fbcd2aec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585229346 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.585229346
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2083303590
Short name T1225
Test name
Test status
Simulation time 30350000 ps
CPU time 17.13 seconds
Started Jun 07 07:42:30 PM PDT 24
Finished Jun 07 07:42:48 PM PDT 24
Peak memory 263636 kb
Host smart-9fc0497a-9a12-40fd-81b5-d98e23e8463a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083303590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.2083303590
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2246923460
Short name T1213
Test name
Test status
Simulation time 55322800 ps
CPU time 13.31 seconds
Started Jun 07 07:42:28 PM PDT 24
Finished Jun 07 07:42:43 PM PDT 24
Peak memory 261132 kb
Host smart-68767dfd-e23c-43c5-b054-36379c2e95af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246923460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.2
246923460
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.23788972
Short name T261
Test name
Test status
Simulation time 17909500 ps
CPU time 13.46 seconds
Started Jun 07 07:42:32 PM PDT 24
Finished Jun 07 07:42:47 PM PDT 24
Peak memory 262112 kb
Host smart-95f76b0d-ff91-4d65-8f29-094fd482a510
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23788972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_mem_partial_access.23788972
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3079420651
Short name T1152
Test name
Test status
Simulation time 51458400 ps
CPU time 13.27 seconds
Started Jun 07 07:42:31 PM PDT 24
Finished Jun 07 07:42:45 PM PDT 24
Peak memory 261128 kb
Host smart-e8b04fbc-11ab-4676-af55-69f8185e4a27
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079420651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.3079420651
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.122395807
Short name T1129
Test name
Test status
Simulation time 358457600 ps
CPU time 18.09 seconds
Started Jun 07 07:42:28 PM PDT 24
Finished Jun 07 07:42:47 PM PDT 24
Peak memory 262552 kb
Host smart-5a1c443c-698c-4c5a-9883-279327f6c90f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122395807 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.122395807
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1369173043
Short name T1215
Test name
Test status
Simulation time 59958200 ps
CPU time 15.99 seconds
Started Jun 07 07:42:29 PM PDT 24
Finished Jun 07 07:42:47 PM PDT 24
Peak memory 253056 kb
Host smart-2d2cf0d0-8e38-42f8-8902-ee4e3b2e4bb0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369173043 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.1369173043
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2281505270
Short name T1204
Test name
Test status
Simulation time 12071300 ps
CPU time 15.76 seconds
Started Jun 07 07:42:30 PM PDT 24
Finished Jun 07 07:42:47 PM PDT 24
Peak memory 252892 kb
Host smart-c1f1d149-5487-4978-bad7-407ef6cc4833
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281505270 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.2281505270
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.29475517
Short name T1231
Test name
Test status
Simulation time 685328100 ps
CPU time 384.04 seconds
Started Jun 07 07:42:29 PM PDT 24
Finished Jun 07 07:48:54 PM PDT 24
Peak memory 263652 kb
Host smart-66f1d127-b6c8-473f-866d-bc7dc2bada73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29475517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_t
l_intg_err.29475517
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3100541287
Short name T1180
Test name
Test status
Simulation time 7970062000 ps
CPU time 38.24 seconds
Started Jun 07 07:42:39 PM PDT 24
Finished Jun 07 07:43:20 PM PDT 24
Peak memory 261260 kb
Host smart-37316ad5-d79a-413a-923b-302828af5f11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100541287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.3100541287
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1391827272
Short name T1118
Test name
Test status
Simulation time 339584600 ps
CPU time 36.31 seconds
Started Jun 07 07:42:39 PM PDT 24
Finished Jun 07 07:43:17 PM PDT 24
Peak memory 261260 kb
Host smart-4358b13e-2f12-49e4-8b9c-fce2b7685b5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391827272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.1391827272
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3028409692
Short name T339
Test name
Test status
Simulation time 104002800 ps
CPU time 46.35 seconds
Started Jun 07 07:42:29 PM PDT 24
Finished Jun 07 07:43:17 PM PDT 24
Peak memory 261092 kb
Host smart-b3bc30ed-3161-4963-be0f-a1ccd8ce3c7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028409692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.3028409692
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1003341870
Short name T340
Test name
Test status
Simulation time 321309200 ps
CPU time 15.45 seconds
Started Jun 07 07:42:37 PM PDT 24
Finished Jun 07 07:42:54 PM PDT 24
Peak memory 271348 kb
Host smart-281e609d-dcff-4fc5-9554-80d18404c916
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003341870 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.1003341870
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1563383949
Short name T335
Test name
Test status
Simulation time 451774000 ps
CPU time 17.5 seconds
Started Jun 07 07:42:31 PM PDT 24
Finished Jun 07 07:42:50 PM PDT 24
Peak memory 261216 kb
Host smart-1970f5dc-81c3-4eae-b68e-163ada66ee5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563383949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.1563383949
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3381239035
Short name T366
Test name
Test status
Simulation time 16335100 ps
CPU time 13.52 seconds
Started Jun 07 07:42:33 PM PDT 24
Finished Jun 07 07:42:47 PM PDT 24
Peak memory 261232 kb
Host smart-ae779056-982a-417a-9d7a-ad553b4f6fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381239035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.3
381239035
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.55126743
Short name T1108
Test name
Test status
Simulation time 16843400 ps
CPU time 13.24 seconds
Started Jun 07 07:42:29 PM PDT 24
Finished Jun 07 07:42:44 PM PDT 24
Peak memory 261116 kb
Host smart-7bbddb77-086a-4d2f-9f47-274e09056525
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55126743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_
walk.55126743
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3613910980
Short name T278
Test name
Test status
Simulation time 1338215500 ps
CPU time 16.26 seconds
Started Jun 07 07:42:38 PM PDT 24
Finished Jun 07 07:42:57 PM PDT 24
Peak memory 262332 kb
Host smart-38278936-3075-4389-950e-f10834af00c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613910980 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.3613910980
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.238619697
Short name T1115
Test name
Test status
Simulation time 12140000 ps
CPU time 15.83 seconds
Started Jun 07 07:42:31 PM PDT 24
Finished Jun 07 07:42:49 PM PDT 24
Peak memory 252960 kb
Host smart-d42321e8-45bd-4645-a993-c1c1eb9399cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238619697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.238619697
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.4178326826
Short name T1120
Test name
Test status
Simulation time 23024600 ps
CPU time 13.13 seconds
Started Jun 07 07:42:30 PM PDT 24
Finished Jun 07 07:42:44 PM PDT 24
Peak memory 252960 kb
Host smart-55260b7c-4507-41af-8af1-d43b3b7456ca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178326826 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.4178326826
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.910198946
Short name T403
Test name
Test status
Simulation time 536191800 ps
CPU time 460.1 seconds
Started Jun 07 07:42:31 PM PDT 24
Finished Jun 07 07:50:13 PM PDT 24
Peak memory 263688 kb
Host smart-700748e0-c94b-4267-9082-e6e1d39fec8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910198946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_
tl_intg_err.910198946
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.626521183
Short name T245
Test name
Test status
Simulation time 197195300 ps
CPU time 19.87 seconds
Started Jun 07 07:43:09 PM PDT 24
Finished Jun 07 07:43:30 PM PDT 24
Peak memory 271972 kb
Host smart-b63d06d4-dc9b-4adc-8014-a443ed625a6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626521183 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.626521183
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.161851212
Short name T1132
Test name
Test status
Simulation time 170977500 ps
CPU time 14.02 seconds
Started Jun 07 07:43:07 PM PDT 24
Finished Jun 07 07:43:22 PM PDT 24
Peak memory 263664 kb
Host smart-02824f34-87fc-4f60-bf2f-a1fb0d38e187
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161851212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.flash_ctrl_csr_rw.161851212
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3269936153
Short name T1212
Test name
Test status
Simulation time 24947000 ps
CPU time 13.41 seconds
Started Jun 07 07:43:06 PM PDT 24
Finished Jun 07 07:43:20 PM PDT 24
Peak memory 261060 kb
Host smart-0832bc7c-99b5-444e-aff4-5dbb1d53c7f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269936153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
3269936153
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3587779412
Short name T1133
Test name
Test status
Simulation time 122005300 ps
CPU time 33.16 seconds
Started Jun 07 07:43:07 PM PDT 24
Finished Jun 07 07:43:41 PM PDT 24
Peak memory 262500 kb
Host smart-bfb2f4c0-ee36-4ce9-9507-0a592e6c88fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587779412 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.3587779412
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1488045123
Short name T1135
Test name
Test status
Simulation time 127783500 ps
CPU time 15.82 seconds
Started Jun 07 07:43:06 PM PDT 24
Finished Jun 07 07:43:23 PM PDT 24
Peak memory 252996 kb
Host smart-3486752a-1e13-4f08-b6ac-d4783cccc82f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488045123 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.1488045123
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3521511586
Short name T1158
Test name
Test status
Simulation time 11995500 ps
CPU time 15.81 seconds
Started Jun 07 07:43:08 PM PDT 24
Finished Jun 07 07:43:25 PM PDT 24
Peak memory 253064 kb
Host smart-f73262b7-6316-4e27-b324-08218a8c8ba3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521511586 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.3521511586
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3692529985
Short name T255
Test name
Test status
Simulation time 34461100 ps
CPU time 16.26 seconds
Started Jun 07 07:43:06 PM PDT 24
Finished Jun 07 07:43:24 PM PDT 24
Peak memory 263708 kb
Host smart-873fc816-29c0-4e85-8edd-d1ff9c5b0fab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692529985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
3692529985
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3591531680
Short name T396
Test name
Test status
Simulation time 3432777100 ps
CPU time 458.6 seconds
Started Jun 07 07:43:07 PM PDT 24
Finished Jun 07 07:50:47 PM PDT 24
Peak memory 263676 kb
Host smart-c798c7d2-9758-482e-a01d-44cfe1ecdcc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591531680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr
l_tl_intg_err.3591531680
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2788367113
Short name T1163
Test name
Test status
Simulation time 29516700 ps
CPU time 18.48 seconds
Started Jun 07 07:43:06 PM PDT 24
Finished Jun 07 07:43:25 PM PDT 24
Peak memory 278272 kb
Host smart-d4906974-dcc0-4980-b12e-6ac28a896902
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788367113 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.2788367113
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1711960130
Short name T1216
Test name
Test status
Simulation time 27945000 ps
CPU time 16.54 seconds
Started Jun 07 07:43:07 PM PDT 24
Finished Jun 07 07:43:25 PM PDT 24
Peak memory 263628 kb
Host smart-62e8e930-37e5-41b2-9109-8698932e18a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711960130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.1711960130
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2939121523
Short name T1156
Test name
Test status
Simulation time 514389800 ps
CPU time 34.67 seconds
Started Jun 07 07:43:07 PM PDT 24
Finished Jun 07 07:43:43 PM PDT 24
Peak memory 263300 kb
Host smart-5bda734f-c1cf-4e77-8999-bef833938bb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939121523 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.2939121523
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2683133965
Short name T1183
Test name
Test status
Simulation time 11646400 ps
CPU time 15.81 seconds
Started Jun 07 07:43:10 PM PDT 24
Finished Jun 07 07:43:26 PM PDT 24
Peak memory 252784 kb
Host smart-97c8fb34-19e3-4781-bc01-b7d75419e47a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683133965 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.2683133965
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.380658463
Short name T1143
Test name
Test status
Simulation time 25495300 ps
CPU time 15.75 seconds
Started Jun 07 07:43:09 PM PDT 24
Finished Jun 07 07:43:26 PM PDT 24
Peak memory 252852 kb
Host smart-d2085451-21ed-4a9c-919f-0c50c90cb8ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380658463 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.380658463
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.4282838055
Short name T253
Test name
Test status
Simulation time 67274900 ps
CPU time 16.87 seconds
Started Jun 07 07:43:09 PM PDT 24
Finished Jun 07 07:43:26 PM PDT 24
Peak memory 263752 kb
Host smart-76363d84-1a5c-44ab-a7d1-55ff14b71c58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282838055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
4282838055
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2555742339
Short name T286
Test name
Test status
Simulation time 1471629200 ps
CPU time 383.31 seconds
Started Jun 07 07:43:07 PM PDT 24
Finished Jun 07 07:49:31 PM PDT 24
Peak memory 263764 kb
Host smart-fcf8a651-a222-441c-8465-748e2b6f17fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555742339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.2555742339
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.132228405
Short name T1121
Test name
Test status
Simulation time 47393000 ps
CPU time 16.78 seconds
Started Jun 07 07:43:17 PM PDT 24
Finished Jun 07 07:43:36 PM PDT 24
Peak memory 270448 kb
Host smart-7959db66-8d35-4993-8b18-3f94ced76a74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132228405 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.132228405
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.83298849
Short name T279
Test name
Test status
Simulation time 40746600 ps
CPU time 16.26 seconds
Started Jun 07 07:43:18 PM PDT 24
Finished Jun 07 07:43:36 PM PDT 24
Peak memory 261116 kb
Host smart-ee64afce-89d3-46a9-b334-cf9a8be61041
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83298849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 12.flash_ctrl_csr_rw.83298849
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1552000306
Short name T1142
Test name
Test status
Simulation time 28838300 ps
CPU time 13.47 seconds
Started Jun 07 07:43:05 PM PDT 24
Finished Jun 07 07:43:20 PM PDT 24
Peak memory 260896 kb
Host smart-841ee4d2-c1cd-4050-a1bc-949d618a690a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552000306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
1552000306
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.242262535
Short name T1184
Test name
Test status
Simulation time 58445600 ps
CPU time 34.08 seconds
Started Jun 07 07:43:07 PM PDT 24
Finished Jun 07 07:43:42 PM PDT 24
Peak memory 261240 kb
Host smart-3e65559d-317e-49d7-8a9d-5e5a982d4e3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242262535 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.242262535
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.4161168547
Short name T1167
Test name
Test status
Simulation time 37282200 ps
CPU time 15.89 seconds
Started Jun 07 07:43:10 PM PDT 24
Finished Jun 07 07:43:26 PM PDT 24
Peak memory 252908 kb
Host smart-93653de0-2df9-4d38-a9fd-099f0cf4d687
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161168547 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.4161168547
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.127020821
Short name T1111
Test name
Test status
Simulation time 26835500 ps
CPU time 13.08 seconds
Started Jun 07 07:43:09 PM PDT 24
Finished Jun 07 07:43:23 PM PDT 24
Peak memory 252856 kb
Host smart-e22832e5-cb5f-4dba-aa02-c433b3a0f541
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127020821 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.127020821
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2567268942
Short name T216
Test name
Test status
Simulation time 1645406700 ps
CPU time 460.52 seconds
Started Jun 07 07:43:09 PM PDT 24
Finished Jun 07 07:50:50 PM PDT 24
Peak memory 263828 kb
Host smart-bd6bb9e7-23b8-423a-bd14-081d6a2c2398
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567268942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr
l_tl_intg_err.2567268942
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.753806389
Short name T1190
Test name
Test status
Simulation time 95780400 ps
CPU time 17.68 seconds
Started Jun 07 07:43:21 PM PDT 24
Finished Jun 07 07:43:41 PM PDT 24
Peak memory 271948 kb
Host smart-bdf7bb9e-f552-45a2-a744-eb98fa096778
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753806389 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.753806389
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2279960112
Short name T1176
Test name
Test status
Simulation time 242278000 ps
CPU time 17.16 seconds
Started Jun 07 07:43:20 PM PDT 24
Finished Jun 07 07:43:39 PM PDT 24
Peak memory 261520 kb
Host smart-ee338bca-bf1a-4507-95bd-c0172963ae54
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279960112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_csr_rw.2279960112
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3985617791
Short name T277
Test name
Test status
Simulation time 61343700 ps
CPU time 18.92 seconds
Started Jun 07 07:43:16 PM PDT 24
Finished Jun 07 07:43:37 PM PDT 24
Peak memory 263724 kb
Host smart-dbcbdb0b-a05f-4871-8acb-467e9471a19d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985617791 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.3985617791
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2657891856
Short name T1227
Test name
Test status
Simulation time 23997700 ps
CPU time 15.3 seconds
Started Jun 07 07:43:17 PM PDT 24
Finished Jun 07 07:43:35 PM PDT 24
Peak memory 252920 kb
Host smart-834422e1-1057-44ad-8ece-0da1e9cea1b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657891856 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.2657891856
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1419116570
Short name T1218
Test name
Test status
Simulation time 94560700 ps
CPU time 15.88 seconds
Started Jun 07 07:43:15 PM PDT 24
Finished Jun 07 07:43:33 PM PDT 24
Peak memory 253008 kb
Host smart-6492a22d-c10a-4ade-a4d4-e0a9538545d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419116570 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.1419116570
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2530273794
Short name T295
Test name
Test status
Simulation time 56960700 ps
CPU time 20.13 seconds
Started Jun 07 07:43:08 PM PDT 24
Finished Jun 07 07:43:29 PM PDT 24
Peak memory 263724 kb
Host smart-acfc89d9-482b-4399-bf9f-6c0a9bdddca0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530273794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.
2530273794
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.769965221
Short name T1147
Test name
Test status
Simulation time 83293500 ps
CPU time 14.56 seconds
Started Jun 07 07:43:16 PM PDT 24
Finished Jun 07 07:43:32 PM PDT 24
Peak memory 262332 kb
Host smart-603353c3-fcf4-4941-83b7-1ed4d1b46b21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769965221 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.769965221
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3707558091
Short name T333
Test name
Test status
Simulation time 132372600 ps
CPU time 16.43 seconds
Started Jun 07 07:43:21 PM PDT 24
Finished Jun 07 07:43:40 PM PDT 24
Peak memory 260948 kb
Host smart-88cfdd23-9757-48cc-ad66-28d9e6fa5e80
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707558091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.3707558091
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.348155654
Short name T1209
Test name
Test status
Simulation time 56485900 ps
CPU time 13.42 seconds
Started Jun 07 07:43:16 PM PDT 24
Finished Jun 07 07:43:31 PM PDT 24
Peak memory 261064 kb
Host smart-2c81c2ee-02a1-48a3-990e-a75832c26b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348155654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.348155654
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3728105347
Short name T1140
Test name
Test status
Simulation time 124771000 ps
CPU time 19.49 seconds
Started Jun 07 07:43:21 PM PDT 24
Finished Jun 07 07:43:43 PM PDT 24
Peak memory 263636 kb
Host smart-b3dc0bbf-1155-4df8-8db1-5e2061081fbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728105347 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.3728105347
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1753934744
Short name T1109
Test name
Test status
Simulation time 94296500 ps
CPU time 15.71 seconds
Started Jun 07 07:43:17 PM PDT 24
Finished Jun 07 07:43:35 PM PDT 24
Peak memory 252928 kb
Host smart-2ae8615e-40b0-4233-8d42-834425cd3cea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753934744 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.1753934744
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2707021593
Short name T1119
Test name
Test status
Simulation time 39900100 ps
CPU time 15.86 seconds
Started Jun 07 07:43:19 PM PDT 24
Finished Jun 07 07:43:36 PM PDT 24
Peak memory 253060 kb
Host smart-457cdbeb-c90a-4aea-8d5e-60acb4a44126
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707021593 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.2707021593
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3137731568
Short name T1192
Test name
Test status
Simulation time 98337800 ps
CPU time 19.3 seconds
Started Jun 07 07:43:19 PM PDT 24
Finished Jun 07 07:43:40 PM PDT 24
Peak memory 263704 kb
Host smart-49c7e928-1f23-4834-b63c-b3553b611261
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137731568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
3137731568
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3823291229
Short name T302
Test name
Test status
Simulation time 1587378900 ps
CPU time 463.58 seconds
Started Jun 07 07:43:21 PM PDT 24
Finished Jun 07 07:51:07 PM PDT 24
Peak memory 263704 kb
Host smart-5bc7658b-28ca-4798-be18-7302b8f78412
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823291229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.3823291229
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.14769581
Short name T71
Test name
Test status
Simulation time 165284800 ps
CPU time 17.45 seconds
Started Jun 07 07:43:17 PM PDT 24
Finished Jun 07 07:43:36 PM PDT 24
Peak memory 272020 kb
Host smart-0019a312-0f80-4d7a-bad3-6871f37c5a9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14769581 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.14769581
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2384401554
Short name T1165
Test name
Test status
Simulation time 397097400 ps
CPU time 17.51 seconds
Started Jun 07 07:43:18 PM PDT 24
Finished Jun 07 07:43:37 PM PDT 24
Peak memory 261504 kb
Host smart-4fe0fba1-45a0-4582-9924-99d31b3b3acc
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384401554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.2384401554
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3303617376
Short name T1160
Test name
Test status
Simulation time 43650400 ps
CPU time 13.21 seconds
Started Jun 07 07:43:16 PM PDT 24
Finished Jun 07 07:43:31 PM PDT 24
Peak memory 261136 kb
Host smart-8a2fbc42-8124-4137-90ea-f39897fa4a2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303617376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
3303617376
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1013255906
Short name T1177
Test name
Test status
Simulation time 87504800 ps
CPU time 18.87 seconds
Started Jun 07 07:43:20 PM PDT 24
Finished Jun 07 07:43:41 PM PDT 24
Peak memory 263628 kb
Host smart-5ccaecc0-da87-4c1c-ae78-1869297210a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013255906 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.1013255906
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1555299519
Short name T1242
Test name
Test status
Simulation time 20734600 ps
CPU time 13.15 seconds
Started Jun 07 07:43:16 PM PDT 24
Finished Jun 07 07:43:30 PM PDT 24
Peak memory 252928 kb
Host smart-97e9d627-e47d-4fc6-9710-4e8518c3b444
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555299519 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.1555299519
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.4009798094
Short name T1106
Test name
Test status
Simulation time 15865000 ps
CPU time 15.81 seconds
Started Jun 07 07:43:17 PM PDT 24
Finished Jun 07 07:43:35 PM PDT 24
Peak memory 252924 kb
Host smart-2ebd94cf-c312-458d-ad04-ce9f3cb7b692
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009798094 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.4009798094
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1146716176
Short name T290
Test name
Test status
Simulation time 75865600 ps
CPU time 15.98 seconds
Started Jun 07 07:43:17 PM PDT 24
Finished Jun 07 07:43:35 PM PDT 24
Peak memory 263784 kb
Host smart-d7d246e8-0fe5-497d-b5f6-71426fcf43f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146716176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
1146716176
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.865747283
Short name T1153
Test name
Test status
Simulation time 50457400 ps
CPU time 17.31 seconds
Started Jun 07 07:43:27 PM PDT 24
Finished Jun 07 07:43:46 PM PDT 24
Peak memory 272036 kb
Host smart-f5280d0d-9a79-4ff5-b8d5-01ee3eebd8d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865747283 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.865747283
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1287999051
Short name T275
Test name
Test status
Simulation time 32413300 ps
CPU time 17.2 seconds
Started Jun 07 07:43:28 PM PDT 24
Finished Jun 07 07:43:47 PM PDT 24
Peak memory 261108 kb
Host smart-ac3cae8b-90bb-4401-b904-a15cb0790a07
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287999051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.1287999051
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1541334589
Short name T1226
Test name
Test status
Simulation time 15578400 ps
CPU time 14.02 seconds
Started Jun 07 07:43:28 PM PDT 24
Finished Jun 07 07:43:43 PM PDT 24
Peak memory 261100 kb
Host smart-32bd55f5-afac-4fdf-ba35-74547592c4e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541334589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
1541334589
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.451648559
Short name T341
Test name
Test status
Simulation time 203983300 ps
CPU time 36.4 seconds
Started Jun 07 07:43:27 PM PDT 24
Finished Jun 07 07:44:05 PM PDT 24
Peak memory 262960 kb
Host smart-439cc6ce-1f47-4617-a6fa-f5afd2c1f179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451648559 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.451648559
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.246928007
Short name T1240
Test name
Test status
Simulation time 12974000 ps
CPU time 15.55 seconds
Started Jun 07 07:43:15 PM PDT 24
Finished Jun 07 07:43:32 PM PDT 24
Peak memory 252780 kb
Host smart-cdc0d3e2-cdc0-464b-8f55-a69cf8d5a1b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246928007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.246928007
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.980592818
Short name T1141
Test name
Test status
Simulation time 22407500 ps
CPU time 13.08 seconds
Started Jun 07 07:43:25 PM PDT 24
Finished Jun 07 07:43:40 PM PDT 24
Peak memory 252952 kb
Host smart-8098426c-8197-4805-8153-19ce3e59fed8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980592818 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.980592818
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3157248454
Short name T1137
Test name
Test status
Simulation time 28725400 ps
CPU time 17.48 seconds
Started Jun 07 07:43:25 PM PDT 24
Finished Jun 07 07:43:44 PM PDT 24
Peak memory 271992 kb
Host smart-5c96caf3-260f-459b-bfea-82d5be908da3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157248454 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.3157248454
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.345570831
Short name T1157
Test name
Test status
Simulation time 151423900 ps
CPU time 16.69 seconds
Started Jun 07 07:43:27 PM PDT 24
Finished Jun 07 07:43:45 PM PDT 24
Peak memory 263616 kb
Host smart-721b81b5-17aa-4e2e-8bb5-ff1643b81bc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345570831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.flash_ctrl_csr_rw.345570831
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.384532379
Short name T1125
Test name
Test status
Simulation time 80835600 ps
CPU time 13.44 seconds
Started Jun 07 07:43:27 PM PDT 24
Finished Jun 07 07:43:42 PM PDT 24
Peak memory 261224 kb
Host smart-54d231ff-df69-4a60-a7ff-019de0876ce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384532379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.384532379
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1563911069
Short name T1235
Test name
Test status
Simulation time 349463300 ps
CPU time 18.57 seconds
Started Jun 07 07:43:26 PM PDT 24
Finished Jun 07 07:43:46 PM PDT 24
Peak memory 262336 kb
Host smart-f87b6359-6b38-47d5-870c-dec106cb3b45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563911069 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.1563911069
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4089331860
Short name T1144
Test name
Test status
Simulation time 30642000 ps
CPU time 13.53 seconds
Started Jun 07 07:43:25 PM PDT 24
Finished Jun 07 07:43:41 PM PDT 24
Peak memory 252924 kb
Host smart-02fc0af2-f4da-47dd-9bc4-fe975254f97c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089331860 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.4089331860
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1329524081
Short name T1139
Test name
Test status
Simulation time 61270500 ps
CPU time 15.93 seconds
Started Jun 07 07:43:28 PM PDT 24
Finished Jun 07 07:43:45 PM PDT 24
Peak memory 252904 kb
Host smart-f4d9a906-8f52-47b4-bcf6-1669ecc0a82c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329524081 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.1329524081
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4251143085
Short name T298
Test name
Test status
Simulation time 71328400 ps
CPU time 16.63 seconds
Started Jun 07 07:43:29 PM PDT 24
Finished Jun 07 07:43:48 PM PDT 24
Peak memory 263752 kb
Host smart-e8171cc1-334e-47f4-addf-9d20c9ad1020
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251143085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.
4251143085
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2481002037
Short name T397
Test name
Test status
Simulation time 1372421000 ps
CPU time 896.29 seconds
Started Jun 07 07:43:31 PM PDT 24
Finished Jun 07 07:58:29 PM PDT 24
Peak memory 263732 kb
Host smart-0a678534-13cf-4cc7-82dd-3560b8a3b88f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481002037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.2481002037
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.507598406
Short name T1166
Test name
Test status
Simulation time 27385900 ps
CPU time 17.34 seconds
Started Jun 07 07:43:35 PM PDT 24
Finished Jun 07 07:43:55 PM PDT 24
Peak memory 277112 kb
Host smart-6a9ecd05-7390-4ae9-85fe-0a6c7bd79df4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507598406 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.507598406
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4030078773
Short name T1196
Test name
Test status
Simulation time 66849700 ps
CPU time 14.62 seconds
Started Jun 07 07:43:40 PM PDT 24
Finished Jun 07 07:43:57 PM PDT 24
Peak memory 261144 kb
Host smart-465aefb2-bdee-48f3-bb1c-205eace7d743
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030078773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.4030078773
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.400126444
Short name T1131
Test name
Test status
Simulation time 17164200 ps
CPU time 14.05 seconds
Started Jun 07 07:43:34 PM PDT 24
Finished Jun 07 07:43:49 PM PDT 24
Peak memory 260948 kb
Host smart-04d12d26-d1d0-410c-b512-27104c69d808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400126444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.400126444
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1202665047
Short name T337
Test name
Test status
Simulation time 191270700 ps
CPU time 34.87 seconds
Started Jun 07 07:43:38 PM PDT 24
Finished Jun 07 07:44:15 PM PDT 24
Peak memory 263576 kb
Host smart-5cac69d4-5199-4213-87e2-a19ac53520b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202665047 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.1202665047
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.451772706
Short name T1130
Test name
Test status
Simulation time 17983400 ps
CPU time 15.93 seconds
Started Jun 07 07:43:39 PM PDT 24
Finished Jun 07 07:43:57 PM PDT 24
Peak memory 252868 kb
Host smart-2c6b1bd9-a666-4457-852c-9fbf9c66e1ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451772706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.451772706
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2171268989
Short name T1243
Test name
Test status
Simulation time 12875400 ps
CPU time 13.04 seconds
Started Jun 07 07:43:36 PM PDT 24
Finished Jun 07 07:43:52 PM PDT 24
Peak memory 253088 kb
Host smart-8390acfd-22bc-43f9-a033-ae15f08c04d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171268989 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.2171268989
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3620041333
Short name T217
Test name
Test status
Simulation time 168605300 ps
CPU time 16.47 seconds
Started Jun 07 07:43:31 PM PDT 24
Finished Jun 07 07:43:49 PM PDT 24
Peak memory 263748 kb
Host smart-fd970fac-c131-4f99-8919-ab5bb2c5d833
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620041333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
3620041333
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2008672587
Short name T296
Test name
Test status
Simulation time 54339900 ps
CPU time 17.13 seconds
Started Jun 07 07:43:37 PM PDT 24
Finished Jun 07 07:43:56 PM PDT 24
Peak memory 278780 kb
Host smart-145d9b65-2ea5-4867-a375-6c9d57b53db9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008672587 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.2008672587
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1197075989
Short name T1173
Test name
Test status
Simulation time 48317100 ps
CPU time 16.78 seconds
Started Jun 07 07:43:35 PM PDT 24
Finished Jun 07 07:43:54 PM PDT 24
Peak memory 263680 kb
Host smart-c830f4ef-656d-42d9-a4ab-a74d886d1790
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197075989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.1197075989
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.4155608942
Short name T1228
Test name
Test status
Simulation time 115674600 ps
CPU time 16.01 seconds
Started Jun 07 07:43:35 PM PDT 24
Finished Jun 07 07:43:54 PM PDT 24
Peak memory 262452 kb
Host smart-fb78ab59-d38d-48ad-bcf4-413e845e12a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155608942 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.4155608942
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2154605556
Short name T1110
Test name
Test status
Simulation time 19565400 ps
CPU time 15.91 seconds
Started Jun 07 07:43:37 PM PDT 24
Finished Jun 07 07:43:55 PM PDT 24
Peak memory 252900 kb
Host smart-a88448a2-466a-41e7-ad59-1225e0e41419
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154605556 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.2154605556
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2212146255
Short name T1232
Test name
Test status
Simulation time 95415100 ps
CPU time 15.77 seconds
Started Jun 07 07:43:38 PM PDT 24
Finished Jun 07 07:43:56 PM PDT 24
Peak memory 253052 kb
Host smart-3dc67e1c-4918-404a-86db-15320cda6701
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212146255 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2212146255
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.356195302
Short name T292
Test name
Test status
Simulation time 108415700 ps
CPU time 18.97 seconds
Started Jun 07 07:43:39 PM PDT 24
Finished Jun 07 07:44:00 PM PDT 24
Peak memory 263776 kb
Host smart-850069e3-3bb6-4e42-9e3e-0fc1a5363d0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356195302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.356195302
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3003506966
Short name T1199
Test name
Test status
Simulation time 4910637600 ps
CPU time 65.35 seconds
Started Jun 07 07:42:42 PM PDT 24
Finished Jun 07 07:43:49 PM PDT 24
Peak memory 261244 kb
Host smart-09e37c16-6dae-4ef4-a2d3-20404b683f59
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003506966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.3003506966
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1325738124
Short name T1194
Test name
Test status
Simulation time 655314100 ps
CPU time 42.58 seconds
Started Jun 07 07:42:36 PM PDT 24
Finished Jun 07 07:43:20 PM PDT 24
Peak memory 261056 kb
Host smart-6ea05d2c-a214-4995-aa52-722b0f8ce935
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325738124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.1325738124
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2105170132
Short name T249
Test name
Test status
Simulation time 89128800 ps
CPU time 45.98 seconds
Started Jun 07 07:42:42 PM PDT 24
Finished Jun 07 07:43:30 PM PDT 24
Peak memory 261172 kb
Host smart-9a418a9c-c638-4d45-9836-d402ccb69757
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105170132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.2105170132
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.575704159
Short name T1210
Test name
Test status
Simulation time 55333200 ps
CPU time 17.67 seconds
Started Jun 07 07:42:37 PM PDT 24
Finished Jun 07 07:42:57 PM PDT 24
Peak memory 263564 kb
Host smart-77ad88e2-2172-4fee-ae02-78421aa63b0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575704159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_csr_rw.575704159
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3128870809
Short name T1207
Test name
Test status
Simulation time 55174500 ps
CPU time 13.57 seconds
Started Jun 07 07:42:37 PM PDT 24
Finished Jun 07 07:42:52 PM PDT 24
Peak memory 261072 kb
Host smart-b0310f16-bdd9-49c1-948b-c700e2b2f06c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128870809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.3
128870809
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.131245676
Short name T260
Test name
Test status
Simulation time 20436400 ps
CPU time 13.81 seconds
Started Jun 07 07:42:40 PM PDT 24
Finished Jun 07 07:42:57 PM PDT 24
Peak memory 262088 kb
Host smart-5ffef67d-d41f-4f00-b3fb-4fe03b591374
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131245676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_mem_partial_access.131245676
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3389699425
Short name T1116
Test name
Test status
Simulation time 26041500 ps
CPU time 13.33 seconds
Started Jun 07 07:42:38 PM PDT 24
Finished Jun 07 07:42:53 PM PDT 24
Peak memory 261100 kb
Host smart-4ea46fd4-3cbb-4b49-a25d-a9e3aff53086
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389699425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.3389699425
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3381341267
Short name T1126
Test name
Test status
Simulation time 118174800 ps
CPU time 18.03 seconds
Started Jun 07 07:42:40 PM PDT 24
Finished Jun 07 07:43:01 PM PDT 24
Peak memory 262412 kb
Host smart-658754ac-101b-4884-83aa-f903509bf13d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381341267 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.3381341267
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2360469475
Short name T1107
Test name
Test status
Simulation time 22508700 ps
CPU time 16.02 seconds
Started Jun 07 07:42:39 PM PDT 24
Finished Jun 07 07:42:56 PM PDT 24
Peak memory 252936 kb
Host smart-7b166aaa-a51e-4f23-8ae9-ab48a2c2e48d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360469475 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2360469475
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.4033262087
Short name T1112
Test name
Test status
Simulation time 94795400 ps
CPU time 15.69 seconds
Started Jun 07 07:42:38 PM PDT 24
Finished Jun 07 07:42:55 PM PDT 24
Peak memory 252956 kb
Host smart-d498f6a3-c5ce-45c3-bb79-00a9763ba3fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033262087 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.4033262087
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2034092753
Short name T400
Test name
Test status
Simulation time 2697366400 ps
CPU time 901.31 seconds
Started Jun 07 07:42:36 PM PDT 24
Finished Jun 07 07:57:39 PM PDT 24
Peak memory 263640 kb
Host smart-1b7b662f-5741-4832-a678-16744976f3ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034092753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_tl_intg_err.2034092753
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.317830560
Short name T1186
Test name
Test status
Simulation time 14728100 ps
CPU time 13.34 seconds
Started Jun 07 07:43:36 PM PDT 24
Finished Jun 07 07:43:52 PM PDT 24
Peak memory 261040 kb
Host smart-3ba15670-cff0-4fba-889c-06f63f2020c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317830560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.317830560
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.476552651
Short name T1171
Test name
Test status
Simulation time 17263600 ps
CPU time 13.44 seconds
Started Jun 07 07:43:36 PM PDT 24
Finished Jun 07 07:43:52 PM PDT 24
Peak memory 261060 kb
Host smart-4d8ca202-d30d-4096-a377-ab046478a944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476552651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.476552651
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2733352348
Short name T1170
Test name
Test status
Simulation time 43382300 ps
CPU time 13.22 seconds
Started Jun 07 07:43:41 PM PDT 24
Finished Jun 07 07:43:56 PM PDT 24
Peak memory 261168 kb
Host smart-236ded9a-72d6-4a25-a119-85dd764a25d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733352348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
2733352348
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.4156010621
Short name T1169
Test name
Test status
Simulation time 17097100 ps
CPU time 13.18 seconds
Started Jun 07 07:43:41 PM PDT 24
Finished Jun 07 07:43:56 PM PDT 24
Peak memory 261168 kb
Host smart-efa73561-3fc4-463e-9e27-b5558a4d80e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156010621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
4156010621
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1350410977
Short name T1145
Test name
Test status
Simulation time 14460300 ps
CPU time 13.24 seconds
Started Jun 07 07:43:35 PM PDT 24
Finished Jun 07 07:43:51 PM PDT 24
Peak memory 261140 kb
Host smart-45887934-13fa-4ce6-ac35-2bcc783a959d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350410977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.
1350410977
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1905498400
Short name T1172
Test name
Test status
Simulation time 44719200 ps
CPU time 13.25 seconds
Started Jun 07 07:43:35 PM PDT 24
Finished Jun 07 07:43:51 PM PDT 24
Peak memory 261056 kb
Host smart-28279873-6b82-47e9-bf56-0a903ad6de21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905498400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
1905498400
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.3321639551
Short name T1195
Test name
Test status
Simulation time 17302800 ps
CPU time 13.42 seconds
Started Jun 07 07:43:36 PM PDT 24
Finished Jun 07 07:43:52 PM PDT 24
Peak memory 261140 kb
Host smart-f270a3bd-f025-4155-b4ee-dcbf5b62571e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321639551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.
3321639551
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.1007086406
Short name T364
Test name
Test status
Simulation time 27892100 ps
CPU time 13.56 seconds
Started Jun 07 07:43:35 PM PDT 24
Finished Jun 07 07:43:51 PM PDT 24
Peak memory 261092 kb
Host smart-956ed42a-d984-4df7-993f-47d40953f9b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007086406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
1007086406
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1428157278
Short name T291
Test name
Test status
Simulation time 25107300 ps
CPU time 13.53 seconds
Started Jun 07 07:43:35 PM PDT 24
Finished Jun 07 07:43:50 PM PDT 24
Peak memory 261100 kb
Host smart-725b6e7c-7b6e-49c4-a81a-22f5c2e0ac0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428157278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
1428157278
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.2898848795
Short name T1197
Test name
Test status
Simulation time 26861200 ps
CPU time 13.9 seconds
Started Jun 07 07:43:37 PM PDT 24
Finished Jun 07 07:43:53 PM PDT 24
Peak memory 261076 kb
Host smart-cda646b3-ffc6-4faf-b078-94bfd1538443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898848795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
2898848795
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3267372039
Short name T1136
Test name
Test status
Simulation time 9323969400 ps
CPU time 67.09 seconds
Started Jun 07 07:42:47 PM PDT 24
Finished Jun 07 07:43:55 PM PDT 24
Peak memory 261048 kb
Host smart-e1535ac8-5207-4262-881a-48ad3de44a65
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267372039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.3267372039
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3672035635
Short name T1154
Test name
Test status
Simulation time 2772279800 ps
CPU time 72.26 seconds
Started Jun 07 07:42:47 PM PDT 24
Finished Jun 07 07:44:00 PM PDT 24
Peak memory 261192 kb
Host smart-00586fe4-74b5-4f2a-a6c9-41647a211290
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672035635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.3672035635
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2175148730
Short name T70
Test name
Test status
Simulation time 47463500 ps
CPU time 45.42 seconds
Started Jun 07 07:42:47 PM PDT 24
Finished Jun 07 07:43:34 PM PDT 24
Peak memory 261272 kb
Host smart-ad6e4770-e64d-44ef-a951-0e55fda62099
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175148730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.2175148730
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4178536524
Short name T246
Test name
Test status
Simulation time 41633500 ps
CPU time 18.72 seconds
Started Jun 07 07:42:54 PM PDT 24
Finished Jun 07 07:43:14 PM PDT 24
Peak memory 271712 kb
Host smart-4ab6915f-7379-4625-b6d0-2f8004342cf0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178536524 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.4178536524
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.204323570
Short name T276
Test name
Test status
Simulation time 37321100 ps
CPU time 16.17 seconds
Started Jun 07 07:42:44 PM PDT 24
Finished Jun 07 07:43:02 PM PDT 24
Peak memory 263668 kb
Host smart-912f0b4f-a6ed-4f2d-918a-9534b890a605
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204323570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_csr_rw.204323570
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1049710070
Short name T1198
Test name
Test status
Simulation time 17986800 ps
CPU time 13.56 seconds
Started Jun 07 07:42:37 PM PDT 24
Finished Jun 07 07:42:52 PM PDT 24
Peak memory 261080 kb
Host smart-3025a831-3ad3-449e-b51b-60b05fe57000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049710070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.1
049710070
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2383551430
Short name T259
Test name
Test status
Simulation time 24156400 ps
CPU time 13.51 seconds
Started Jun 07 07:42:48 PM PDT 24
Finished Jun 07 07:43:02 PM PDT 24
Peak memory 262056 kb
Host smart-5e238311-a746-4112-b07a-71e9a666a113
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383551430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.2383551430
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1239055391
Short name T1117
Test name
Test status
Simulation time 15429400 ps
CPU time 13.48 seconds
Started Jun 07 07:42:39 PM PDT 24
Finished Jun 07 07:42:55 PM PDT 24
Peak memory 260948 kb
Host smart-0292a007-14ac-4e56-af53-f1d4506ffa8f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239055391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.1239055391
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3603909752
Short name T338
Test name
Test status
Simulation time 205704200 ps
CPU time 20.63 seconds
Started Jun 07 07:42:45 PM PDT 24
Finished Jun 07 07:43:07 PM PDT 24
Peak memory 262984 kb
Host smart-09c3c50b-7621-4bd7-95fe-3a76628f30d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603909752 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.3603909752
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2212058929
Short name T1114
Test name
Test status
Simulation time 28953800 ps
CPU time 13.19 seconds
Started Jun 07 07:42:38 PM PDT 24
Finished Jun 07 07:42:53 PM PDT 24
Peak memory 252912 kb
Host smart-57ebf329-8acc-467c-acad-5deecf40f243
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212058929 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.2212058929
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2084843036
Short name T1161
Test name
Test status
Simulation time 33303200 ps
CPU time 15.89 seconds
Started Jun 07 07:42:37 PM PDT 24
Finished Jun 07 07:42:55 PM PDT 24
Peak memory 252940 kb
Host smart-b3588ad3-1de6-4b05-a007-f37e56500e2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084843036 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.2084843036
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.950169462
Short name T1219
Test name
Test status
Simulation time 65583400 ps
CPU time 20.87 seconds
Started Jun 07 07:42:37 PM PDT 24
Finished Jun 07 07:42:59 PM PDT 24
Peak memory 263760 kb
Host smart-cbc001a6-c3eb-45dd-933c-8371723ef3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950169462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.950169462
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3657312244
Short name T401
Test name
Test status
Simulation time 176933400 ps
CPU time 385.55 seconds
Started Jun 07 07:42:38 PM PDT 24
Finished Jun 07 07:49:05 PM PDT 24
Peak memory 263760 kb
Host smart-7eb50c51-b389-4975-b02a-01e64afdc5a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657312244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.3657312244
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1474742170
Short name T1208
Test name
Test status
Simulation time 57418700 ps
CPU time 13.18 seconds
Started Jun 07 07:43:40 PM PDT 24
Finished Jun 07 07:43:56 PM PDT 24
Peak memory 261100 kb
Host smart-994c9065-b342-46de-8599-94b72db75586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474742170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.
1474742170
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2967113860
Short name T392
Test name
Test status
Simulation time 17564800 ps
CPU time 13.37 seconds
Started Jun 07 07:43:34 PM PDT 24
Finished Jun 07 07:43:48 PM PDT 24
Peak memory 261148 kb
Host smart-17266c9f-689f-4103-9428-3b22a7eec2d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967113860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
2967113860
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.4008994286
Short name T1181
Test name
Test status
Simulation time 50744400 ps
CPU time 13.23 seconds
Started Jun 07 07:43:35 PM PDT 24
Finished Jun 07 07:43:51 PM PDT 24
Peak memory 261132 kb
Host smart-46d51163-3e8a-4eef-b8a5-6db76ceb3951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008994286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
4008994286
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1566505716
Short name T1239
Test name
Test status
Simulation time 31743400 ps
CPU time 13.21 seconds
Started Jun 07 07:43:35 PM PDT 24
Finished Jun 07 07:43:50 PM PDT 24
Peak memory 260956 kb
Host smart-8b3b77a1-77a4-4c1e-b8a3-e4a580ad3666
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566505716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.
1566505716
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2396889097
Short name T1175
Test name
Test status
Simulation time 49128500 ps
CPU time 13.35 seconds
Started Jun 07 07:43:35 PM PDT 24
Finished Jun 07 07:43:49 PM PDT 24
Peak memory 261060 kb
Host smart-56658b0b-bef0-468e-8a6d-f34a71a9915c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396889097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
2396889097
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3858895747
Short name T371
Test name
Test status
Simulation time 15911000 ps
CPU time 13.78 seconds
Started Jun 07 07:43:38 PM PDT 24
Finished Jun 07 07:43:54 PM PDT 24
Peak memory 261072 kb
Host smart-1cbfdfce-d858-43d7-a66a-8f5b580bbcfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858895747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
3858895747
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3910914823
Short name T1146
Test name
Test status
Simulation time 32074900 ps
CPU time 13.64 seconds
Started Jun 07 07:43:50 PM PDT 24
Finished Jun 07 07:44:06 PM PDT 24
Peak memory 261164 kb
Host smart-a79c0d7d-567e-4d26-92c3-a810a54d28cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910914823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
3910914823
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1658092496
Short name T1155
Test name
Test status
Simulation time 54867000 ps
CPU time 13.14 seconds
Started Jun 07 07:43:49 PM PDT 24
Finished Jun 07 07:44:04 PM PDT 24
Peak memory 261024 kb
Host smart-14eac8d6-06b0-461c-8a06-6c6743f7a076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658092496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
1658092496
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.2888474997
Short name T1159
Test name
Test status
Simulation time 46155900 ps
CPU time 13.43 seconds
Started Jun 07 07:43:45 PM PDT 24
Finished Jun 07 07:44:00 PM PDT 24
Peak memory 260956 kb
Host smart-23ffbe68-64dc-4e5a-9e45-068c4305c325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888474997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
2888474997
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.950025432
Short name T1205
Test name
Test status
Simulation time 112098500 ps
CPU time 13.27 seconds
Started Jun 07 07:43:45 PM PDT 24
Finished Jun 07 07:44:00 PM PDT 24
Peak memory 261160 kb
Host smart-60bdd13b-b583-4544-b1c4-95f29ad6281b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950025432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.950025432
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.4149897346
Short name T332
Test name
Test status
Simulation time 1631159800 ps
CPU time 40.05 seconds
Started Jun 07 07:42:55 PM PDT 24
Finished Jun 07 07:43:36 PM PDT 24
Peak memory 260952 kb
Host smart-45aa2488-9d18-4c60-89a3-bb35b6be505a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149897346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_aliasing.4149897346
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.4173044283
Short name T1168
Test name
Test status
Simulation time 1316948300 ps
CPU time 63.15 seconds
Started Jun 07 07:42:58 PM PDT 24
Finished Jun 07 07:44:03 PM PDT 24
Peak memory 261140 kb
Host smart-97989e0b-eac1-4b9a-b734-3b55755a4f4d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173044283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.4173044283
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2527565865
Short name T1179
Test name
Test status
Simulation time 35802800 ps
CPU time 25.93 seconds
Started Jun 07 07:42:54 PM PDT 24
Finished Jun 07 07:43:22 PM PDT 24
Peak memory 262864 kb
Host smart-c849c508-9dbc-4819-87e0-90cf43e392dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527565865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_hw_reset.2527565865
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1968861857
Short name T299
Test name
Test status
Simulation time 205441700 ps
CPU time 19.43 seconds
Started Jun 07 07:42:57 PM PDT 24
Finished Jun 07 07:43:17 PM PDT 24
Peak memory 277448 kb
Host smart-e69cf300-ecd0-4a8b-99fa-979434778791
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968861857 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.1968861857
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3264913235
Short name T1220
Test name
Test status
Simulation time 129969200 ps
CPU time 17.45 seconds
Started Jun 07 07:42:46 PM PDT 24
Finished Jun 07 07:43:05 PM PDT 24
Peak memory 263664 kb
Host smart-e3339269-aff3-4164-8ad0-d320dae9d5e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264913235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.3264913235
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3849544968
Short name T1162
Test name
Test status
Simulation time 16513700 ps
CPU time 13.74 seconds
Started Jun 07 07:42:47 PM PDT 24
Finished Jun 07 07:43:01 PM PDT 24
Peak memory 261112 kb
Host smart-46a001e1-5801-4982-a6fe-0a71f6a5bd1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849544968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.3
849544968
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2536900248
Short name T262
Test name
Test status
Simulation time 42171500 ps
CPU time 13.75 seconds
Started Jun 07 07:42:47 PM PDT 24
Finished Jun 07 07:43:02 PM PDT 24
Peak memory 262852 kb
Host smart-9b4b3b09-e974-4f13-aeff-ed067c86337c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536900248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_mem_partial_access.2536900248
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.129745956
Short name T1128
Test name
Test status
Simulation time 17188400 ps
CPU time 13.31 seconds
Started Jun 07 07:42:47 PM PDT 24
Finished Jun 07 07:43:02 PM PDT 24
Peak memory 261064 kb
Host smart-eab507a5-ce83-4010-b0b4-ad2feee08613
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129745956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem
_walk.129745956
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1028308536
Short name T1150
Test name
Test status
Simulation time 228641400 ps
CPU time 28.66 seconds
Started Jun 07 07:42:57 PM PDT 24
Finished Jun 07 07:43:27 PM PDT 24
Peak memory 262484 kb
Host smart-9ac3f10b-6cec-42f2-bf30-73f2d3f02be3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028308536 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.1028308536
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2438550118
Short name T1244
Test name
Test status
Simulation time 14159600 ps
CPU time 15.78 seconds
Started Jun 07 07:42:47 PM PDT 24
Finished Jun 07 07:43:04 PM PDT 24
Peak memory 253020 kb
Host smart-af3f31c7-84c4-4dd1-9e01-1af80be3627a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438550118 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.2438550118
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.718642271
Short name T1233
Test name
Test status
Simulation time 13342200 ps
CPU time 15.59 seconds
Started Jun 07 07:42:45 PM PDT 24
Finished Jun 07 07:43:02 PM PDT 24
Peak memory 252812 kb
Host smart-786c39e3-7287-4480-9972-db97d5838691
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718642271 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.718642271
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2234372209
Short name T254
Test name
Test status
Simulation time 205588800 ps
CPU time 18.82 seconds
Started Jun 07 07:42:46 PM PDT 24
Finished Jun 07 07:43:06 PM PDT 24
Peak memory 263672 kb
Host smart-759ee137-8b6e-4402-942d-a5614af11a86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234372209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.2
234372209
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1266309325
Short name T301
Test name
Test status
Simulation time 8560801900 ps
CPU time 909.79 seconds
Started Jun 07 07:42:45 PM PDT 24
Finished Jun 07 07:57:56 PM PDT 24
Peak memory 263760 kb
Host smart-40f1a09e-f3a4-453c-9abf-30f2688bd1cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266309325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.1266309325
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1197719840
Short name T1134
Test name
Test status
Simulation time 15647100 ps
CPU time 13.4 seconds
Started Jun 07 07:43:47 PM PDT 24
Finished Jun 07 07:44:02 PM PDT 24
Peak memory 261012 kb
Host smart-63360193-aeac-42ba-9a0f-6848e0ac6396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197719840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
1197719840
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1006176854
Short name T1238
Test name
Test status
Simulation time 54479500 ps
CPU time 13.54 seconds
Started Jun 07 07:43:47 PM PDT 24
Finished Jun 07 07:44:03 PM PDT 24
Peak memory 261204 kb
Host smart-4d1b25d9-36a5-4bc8-8202-f93e95aeaa6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006176854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
1006176854
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.531561282
Short name T1182
Test name
Test status
Simulation time 47979200 ps
CPU time 13.18 seconds
Started Jun 07 07:43:49 PM PDT 24
Finished Jun 07 07:44:05 PM PDT 24
Peak memory 261156 kb
Host smart-98581aaf-578a-4a3a-b6b2-0c424cf3f5d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531561282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.531561282
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.59846629
Short name T369
Test name
Test status
Simulation time 31971200 ps
CPU time 13.1 seconds
Started Jun 07 07:43:48 PM PDT 24
Finished Jun 07 07:44:03 PM PDT 24
Peak memory 261028 kb
Host smart-63e6fb97-4eb3-4d47-ac68-619ac1e0ab11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59846629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.59846629
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.3677567540
Short name T1193
Test name
Test status
Simulation time 112258100 ps
CPU time 13.38 seconds
Started Jun 07 07:43:45 PM PDT 24
Finished Jun 07 07:44:00 PM PDT 24
Peak memory 261172 kb
Host smart-41c775d4-9897-4375-b709-c921c9902139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677567540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
3677567540
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1289927114
Short name T1245
Test name
Test status
Simulation time 17624200 ps
CPU time 13.41 seconds
Started Jun 07 07:43:50 PM PDT 24
Finished Jun 07 07:44:05 PM PDT 24
Peak memory 261092 kb
Host smart-d2fe4d3a-8810-4100-9e68-4b44604e54dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289927114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
1289927114
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3798561916
Short name T1234
Test name
Test status
Simulation time 80746900 ps
CPU time 13.46 seconds
Started Jun 07 07:43:50 PM PDT 24
Finished Jun 07 07:44:06 PM PDT 24
Peak memory 261096 kb
Host smart-3bc8843a-f017-471c-9478-4622ab8ab9eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798561916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
3798561916
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3792696255
Short name T1185
Test name
Test status
Simulation time 25708600 ps
CPU time 13.46 seconds
Started Jun 07 07:43:50 PM PDT 24
Finished Jun 07 07:44:06 PM PDT 24
Peak memory 261164 kb
Host smart-556eb99a-51e6-46c8-8148-f8892336495f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792696255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
3792696255
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2991199648
Short name T367
Test name
Test status
Simulation time 14681100 ps
CPU time 13.33 seconds
Started Jun 07 07:43:44 PM PDT 24
Finished Jun 07 07:43:59 PM PDT 24
Peak memory 261224 kb
Host smart-3a0418d6-d4a5-4903-bdd6-e44b641d04fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991199648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
2991199648
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.1482230107
Short name T1188
Test name
Test status
Simulation time 56521300 ps
CPU time 13.43 seconds
Started Jun 07 07:43:44 PM PDT 24
Finished Jun 07 07:43:59 PM PDT 24
Peak memory 261076 kb
Host smart-38670ef7-3560-4cd5-bf72-9ae6793c887c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482230107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
1482230107
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4129079160
Short name T393
Test name
Test status
Simulation time 397338600 ps
CPU time 19.29 seconds
Started Jun 07 07:42:55 PM PDT 24
Finished Jun 07 07:43:15 PM PDT 24
Peak memory 278712 kb
Host smart-973be3b0-ca9b-4b23-8b9b-7f75e2291bab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129079160 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.4129079160
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1673689265
Short name T1127
Test name
Test status
Simulation time 21605700 ps
CPU time 14.45 seconds
Started Jun 07 07:42:56 PM PDT 24
Finished Jun 07 07:43:12 PM PDT 24
Peak memory 261176 kb
Host smart-bfdcd51e-4d81-4d23-b4f6-cf15cb09cfea
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673689265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.1673689265
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.164637192
Short name T1122
Test name
Test status
Simulation time 40505800 ps
CPU time 13.56 seconds
Started Jun 07 07:42:56 PM PDT 24
Finished Jun 07 07:43:11 PM PDT 24
Peak memory 261224 kb
Host smart-2324af3d-5a88-417c-9527-4f13b86fa3d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164637192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.164637192
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3833766808
Short name T1191
Test name
Test status
Simulation time 36981300 ps
CPU time 17.81 seconds
Started Jun 07 07:42:55 PM PDT 24
Finished Jun 07 07:43:14 PM PDT 24
Peak memory 263736 kb
Host smart-fbf5ee6b-dbbc-49ca-b2b4-3118c8276e4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833766808 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.3833766808
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2811356741
Short name T1187
Test name
Test status
Simulation time 15033500 ps
CPU time 13.48 seconds
Started Jun 07 07:42:58 PM PDT 24
Finished Jun 07 07:43:13 PM PDT 24
Peak memory 252920 kb
Host smart-e065f1e8-d711-41be-9806-5fe49d03c0a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811356741 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.2811356741
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1726517509
Short name T1201
Test name
Test status
Simulation time 70166700 ps
CPU time 13.24 seconds
Started Jun 07 07:42:55 PM PDT 24
Finished Jun 07 07:43:09 PM PDT 24
Peak memory 252944 kb
Host smart-b01aae7c-fbd9-4899-bbb9-c6e25471806d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726517509 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.1726517509
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4000674172
Short name T1236
Test name
Test status
Simulation time 106539400 ps
CPU time 19.85 seconds
Started Jun 07 07:42:59 PM PDT 24
Finished Jun 07 07:43:20 PM PDT 24
Peak memory 262940 kb
Host smart-575e5ece-f4a8-43c5-9523-55ebf5f61897
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000674172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.4
000674172
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.869768000
Short name T1178
Test name
Test status
Simulation time 81830600 ps
CPU time 17.39 seconds
Started Jun 07 07:42:57 PM PDT 24
Finished Jun 07 07:43:16 PM PDT 24
Peak memory 263800 kb
Host smart-96d20979-1247-44d2-802a-b9964e3e3cc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869768000 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.869768000
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3655487179
Short name T1224
Test name
Test status
Simulation time 25729900 ps
CPU time 17.3 seconds
Started Jun 07 07:42:56 PM PDT 24
Finished Jun 07 07:43:15 PM PDT 24
Peak memory 263668 kb
Host smart-fc2147e0-c0ae-4970-8e90-98b48032f128
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655487179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.3655487179
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2149167624
Short name T1174
Test name
Test status
Simulation time 48111500 ps
CPU time 13.45 seconds
Started Jun 07 07:42:58 PM PDT 24
Finished Jun 07 07:43:13 PM PDT 24
Peak memory 261024 kb
Host smart-e299d903-6351-48a5-8fe1-863d370147c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149167624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.2
149167624
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2983024016
Short name T1211
Test name
Test status
Simulation time 529977300 ps
CPU time 18.38 seconds
Started Jun 07 07:42:56 PM PDT 24
Finished Jun 07 07:43:16 PM PDT 24
Peak memory 263700 kb
Host smart-92377d5e-5644-4f40-b8ba-2f5e1225addc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983024016 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.2983024016
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3733886293
Short name T1222
Test name
Test status
Simulation time 24260000 ps
CPU time 15.48 seconds
Started Jun 07 07:42:56 PM PDT 24
Finished Jun 07 07:43:13 PM PDT 24
Peak memory 253000 kb
Host smart-a503c584-820c-4417-b5c4-5c98d536a41b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733886293 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.3733886293
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2904749259
Short name T1206
Test name
Test status
Simulation time 13569500 ps
CPU time 13.46 seconds
Started Jun 07 07:42:57 PM PDT 24
Finished Jun 07 07:43:12 PM PDT 24
Peak memory 252948 kb
Host smart-d94c95dc-8de1-45dd-8931-abe876dbdc22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904749259 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.2904749259
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2796012846
Short name T252
Test name
Test status
Simulation time 36654800 ps
CPU time 16.19 seconds
Started Jun 07 07:42:56 PM PDT 24
Finished Jun 07 07:43:14 PM PDT 24
Peak memory 263664 kb
Host smart-8ac70c43-c3d6-4abd-8264-2c0e5797e2dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796012846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.2
796012846
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3028907960
Short name T394
Test name
Test status
Simulation time 1265842300 ps
CPU time 383.31 seconds
Started Jun 07 07:42:56 PM PDT 24
Finished Jun 07 07:49:20 PM PDT 24
Peak memory 263780 kb
Host smart-8642e698-0b55-405e-a897-c1b361234ea9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028907960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.3028907960
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2270664340
Short name T1189
Test name
Test status
Simulation time 193501900 ps
CPU time 15.08 seconds
Started Jun 07 07:43:07 PM PDT 24
Finished Jun 07 07:43:23 PM PDT 24
Peak memory 263876 kb
Host smart-68a6adcd-9513-47e1-97e0-71bf74c0dd28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270664340 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.2270664340
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3523690772
Short name T1229
Test name
Test status
Simulation time 30977400 ps
CPU time 16.63 seconds
Started Jun 07 07:42:56 PM PDT 24
Finished Jun 07 07:43:14 PM PDT 24
Peak memory 261128 kb
Host smart-2a0228ae-fbf9-4bc9-8292-0dbf964cd343
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523690772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_csr_rw.3523690772
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3370619237
Short name T1164
Test name
Test status
Simulation time 53835200 ps
CPU time 13.26 seconds
Started Jun 07 07:42:56 PM PDT 24
Finished Jun 07 07:43:11 PM PDT 24
Peak memory 261160 kb
Host smart-9c13c081-ca44-431b-9315-b98b6989b518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370619237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.3
370619237
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3103312521
Short name T1241
Test name
Test status
Simulation time 109144400 ps
CPU time 15.22 seconds
Started Jun 07 07:42:58 PM PDT 24
Finished Jun 07 07:43:15 PM PDT 24
Peak memory 261228 kb
Host smart-7d546a20-1c1c-4fe0-9a3d-f6088c7173be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103312521 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.3103312521
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1889222825
Short name T1223
Test name
Test status
Simulation time 15775100 ps
CPU time 15.75 seconds
Started Jun 07 07:42:57 PM PDT 24
Finished Jun 07 07:43:14 PM PDT 24
Peak memory 252924 kb
Host smart-f9b3282d-3a6b-4b9f-86b3-5a2256e5a01e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889222825 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.1889222825
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1683611778
Short name T1202
Test name
Test status
Simulation time 42132500 ps
CPU time 15.56 seconds
Started Jun 07 07:42:59 PM PDT 24
Finished Jun 07 07:43:16 PM PDT 24
Peak memory 252824 kb
Host smart-6fc77472-c540-45c5-bb08-6cad1bb4d6cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683611778 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.1683611778
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.241001040
Short name T256
Test name
Test status
Simulation time 753007300 ps
CPU time 19.85 seconds
Started Jun 07 07:42:57 PM PDT 24
Finished Jun 07 07:43:19 PM PDT 24
Peak memory 262896 kb
Host smart-3521ed5a-6a8f-4356-8c0c-99c0e85f323a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241001040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.241001040
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1688495604
Short name T1200
Test name
Test status
Simulation time 24351400 ps
CPU time 17.25 seconds
Started Jun 07 07:43:06 PM PDT 24
Finished Jun 07 07:43:24 PM PDT 24
Peak memory 272012 kb
Host smart-04a3e55a-e286-4f3d-8454-8b382994ab90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688495604 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.1688495604
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1077092871
Short name T1221
Test name
Test status
Simulation time 21534900 ps
CPU time 16.46 seconds
Started Jun 07 07:43:07 PM PDT 24
Finished Jun 07 07:43:25 PM PDT 24
Peak memory 263652 kb
Host smart-1c61a7c8-567c-4981-8429-8c46645ba914
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077092871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.1077092871
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3826551732
Short name T370
Test name
Test status
Simulation time 109084100 ps
CPU time 13.47 seconds
Started Jun 07 07:43:06 PM PDT 24
Finished Jun 07 07:43:21 PM PDT 24
Peak memory 260972 kb
Host smart-e1679cf8-b489-40aa-8efd-5b40b85aa5b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826551732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.3
826551732
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.339212175
Short name T342
Test name
Test status
Simulation time 3511886600 ps
CPU time 38.05 seconds
Started Jun 07 07:43:06 PM PDT 24
Finished Jun 07 07:43:46 PM PDT 24
Peak memory 261224 kb
Host smart-6063c3d7-8053-4c0e-94b3-7c97eb3b6076
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339212175 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.339212175
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1877304135
Short name T1113
Test name
Test status
Simulation time 20020900 ps
CPU time 13.16 seconds
Started Jun 07 07:43:05 PM PDT 24
Finished Jun 07 07:43:19 PM PDT 24
Peak memory 253008 kb
Host smart-9bb4ac49-4ae6-489a-ba8a-b73cdd0e62ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877304135 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.1877304135
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1462097596
Short name T1151
Test name
Test status
Simulation time 12186400 ps
CPU time 12.97 seconds
Started Jun 07 07:43:16 PM PDT 24
Finished Jun 07 07:43:31 PM PDT 24
Peak memory 252876 kb
Host smart-7144b274-94a9-4e6a-ba97-0f088f7bbd8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462097596 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.1462097596
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3793742224
Short name T1237
Test name
Test status
Simulation time 109776300 ps
CPU time 19.19 seconds
Started Jun 07 07:43:16 PM PDT 24
Finished Jun 07 07:43:37 PM PDT 24
Peak memory 263696 kb
Host smart-512e0dab-bf08-48cc-8181-e3af09d8cb86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793742224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3
793742224
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.4281404835
Short name T399
Test name
Test status
Simulation time 1151168000 ps
CPU time 461.47 seconds
Started Jun 07 07:43:09 PM PDT 24
Finished Jun 07 07:50:51 PM PDT 24
Peak memory 263740 kb
Host smart-c0fcb85f-865d-411b-b67a-2915bbfb7956
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281404835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.4281404835
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.673266174
Short name T1214
Test name
Test status
Simulation time 108042000 ps
CPU time 21.5 seconds
Started Jun 07 07:43:09 PM PDT 24
Finished Jun 07 07:43:31 PM PDT 24
Peak memory 270700 kb
Host smart-b418c567-61b6-4275-b016-76cb5823f49c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673266174 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.673266174
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1804137891
Short name T1149
Test name
Test status
Simulation time 105262800 ps
CPU time 13.88 seconds
Started Jun 07 07:43:07 PM PDT 24
Finished Jun 07 07:43:22 PM PDT 24
Peak memory 263632 kb
Host smart-721a9c41-4637-4310-9e80-f9d9e758c419
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804137891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.1804137891
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.663069117
Short name T365
Test name
Test status
Simulation time 52187700 ps
CPU time 13.53 seconds
Started Jun 07 07:43:06 PM PDT 24
Finished Jun 07 07:43:21 PM PDT 24
Peak memory 261092 kb
Host smart-fa8c5a35-7607-48d9-ac91-e7360082f7d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663069117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.663069117
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.917423870
Short name T1203
Test name
Test status
Simulation time 2647127900 ps
CPU time 21.77 seconds
Started Jun 07 07:43:08 PM PDT 24
Finished Jun 07 07:43:31 PM PDT 24
Peak memory 263552 kb
Host smart-eee5c2f2-9274-406b-aedc-8a9a42d60f50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917423870 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.917423870
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.902490719
Short name T1217
Test name
Test status
Simulation time 36701200 ps
CPU time 16.27 seconds
Started Jun 07 07:43:07 PM PDT 24
Finished Jun 07 07:43:24 PM PDT 24
Peak memory 252920 kb
Host smart-3c1649f9-dae2-4540-a1c2-32da8f838926
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902490719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.902490719
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3334669003
Short name T1230
Test name
Test status
Simulation time 15127100 ps
CPU time 15.72 seconds
Started Jun 07 07:43:05 PM PDT 24
Finished Jun 07 07:43:22 PM PDT 24
Peak memory 252944 kb
Host smart-eee89a61-ea13-47e7-8737-39a969aa7a2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334669003 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.3334669003
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3940964895
Short name T303
Test name
Test status
Simulation time 32494900 ps
CPU time 15.45 seconds
Started Jun 07 07:43:06 PM PDT 24
Finished Jun 07 07:43:22 PM PDT 24
Peak memory 263772 kb
Host smart-e9d78281-b644-4672-b6a1-2c2e492cb12d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940964895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.3
940964895
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2069185432
Short name T395
Test name
Test status
Simulation time 340345600 ps
CPU time 386.33 seconds
Started Jun 07 07:43:11 PM PDT 24
Finished Jun 07 07:49:37 PM PDT 24
Peak memory 263700 kb
Host smart-460c2502-3abb-4ea5-994e-e7ccd319bce9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069185432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl
_tl_intg_err.2069185432
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.3121488020
Short name T683
Test name
Test status
Simulation time 35806300 ps
CPU time 13.75 seconds
Started Jun 07 06:58:59 PM PDT 24
Finished Jun 07 06:59:13 PM PDT 24
Peak memory 258584 kb
Host smart-96ec938d-f7f4-41ab-af07-06129b8d06e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121488020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.3
121488020
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.2694582338
Short name T1049
Test name
Test status
Simulation time 86819300 ps
CPU time 16.37 seconds
Started Jun 07 06:58:46 PM PDT 24
Finished Jun 07 06:59:03 PM PDT 24
Peak memory 284472 kb
Host smart-ff7d6280-4f5e-48c8-8b3f-421203eb62b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694582338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2694582338
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.282498430
Short name T1081
Test name
Test status
Simulation time 141053100 ps
CPU time 101.68 seconds
Started Jun 07 06:58:45 PM PDT 24
Finished Jun 07 07:00:28 PM PDT 24
Peak memory 275092 kb
Host smart-4d7da937-2f87-4791-b599-693b273774cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282498430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_derr_detect.282498430
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.3747305169
Short name T939
Test name
Test status
Simulation time 2088998900 ps
CPU time 397.15 seconds
Started Jun 07 06:58:30 PM PDT 24
Finished Jun 07 07:05:08 PM PDT 24
Peak memory 263688 kb
Host smart-caff6413-4865-4bec-b062-c50b361eeda9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3747305169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.3747305169
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.2710208741
Short name T630
Test name
Test status
Simulation time 203571600 ps
CPU time 99.07 seconds
Started Jun 07 06:58:35 PM PDT 24
Finished Jun 07 07:00:15 PM PDT 24
Peak memory 265648 kb
Host smart-fef57730-a5e3-4a24-805c-dc0fdd5c4b28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2710208741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2710208741
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.1109888574
Short name T84
Test name
Test status
Simulation time 339464439900 ps
CPU time 1891.06 seconds
Started Jun 07 06:58:31 PM PDT 24
Finished Jun 07 07:30:03 PM PDT 24
Peak memory 264264 kb
Host smart-b0049137-f144-496d-848f-2e17ca42e794
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109888574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.1109888574
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.4238958737
Short name T169
Test name
Test status
Simulation time 180187999500 ps
CPU time 816.28 seconds
Started Jun 07 06:58:39 PM PDT 24
Finished Jun 07 07:12:16 PM PDT 24
Peak memory 264228 kb
Host smart-8d1732c3-f6c2-43ef-8ba0-cdd2a30e3d81
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238958737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.4238958737
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.1205085559
Short name T978
Test name
Test status
Simulation time 942787400 ps
CPU time 40.33 seconds
Started Jun 07 06:58:29 PM PDT 24
Finished Jun 07 06:59:10 PM PDT 24
Peak memory 262896 kb
Host smart-d005ba97-1c70-4246-a46b-18a284f8b90a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205085559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.1205085559
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.1283083421
Short name T273
Test name
Test status
Simulation time 4401808400 ps
CPU time 613.75 seconds
Started Jun 07 06:58:45 PM PDT 24
Finished Jun 07 07:08:59 PM PDT 24
Peak memory 330552 kb
Host smart-58e11a0c-b9fd-439a-8880-04d4efc556ed
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283083421 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_integrity.1283083421
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.2046182009
Short name T1028
Test name
Test status
Simulation time 2534293500 ps
CPU time 126.49 seconds
Started Jun 07 06:58:46 PM PDT 24
Finished Jun 07 07:00:53 PM PDT 24
Peak memory 294436 kb
Host smart-70bf6b54-c69b-43ec-840c-dc4695368d69
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046182009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_intr_rd.2046182009
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.1610374497
Short name T686
Test name
Test status
Simulation time 56058725100 ps
CPU time 148.03 seconds
Started Jun 07 06:58:48 PM PDT 24
Finished Jun 07 07:01:17 PM PDT 24
Peak memory 293088 kb
Host smart-1125132a-1a4a-4f50-8417-b78988f78389
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610374497 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.1610374497
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.4103236856
Short name T500
Test name
Test status
Simulation time 10977888000 ps
CPU time 76.43 seconds
Started Jun 07 06:58:46 PM PDT 24
Finished Jun 07 07:00:03 PM PDT 24
Peak memory 260196 kb
Host smart-32bfcf49-8007-47be-b8aa-2c48b7f45799
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103236856 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.4103236856
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.1704557647
Short name T547
Test name
Test status
Simulation time 73683505300 ps
CPU time 230.77 seconds
Started Jun 07 06:58:45 PM PDT 24
Finished Jun 07 07:02:37 PM PDT 24
Peak memory 260600 kb
Host smart-ba00b3af-9dba-463a-8003-7766b7e43447
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170
4557647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.1704557647
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.1457583879
Short name T117
Test name
Test status
Simulation time 11238269100 ps
CPU time 70.81 seconds
Started Jun 07 06:58:37 PM PDT 24
Finished Jun 07 06:59:49 PM PDT 24
Peak memory 260748 kb
Host smart-1cb0fb51-05f1-4874-bbd2-40a2b7ce2f9d
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457583879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.1457583879
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.3531491716
Short name T950
Test name
Test status
Simulation time 43885400 ps
CPU time 13.45 seconds
Started Jun 07 06:58:54 PM PDT 24
Finished Jun 07 06:59:08 PM PDT 24
Peak memory 265244 kb
Host smart-fc742100-88f4-427b-9435-fda0bc5bd991
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531491716 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.3531491716
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.2565788905
Short name T89
Test name
Test status
Simulation time 24199518000 ps
CPU time 298.9 seconds
Started Jun 07 06:58:37 PM PDT 24
Finished Jun 07 07:03:37 PM PDT 24
Peak memory 274956 kb
Host smart-f9ef09f7-c09c-4ba5-84bf-d3507d2c48b3
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565788905 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.2565788905
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.1836947544
Short name T145
Test name
Test status
Simulation time 496117500 ps
CPU time 132.39 seconds
Started Jun 07 06:58:38 PM PDT 24
Finished Jun 07 07:00:52 PM PDT 24
Peak memory 260176 kb
Host smart-2aa4a04d-2b97-4932-8c5d-d7b0b7a4eb47
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836947544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.1836947544
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.3398403471
Short name T329
Test name
Test status
Simulation time 4723059800 ps
CPU time 165.17 seconds
Started Jun 07 06:58:45 PM PDT 24
Finished Jun 07 07:01:31 PM PDT 24
Peak memory 282240 kb
Host smart-0f726257-d7d9-4e02-94bb-47621855fc44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398403471 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.3398403471
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.3652424022
Short name T724
Test name
Test status
Simulation time 128630700 ps
CPU time 68.89 seconds
Started Jun 07 06:58:30 PM PDT 24
Finished Jun 07 06:59:39 PM PDT 24
Peak memory 263428 kb
Host smart-567b7a90-46b3-4286-8f37-d3643741fdb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3652424022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.3652424022
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.168477303
Short name T112
Test name
Test status
Simulation time 52702700 ps
CPU time 14.05 seconds
Started Jun 07 06:58:53 PM PDT 24
Finished Jun 07 06:59:08 PM PDT 24
Peak memory 266008 kb
Host smart-3506a74e-951a-4e6b-b6c8-aa2f92ce3802
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168477303 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.168477303
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.1255961050
Short name T433
Test name
Test status
Simulation time 5256929800 ps
CPU time 191.32 seconds
Started Jun 07 06:58:44 PM PDT 24
Finished Jun 07 07:01:56 PM PDT 24
Peak memory 265416 kb
Host smart-638d248f-a542-47e8-b9d0-954b9a9d0444
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255961050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.1255961050
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.2880182017
Short name T134
Test name
Test status
Simulation time 298443300 ps
CPU time 844.73 seconds
Started Jun 07 06:58:29 PM PDT 24
Finished Jun 07 07:12:34 PM PDT 24
Peak memory 283096 kb
Host smart-a9d4051c-5cad-430b-ac5e-4994c42f6314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880182017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.2880182017
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.2201782907
Short name T55
Test name
Test status
Simulation time 1434265700 ps
CPU time 150.06 seconds
Started Jun 07 06:58:30 PM PDT 24
Finished Jun 07 07:01:00 PM PDT 24
Peak memory 262904 kb
Host smart-08c011f7-a6d5-4efb-95a0-6161364255f3
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2201782907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.2201782907
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.3558609214
Short name T388
Test name
Test status
Simulation time 69066200 ps
CPU time 32.17 seconds
Started Jun 07 06:58:45 PM PDT 24
Finished Jun 07 06:59:18 PM PDT 24
Peak memory 280656 kb
Host smart-a9d7a8da-7182-4568-ace6-0bc174a1baa2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558609214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.3558609214
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.1936567246
Short name T819
Test name
Test status
Simulation time 134030200 ps
CPU time 45.46 seconds
Started Jun 07 06:58:59 PM PDT 24
Finished Jun 07 06:59:45 PM PDT 24
Peak memory 275668 kb
Host smart-0e87efa9-915b-4c73-9b6f-3f8bdc81f635
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936567246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.1936567246
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.606144904
Short name T31
Test name
Test status
Simulation time 61834600 ps
CPU time 34.17 seconds
Started Jun 07 06:58:46 PM PDT 24
Finished Jun 07 06:59:21 PM PDT 24
Peak memory 275700 kb
Host smart-55151fb1-be1e-4068-90d4-2c47dd0b30cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606144904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_re_evict.606144904
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.3987894943
Short name T573
Test name
Test status
Simulation time 81540700 ps
CPU time 14.12 seconds
Started Jun 07 06:58:36 PM PDT 24
Finished Jun 07 06:58:51 PM PDT 24
Peak memory 265160 kb
Host smart-88948fee-8c79-43bb-80f4-1141b9af0ee7
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3987894943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.3987894943
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.4082226073
Short name T792
Test name
Test status
Simulation time 24925300 ps
CPU time 22.36 seconds
Started Jun 07 06:58:37 PM PDT 24
Finished Jun 07 06:59:00 PM PDT 24
Peak memory 265240 kb
Host smart-8a0a531c-4779-4ca1-b758-721e68d6dc13
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082226073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.4082226073
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.1351013092
Short name T229
Test name
Test status
Simulation time 2869890100 ps
CPU time 146.68 seconds
Started Jun 07 06:58:36 PM PDT 24
Finished Jun 07 07:01:04 PM PDT 24
Peak memory 290452 kb
Host smart-6b7922f1-812b-4e63-a0c2-cb6629712401
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1351013092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.1351013092
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.2518976923
Short name T311
Test name
Test status
Simulation time 900486400 ps
CPU time 152.05 seconds
Started Jun 07 06:58:37 PM PDT 24
Finished Jun 07 07:01:10 PM PDT 24
Peak memory 282196 kb
Host smart-4282b4b5-a9e7-4eb2-ad00-b7a4e3bf4fd0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518976923 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.2518976923
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.2733162601
Short name T695
Test name
Test status
Simulation time 15762770200 ps
CPU time 630.67 seconds
Started Jun 07 06:58:39 PM PDT 24
Finished Jun 07 07:09:11 PM PDT 24
Peak memory 315048 kb
Host smart-5d9c2f99-f315-490d-9f74-5047dacf8991
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733162601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.2733162601
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.918332339
Short name T651
Test name
Test status
Simulation time 27690038800 ps
CPU time 609.6 seconds
Started Jun 07 06:58:36 PM PDT 24
Finished Jun 07 07:08:47 PM PDT 24
Peak memory 325816 kb
Host smart-5123cd6c-c5ae-4a72-bbf9-34d95e756aa6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918332339 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.flash_ctrl_rw_derr.918332339
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.1953806257
Short name T385
Test name
Test status
Simulation time 44600100 ps
CPU time 30.74 seconds
Started Jun 07 06:58:48 PM PDT 24
Finished Jun 07 06:59:19 PM PDT 24
Peak memory 276824 kb
Host smart-bb27a4bf-55cf-4f63-ab7b-0ffb1c49bd76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953806257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_rw_evict.1953806257
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.1634282246
Short name T989
Test name
Test status
Simulation time 1162815100 ps
CPU time 60.94 seconds
Started Jun 07 06:58:46 PM PDT 24
Finished Jun 07 06:59:47 PM PDT 24
Peak memory 264292 kb
Host smart-c24808de-c444-4cfd-862b-d912c54c4544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634282246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.1634282246
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.1678794841
Short name T419
Test name
Test status
Simulation time 7000392700 ps
CPU time 84.61 seconds
Started Jun 07 06:58:40 PM PDT 24
Finished Jun 07 07:00:05 PM PDT 24
Peak memory 273932 kb
Host smart-5154bf5d-7a13-4ca7-bec8-4e6424adc13f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678794841 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.1678794841
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.3205819536
Short name T633
Test name
Test status
Simulation time 1145275700 ps
CPU time 58.77 seconds
Started Jun 07 06:58:37 PM PDT 24
Finished Jun 07 06:59:37 PM PDT 24
Peak memory 265888 kb
Host smart-85b33021-badf-4a65-81bb-938203f35382
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205819536 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.3205819536
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.3208695579
Short name T617
Test name
Test status
Simulation time 125054600 ps
CPU time 98.03 seconds
Started Jun 07 06:58:30 PM PDT 24
Finished Jun 07 07:00:08 PM PDT 24
Peak memory 276008 kb
Host smart-af0acf59-583e-4cb2-970e-464c35ff32d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208695579 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.3208695579
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.2277036845
Short name T57
Test name
Test status
Simulation time 44627200 ps
CPU time 25.69 seconds
Started Jun 07 06:58:29 PM PDT 24
Finished Jun 07 06:58:56 PM PDT 24
Peak memory 259916 kb
Host smart-b04b1e4b-7962-469c-8333-c5007aace578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277036845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.2277036845
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.2524067393
Short name T641
Test name
Test status
Simulation time 127974000 ps
CPU time 453.98 seconds
Started Jun 07 06:58:45 PM PDT 24
Finished Jun 07 07:06:19 PM PDT 24
Peak memory 281952 kb
Host smart-29567698-6fc8-4bf8-ae38-e8192ef7ef60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524067393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.2524067393
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.1421223220
Short name T899
Test name
Test status
Simulation time 24795500 ps
CPU time 26.92 seconds
Started Jun 07 06:58:32 PM PDT 24
Finished Jun 07 06:58:59 PM PDT 24
Peak memory 262436 kb
Host smart-d89ad142-a8e2-422f-af71-a6fa8d788470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421223220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.1421223220
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.3880789762
Short name T428
Test name
Test status
Simulation time 3960482800 ps
CPU time 177.07 seconds
Started Jun 07 06:58:36 PM PDT 24
Finished Jun 07 07:01:34 PM PDT 24
Peak memory 265456 kb
Host smart-32c646a0-039b-4303-bf5e-98a9b5663876
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880789762 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_wo.3880789762
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.3597710573
Short name T970
Test name
Test status
Simulation time 149678800 ps
CPU time 15.35 seconds
Started Jun 07 06:58:32 PM PDT 24
Finished Jun 07 06:58:48 PM PDT 24
Peak memory 259060 kb
Host smart-bbf1e5f7-720a-4b34-8cb4-12fde3da4f6e
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3597710573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.3597710573
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.328240759
Short name T19
Test name
Test status
Simulation time 20182800 ps
CPU time 13.75 seconds
Started Jun 07 06:59:22 PM PDT 24
Finished Jun 07 06:59:38 PM PDT 24
Peak memory 261684 kb
Host smart-dcc4a551-1604-4f40-9e5b-624d6bfb76cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328240759 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.328240759
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.1578831422
Short name T484
Test name
Test status
Simulation time 18260200 ps
CPU time 13.78 seconds
Started Jun 07 06:59:32 PM PDT 24
Finished Jun 07 06:59:46 PM PDT 24
Peak memory 258604 kb
Host smart-83cbfe2c-63fd-4d0a-ae0a-b98fc0dec1de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578831422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.1
578831422
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.3348994844
Short name T896
Test name
Test status
Simulation time 226288900 ps
CPU time 14.01 seconds
Started Jun 07 06:59:23 PM PDT 24
Finished Jun 07 06:59:38 PM PDT 24
Peak memory 261908 kb
Host smart-8a7a3e58-8bf7-4699-80a7-77197ab282df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348994844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.3348994844
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.3875371011
Short name T870
Test name
Test status
Simulation time 44756500 ps
CPU time 15.92 seconds
Started Jun 07 06:59:15 PM PDT 24
Finished Jun 07 06:59:32 PM PDT 24
Peak memory 275236 kb
Host smart-bcf5faf3-4df1-467d-aa13-d8137616b9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875371011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.3875371011
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.3688155488
Short name T923
Test name
Test status
Simulation time 222379700 ps
CPU time 104.34 seconds
Started Jun 07 06:59:15 PM PDT 24
Finished Jun 07 07:01:00 PM PDT 24
Peak memory 274044 kb
Host smart-d35d36e0-2880-4385-972c-56773364689b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688155488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.3688155488
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.251455500
Short name T784
Test name
Test status
Simulation time 18414000 ps
CPU time 22.23 seconds
Started Jun 07 06:59:16 PM PDT 24
Finished Jun 07 06:59:39 PM PDT 24
Peak memory 273972 kb
Host smart-f3c44ade-3d4c-46ee-a6f2-1b7ba5f451cc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251455500 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.251455500
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.2837508843
Short name T177
Test name
Test status
Simulation time 5571059600 ps
CPU time 358.82 seconds
Started Jun 07 06:58:59 PM PDT 24
Finished Jun 07 07:04:58 PM PDT 24
Peak memory 263560 kb
Host smart-20075f91-3c2b-4dd0-8b57-ac675f7e258d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837508843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.2837508843
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.1747142047
Short name T540
Test name
Test status
Simulation time 7458131500 ps
CPU time 2287.94 seconds
Started Jun 07 06:59:07 PM PDT 24
Finished Jun 07 07:37:17 PM PDT 24
Peak memory 265464 kb
Host smart-c3def57b-d7db-496c-b3a4-c5d23e0acf23
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747142047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.1747142047
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.2917075831
Short name T209
Test name
Test status
Simulation time 3982230400 ps
CPU time 2450.34 seconds
Started Jun 07 06:59:00 PM PDT 24
Finished Jun 07 07:39:51 PM PDT 24
Peak memory 264356 kb
Host smart-7f749578-236d-475c-8242-e5521ed5ca93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917075831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.2917075831
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.2994536126
Short name T863
Test name
Test status
Simulation time 653678900 ps
CPU time 872.58 seconds
Started Jun 07 06:59:00 PM PDT 24
Finished Jun 07 07:13:33 PM PDT 24
Peak memory 270628 kb
Host smart-8c6eaf13-7e27-4ba0-a540-ff78b499fd3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994536126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2994536126
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.2366907937
Short name T987
Test name
Test status
Simulation time 696080600 ps
CPU time 26.21 seconds
Started Jun 07 06:59:01 PM PDT 24
Finished Jun 07 06:59:28 PM PDT 24
Peak memory 262800 kb
Host smart-230277c5-b76a-44d1-a2df-55739140c1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366907937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.2366907937
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.3796506136
Short name T207
Test name
Test status
Simulation time 1941706400 ps
CPU time 41.96 seconds
Started Jun 07 06:59:21 PM PDT 24
Finished Jun 07 07:00:04 PM PDT 24
Peak memory 263264 kb
Host smart-95760b38-70c2-448f-a5dd-840f046d0d5f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796506136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.3796506136
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.1463080019
Short name T56
Test name
Test status
Simulation time 330830825400 ps
CPU time 2923.12 seconds
Started Jun 07 06:58:57 PM PDT 24
Finished Jun 07 07:47:41 PM PDT 24
Peak memory 265592 kb
Host smart-ce908071-1394-463e-8457-7ee5426a213b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463080019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.1463080019
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.1246809977
Short name T158
Test name
Test status
Simulation time 351955572600 ps
CPU time 2237.27 seconds
Started Jun 07 06:59:00 PM PDT 24
Finished Jun 07 07:36:19 PM PDT 24
Peak memory 264252 kb
Host smart-78184bc0-dd18-43c5-8978-f531181bfa08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246809977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_host_ctrl_arb.1246809977
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.2581592391
Short name T316
Test name
Test status
Simulation time 206832800 ps
CPU time 99.08 seconds
Started Jun 07 06:58:58 PM PDT 24
Finished Jun 07 07:00:38 PM PDT 24
Peak memory 265632 kb
Host smart-a1e0eff3-068b-4be1-ad23-4f876eebf741
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2581592391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.2581592391
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1177532832
Short name T865
Test name
Test status
Simulation time 10105269000 ps
CPU time 44.25 seconds
Started Jun 07 06:59:31 PM PDT 24
Finished Jun 07 07:00:16 PM PDT 24
Peak memory 265796 kb
Host smart-c59e319f-aa41-4efc-b9ce-211f3bcb2a9b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177532832 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.1177532832
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.3406347499
Short name T1012
Test name
Test status
Simulation time 169004386600 ps
CPU time 2050.98 seconds
Started Jun 07 06:58:59 PM PDT 24
Finished Jun 07 07:33:11 PM PDT 24
Peak memory 265376 kb
Host smart-d3b49fde-228f-4bc4-a488-b902510d5c1d
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406347499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.3406347499
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2517223743
Short name T717
Test name
Test status
Simulation time 160169861800 ps
CPU time 936.86 seconds
Started Jun 07 06:58:59 PM PDT 24
Finished Jun 07 07:14:37 PM PDT 24
Peak memory 264456 kb
Host smart-e7b21965-3d17-4013-8990-db2d227a2032
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517223743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.2517223743
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.624279103
Short name T1010
Test name
Test status
Simulation time 2444702700 ps
CPU time 59.55 seconds
Started Jun 07 06:58:59 PM PDT 24
Finished Jun 07 06:59:59 PM PDT 24
Peak memory 263484 kb
Host smart-8fb2148b-62d0-4474-ba62-90581815f17b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624279103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw
_sec_otp.624279103
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.1049014699
Short name T274
Test name
Test status
Simulation time 4332791700 ps
CPU time 688.69 seconds
Started Jun 07 06:59:15 PM PDT 24
Finished Jun 07 07:10:45 PM PDT 24
Peak memory 319256 kb
Host smart-4334745a-f8a1-47ba-991f-bbc7d5c8a4e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049014699 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.1049014699
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.1103288107
Short name T824
Test name
Test status
Simulation time 1987190400 ps
CPU time 117.19 seconds
Started Jun 07 06:59:14 PM PDT 24
Finished Jun 07 07:01:12 PM PDT 24
Peak memory 294520 kb
Host smart-c9efb073-6e4e-4be2-83f5-dff7a76d1a88
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103288107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.1103288107
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.3534952225
Short name T1072
Test name
Test status
Simulation time 10592356200 ps
CPU time 121.58 seconds
Started Jun 07 06:59:16 PM PDT 24
Finished Jun 07 07:01:18 PM PDT 24
Peak memory 292808 kb
Host smart-258de287-dfd9-4c21-8a8e-64c37ba6a9ca
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534952225 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.3534952225
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.1404376667
Short name T699
Test name
Test status
Simulation time 2499105300 ps
CPU time 77.1 seconds
Started Jun 07 06:59:16 PM PDT 24
Finished Jun 07 07:00:34 PM PDT 24
Peak memory 260860 kb
Host smart-499b2022-c571-483d-8130-ce2143153f31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404376667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.1404376667
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.2716582963
Short name T527
Test name
Test status
Simulation time 85715810300 ps
CPU time 197.89 seconds
Started Jun 07 06:59:13 PM PDT 24
Finished Jun 07 07:02:32 PM PDT 24
Peak memory 265404 kb
Host smart-235ee809-e607-437f-a60c-ec306986b239
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271
6582963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.2716582963
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.3076131818
Short name T710
Test name
Test status
Simulation time 8340028800 ps
CPU time 70.88 seconds
Started Jun 07 06:59:08 PM PDT 24
Finished Jun 07 07:00:20 PM PDT 24
Peak memory 263800 kb
Host smart-0f4a757d-ebbc-42f9-a22e-b15b67e228c6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076131818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.3076131818
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.3265697248
Short name T205
Test name
Test status
Simulation time 20124500 ps
CPU time 13.62 seconds
Started Jun 07 06:59:21 PM PDT 24
Finished Jun 07 06:59:36 PM PDT 24
Peak memory 260148 kb
Host smart-12bb6aa0-5f05-477e-8758-9008cc1a4286
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265697248 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.3265697248
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.1300304136
Short name T174
Test name
Test status
Simulation time 1475668800 ps
CPU time 70.78 seconds
Started Jun 07 06:59:08 PM PDT 24
Finished Jun 07 07:00:20 PM PDT 24
Peak memory 260936 kb
Host smart-d42906d1-4843-4925-9148-bb18a9ea183f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300304136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.1300304136
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/1.flash_ctrl_mp_regions.3447312607
Short name T1066
Test name
Test status
Simulation time 17700620400 ps
CPU time 136.77 seconds
Started Jun 07 06:59:02 PM PDT 24
Finished Jun 07 07:01:19 PM PDT 24
Peak memory 265476 kb
Host smart-464fe50e-b6ec-444d-8ac0-e1021c9653c4
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447312607 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_mp_regions.3447312607
Directory /workspace/1.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.79117406
Short name T492
Test name
Test status
Simulation time 440507900 ps
CPU time 131.13 seconds
Started Jun 07 06:58:59 PM PDT 24
Finished Jun 07 07:01:11 PM PDT 24
Peak memory 261312 kb
Host smart-8606194b-3661-4d3d-984b-080428528e50
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79117406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_
reset.79117406
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.2719641311
Short name T975
Test name
Test status
Simulation time 1337226400 ps
CPU time 193.1 seconds
Started Jun 07 06:59:15 PM PDT 24
Finished Jun 07 07:02:29 PM PDT 24
Peak memory 282272 kb
Host smart-6c473d94-7610-4a07-849f-9b2566b30c04
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719641311 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.2719641311
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.525090330
Short name T621
Test name
Test status
Simulation time 68099100 ps
CPU time 151.04 seconds
Started Jun 07 06:59:02 PM PDT 24
Finished Jun 07 07:01:34 PM PDT 24
Peak memory 263268 kb
Host smart-7a4b4001-3cc5-4094-90f4-281257bb5ee9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525090330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.525090330
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.2581902229
Short name T182
Test name
Test status
Simulation time 15438400 ps
CPU time 14.04 seconds
Started Jun 07 06:59:23 PM PDT 24
Finished Jun 07 06:59:38 PM PDT 24
Peak memory 263484 kb
Host smart-dedbb965-3d73-4988-83a7-99b09f929462
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581902229 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.2581902229
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.1701272087
Short name T611
Test name
Test status
Simulation time 9629083000 ps
CPU time 240.76 seconds
Started Jun 07 06:59:15 PM PDT 24
Finished Jun 07 07:03:17 PM PDT 24
Peak memory 260624 kb
Host smart-a32d2eec-3a07-476a-b950-b155ae26ae29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701272087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.1701272087
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.3960870313
Short name T904
Test name
Test status
Simulation time 613933800 ps
CPU time 326.61 seconds
Started Jun 07 06:58:59 PM PDT 24
Finished Jun 07 07:04:26 PM PDT 24
Peak memory 281896 kb
Host smart-ffa5a541-a9f5-4b43-bccc-15bb6cef8963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960870313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.3960870313
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.1369844899
Short name T130
Test name
Test status
Simulation time 63462600 ps
CPU time 32.25 seconds
Started Jun 07 06:59:14 PM PDT 24
Finished Jun 07 06:59:47 PM PDT 24
Peak memory 274908 kb
Host smart-9fe54a68-7e7c-4373-8163-f1b5176f9597
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369844899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.1369844899
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.2922637916
Short name T378
Test name
Test status
Simulation time 95310200 ps
CPU time 34.58 seconds
Started Jun 07 06:59:15 PM PDT 24
Finished Jun 07 06:59:50 PM PDT 24
Peak memory 275728 kb
Host smart-8c45a903-4ecd-4547-bf11-3c3e61083ccf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922637916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.2922637916
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.3050774693
Short name T1030
Test name
Test status
Simulation time 38077500 ps
CPU time 22.37 seconds
Started Jun 07 06:59:07 PM PDT 24
Finished Jun 07 06:59:31 PM PDT 24
Peak memory 265700 kb
Host smart-14aa739b-0085-4933-bc71-c30624b1ccfc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050774693 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.3050774693
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.477046442
Short name T431
Test name
Test status
Simulation time 45191500 ps
CPU time 21.54 seconds
Started Jun 07 06:59:10 PM PDT 24
Finished Jun 07 06:59:33 PM PDT 24
Peak memory 265784 kb
Host smart-c2631e16-4ccc-454d-a681-9a7ac85d9c24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477046442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_read_word_sweep_serr.477046442
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.2380780380
Short name T149
Test name
Test status
Simulation time 66196994500 ps
CPU time 1247.79 seconds
Started Jun 07 06:59:23 PM PDT 24
Finished Jun 07 07:20:12 PM PDT 24
Peak memory 432296 kb
Host smart-60361c7d-727b-4a21-87ba-446f4e8c75ae
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380780380 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.2380780380
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.537316208
Short name T746
Test name
Test status
Simulation time 1355377900 ps
CPU time 148.59 seconds
Started Jun 07 06:59:15 PM PDT 24
Finished Jun 07 07:01:44 PM PDT 24
Peak memory 282260 kb
Host smart-b7982b3f-3278-4fdc-8cf3-52ce9e2572be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
537316208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.537316208
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.992082814
Short name T510
Test name
Test status
Simulation time 1292152100 ps
CPU time 121.37 seconds
Started Jun 07 06:59:09 PM PDT 24
Finished Jun 07 07:01:12 PM PDT 24
Peak memory 282252 kb
Host smart-686dcb94-7241-463e-aff2-4a34a2aaef44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992082814 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.992082814
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.282373588
Short name T1050
Test name
Test status
Simulation time 10375955700 ps
CPU time 590.06 seconds
Started Jun 07 06:59:08 PM PDT 24
Finished Jun 07 07:08:59 PM PDT 24
Peak memory 314504 kb
Host smart-f601c4cc-40c0-4adc-8f24-e2c615d46bb9
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282373588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.flash_ctrl_rw.282373588
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.3058999214
Short name T632
Test name
Test status
Simulation time 124704000 ps
CPU time 30.42 seconds
Started Jun 07 06:59:14 PM PDT 24
Finished Jun 07 06:59:45 PM PDT 24
Peak memory 276800 kb
Host smart-4031069e-a3ff-4d42-94a2-d6f4513ac82d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058999214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.3058999214
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.293097534
Short name T122
Test name
Test status
Simulation time 67133400 ps
CPU time 31.14 seconds
Started Jun 07 06:59:14 PM PDT 24
Finished Jun 07 06:59:46 PM PDT 24
Peak memory 275980 kb
Host smart-ef67d207-2d75-48e1-88c1-a4236b5542c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293097534 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.293097534
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_serr.1732510024
Short name T196
Test name
Test status
Simulation time 6385347700 ps
CPU time 629.86 seconds
Started Jun 07 06:59:11 PM PDT 24
Finished Jun 07 07:09:42 PM PDT 24
Peak memory 314812 kb
Host smart-34b44384-d80a-4317-8a98-7d67b6615040
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732510024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_s
err.1732510024
Directory /workspace/1.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.3911868265
Short name T550
Test name
Test status
Simulation time 23056676500 ps
CPU time 73.56 seconds
Started Jun 07 06:59:14 PM PDT 24
Finished Jun 07 07:00:29 PM PDT 24
Peak memory 263928 kb
Host smart-598de339-493f-4a8e-a2bb-f4e6618b1a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911868265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.3911868265
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.1008813128
Short name T649
Test name
Test status
Simulation time 522470400 ps
CPU time 62.82 seconds
Started Jun 07 06:59:12 PM PDT 24
Finished Jun 07 07:00:16 PM PDT 24
Peak memory 265512 kb
Host smart-b4b71583-5b7a-4b07-b7bf-cd3aba1f5781
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008813128 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.1008813128
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.1882959466
Short name T543
Test name
Test status
Simulation time 2776044600 ps
CPU time 77.95 seconds
Started Jun 07 06:59:11 PM PDT 24
Finished Jun 07 07:00:30 PM PDT 24
Peak memory 273900 kb
Host smart-6a3a718c-0690-4a2e-a42a-e45fdb216019
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882959466 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_serr_counter.1882959466
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.393212753
Short name T654
Test name
Test status
Simulation time 43825100 ps
CPU time 52.38 seconds
Started Jun 07 06:59:02 PM PDT 24
Finished Jun 07 06:59:55 PM PDT 24
Peak memory 268932 kb
Host smart-fae6aa28-f121-4852-8479-378df7815ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393212753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.393212753
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.1339641497
Short name T472
Test name
Test status
Simulation time 44147200 ps
CPU time 26.61 seconds
Started Jun 07 06:58:59 PM PDT 24
Finished Jun 07 06:59:27 PM PDT 24
Peak memory 259916 kb
Host smart-5cc10caa-f0bd-4f8b-bfd9-5eb268b8ff10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339641497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.1339641497
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.854770863
Short name T786
Test name
Test status
Simulation time 993554800 ps
CPU time 1048.64 seconds
Started Jun 07 06:59:15 PM PDT 24
Finished Jun 07 07:16:44 PM PDT 24
Peak memory 287792 kb
Host smart-5f6fa291-cf56-48eb-a83b-05269fd7bde4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854770863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress
_all.854770863
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.1113246040
Short name T15
Test name
Test status
Simulation time 74636400 ps
CPU time 26.75 seconds
Started Jun 07 06:59:00 PM PDT 24
Finished Jun 07 06:59:28 PM PDT 24
Peak memory 262472 kb
Host smart-d87f1928-3c40-4c9b-bf2d-b2b589b33bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113246040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.1113246040
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_wo.3289118760
Short name T664
Test name
Test status
Simulation time 2139855700 ps
CPU time 157.65 seconds
Started Jun 07 06:59:07 PM PDT 24
Finished Jun 07 07:01:45 PM PDT 24
Peak memory 260128 kb
Host smart-aa434c2d-5c71-4381-8bf4-278cbde726f0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289118760 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_wo.3289118760
Directory /workspace/1.flash_ctrl_wo/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.1665172025
Short name T1018
Test name
Test status
Simulation time 30690000 ps
CPU time 13.53 seconds
Started Jun 07 07:02:50 PM PDT 24
Finished Jun 07 07:03:04 PM PDT 24
Peak memory 258572 kb
Host smart-d184e5a2-52f7-48c9-a760-343a2ba337d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665172025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
1665172025
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.489008065
Short name T166
Test name
Test status
Simulation time 10012614200 ps
CPU time 144.18 seconds
Started Jun 07 07:02:51 PM PDT 24
Finished Jun 07 07:05:16 PM PDT 24
Peak memory 373768 kb
Host smart-427f92b4-216f-4b6a-87b6-abb32f3add37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489008065 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.489008065
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.2523604063
Short name T766
Test name
Test status
Simulation time 24908300 ps
CPU time 13.73 seconds
Started Jun 07 07:02:44 PM PDT 24
Finished Jun 07 07:02:59 PM PDT 24
Peak memory 259792 kb
Host smart-cd35b27c-21a0-4a29-baca-4d385926e68e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523604063 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.2523604063
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.961876677
Short name T168
Test name
Test status
Simulation time 40124484100 ps
CPU time 837.67 seconds
Started Jun 07 07:02:33 PM PDT 24
Finished Jun 07 07:16:32 PM PDT 24
Peak memory 264032 kb
Host smart-c7b0a337-39ec-447f-9947-41ac3f2b9c10
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961876677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 10.flash_ctrl_hw_rma_reset.961876677
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.2606275321
Short name T345
Test name
Test status
Simulation time 2071370900 ps
CPU time 168.39 seconds
Started Jun 07 07:02:34 PM PDT 24
Finished Jun 07 07:05:23 PM PDT 24
Peak memory 263332 kb
Host smart-8712cc55-eae6-4c2e-9b87-2a4f0bd8ce01
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606275321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.2606275321
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.2242668366
Short name T816
Test name
Test status
Simulation time 8325694000 ps
CPU time 227.64 seconds
Started Jun 07 07:02:45 PM PDT 24
Finished Jun 07 07:06:33 PM PDT 24
Peak memory 291372 kb
Host smart-92092f8e-20d5-4bf7-8323-fd51cc4d6596
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242668366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_intr_rd.2242668366
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.509187537
Short name T201
Test name
Test status
Simulation time 6811770200 ps
CPU time 163.12 seconds
Started Jun 07 07:02:44 PM PDT 24
Finished Jun 07 07:05:28 PM PDT 24
Peak memory 293372 kb
Host smart-81f15cd5-e307-4a1f-91ff-dfee4fecee97
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509187537 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.509187537
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.619427128
Short name T855
Test name
Test status
Simulation time 2131528800 ps
CPU time 69.13 seconds
Started Jun 07 07:02:34 PM PDT 24
Finished Jun 07 07:03:44 PM PDT 24
Peak memory 263904 kb
Host smart-6156bc2c-c80c-4329-958a-946e7470fe4f
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619427128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.619427128
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.2859594216
Short name T1073
Test name
Test status
Simulation time 17440900 ps
CPU time 13.34 seconds
Started Jun 07 07:02:44 PM PDT 24
Finished Jun 07 07:02:58 PM PDT 24
Peak memory 260144 kb
Host smart-a3bc8555-767a-461a-bd83-19c6f5ef7331
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859594216 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.2859594216
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.1247800928
Short name T94
Test name
Test status
Simulation time 18629397600 ps
CPU time 441.77 seconds
Started Jun 07 07:02:35 PM PDT 24
Finished Jun 07 07:09:58 PM PDT 24
Peak memory 275116 kb
Host smart-f13f0683-f564-4aa9-973d-41fd5cefacdd
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247800928 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.1247800928
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.894872570
Short name T903
Test name
Test status
Simulation time 69203100 ps
CPU time 111.47 seconds
Started Jun 07 07:02:34 PM PDT 24
Finished Jun 07 07:04:26 PM PDT 24
Peak memory 260212 kb
Host smart-ac8f9ab6-baf0-41af-8933-27d8db4cb617
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894872570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ot
p_reset.894872570
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.2899683449
Short name T984
Test name
Test status
Simulation time 138132000 ps
CPU time 156.87 seconds
Started Jun 07 07:02:36 PM PDT 24
Finished Jun 07 07:05:14 PM PDT 24
Peak memory 263416 kb
Host smart-b99b37de-a9ed-461d-812d-37bb1ea0bf98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899683449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.2899683449
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.2305583872
Short name T430
Test name
Test status
Simulation time 68837300 ps
CPU time 14 seconds
Started Jun 07 07:02:44 PM PDT 24
Finished Jun 07 07:02:59 PM PDT 24
Peak memory 259412 kb
Host smart-1e1ca9a5-eccc-4f04-acbf-f25885661a6d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305583872 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.2305583872
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.2225268964
Short name T136
Test name
Test status
Simulation time 782437000 ps
CPU time 1090.28 seconds
Started Jun 07 07:02:35 PM PDT 24
Finished Jun 07 07:20:46 PM PDT 24
Peak memory 286468 kb
Host smart-afbf5dd5-a38d-4edc-b90d-430537fe78a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225268964 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2225268964
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.2410548253
Short name T673
Test name
Test status
Simulation time 274259700 ps
CPU time 32.82 seconds
Started Jun 07 07:02:43 PM PDT 24
Finished Jun 07 07:03:16 PM PDT 24
Peak memory 278184 kb
Host smart-d78fef34-4199-44cf-9016-66f2e34bcda2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410548253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.2410548253
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.3269031523
Short name T320
Test name
Test status
Simulation time 2117896200 ps
CPU time 126.14 seconds
Started Jun 07 07:02:37 PM PDT 24
Finished Jun 07 07:04:44 PM PDT 24
Peak memory 282124 kb
Host smart-5e7f2723-0240-4d05-98c2-37dd2b630402
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269031523 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 10.flash_ctrl_ro.3269031523
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.1368116424
Short name T853
Test name
Test status
Simulation time 8019870500 ps
CPU time 613.37 seconds
Started Jun 07 07:02:44 PM PDT 24
Finished Jun 07 07:12:58 PM PDT 24
Peak memory 319128 kb
Host smart-216a5832-d92c-4fdb-bce5-5f2d548f5022
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368116424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.flash_ctrl_rw.1368116424
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.481734559
Short name T232
Test name
Test status
Simulation time 31834200 ps
CPU time 31.08 seconds
Started Jun 07 07:02:43 PM PDT 24
Finished Jun 07 07:03:15 PM PDT 24
Peak memory 276044 kb
Host smart-7a4c6162-0d61-4ffb-b1fb-8757cf18e571
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481734559 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.481734559
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.3279304176
Short name T37
Test name
Test status
Simulation time 9347759800 ps
CPU time 66.61 seconds
Started Jun 07 07:02:44 PM PDT 24
Finished Jun 07 07:03:52 PM PDT 24
Peak memory 263344 kb
Host smart-a348af1b-bd05-44aa-a06d-33c32ff59aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279304176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.3279304176
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.3148939390
Short name T682
Test name
Test status
Simulation time 44210000 ps
CPU time 211.35 seconds
Started Jun 07 07:02:36 PM PDT 24
Finished Jun 07 07:06:08 PM PDT 24
Peak memory 278068 kb
Host smart-01606cc9-4735-4ea0-8366-05ad87d8e297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148939390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.3148939390
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.626846239
Short name T106
Test name
Test status
Simulation time 2637661100 ps
CPU time 227.94 seconds
Started Jun 07 07:02:33 PM PDT 24
Finished Jun 07 07:06:22 PM PDT 24
Peak memory 265608 kb
Host smart-ab98880c-4e1c-4560-ae9d-f5ccb0056f34
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626846239 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.flash_ctrl_wo.626846239
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.3474534503
Short name T716
Test name
Test status
Simulation time 152668000 ps
CPU time 13.54 seconds
Started Jun 07 07:02:57 PM PDT 24
Finished Jun 07 07:03:11 PM PDT 24
Peak memory 265624 kb
Host smart-ebc02515-f8ea-4bb3-ae83-f4d83062dc0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474534503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
3474534503
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.2645357219
Short name T481
Test name
Test status
Simulation time 25662400 ps
CPU time 15.76 seconds
Started Jun 07 07:02:58 PM PDT 24
Finished Jun 07 07:03:15 PM PDT 24
Peak memory 275024 kb
Host smart-182bc4f6-9091-454a-aaf0-644f4cf257d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645357219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.2645357219
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.502402556
Short name T902
Test name
Test status
Simulation time 15411200 ps
CPU time 13.48 seconds
Started Jun 07 07:02:57 PM PDT 24
Finished Jun 07 07:03:11 PM PDT 24
Peak memory 260488 kb
Host smart-050b793d-56f5-4cb0-ba2d-f94b26d7bc3e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502402556 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.502402556
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.3543312956
Short name T837
Test name
Test status
Simulation time 160191656500 ps
CPU time 915.44 seconds
Started Jun 07 07:02:51 PM PDT 24
Finished Jun 07 07:18:07 PM PDT 24
Peak memory 264236 kb
Host smart-06c810cc-29f1-48c1-b68b-8ff11de9759a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543312956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.3543312956
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.3199197973
Short name T1078
Test name
Test status
Simulation time 1369279000 ps
CPU time 75.73 seconds
Started Jun 07 07:02:51 PM PDT 24
Finished Jun 07 07:04:08 PM PDT 24
Peak memory 262928 kb
Host smart-14427fa6-d0b5-4ed8-b970-ef432dc25a62
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199197973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.3199197973
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.389386823
Short name T230
Test name
Test status
Simulation time 3982161100 ps
CPU time 161.15 seconds
Started Jun 07 07:02:52 PM PDT 24
Finished Jun 07 07:05:34 PM PDT 24
Peak memory 294596 kb
Host smart-3083c51d-ef10-4ff0-a652-fadb076a4ba3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389386823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flas
h_ctrl_intr_rd.389386823
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.1198453044
Short name T272
Test name
Test status
Simulation time 5810708900 ps
CPU time 149.8 seconds
Started Jun 07 07:02:52 PM PDT 24
Finished Jun 07 07:05:23 PM PDT 24
Peak memory 293324 kb
Host smart-48f0b21f-3170-4cf5-8c18-39602413466e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198453044 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.1198453044
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.883876576
Short name T862
Test name
Test status
Simulation time 2030607100 ps
CPU time 80.29 seconds
Started Jun 07 07:02:50 PM PDT 24
Finished Jun 07 07:04:11 PM PDT 24
Peak memory 261076 kb
Host smart-12ea9a9b-b16a-404f-b5eb-60a5f757cd3c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883876576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.883876576
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.1234931674
Short name T268
Test name
Test status
Simulation time 17708500 ps
CPU time 13.49 seconds
Started Jun 07 07:03:00 PM PDT 24
Finished Jun 07 07:03:14 PM PDT 24
Peak memory 265348 kb
Host smart-5786e74f-6162-4449-8f60-26b0258d7dc5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234931674 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.1234931674
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.3320764221
Short name T829
Test name
Test status
Simulation time 34802222500 ps
CPU time 437.35 seconds
Started Jun 07 07:02:50 PM PDT 24
Finished Jun 07 07:10:08 PM PDT 24
Peak memory 274768 kb
Host smart-dc740b4f-2fda-42a7-830c-8693ef4296c5
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320764221 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.3320764221
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.1042095547
Short name T442
Test name
Test status
Simulation time 80574200 ps
CPU time 109.71 seconds
Started Jun 07 07:02:51 PM PDT 24
Finished Jun 07 07:04:42 PM PDT 24
Peak memory 265364 kb
Host smart-8ce3a335-32a1-4ab7-8370-214492f37df8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042095547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.1042095547
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.3326263420
Short name T476
Test name
Test status
Simulation time 82615200 ps
CPU time 277.26 seconds
Started Jun 07 07:02:52 PM PDT 24
Finished Jun 07 07:07:30 PM PDT 24
Peak memory 263408 kb
Host smart-86454739-83c2-4a41-996e-7f6fac5d353e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3326263420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.3326263420
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.2539857391
Short name T4
Test name
Test status
Simulation time 27021000 ps
CPU time 13.64 seconds
Started Jun 07 07:02:58 PM PDT 24
Finished Jun 07 07:03:12 PM PDT 24
Peak memory 265576 kb
Host smart-894071fc-a244-4997-b663-c9a5fd51621e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539857391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.2539857391
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.781354166
Short name T41
Test name
Test status
Simulation time 749069700 ps
CPU time 649.74 seconds
Started Jun 07 07:02:53 PM PDT 24
Finished Jun 07 07:13:44 PM PDT 24
Peak memory 285020 kb
Host smart-f6b9c198-16cd-429c-8e15-049eba6afb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781354166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.781354166
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.205326666
Short name T544
Test name
Test status
Simulation time 537117000 ps
CPU time 111.27 seconds
Started Jun 07 07:02:52 PM PDT 24
Finished Jun 07 07:04:44 PM PDT 24
Peak memory 289536 kb
Host smart-1ecd087d-df19-4705-9625-8b0ccbbc2342
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205326666 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.flash_ctrl_ro.205326666
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.3019605116
Short name T841
Test name
Test status
Simulation time 7667805100 ps
CPU time 557.95 seconds
Started Jun 07 07:02:51 PM PDT 24
Finished Jun 07 07:12:09 PM PDT 24
Peak memory 314920 kb
Host smart-bef3abf8-c8f9-4511-8c0d-4f11e9bc62df
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019605116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.flash_ctrl_rw.3019605116
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.1743710700
Short name T907
Test name
Test status
Simulation time 65439200 ps
CPU time 28.55 seconds
Started Jun 07 07:03:02 PM PDT 24
Finished Jun 07 07:03:31 PM PDT 24
Peak memory 276052 kb
Host smart-3f4703b3-17e2-4011-8439-e2afa585ac92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743710700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.1743710700
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.3727844150
Short name T26
Test name
Test status
Simulation time 36293700 ps
CPU time 30.81 seconds
Started Jun 07 07:03:01 PM PDT 24
Finished Jun 07 07:03:33 PM PDT 24
Peak memory 267996 kb
Host smart-661ee7ec-4810-4901-9ae1-ebb977d37563
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727844150 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.3727844150
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.2209357673
Short name T992
Test name
Test status
Simulation time 40881100 ps
CPU time 48.69 seconds
Started Jun 07 07:02:53 PM PDT 24
Finished Jun 07 07:03:42 PM PDT 24
Peak memory 271472 kb
Host smart-fbb82880-e60b-465d-9a0e-06fe882e7f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209357673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.2209357673
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.1860856534
Short name T478
Test name
Test status
Simulation time 2136213900 ps
CPU time 175.04 seconds
Started Jun 07 07:02:51 PM PDT 24
Finished Jun 07 07:05:47 PM PDT 24
Peak memory 260300 kb
Host smart-d0e56555-cd4d-4916-a085-f8cbab3c36c5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860856534 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.flash_ctrl_wo.1860856534
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.962230107
Short name T1008
Test name
Test status
Simulation time 66978800 ps
CPU time 13.75 seconds
Started Jun 07 07:03:14 PM PDT 24
Finished Jun 07 07:03:29 PM PDT 24
Peak memory 265544 kb
Host smart-55222ed7-fa60-4a18-a309-23b655e2f792
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962230107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.962230107
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.2561218422
Short name T930
Test name
Test status
Simulation time 25885200 ps
CPU time 13.21 seconds
Started Jun 07 07:03:07 PM PDT 24
Finished Jun 07 07:03:22 PM PDT 24
Peak memory 275244 kb
Host smart-783f1d71-9dca-4650-8d48-ed3119558cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561218422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.2561218422
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.1161851696
Short name T872
Test name
Test status
Simulation time 10274000 ps
CPU time 21.91 seconds
Started Jun 07 07:03:05 PM PDT 24
Finished Jun 07 07:03:28 PM PDT 24
Peak memory 265208 kb
Host smart-be2f40ca-a165-4342-9450-16a51fa2caef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161851696 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.1161851696
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1358229131
Short name T579
Test name
Test status
Simulation time 10012520700 ps
CPU time 153.2 seconds
Started Jun 07 07:03:14 PM PDT 24
Finished Jun 07 07:05:49 PM PDT 24
Peak memory 398084 kb
Host smart-beb0cdaa-415f-4556-8744-c67fcfbfc02f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358229131 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.1358229131
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.3759288732
Short name T920
Test name
Test status
Simulation time 15099600 ps
CPU time 13.52 seconds
Started Jun 07 07:03:14 PM PDT 24
Finished Jun 07 07:03:29 PM PDT 24
Peak memory 259656 kb
Host smart-ed8f8458-7f3b-48ba-8f0d-cb8a35da0430
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759288732 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.3759288732
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.1534026648
Short name T148
Test name
Test status
Simulation time 240223437000 ps
CPU time 849.47 seconds
Started Jun 07 07:03:07 PM PDT 24
Finished Jun 07 07:17:18 PM PDT 24
Peak memory 264612 kb
Host smart-76e99706-7938-4924-9d2e-9cf93f3af052
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534026648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.1534026648
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.851942938
Short name T782
Test name
Test status
Simulation time 8263238600 ps
CPU time 168.18 seconds
Started Jun 07 07:03:08 PM PDT 24
Finished Jun 07 07:05:57 PM PDT 24
Peak memory 263276 kb
Host smart-d46feb5a-3e37-4a22-ade7-36cdabe21e25
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851942938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_h
w_sec_otp.851942938
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.1825562130
Short name T812
Test name
Test status
Simulation time 8511715000 ps
CPU time 69.58 seconds
Started Jun 07 07:03:07 PM PDT 24
Finished Jun 07 07:04:18 PM PDT 24
Peak memory 260836 kb
Host smart-021a45cc-0dfa-4755-8e46-6bf694e6f466
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825562130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.1
825562130
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.3546269882
Short name T326
Test name
Test status
Simulation time 15932200 ps
CPU time 13.28 seconds
Started Jun 07 07:03:15 PM PDT 24
Finished Jun 07 07:03:29 PM PDT 24
Peak memory 265260 kb
Host smart-76528162-8876-4004-b34b-0a8ed02dea3d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546269882 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.3546269882
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.2384866073
Short name T93
Test name
Test status
Simulation time 27119379600 ps
CPU time 1069.59 seconds
Started Jun 07 07:03:07 PM PDT 24
Finished Jun 07 07:20:58 PM PDT 24
Peak memory 275172 kb
Host smart-b75fdb3c-66d8-4613-8e8d-d52a5bf0c568
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384866073 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.2384866073
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.2121487444
Short name T997
Test name
Test status
Simulation time 146914600 ps
CPU time 133.27 seconds
Started Jun 07 07:03:08 PM PDT 24
Finished Jun 07 07:05:22 PM PDT 24
Peak memory 260248 kb
Host smart-90b4d12d-e85c-4de3-8662-1d730ce7d6e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121487444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o
tp_reset.2121487444
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.2405134946
Short name T477
Test name
Test status
Simulation time 63037600 ps
CPU time 276.45 seconds
Started Jun 07 07:03:07 PM PDT 24
Finished Jun 07 07:07:45 PM PDT 24
Peak memory 263432 kb
Host smart-cbe618c4-696c-4df2-88b5-1bb29a191250
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2405134946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.2405134946
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.2723058202
Short name T834
Test name
Test status
Simulation time 1419666200 ps
CPU time 270.31 seconds
Started Jun 07 07:03:02 PM PDT 24
Finished Jun 07 07:07:34 PM PDT 24
Peak memory 281872 kb
Host smart-09a872c5-17fd-4bc6-bc66-aa24cdf4d094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723058202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.2723058202
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.1029686789
Short name T42
Test name
Test status
Simulation time 3586084300 ps
CPU time 531.68 seconds
Started Jun 07 07:03:08 PM PDT 24
Finished Jun 07 07:12:01 PM PDT 24
Peak memory 310172 kb
Host smart-dd8fba96-d4cb-4477-9198-756384f756eb
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029686789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.1029686789
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.510310566
Short name T553
Test name
Test status
Simulation time 118314000 ps
CPU time 30.88 seconds
Started Jun 07 07:03:07 PM PDT 24
Finished Jun 07 07:03:40 PM PDT 24
Peak memory 270176 kb
Host smart-d7b9fb19-103a-4097-918c-7a242612528d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510310566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_rw_evict.510310566
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.3632944107
Short name T120
Test name
Test status
Simulation time 143448200 ps
CPU time 27.86 seconds
Started Jun 07 07:03:08 PM PDT 24
Finished Jun 07 07:03:37 PM PDT 24
Peak memory 276060 kb
Host smart-ed5b3abf-dc1d-4e65-89a7-5434cd702f44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632944107 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.3632944107
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.2829445424
Short name T758
Test name
Test status
Simulation time 1788351500 ps
CPU time 77.17 seconds
Started Jun 07 07:03:08 PM PDT 24
Finished Jun 07 07:04:26 PM PDT 24
Peak memory 264264 kb
Host smart-968568b9-1439-4886-8148-38d596a05faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829445424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.2829445424
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.1128224981
Short name T869
Test name
Test status
Simulation time 137617500 ps
CPU time 167.82 seconds
Started Jun 07 07:03:01 PM PDT 24
Finished Jun 07 07:05:50 PM PDT 24
Peak memory 278276 kb
Host smart-541d886e-5978-47af-bdbc-bb5e1a5051aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128224981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1128224981
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.317916370
Short name T1042
Test name
Test status
Simulation time 1948522100 ps
CPU time 168.73 seconds
Started Jun 07 07:03:07 PM PDT 24
Finished Jun 07 07:05:57 PM PDT 24
Peak memory 265372 kb
Host smart-5427549d-6df9-4b7c-92b7-9ccbf36b76cc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317916370 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.flash_ctrl_wo.317916370
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.2661813498
Short name T483
Test name
Test status
Simulation time 71558200 ps
CPU time 13.46 seconds
Started Jun 07 07:03:29 PM PDT 24
Finished Jun 07 07:03:43 PM PDT 24
Peak memory 258536 kb
Host smart-c5a4197b-542e-4153-a68b-f9a6c7fdf09e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661813498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.
2661813498
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.1278431233
Short name T803
Test name
Test status
Simulation time 13437200 ps
CPU time 13.17 seconds
Started Jun 07 07:03:21 PM PDT 24
Finished Jun 07 07:03:35 PM PDT 24
Peak memory 275068 kb
Host smart-cac30a12-966a-47c0-aa13-49e46b659ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278431233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.1278431233
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.2265444999
Short name T407
Test name
Test status
Simulation time 21450500 ps
CPU time 20.38 seconds
Started Jun 07 07:03:22 PM PDT 24
Finished Jun 07 07:03:43 PM PDT 24
Peak memory 273960 kb
Host smart-deff4ed5-d691-469d-b0b8-34d4e90694c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265444999 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.2265444999
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2253282642
Short name T674
Test name
Test status
Simulation time 10034725100 ps
CPU time 97.49 seconds
Started Jun 07 07:03:30 PM PDT 24
Finished Jun 07 07:05:08 PM PDT 24
Peak memory 270216 kb
Host smart-ee30b323-3c60-42a9-bda4-79da79c1050c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253282642 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.2253282642
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.571196904
Short name T1043
Test name
Test status
Simulation time 140365700 ps
CPU time 13.43 seconds
Started Jun 07 07:03:27 PM PDT 24
Finished Jun 07 07:03:41 PM PDT 24
Peak memory 259748 kb
Host smart-b0922757-351c-4df3-85c2-3d483f01bb7a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571196904 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.571196904
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.445005531
Short name T616
Test name
Test status
Simulation time 120149407100 ps
CPU time 889.04 seconds
Started Jun 07 07:03:13 PM PDT 24
Finished Jun 07 07:18:03 PM PDT 24
Peak memory 264504 kb
Host smart-5d0d6714-b30b-49cc-948e-cbae7f14f2f6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445005531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 13.flash_ctrl_hw_rma_reset.445005531
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3951535732
Short name T613
Test name
Test status
Simulation time 2874912800 ps
CPU time 84.39 seconds
Started Jun 07 07:03:14 PM PDT 24
Finished Jun 07 07:04:40 PM PDT 24
Peak memory 263152 kb
Host smart-2a0e973e-ddb6-41e1-a4bf-7d271c6e8b9e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951535732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.3951535732
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.67985024
Short name T221
Test name
Test status
Simulation time 2068315200 ps
CPU time 121.38 seconds
Started Jun 07 07:03:23 PM PDT 24
Finished Jun 07 07:05:25 PM PDT 24
Peak memory 294444 kb
Host smart-0cc81042-88d4-4a2a-bf73-d0163f41a308
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67985024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash
_ctrl_intr_rd.67985024
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2458245498
Short name T705
Test name
Test status
Simulation time 27863515700 ps
CPU time 312.3 seconds
Started Jun 07 07:03:21 PM PDT 24
Finished Jun 07 07:08:34 PM PDT 24
Peak memory 290296 kb
Host smart-6e2ce003-b494-4a18-8532-598d1ed023d7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458245498 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.2458245498
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.4097945979
Short name T115
Test name
Test status
Simulation time 13709118500 ps
CPU time 76.62 seconds
Started Jun 07 07:03:12 PM PDT 24
Finished Jun 07 07:04:29 PM PDT 24
Peak memory 260940 kb
Host smart-72d683cb-66da-4edd-97f6-4f757cbb6441
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097945979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.4
097945979
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2248955881
Short name T574
Test name
Test status
Simulation time 30311800 ps
CPU time 13.19 seconds
Started Jun 07 07:03:31 PM PDT 24
Finished Jun 07 07:03:45 PM PDT 24
Peak memory 260184 kb
Host smart-5a7ebd06-6083-47f2-b91a-04834748b1b2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248955881 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2248955881
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.321330699
Short name T90
Test name
Test status
Simulation time 41264174100 ps
CPU time 920.6 seconds
Started Jun 07 07:03:14 PM PDT 24
Finished Jun 07 07:18:35 PM PDT 24
Peak memory 274724 kb
Host smart-3fe2d77c-c0a4-4c94-8d1f-58c164ddd40e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321330699 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_mp_regions.321330699
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.3226798920
Short name T512
Test name
Test status
Simulation time 170947400 ps
CPU time 109.6 seconds
Started Jun 07 07:03:16 PM PDT 24
Finished Jun 07 07:05:06 PM PDT 24
Peak memory 260372 kb
Host smart-79d1e262-7475-4879-9440-bfa805a87ae8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226798920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.3226798920
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.3616511143
Short name T628
Test name
Test status
Simulation time 241263900 ps
CPU time 280.87 seconds
Started Jun 07 07:03:13 PM PDT 24
Finished Jun 07 07:07:55 PM PDT 24
Peak memory 263404 kb
Host smart-33af439e-82f8-47cd-af23-e5ff1a8be98c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3616511143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.3616511143
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.1582115453
Short name T610
Test name
Test status
Simulation time 24327700 ps
CPU time 13.69 seconds
Started Jun 07 07:03:21 PM PDT 24
Finished Jun 07 07:03:35 PM PDT 24
Peak memory 259292 kb
Host smart-cb0e1439-c08c-4b94-b6db-3ad5780efec4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582115453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_re
set.1582115453
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.3300200678
Short name T264
Test name
Test status
Simulation time 1023408500 ps
CPU time 953.98 seconds
Started Jun 07 07:03:15 PM PDT 24
Finished Jun 07 07:19:10 PM PDT 24
Peak memory 286776 kb
Host smart-1ffd195d-e11c-43e5-b185-8121a2c0cb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300200678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.3300200678
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.2209941077
Short name T354
Test name
Test status
Simulation time 253753000 ps
CPU time 38.85 seconds
Started Jun 07 07:03:22 PM PDT 24
Finished Jun 07 07:04:02 PM PDT 24
Peak memory 275748 kb
Host smart-46486df7-d905-43fb-9c11-47e30713cf9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209941077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.2209941077
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.2701414280
Short name T102
Test name
Test status
Simulation time 3825855600 ps
CPU time 125.18 seconds
Started Jun 07 07:03:20 PM PDT 24
Finished Jun 07 07:05:26 PM PDT 24
Peak memory 290356 kb
Host smart-49c01865-95f5-4b39-8ef0-e7c38bf10f31
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701414280 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.flash_ctrl_ro.2701414280
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.3418083375
Short name T309
Test name
Test status
Simulation time 93940400 ps
CPU time 31.75 seconds
Started Jun 07 07:03:23 PM PDT 24
Finished Jun 07 07:03:55 PM PDT 24
Peak memory 275820 kb
Host smart-bdeae432-4fdb-4553-b38e-0baef86dc4cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418083375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.3418083375
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.3283174455
Short name T1046
Test name
Test status
Simulation time 48838100 ps
CPU time 28.6 seconds
Started Jun 07 07:03:23 PM PDT 24
Finished Jun 07 07:03:52 PM PDT 24
Peak memory 267884 kb
Host smart-9917d3f4-67d5-4495-aa26-23874746da78
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283174455 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.3283174455
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.2674026840
Short name T192
Test name
Test status
Simulation time 23680936300 ps
CPU time 61.77 seconds
Started Jun 07 07:03:21 PM PDT 24
Finished Jun 07 07:04:24 PM PDT 24
Peak memory 263888 kb
Host smart-c8b55cc4-5779-49c3-ae18-98c91bbf99a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674026840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2674026840
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.2362551802
Short name T900
Test name
Test status
Simulation time 18654900 ps
CPU time 150.14 seconds
Started Jun 07 07:03:14 PM PDT 24
Finished Jun 07 07:05:45 PM PDT 24
Peak memory 278260 kb
Host smart-6d01f7b5-1eaa-4c7b-adf0-78d1a1d584d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362551802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2362551802
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.3980236505
Short name T935
Test name
Test status
Simulation time 16073801800 ps
CPU time 132.08 seconds
Started Jun 07 07:03:14 PM PDT 24
Finished Jun 07 07:05:27 PM PDT 24
Peak memory 265708 kb
Host smart-b6137696-9f7a-4b98-a109-b6f56f2701e7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980236505 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.flash_ctrl_wo.3980236505
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.52503690
Short name T14
Test name
Test status
Simulation time 27631300 ps
CPU time 13.27 seconds
Started Jun 07 07:03:45 PM PDT 24
Finished Jun 07 07:03:59 PM PDT 24
Peak memory 258652 kb
Host smart-1303eb3f-8a78-4db9-a480-2f86d28768c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52503690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.52503690
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.3890679622
Short name T804
Test name
Test status
Simulation time 14473500 ps
CPU time 15.82 seconds
Started Jun 07 07:03:47 PM PDT 24
Finished Jun 07 07:04:04 PM PDT 24
Peak memory 275112 kb
Host smart-ce322404-d408-497f-a5d9-921e09a8c7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890679622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.3890679622
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2427897774
Short name T325
Test name
Test status
Simulation time 10012331600 ps
CPU time 310.03 seconds
Started Jun 07 07:03:46 PM PDT 24
Finished Jun 07 07:08:57 PM PDT 24
Peak memory 290744 kb
Host smart-37e0f88e-3bb8-4186-903c-333e98f0e4c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427897774 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.2427897774
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.2739404639
Short name T65
Test name
Test status
Simulation time 15598300 ps
CPU time 13.56 seconds
Started Jun 07 07:03:46 PM PDT 24
Finished Jun 07 07:04:00 PM PDT 24
Peak memory 258884 kb
Host smart-0a8fb9e9-e860-4478-b201-5afe61138f44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739404639 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.2739404639
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.2315218540
Short name T440
Test name
Test status
Simulation time 40126624100 ps
CPU time 865.84 seconds
Started Jun 07 07:03:29 PM PDT 24
Finished Jun 07 07:17:56 PM PDT 24
Peak memory 264544 kb
Host smart-6acf0a71-38bb-4add-bc7f-63c8ef969373
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315218540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.flash_ctrl_hw_rma_reset.2315218540
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.2074027387
Short name T508
Test name
Test status
Simulation time 9679547700 ps
CPU time 202.6 seconds
Started Jun 07 07:03:30 PM PDT 24
Finished Jun 07 07:06:53 PM PDT 24
Peak memory 263252 kb
Host smart-77fe9232-e7ad-4a9a-83e4-f778b78f6c21
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074027387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.2074027387
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.3900454344
Short name T964
Test name
Test status
Simulation time 1730763200 ps
CPU time 124.62 seconds
Started Jun 07 07:03:41 PM PDT 24
Finished Jun 07 07:05:46 PM PDT 24
Peak memory 294344 kb
Host smart-85f8eea3-fa36-4613-987b-50521c30e298
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900454344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_intr_rd.3900454344
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.2066559729
Short name T1044
Test name
Test status
Simulation time 14856615200 ps
CPU time 326.29 seconds
Started Jun 07 07:03:37 PM PDT 24
Finished Jun 07 07:09:04 PM PDT 24
Peak memory 292352 kb
Host smart-f9dc88c7-96e2-4053-87d4-4c9632e0a062
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066559729 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.2066559729
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.3831109913
Short name T707
Test name
Test status
Simulation time 1834848000 ps
CPU time 71.54 seconds
Started Jun 07 07:03:37 PM PDT 24
Finished Jun 07 07:04:49 PM PDT 24
Peak memory 260772 kb
Host smart-88f06484-71a0-46ac-b059-43fb3ec5b466
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831109913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.3
831109913
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.210438287
Short name T327
Test name
Test status
Simulation time 122863300 ps
CPU time 13.72 seconds
Started Jun 07 07:03:46 PM PDT 24
Finished Jun 07 07:04:01 PM PDT 24
Peak memory 260240 kb
Host smart-5017b9d3-aeb6-47aa-b1cb-1e5fb30efc50
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210438287 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.210438287
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.4084528067
Short name T250
Test name
Test status
Simulation time 11121854600 ps
CPU time 163.73 seconds
Started Jun 07 07:03:39 PM PDT 24
Finished Jun 07 07:06:24 PM PDT 24
Peak memory 265496 kb
Host smart-7e3b5d91-20ba-4a5e-b466-1d9617e82cbe
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084528067 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.4084528067
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.2206436970
Short name T144
Test name
Test status
Simulation time 42508000 ps
CPU time 109.77 seconds
Started Jun 07 07:03:28 PM PDT 24
Finished Jun 07 07:05:18 PM PDT 24
Peak memory 260092 kb
Host smart-46d530c3-d36f-4378-9a69-5f8aab013e4c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206436970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.2206436970
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.3506336377
Short name T1102
Test name
Test status
Simulation time 389450900 ps
CPU time 360.31 seconds
Started Jun 07 07:03:31 PM PDT 24
Finished Jun 07 07:09:32 PM PDT 24
Peak memory 263304 kb
Host smart-de8415a3-48b1-4ba7-b007-f8ed1495963e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3506336377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.3506336377
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.1198502614
Short name T1036
Test name
Test status
Simulation time 32636900 ps
CPU time 13.36 seconds
Started Jun 07 07:03:36 PM PDT 24
Finished Jun 07 07:03:50 PM PDT 24
Peak memory 259052 kb
Host smart-57c70b89-2558-4f63-9359-4486d97f3b4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198502614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.1198502614
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.1851331282
Short name T506
Test name
Test status
Simulation time 189607200 ps
CPU time 178.35 seconds
Started Jun 07 07:03:31 PM PDT 24
Finished Jun 07 07:06:30 PM PDT 24
Peak memory 281916 kb
Host smart-bc7c5ad8-271f-4e9f-a052-d16fc884ad89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851331282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.1851331282
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.870973783
Short name T482
Test name
Test status
Simulation time 178643900 ps
CPU time 36.24 seconds
Started Jun 07 07:03:47 PM PDT 24
Finished Jun 07 07:04:24 PM PDT 24
Peak memory 275820 kb
Host smart-61070d50-3089-4acb-8eb0-02ff1a51710c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870973783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_re_evict.870973783
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.3736348112
Short name T554
Test name
Test status
Simulation time 12575376500 ps
CPU time 134.17 seconds
Started Jun 07 07:03:36 PM PDT 24
Finished Jun 07 07:05:51 PM PDT 24
Peak memory 290292 kb
Host smart-c699af32-a4a1-47c3-b263-b900a076d651
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736348112 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.flash_ctrl_ro.3736348112
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.1211784871
Short name T110
Test name
Test status
Simulation time 4386231900 ps
CPU time 544.68 seconds
Started Jun 07 07:03:36 PM PDT 24
Finished Jun 07 07:12:41 PM PDT 24
Peak memory 314568 kb
Host smart-b4345e71-4f3a-4709-9f27-07872a77ae19
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211784871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.1211784871
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.2054788469
Short name T860
Test name
Test status
Simulation time 68189600 ps
CPU time 31.33 seconds
Started Jun 07 07:03:46 PM PDT 24
Finished Jun 07 07:04:18 PM PDT 24
Peak memory 275928 kb
Host smart-440ce7b7-8841-4427-824f-41c44ad46985
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054788469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.2054788469
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.659225318
Short name T1011
Test name
Test status
Simulation time 51589500 ps
CPU time 31.39 seconds
Started Jun 07 07:03:46 PM PDT 24
Finished Jun 07 07:04:18 PM PDT 24
Peak memory 275984 kb
Host smart-9189771f-f6fe-4336-b786-067bbb3f139b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659225318 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.659225318
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.1754605742
Short name T1101
Test name
Test status
Simulation time 16412338200 ps
CPU time 67.75 seconds
Started Jun 07 07:03:45 PM PDT 24
Finished Jun 07 07:04:54 PM PDT 24
Peak memory 263188 kb
Host smart-4ab26a7e-4c85-41b0-80c9-742f27e01efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754605742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.1754605742
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.2320018196
Short name T427
Test name
Test status
Simulation time 52638100 ps
CPU time 98.59 seconds
Started Jun 07 07:03:29 PM PDT 24
Finished Jun 07 07:05:08 PM PDT 24
Peak memory 275760 kb
Host smart-37afac00-4dd5-46fb-8c2f-3f0e173f2459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320018196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.2320018196
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.1283306758
Short name T643
Test name
Test status
Simulation time 13673359700 ps
CPU time 190.52 seconds
Started Jun 07 07:03:39 PM PDT 24
Finished Jun 07 07:06:51 PM PDT 24
Peak memory 265708 kb
Host smart-de4ade20-a3f0-441c-bd99-6284eaee6348
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283306758 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.1283306758
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.3147927762
Short name T689
Test name
Test status
Simulation time 28100900 ps
CPU time 13.87 seconds
Started Jun 07 07:04:01 PM PDT 24
Finished Jun 07 07:04:16 PM PDT 24
Peak memory 265408 kb
Host smart-acd1fc4d-fd05-476c-a6f9-1ec6f6dccca7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147927762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
3147927762
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.1080169573
Short name T551
Test name
Test status
Simulation time 16100100 ps
CPU time 15.9 seconds
Started Jun 07 07:03:59 PM PDT 24
Finished Jun 07 07:04:16 PM PDT 24
Peak memory 284564 kb
Host smart-8c1f1ce7-3d3d-4ac5-a3b2-399bb9ba95b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080169573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1080169573
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.3486715471
Short name T754
Test name
Test status
Simulation time 42317300 ps
CPU time 20.48 seconds
Started Jun 07 07:03:59 PM PDT 24
Finished Jun 07 07:04:20 PM PDT 24
Peak memory 265236 kb
Host smart-aa22b02b-7d49-46fa-bf2d-5a045dac02b1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486715471 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.3486715471
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2047475205
Short name T1096
Test name
Test status
Simulation time 10012072700 ps
CPU time 122.51 seconds
Started Jun 07 07:04:01 PM PDT 24
Finished Jun 07 07:06:05 PM PDT 24
Peak memory 331396 kb
Host smart-12b87379-ce57-4a67-aa5c-f21d82c45700
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047475205 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.2047475205
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.407374164
Short name T709
Test name
Test status
Simulation time 24825800 ps
CPU time 13.8 seconds
Started Jun 07 07:03:59 PM PDT 24
Finished Jun 07 07:04:14 PM PDT 24
Peak memory 258800 kb
Host smart-84c0948a-301f-4bdb-9906-6a9c6d5d70aa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407374164 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.407374164
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.4220177691
Short name T1041
Test name
Test status
Simulation time 80148379600 ps
CPU time 827.13 seconds
Started Jun 07 07:03:50 PM PDT 24
Finished Jun 07 07:17:38 PM PDT 24
Peak memory 264660 kb
Host smart-94f73a9f-e290-4c22-8282-bd7534fe2638
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220177691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.4220177691
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.1594090931
Short name T535
Test name
Test status
Simulation time 1984137200 ps
CPU time 70.19 seconds
Started Jun 07 07:03:52 PM PDT 24
Finished Jun 07 07:05:03 PM PDT 24
Peak memory 263232 kb
Host smart-05abd832-4247-45e3-803f-707c54397c50
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594090931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.1594090931
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.1678242909
Short name T703
Test name
Test status
Simulation time 46764330700 ps
CPU time 281.72 seconds
Started Jun 07 07:03:52 PM PDT 24
Finished Jun 07 07:08:34 PM PDT 24
Peak memory 285248 kb
Host smart-69f7c53f-30ac-4082-ba5d-08562a714a1a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678242909 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.1678242909
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.780867617
Short name T932
Test name
Test status
Simulation time 20895100 ps
CPU time 13.51 seconds
Started Jun 07 07:04:00 PM PDT 24
Finished Jun 07 07:04:15 PM PDT 24
Peak memory 265232 kb
Host smart-f3788caf-45d0-409a-b7e9-ab56376a0a64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780867617 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.780867617
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.3450644203
Short name T818
Test name
Test status
Simulation time 42246188700 ps
CPU time 300.79 seconds
Started Jun 07 07:03:52 PM PDT 24
Finished Jun 07 07:08:54 PM PDT 24
Peak memory 274824 kb
Host smart-152c06ee-3de7-495f-9a67-f8d613728fda
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450644203 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.3450644203
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.1766398682
Short name T161
Test name
Test status
Simulation time 84606400 ps
CPU time 130 seconds
Started Jun 07 07:03:51 PM PDT 24
Finished Jun 07 07:06:02 PM PDT 24
Peak memory 260236 kb
Host smart-b37b7e2d-6f91-480a-aa22-0933862aac02
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766398682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.1766398682
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.1414499748
Short name T957
Test name
Test status
Simulation time 88895500 ps
CPU time 411.81 seconds
Started Jun 07 07:03:47 PM PDT 24
Finished Jun 07 07:10:39 PM PDT 24
Peak memory 263400 kb
Host smart-b6c9d3e1-6c2f-4a10-a507-8dd7b4746b3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1414499748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.1414499748
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.894176237
Short name T503
Test name
Test status
Simulation time 235052700 ps
CPU time 13.93 seconds
Started Jun 07 07:03:59 PM PDT 24
Finished Jun 07 07:04:14 PM PDT 24
Peak memory 259476 kb
Host smart-5ad80069-5b05-4a57-aaaa-cb39ebfae56d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894176237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_res
et.894176237
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.1988102019
Short name T955
Test name
Test status
Simulation time 159082300 ps
CPU time 969.83 seconds
Started Jun 07 07:03:45 PM PDT 24
Finished Jun 07 07:19:56 PM PDT 24
Peak memory 287720 kb
Host smart-e4bc321b-97e7-4e99-a740-f874ea3e3d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988102019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.1988102019
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.1201921188
Short name T379
Test name
Test status
Simulation time 72338800 ps
CPU time 34.63 seconds
Started Jun 07 07:04:02 PM PDT 24
Finished Jun 07 07:04:37 PM PDT 24
Peak memory 276036 kb
Host smart-59f7b76d-d459-4445-8c49-ec9158f5277f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201921188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.1201921188
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.800091105
Short name T1037
Test name
Test status
Simulation time 1126549500 ps
CPU time 122.97 seconds
Started Jun 07 07:03:52 PM PDT 24
Finished Jun 07 07:05:56 PM PDT 24
Peak memory 290784 kb
Host smart-04d73929-2fc9-4495-ba52-81b2a57ba801
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800091105 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.flash_ctrl_ro.800091105
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.8691832
Short name T568
Test name
Test status
Simulation time 7518791000 ps
CPU time 607.96 seconds
Started Jun 07 07:03:52 PM PDT 24
Finished Jun 07 07:14:01 PM PDT 24
Peak memory 314976 kb
Host smart-e1e00e24-426b-4257-b83c-55804fc7935e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8691832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.flash_ctrl_rw.8691832
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.1993362830
Short name T386
Test name
Test status
Simulation time 105554600 ps
CPU time 31.7 seconds
Started Jun 07 07:04:00 PM PDT 24
Finished Jun 07 07:04:32 PM PDT 24
Peak memory 267912 kb
Host smart-b5ad3b24-0f13-4e34-8437-63fbbecfbcfd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993362830 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.1993362830
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.2754290782
Short name T866
Test name
Test status
Simulation time 5632053900 ps
CPU time 68.75 seconds
Started Jun 07 07:03:59 PM PDT 24
Finished Jun 07 07:05:08 PM PDT 24
Peak memory 264936 kb
Host smart-1b06214a-fe1f-4835-8e7b-ea3aa9cbdb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754290782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.2754290782
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.1726722796
Short name T546
Test name
Test status
Simulation time 83719300 ps
CPU time 191.29 seconds
Started Jun 07 07:03:44 PM PDT 24
Finished Jun 07 07:06:56 PM PDT 24
Peak memory 277912 kb
Host smart-a2de52b9-5e58-4b80-867c-a58c432f7d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726722796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.1726722796
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.3643291220
Short name T511
Test name
Test status
Simulation time 19571018400 ps
CPU time 230.08 seconds
Started Jun 07 07:03:51 PM PDT 24
Finished Jun 07 07:07:42 PM PDT 24
Peak memory 260340 kb
Host smart-4a770646-e189-4e5b-b121-22dc4b41d435
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643291220 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.flash_ctrl_wo.3643291220
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.1136536096
Short name T976
Test name
Test status
Simulation time 90262900 ps
CPU time 13.51 seconds
Started Jun 07 07:04:16 PM PDT 24
Finished Jun 07 07:04:30 PM PDT 24
Peak memory 258576 kb
Host smart-24d474ad-58b4-4f43-b71f-a02584ed3cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136536096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
1136536096
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.3225697411
Short name T505
Test name
Test status
Simulation time 14363300 ps
CPU time 15.54 seconds
Started Jun 07 07:04:14 PM PDT 24
Finished Jun 07 07:04:30 PM PDT 24
Peak memory 275212 kb
Host smart-2fe51fae-b5a7-411d-958d-1de74605bf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225697411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.3225697411
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.4242363355
Short name T1009
Test name
Test status
Simulation time 30921300 ps
CPU time 21.68 seconds
Started Jun 07 07:04:07 PM PDT 24
Finished Jun 07 07:04:30 PM PDT 24
Peak memory 265356 kb
Host smart-07139cc2-25df-44ab-bbd7-20bfaecdc459
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242363355 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.4242363355
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.2288588901
Short name T1033
Test name
Test status
Simulation time 58361200 ps
CPU time 13.17 seconds
Started Jun 07 07:04:15 PM PDT 24
Finished Jun 07 07:04:29 PM PDT 24
Peak memory 258852 kb
Host smart-6f89ea6a-a575-42b7-88ba-0e0c7acd228d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288588901 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.2288588901
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.3694693269
Short name T715
Test name
Test status
Simulation time 100143836100 ps
CPU time 895.78 seconds
Started Jun 07 07:04:07 PM PDT 24
Finished Jun 07 07:19:04 PM PDT 24
Peak memory 264064 kb
Host smart-df3a85e8-5118-4f3c-ae3e-99f06bdd8dc8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694693269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.3694693269
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.4262798032
Short name T631
Test name
Test status
Simulation time 9610186900 ps
CPU time 94 seconds
Started Jun 07 07:04:01 PM PDT 24
Finished Jun 07 07:05:36 PM PDT 24
Peak memory 263376 kb
Host smart-6f64c2be-2601-4202-81a5-bbe4352f67bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262798032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.4262798032
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.287599366
Short name T521
Test name
Test status
Simulation time 5959505300 ps
CPU time 133.65 seconds
Started Jun 07 07:04:07 PM PDT 24
Finished Jun 07 07:06:21 PM PDT 24
Peak memory 292900 kb
Host smart-6075e1ee-87a5-4510-9788-07a940d768f2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287599366 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.287599366
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2337682720
Short name T658
Test name
Test status
Simulation time 34398500 ps
CPU time 13.56 seconds
Started Jun 07 07:04:13 PM PDT 24
Finished Jun 07 07:04:28 PM PDT 24
Peak memory 265204 kb
Host smart-b5c5beab-6e1b-4c59-9e06-039e294edbc7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337682720 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.2337682720
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.4231521710
Short name T969
Test name
Test status
Simulation time 40896073500 ps
CPU time 820.43 seconds
Started Jun 07 07:04:07 PM PDT 24
Finished Jun 07 07:17:48 PM PDT 24
Peak memory 275496 kb
Host smart-dbce7985-852f-4257-b607-89b90bbf1763
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231521710 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.4231521710
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.1877354357
Short name T1020
Test name
Test status
Simulation time 157427700 ps
CPU time 129.59 seconds
Started Jun 07 07:04:07 PM PDT 24
Finished Jun 07 07:06:17 PM PDT 24
Peak memory 261472 kb
Host smart-0cda9dff-3546-4d2f-a571-875e99950367
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877354357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.1877354357
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.3406734094
Short name T1105
Test name
Test status
Simulation time 5533082400 ps
CPU time 580.34 seconds
Started Jun 07 07:04:01 PM PDT 24
Finished Jun 07 07:13:42 PM PDT 24
Peak memory 263472 kb
Host smart-cbcbe990-3f3e-412a-b7de-d3aceec4b0fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3406734094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.3406734094
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.679079045
Short name T501
Test name
Test status
Simulation time 36528400 ps
CPU time 13.85 seconds
Started Jun 07 07:04:08 PM PDT 24
Finished Jun 07 07:04:23 PM PDT 24
Peak memory 265700 kb
Host smart-ee31cced-b33d-4a01-bd1f-83b1cb797c13
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679079045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_res
et.679079045
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.414709936
Short name T954
Test name
Test status
Simulation time 6196450800 ps
CPU time 1342.56 seconds
Started Jun 07 07:04:00 PM PDT 24
Finished Jun 07 07:26:23 PM PDT 24
Peak memory 289452 kb
Host smart-1b703424-5f61-4b16-924b-b1a3c513ad28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414709936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.414709936
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.3048852290
Short name T559
Test name
Test status
Simulation time 137320400 ps
CPU time 34.32 seconds
Started Jun 07 07:04:09 PM PDT 24
Finished Jun 07 07:04:44 PM PDT 24
Peak memory 275776 kb
Host smart-1e592afe-0719-453b-b925-7cf0ebb939fc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048852290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_re_evict.3048852290
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.3783449722
Short name T702
Test name
Test status
Simulation time 1594881900 ps
CPU time 143.3 seconds
Started Jun 07 07:04:07 PM PDT 24
Finished Jun 07 07:06:31 PM PDT 24
Peak memory 282112 kb
Host smart-3ff0245e-3d8e-4674-b121-06dfd281b583
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783449722 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.3783449722
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.324965259
Short name T132
Test name
Test status
Simulation time 66289800 ps
CPU time 30.93 seconds
Started Jun 07 07:04:07 PM PDT 24
Finished Jun 07 07:04:39 PM PDT 24
Peak memory 276108 kb
Host smart-81652f71-1ae1-40f7-ba35-88a7bd2e65c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324965259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_rw_evict.324965259
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.3702659914
Short name T223
Test name
Test status
Simulation time 91553400 ps
CPU time 28.74 seconds
Started Jun 07 07:04:08 PM PDT 24
Finished Jun 07 07:04:37 PM PDT 24
Peak memory 275936 kb
Host smart-45295689-8468-4bba-ae42-9c1d523e67fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702659914 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.3702659914
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.3544874248
Short name T453
Test name
Test status
Simulation time 15331507600 ps
CPU time 78.64 seconds
Started Jun 07 07:04:15 PM PDT 24
Finished Jun 07 07:05:35 PM PDT 24
Peak memory 263248 kb
Host smart-92d8ffc6-260f-4223-8ec4-3bccd20a2547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544874248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3544874248
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.2009288121
Short name T420
Test name
Test status
Simulation time 27380800 ps
CPU time 74.56 seconds
Started Jun 07 07:03:59 PM PDT 24
Finished Jun 07 07:05:14 PM PDT 24
Peak memory 275732 kb
Host smart-344c5dba-502f-4ec0-8f5d-9a34dbf956b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009288121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.2009288121
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.2310577624
Short name T111
Test name
Test status
Simulation time 18157087200 ps
CPU time 193 seconds
Started Jun 07 07:04:07 PM PDT 24
Finished Jun 07 07:07:21 PM PDT 24
Peak memory 261244 kb
Host smart-37546836-f79a-483d-adeb-6e29d5e33281
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310577624 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.flash_ctrl_wo.2310577624
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.3924305563
Short name T1092
Test name
Test status
Simulation time 110010300 ps
CPU time 14.25 seconds
Started Jun 07 07:04:24 PM PDT 24
Finished Jun 07 07:04:39 PM PDT 24
Peak memory 259064 kb
Host smart-0da4892a-9bb8-4508-ad47-84d1e015aa50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924305563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.
3924305563
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.4260705912
Short name T571
Test name
Test status
Simulation time 28010800 ps
CPU time 16.25 seconds
Started Jun 07 07:04:26 PM PDT 24
Finished Jun 07 07:04:43 PM PDT 24
Peak memory 275052 kb
Host smart-ca74a186-be5c-4adf-a5eb-e8b4632ec269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260705912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.4260705912
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.4094474971
Short name T999
Test name
Test status
Simulation time 10973600 ps
CPU time 22.14 seconds
Started Jun 07 07:04:25 PM PDT 24
Finished Jun 07 07:04:48 PM PDT 24
Peak memory 265424 kb
Host smart-432f539d-13d5-4c4e-bf45-d8b0f66ba023
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094474971 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.4094474971
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.1695732925
Short name T760
Test name
Test status
Simulation time 10022747400 ps
CPU time 61.82 seconds
Started Jun 07 07:04:25 PM PDT 24
Finished Jun 07 07:05:28 PM PDT 24
Peak memory 279376 kb
Host smart-069284e1-21ae-4eda-adf9-4dd64144cd1d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695732925 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.1695732925
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.2015471708
Short name T810
Test name
Test status
Simulation time 16148900 ps
CPU time 13.19 seconds
Started Jun 07 07:04:23 PM PDT 24
Finished Jun 07 07:04:38 PM PDT 24
Peak memory 259760 kb
Host smart-353318b4-8345-4add-94ff-b302ac58cd17
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015471708 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.2015471708
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.3869137809
Short name T796
Test name
Test status
Simulation time 160193181300 ps
CPU time 874.36 seconds
Started Jun 07 07:04:15 PM PDT 24
Finished Jun 07 07:18:50 PM PDT 24
Peak memory 264116 kb
Host smart-d24646cf-7a7a-4878-a8b8-902ab145e2e3
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869137809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_hw_rma_reset.3869137809
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.2142584881
Short name T665
Test name
Test status
Simulation time 1363916200 ps
CPU time 55.72 seconds
Started Jun 07 07:04:14 PM PDT 24
Finished Jun 07 07:05:10 PM PDT 24
Peak memory 263020 kb
Host smart-033a44e7-f1c1-43f1-9a8e-fbe764b064f1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142584881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.2142584881
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.3359388491
Short name T738
Test name
Test status
Simulation time 5189709200 ps
CPU time 225.16 seconds
Started Jun 07 07:04:26 PM PDT 24
Finished Jun 07 07:08:12 PM PDT 24
Peak memory 285220 kb
Host smart-9924be5f-1e4c-46bc-9d41-753bfbecbbba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359388491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.3359388491
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.1929527156
Short name T585
Test name
Test status
Simulation time 23588475400 ps
CPU time 135.6 seconds
Started Jun 07 07:04:24 PM PDT 24
Finished Jun 07 07:06:41 PM PDT 24
Peak memory 293296 kb
Host smart-c2ffeb07-3e81-4104-bbd8-9f6ec12243d2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929527156 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.1929527156
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.3085018461
Short name T1104
Test name
Test status
Simulation time 2155457200 ps
CPU time 87.37 seconds
Started Jun 07 07:04:16 PM PDT 24
Finished Jun 07 07:05:44 PM PDT 24
Peak memory 263144 kb
Host smart-efac611c-72e3-4db8-906a-fe8c8bed5121
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085018461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.3
085018461
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.1702315221
Short name T565
Test name
Test status
Simulation time 19634100 ps
CPU time 13.69 seconds
Started Jun 07 07:04:21 PM PDT 24
Finished Jun 07 07:04:36 PM PDT 24
Peak memory 265236 kb
Host smart-08f39be1-d024-46af-b06d-d5bddda542d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702315221 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.1702315221
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.2853900658
Short name T125
Test name
Test status
Simulation time 67531502300 ps
CPU time 400.17 seconds
Started Jun 07 07:04:16 PM PDT 24
Finished Jun 07 07:10:57 PM PDT 24
Peak memory 275072 kb
Host smart-5dd6bcce-036b-42b1-8ac0-bf4bf50b2504
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853900658 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.2853900658
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.1319372567
Short name T545
Test name
Test status
Simulation time 156062200 ps
CPU time 133.54 seconds
Started Jun 07 07:04:15 PM PDT 24
Finished Jun 07 07:06:30 PM PDT 24
Peak memory 261340 kb
Host smart-fc94419f-a71a-4bbd-a0c3-012feaff2930
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319372567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o
tp_reset.1319372567
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.1319311007
Short name T195
Test name
Test status
Simulation time 1465605800 ps
CPU time 339.74 seconds
Started Jun 07 07:04:17 PM PDT 24
Finished Jun 07 07:09:57 PM PDT 24
Peak memory 263344 kb
Host smart-9986d641-bc08-49ed-8c11-c82ad2925096
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319311007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1319311007
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.2274105141
Short name T945
Test name
Test status
Simulation time 246157600 ps
CPU time 13.74 seconds
Started Jun 07 07:04:24 PM PDT 24
Finished Jun 07 07:04:38 PM PDT 24
Peak memory 265536 kb
Host smart-9b623982-a505-407b-8054-bd791f83896b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274105141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.2274105141
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.2008319196
Short name T123
Test name
Test status
Simulation time 783542000 ps
CPU time 860.87 seconds
Started Jun 07 07:04:17 PM PDT 24
Finished Jun 07 07:18:39 PM PDT 24
Peak memory 286556 kb
Host smart-b4fe3eb2-f9ae-42cb-b402-dc4dae96cb9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008319196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2008319196
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.2964332565
Short name T1058
Test name
Test status
Simulation time 44449700 ps
CPU time 32.39 seconds
Started Jun 07 07:04:24 PM PDT 24
Finished Jun 07 07:04:58 PM PDT 24
Peak memory 278148 kb
Host smart-496d1e2d-9920-4066-b0e6-cf1e88a28131
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964332565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.2964332565
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.1880153918
Short name T562
Test name
Test status
Simulation time 1465267800 ps
CPU time 107.66 seconds
Started Jun 07 07:04:24 PM PDT 24
Finished Jun 07 07:06:12 PM PDT 24
Peak memory 291612 kb
Host smart-f15ae664-1b64-4092-8c7b-d7f13d11c89c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880153918 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.flash_ctrl_ro.1880153918
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.556365957
Short name T821
Test name
Test status
Simulation time 88299900 ps
CPU time 30.84 seconds
Started Jun 07 07:04:23 PM PDT 24
Finished Jun 07 07:04:55 PM PDT 24
Peak memory 276040 kb
Host smart-cd7b10f9-9710-46a8-9b69-da39a88666d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556365957 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.556365957
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.1479814555
Short name T555
Test name
Test status
Simulation time 852060100 ps
CPU time 80.89 seconds
Started Jun 07 07:04:24 PM PDT 24
Finished Jun 07 07:05:46 PM PDT 24
Peak memory 263920 kb
Host smart-ee49a049-3b66-4474-9c5c-c04c220700f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479814555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1479814555
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.1190329202
Short name T946
Test name
Test status
Simulation time 26602500 ps
CPU time 74.79 seconds
Started Jun 07 07:04:14 PM PDT 24
Finished Jun 07 07:05:29 PM PDT 24
Peak memory 276736 kb
Host smart-355b891d-5f16-4634-94ff-2da1e45670d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190329202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.1190329202
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.55160425
Short name T1
Test name
Test status
Simulation time 3884126400 ps
CPU time 137.45 seconds
Started Jun 07 07:04:15 PM PDT 24
Finished Jun 07 07:06:33 PM PDT 24
Peak memory 260156 kb
Host smart-655b5d9f-fa7c-40d2-989b-3bb47bd30307
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55160425 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.flash_ctrl_wo.55160425
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.3453140441
Short name T530
Test name
Test status
Simulation time 31907000 ps
CPU time 13.6 seconds
Started Jun 07 07:04:41 PM PDT 24
Finished Jun 07 07:04:56 PM PDT 24
Peak memory 258652 kb
Host smart-9141e4f7-7791-43c4-94ae-8a9355d34498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453140441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
3453140441
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.2035956209
Short name T638
Test name
Test status
Simulation time 42902900 ps
CPU time 15.69 seconds
Started Jun 07 07:04:39 PM PDT 24
Finished Jun 07 07:04:56 PM PDT 24
Peak memory 284432 kb
Host smart-c88bc6bb-75fa-439f-84b9-dcf9ede4b5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035956209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.2035956209
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.1117977626
Short name T445
Test name
Test status
Simulation time 13183100 ps
CPU time 21.63 seconds
Started Jun 07 07:04:31 PM PDT 24
Finished Jun 07 07:04:53 PM PDT 24
Peak memory 273932 kb
Host smart-4f04dfb5-db5c-41a9-8c03-d4ac69853e20
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117977626 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.1117977626
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.4129178750
Short name T153
Test name
Test status
Simulation time 10050839800 ps
CPU time 41.58 seconds
Started Jun 07 07:04:40 PM PDT 24
Finished Jun 07 07:05:22 PM PDT 24
Peak memory 265924 kb
Host smart-727c797f-257d-40ef-919b-7fc411c695c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129178750 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.4129178750
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.330010494
Short name T389
Test name
Test status
Simulation time 16203100 ps
CPU time 13.5 seconds
Started Jun 07 07:04:41 PM PDT 24
Finished Jun 07 07:04:55 PM PDT 24
Peak memory 265764 kb
Host smart-5364d14f-3573-46f2-9559-07bf56b958d4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330010494 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.330010494
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.4230032925
Short name T789
Test name
Test status
Simulation time 40123274400 ps
CPU time 845.9 seconds
Started Jun 07 07:04:24 PM PDT 24
Finished Jun 07 07:18:31 PM PDT 24
Peak memory 264540 kb
Host smart-5cf27bd0-9fe1-498c-8215-15a4d472401e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230032925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.4230032925
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.3300805728
Short name T507
Test name
Test status
Simulation time 4426968000 ps
CPU time 93.2 seconds
Started Jun 07 07:04:23 PM PDT 24
Finished Jun 07 07:05:57 PM PDT 24
Peak memory 261660 kb
Host smart-c2699720-536b-4948-8049-401d81ab01cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300805728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.3300805728
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.3849748828
Short name T28
Test name
Test status
Simulation time 1442101800 ps
CPU time 128.73 seconds
Started Jun 07 07:04:32 PM PDT 24
Finished Jun 07 07:06:41 PM PDT 24
Peak memory 292972 kb
Host smart-8ef55918-93f5-4687-beb8-ea31b28a2f83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849748828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.3849748828
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.3067801240
Short name T809
Test name
Test status
Simulation time 130539527200 ps
CPU time 349.4 seconds
Started Jun 07 07:04:31 PM PDT 24
Finished Jun 07 07:10:21 PM PDT 24
Peak memory 292216 kb
Host smart-bb4ae097-3e6b-4a42-b096-fa0dcfd66a97
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067801240 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.3067801240
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.1459874814
Short name T642
Test name
Test status
Simulation time 1993987100 ps
CPU time 77.94 seconds
Started Jun 07 07:04:32 PM PDT 24
Finished Jun 07 07:05:51 PM PDT 24
Peak memory 261012 kb
Host smart-230dfc53-ba77-40b4-9253-f3d5b254053b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459874814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.1
459874814
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2585809710
Short name T918
Test name
Test status
Simulation time 16004000 ps
CPU time 13.36 seconds
Started Jun 07 07:04:42 PM PDT 24
Finished Jun 07 07:04:56 PM PDT 24
Peak memory 260240 kb
Host smart-1e09b2fb-a760-4be3-a021-019c091728e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585809710 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.2585809710
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.3555231343
Short name T1084
Test name
Test status
Simulation time 45013900 ps
CPU time 130.92 seconds
Started Jun 07 07:04:33 PM PDT 24
Finished Jun 07 07:06:45 PM PDT 24
Peak memory 260244 kb
Host smart-c142a680-99ce-4e2c-946e-9b4da3d4c979
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555231343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.3555231343
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.1555196893
Short name T762
Test name
Test status
Simulation time 5505615500 ps
CPU time 523.14 seconds
Started Jun 07 07:04:24 PM PDT 24
Finished Jun 07 07:13:08 PM PDT 24
Peak memory 263328 kb
Host smart-d46ea463-65c3-4e5f-bb2b-14842bd6f427
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1555196893 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1555196893
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.1412376116
Short name T487
Test name
Test status
Simulation time 18192600 ps
CPU time 13.49 seconds
Started Jun 07 07:04:33 PM PDT 24
Finished Jun 07 07:04:47 PM PDT 24
Peak memory 265712 kb
Host smart-897e021b-1faf-4516-bbdc-996dd1b63876
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412376116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.1412376116
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.366048501
Short name T696
Test name
Test status
Simulation time 166173300 ps
CPU time 102.75 seconds
Started Jun 07 07:04:24 PM PDT 24
Finished Jun 07 07:06:08 PM PDT 24
Peak memory 276716 kb
Host smart-e1a53ff9-3cff-414d-b644-c711e02d98dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366048501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.366048501
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.2439959661
Short name T101
Test name
Test status
Simulation time 89836600 ps
CPU time 35.87 seconds
Started Jun 07 07:04:40 PM PDT 24
Finished Jun 07 07:05:16 PM PDT 24
Peak memory 278232 kb
Host smart-6bc01a36-3b77-427f-b546-a44b283fed7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439959661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.2439959661
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.1064122444
Short name T944
Test name
Test status
Simulation time 2753298200 ps
CPU time 102.45 seconds
Started Jun 07 07:04:36 PM PDT 24
Finished Jun 07 07:06:19 PM PDT 24
Peak memory 289476 kb
Host smart-d0b9c1c0-0cd9-4c92-accb-509990484dca
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064122444 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_ro.1064122444
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.856359639
Short name T745
Test name
Test status
Simulation time 6828053000 ps
CPU time 632.26 seconds
Started Jun 07 07:04:33 PM PDT 24
Finished Jun 07 07:15:06 PM PDT 24
Peak memory 314836 kb
Host smart-d8b9877f-b363-43b3-b8c0-9c73da73c14d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856359639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.flash_ctrl_rw.856359639
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict.950832151
Short name T313
Test name
Test status
Simulation time 59879300 ps
CPU time 28.73 seconds
Started Jun 07 07:04:33 PM PDT 24
Finished Jun 07 07:05:03 PM PDT 24
Peak memory 277936 kb
Host smart-d0988dbd-3ea3-49bf-a41c-9d2b66bc46a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950832151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_rw_evict.950832151
Directory /workspace/18.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.1790612104
Short name T753
Test name
Test status
Simulation time 38853000 ps
CPU time 30.63 seconds
Started Jun 07 07:04:31 PM PDT 24
Finished Jun 07 07:05:02 PM PDT 24
Peak memory 273984 kb
Host smart-380a5a94-3137-488b-abb2-4cdfc26ba61f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790612104 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.1790612104
Directory /workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.2339253712
Short name T685
Test name
Test status
Simulation time 6331263100 ps
CPU time 67.25 seconds
Started Jun 07 07:04:40 PM PDT 24
Finished Jun 07 07:05:48 PM PDT 24
Peak memory 259928 kb
Host smart-6d56e2f3-0dd7-49b6-9fea-8b5d81ac7c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339253712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.2339253712
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.3894951927
Short name T659
Test name
Test status
Simulation time 64431500 ps
CPU time 97.22 seconds
Started Jun 07 07:04:22 PM PDT 24
Finished Jun 07 07:06:00 PM PDT 24
Peak memory 276104 kb
Host smart-537955ba-27e9-48aa-adc7-b5f35092420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894951927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.3894951927
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.2743556442
Short name T825
Test name
Test status
Simulation time 2379192400 ps
CPU time 168.32 seconds
Started Jun 07 07:04:36 PM PDT 24
Finished Jun 07 07:07:25 PM PDT 24
Peak memory 265688 kb
Host smart-ed1bfecb-c7a9-46cf-a488-7e7005b6872b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743556442 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.2743556442
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.1580107706
Short name T828
Test name
Test status
Simulation time 23880100 ps
CPU time 13.42 seconds
Started Jun 07 07:04:54 PM PDT 24
Finished Jun 07 07:05:09 PM PDT 24
Peak memory 265444 kb
Host smart-d74f4ed4-53d7-4720-9ecc-f57775dff24d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580107706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
1580107706
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.2587434624
Short name T1052
Test name
Test status
Simulation time 14184200 ps
CPU time 15.58 seconds
Started Jun 07 07:04:54 PM PDT 24
Finished Jun 07 07:05:11 PM PDT 24
Peak memory 275052 kb
Host smart-91e81e75-c0ad-4e2f-bcf5-222f8ebdfb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587434624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.2587434624
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.2738009185
Short name T411
Test name
Test status
Simulation time 26710600 ps
CPU time 22.35 seconds
Started Jun 07 07:04:55 PM PDT 24
Finished Jun 07 07:05:18 PM PDT 24
Peak memory 274004 kb
Host smart-8c11daf7-53e3-43fa-95a7-3dcd8a9a7c44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738009185 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.2738009185
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.269003184
Short name T556
Test name
Test status
Simulation time 10031833700 ps
CPU time 56.42 seconds
Started Jun 07 07:04:53 PM PDT 24
Finished Jun 07 07:05:50 PM PDT 24
Peak memory 290492 kb
Host smart-a768c5e1-56a8-4c26-974d-9f262c4ecddc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269003184 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.269003184
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.1572302699
Short name T878
Test name
Test status
Simulation time 15788400 ps
CPU time 13.71 seconds
Started Jun 07 07:04:55 PM PDT 24
Finished Jun 07 07:05:10 PM PDT 24
Peak memory 265200 kb
Host smart-cb092889-9c25-4b77-90a9-64713e075996
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572302699 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.1572302699
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.150314735
Short name T671
Test name
Test status
Simulation time 160192454800 ps
CPU time 924.79 seconds
Started Jun 07 07:04:47 PM PDT 24
Finished Jun 07 07:20:12 PM PDT 24
Peak memory 263988 kb
Host smart-735a14cf-151d-43ed-839a-b43b651ad461
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150314735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 19.flash_ctrl_hw_rma_reset.150314735
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.1916521606
Short name T343
Test name
Test status
Simulation time 5019953700 ps
CPU time 195.98 seconds
Started Jun 07 07:04:42 PM PDT 24
Finished Jun 07 07:07:59 PM PDT 24
Peak memory 263356 kb
Host smart-0d8c1bdd-8fdb-4e54-8477-2bf47081f4c5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916521606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.1916521606
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.3080713623
Short name T567
Test name
Test status
Simulation time 3188808600 ps
CPU time 202.58 seconds
Started Jun 07 07:04:48 PM PDT 24
Finished Jun 07 07:08:12 PM PDT 24
Peak memory 284912 kb
Host smart-73d1958b-b96e-45bc-a9be-400bb480d7f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080713623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.3080713623
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.1061838223
Short name T363
Test name
Test status
Simulation time 14555700200 ps
CPU time 253.85 seconds
Started Jun 07 07:04:46 PM PDT 24
Finished Jun 07 07:09:01 PM PDT 24
Peak memory 291352 kb
Host smart-e8ffa694-27d7-4d88-a1a3-bab850294369
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061838223 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.1061838223
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.2676113354
Short name T584
Test name
Test status
Simulation time 1991618200 ps
CPU time 84.3 seconds
Started Jun 07 07:04:47 PM PDT 24
Finished Jun 07 07:06:12 PM PDT 24
Peak memory 260748 kb
Host smart-6ad3e270-3eee-4f26-9227-dc3516b81018
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676113354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.2
676113354
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.2434603248
Short name T1055
Test name
Test status
Simulation time 15426700 ps
CPU time 13.5 seconds
Started Jun 07 07:04:55 PM PDT 24
Finished Jun 07 07:05:09 PM PDT 24
Peak memory 260156 kb
Host smart-8a96f626-abc8-4a26-80d1-3accbbd4db64
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434603248 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.2434603248
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.2800042933
Short name T124
Test name
Test status
Simulation time 53130749700 ps
CPU time 1076.49 seconds
Started Jun 07 07:04:46 PM PDT 24
Finished Jun 07 07:22:44 PM PDT 24
Peak memory 274992 kb
Host smart-935ac3de-877a-4a65-9a6b-c17ea50216a0
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800042933 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_mp_regions.2800042933
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.4197115075
Short name T95
Test name
Test status
Simulation time 36852300 ps
CPU time 108.81 seconds
Started Jun 07 07:04:46 PM PDT 24
Finished Jun 07 07:06:35 PM PDT 24
Peak memory 265488 kb
Host smart-c6e22fd6-577e-499c-939e-dee560bf7f89
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197115075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.4197115075
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.1898523168
Short name T599
Test name
Test status
Simulation time 52127800 ps
CPU time 234.96 seconds
Started Jun 07 07:04:39 PM PDT 24
Finished Jun 07 07:08:35 PM PDT 24
Peak memory 263308 kb
Host smart-9adca8b3-d01d-4431-9981-4de63d3771f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1898523168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1898523168
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.2873147710
Short name T697
Test name
Test status
Simulation time 277230100 ps
CPU time 13.83 seconds
Started Jun 07 07:04:46 PM PDT 24
Finished Jun 07 07:05:00 PM PDT 24
Peak memory 265460 kb
Host smart-2858964a-7aeb-4bbb-bf22-8197393bba24
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873147710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.2873147710
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.3478251706
Short name T586
Test name
Test status
Simulation time 111430900 ps
CPU time 498.66 seconds
Started Jun 07 07:04:41 PM PDT 24
Finished Jun 07 07:13:00 PM PDT 24
Peak memory 282836 kb
Host smart-26e72292-566e-4fd4-97d8-abe6b56ac4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478251706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.3478251706
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.2436379166
Short name T519
Test name
Test status
Simulation time 128238400 ps
CPU time 31.45 seconds
Started Jun 07 07:04:50 PM PDT 24
Finished Jun 07 07:05:22 PM PDT 24
Peak memory 275700 kb
Host smart-f5b35536-9bb1-44b8-8d4a-94513ba08e4e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436379166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_re_evict.2436379166
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.3047074238
Short name T227
Test name
Test status
Simulation time 903560600 ps
CPU time 111.5 seconds
Started Jun 07 07:04:45 PM PDT 24
Finished Jun 07 07:06:37 PM PDT 24
Peak memory 282192 kb
Host smart-a957a4c0-bd52-412f-a85b-d3d79795934a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047074238 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.flash_ctrl_ro.3047074238
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.1639746099
Short name T768
Test name
Test status
Simulation time 29419943400 ps
CPU time 469.22 seconds
Started Jun 07 07:04:46 PM PDT 24
Finished Jun 07 07:12:36 PM PDT 24
Peak memory 310144 kb
Host smart-36974ce9-5990-452a-a20e-286614b9c847
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639746099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.1639746099
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.710212114
Short name T832
Test name
Test status
Simulation time 27429100 ps
CPU time 30.13 seconds
Started Jun 07 07:04:45 PM PDT 24
Finished Jun 07 07:05:16 PM PDT 24
Peak memory 276984 kb
Host smart-a0522881-31cb-4416-90f7-2ad4a4a84812
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710212114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_rw_evict.710212114
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.3879634537
Short name T775
Test name
Test status
Simulation time 6711817400 ps
CPU time 93.99 seconds
Started Jun 07 07:04:54 PM PDT 24
Finished Jun 07 07:06:29 PM PDT 24
Peak memory 263816 kb
Host smart-0cf562d7-24ef-449f-91f4-c78be39b4a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879634537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3879634537
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.1142476600
Short name T518
Test name
Test status
Simulation time 402044700 ps
CPU time 122.83 seconds
Started Jun 07 07:04:41 PM PDT 24
Finished Jun 07 07:06:45 PM PDT 24
Peak memory 276464 kb
Host smart-1e30fa03-acb4-4e0b-aea7-453c1e147e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142476600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1142476600
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.1313913767
Short name T661
Test name
Test status
Simulation time 4117935600 ps
CPU time 175.3 seconds
Started Jun 07 07:04:51 PM PDT 24
Finished Jun 07 07:07:47 PM PDT 24
Peak memory 265500 kb
Host smart-a6767a80-ed30-4bb5-8bab-2cd40588dece
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313913767 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.flash_ctrl_wo.1313913767
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.945919307
Short name T64
Test name
Test status
Simulation time 12876300 ps
CPU time 13.7 seconds
Started Jun 07 06:59:51 PM PDT 24
Finished Jun 07 07:00:06 PM PDT 24
Peak memory 265812 kb
Host smart-fffb9bb5-2586-4d22-803f-cb80c07ff115
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945919307 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.945919307
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.343098627
Short name T822
Test name
Test status
Simulation time 159164500 ps
CPU time 13.7 seconds
Started Jun 07 07:00:00 PM PDT 24
Finished Jun 07 07:00:15 PM PDT 24
Peak memory 265420 kb
Host smart-c8d5594b-6c5e-4777-9e6d-094e3c325652
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343098627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.343098627
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.1956158713
Short name T979
Test name
Test status
Simulation time 42065700 ps
CPU time 13.97 seconds
Started Jun 07 06:59:53 PM PDT 24
Finished Jun 07 07:00:08 PM PDT 24
Peak memory 261912 kb
Host smart-0bc08880-457f-4eb0-982c-20bf20f1c108
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956158713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.1956158713
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.3552909762
Short name T495
Test name
Test status
Simulation time 14218900 ps
CPU time 13.41 seconds
Started Jun 07 06:59:52 PM PDT 24
Finished Jun 07 07:00:07 PM PDT 24
Peak memory 275200 kb
Host smart-5baf4aeb-7128-49d9-9293-56c0e59f4a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552909762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.3552909762
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.3057872284
Short name T531
Test name
Test status
Simulation time 1172434700 ps
CPU time 105.11 seconds
Started Jun 07 06:59:45 PM PDT 24
Finished Jun 07 07:01:32 PM PDT 24
Peak memory 274040 kb
Host smart-29f43743-ef15-4185-ab6a-38d034e89432
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057872284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_derr_detect.3057872284
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.1758524045
Short name T972
Test name
Test status
Simulation time 11531000 ps
CPU time 22.28 seconds
Started Jun 07 06:59:52 PM PDT 24
Finished Jun 07 07:00:16 PM PDT 24
Peak memory 265900 kb
Host smart-a63c1461-ebda-43d7-a462-3296984a7302
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758524045 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.1758524045
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.2552055370
Short name T748
Test name
Test status
Simulation time 37261114600 ps
CPU time 562.97 seconds
Started Jun 07 06:59:33 PM PDT 24
Finished Jun 07 07:08:57 PM PDT 24
Peak memory 263684 kb
Host smart-66917af0-ae74-40e2-b653-6d265b7d9bfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552055370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.2552055370
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.1684519995
Short name T577
Test name
Test status
Simulation time 3776614000 ps
CPU time 2347.13 seconds
Started Jun 07 06:59:44 PM PDT 24
Finished Jun 07 07:38:53 PM PDT 24
Peak memory 265324 kb
Host smart-3213e7fa-43fb-4def-a73c-4bd740de9a98
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684519995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.1684519995
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.4031991432
Short name T188
Test name
Test status
Simulation time 1914355100 ps
CPU time 2150.41 seconds
Started Jun 07 06:59:43 PM PDT 24
Finished Jun 07 07:35:35 PM PDT 24
Peak memory 262360 kb
Host smart-a90cbd77-b02d-4d5a-995c-4665fdd8b603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031991432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.4031991432
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.2530863641
Short name T330
Test name
Test status
Simulation time 1389425600 ps
CPU time 812.2 seconds
Started Jun 07 06:59:45 PM PDT 24
Finished Jun 07 07:13:19 PM PDT 24
Peak memory 272796 kb
Host smart-9264c81d-4fac-4027-a527-216f7ff826db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530863641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.2530863641
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.679926852
Short name T66
Test name
Test status
Simulation time 241916400 ps
CPU time 26.09 seconds
Started Jun 07 06:59:44 PM PDT 24
Finished Jun 07 07:00:11 PM PDT 24
Peak memory 263644 kb
Host smart-3c3d8edd-2c61-4d4b-993e-a8fc86a3be74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679926852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.679926852
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.3476600475
Short name T787
Test name
Test status
Simulation time 635158700 ps
CPU time 40.36 seconds
Started Jun 07 06:59:54 PM PDT 24
Finished Jun 07 07:00:36 PM PDT 24
Peak memory 263208 kb
Host smart-961d0484-09ab-4e96-acce-52999b3bd7d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476600475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.3476600475
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.3275945624
Short name T88
Test name
Test status
Simulation time 417230743100 ps
CPU time 2937.62 seconds
Started Jun 07 06:59:46 PM PDT 24
Finished Jun 07 07:48:45 PM PDT 24
Peak memory 265684 kb
Host smart-42fa501a-af96-4247-9d48-fc69eb861a98
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275945624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_full_mem_access.3275945624
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.4173695640
Short name T413
Test name
Test status
Simulation time 50574300 ps
CPU time 90.4 seconds
Started Jun 07 06:59:29 PM PDT 24
Finished Jun 07 07:01:01 PM PDT 24
Peak memory 262884 kb
Host smart-6813edbe-69f6-48c2-b889-c6af1aabaff4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173695640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.4173695640
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.2132052514
Short name T730
Test name
Test status
Simulation time 10031049700 ps
CPU time 105.78 seconds
Started Jun 07 07:00:01 PM PDT 24
Finished Jun 07 07:01:47 PM PDT 24
Peak memory 275780 kb
Host smart-70033f67-63ea-4db2-a3e2-ff4419def8d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132052514 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.2132052514
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.1247620623
Short name T139
Test name
Test status
Simulation time 46507400 ps
CPU time 13.33 seconds
Started Jun 07 06:59:58 PM PDT 24
Finished Jun 07 07:00:12 PM PDT 24
Peak memory 265180 kb
Host smart-9a008c6a-e85f-4b61-bf5c-c443703135ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247620623 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.1247620623
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.3655065983
Short name T541
Test name
Test status
Simulation time 211723535700 ps
CPU time 1966.82 seconds
Started Jun 07 06:59:31 PM PDT 24
Finished Jun 07 07:32:19 PM PDT 24
Peak memory 265260 kb
Host smart-1fea2050-5091-47f6-b29f-f871fdf888ba
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655065983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.3655065983
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.524468357
Short name T206
Test name
Test status
Simulation time 40128989600 ps
CPU time 912.87 seconds
Started Jun 07 06:59:30 PM PDT 24
Finished Jun 07 07:14:44 PM PDT 24
Peak memory 264544 kb
Host smart-855280cb-8af4-4402-9511-f0f5c3273b0c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524468357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_hw_rma_reset.524468357
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.1401958692
Short name T583
Test name
Test status
Simulation time 2249455600 ps
CPU time 85.87 seconds
Started Jun 07 06:59:31 PM PDT 24
Finished Jun 07 07:00:58 PM PDT 24
Peak memory 262884 kb
Host smart-6fec123b-26dc-43cb-b421-ff6227707d6a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401958692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_h
w_sec_otp.1401958692
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.2002114770
Short name T263
Test name
Test status
Simulation time 9569211100 ps
CPU time 749.81 seconds
Started Jun 07 06:59:46 PM PDT 24
Finished Jun 07 07:12:17 PM PDT 24
Peak memory 345000 kb
Host smart-06fbc5c1-8d20-493d-ab66-de7da9dd6be6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002114770 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.2002114770
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.3890483306
Short name T239
Test name
Test status
Simulation time 2747773100 ps
CPU time 128.99 seconds
Started Jun 07 06:59:44 PM PDT 24
Finished Jun 07 07:01:54 PM PDT 24
Peak memory 291548 kb
Host smart-99110236-a0ca-4560-873b-4e9a8c29b2c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890483306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.3890483306
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.2427779197
Short name T985
Test name
Test status
Simulation time 57937869000 ps
CPU time 148.31 seconds
Started Jun 07 06:59:45 PM PDT 24
Finished Jun 07 07:02:15 PM PDT 24
Peak memory 292820 kb
Host smart-3313b07d-4a79-4833-8377-f02f0eaebd8a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427779197 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.2427779197
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.3348797809
Short name T32
Test name
Test status
Simulation time 5532839400 ps
CPU time 68.9 seconds
Started Jun 07 06:59:48 PM PDT 24
Finished Jun 07 07:00:58 PM PDT 24
Peak memory 260792 kb
Host smart-167d97c8-7020-4f37-9d3d-772b41a64012
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348797809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.3348797809
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.4003610236
Short name T751
Test name
Test status
Simulation time 21353746300 ps
CPU time 185.84 seconds
Started Jun 07 06:59:43 PM PDT 24
Finished Jun 07 07:02:49 PM PDT 24
Peak memory 260820 kb
Host smart-c5b234a4-8c5d-4781-826a-7dd1f5128dd5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400
3610236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.4003610236
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.2698287212
Short name T464
Test name
Test status
Simulation time 4336511700 ps
CPU time 74.39 seconds
Started Jun 07 06:59:45 PM PDT 24
Finished Jun 07 07:01:00 PM PDT 24
Peak memory 260748 kb
Host smart-56257259-d854-4eb9-8df9-a43a452b8b0f
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698287212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.2698287212
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.2018881676
Short name T943
Test name
Test status
Simulation time 47242700 ps
CPU time 13.54 seconds
Started Jun 07 06:59:52 PM PDT 24
Finished Jun 07 07:00:06 PM PDT 24
Peak memory 260232 kb
Host smart-fefca1ca-9b41-495f-a52b-0b64c0219e00
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018881676 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.2018881676
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.3782077576
Short name T183
Test name
Test status
Simulation time 11709060900 ps
CPU time 74.64 seconds
Started Jun 07 06:59:44 PM PDT 24
Finished Jun 07 07:01:00 PM PDT 24
Peak memory 260736 kb
Host smart-3ac78f10-a773-4920-b51a-69aba8914d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782077576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.3782077576
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.153918426
Short name T1059
Test name
Test status
Simulation time 10770159200 ps
CPU time 806.3 seconds
Started Jun 07 06:59:46 PM PDT 24
Finished Jun 07 07:13:13 PM PDT 24
Peak memory 274268 kb
Host smart-fc307e0a-1d96-4a7d-9518-0e9a2291c864
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153918426 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_mp_regions.153918426
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.402296203
Short name T680
Test name
Test status
Simulation time 70905300 ps
CPU time 137.46 seconds
Started Jun 07 06:59:44 PM PDT 24
Finished Jun 07 07:02:03 PM PDT 24
Peak memory 261312 kb
Host smart-c67c8b05-fb55-4ab5-8fa2-a0d206baba47
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402296203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp
_reset.402296203
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.4230936244
Short name T800
Test name
Test status
Simulation time 3208754900 ps
CPU time 150.69 seconds
Started Jun 07 06:59:48 PM PDT 24
Finished Jun 07 07:02:19 PM PDT 24
Peak memory 282284 kb
Host smart-1d55438d-8c70-40a6-949e-12368e2a6540
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230936244 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.4230936244
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.1728772874
Short name T44
Test name
Test status
Simulation time 15494300 ps
CPU time 14.03 seconds
Started Jun 07 06:59:52 PM PDT 24
Finished Jun 07 07:00:07 PM PDT 24
Peak memory 279668 kb
Host smart-ec219f79-b10f-49d3-a976-12982eec9989
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1728772874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.1728772874
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.4193571509
Short name T884
Test name
Test status
Simulation time 718010400 ps
CPU time 244.85 seconds
Started Jun 07 06:59:31 PM PDT 24
Finished Jun 07 07:03:36 PM PDT 24
Peak memory 263384 kb
Host smart-8e20c559-6fcf-4915-ba78-6ea40c83dbe1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4193571509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.4193571509
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.2969530606
Short name T79
Test name
Test status
Simulation time 907416100 ps
CPU time 17 seconds
Started Jun 07 06:59:53 PM PDT 24
Finished Jun 07 07:00:11 PM PDT 24
Peak memory 265464 kb
Host smart-0c50584d-f059-4e42-9374-4e99f1f27b11
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969530606 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.2969530606
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.1105503126
Short name T1057
Test name
Test status
Simulation time 15374700 ps
CPU time 13.92 seconds
Started Jun 07 06:59:53 PM PDT 24
Finished Jun 07 07:00:08 PM PDT 24
Peak memory 263284 kb
Host smart-5727d9f9-10a7-4828-9c5d-a9caa6579642
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105503126 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.1105503126
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.1628530419
Short name T960
Test name
Test status
Simulation time 75827100 ps
CPU time 14.04 seconds
Started Jun 07 06:59:44 PM PDT 24
Finished Jun 07 06:59:59 PM PDT 24
Peak memory 259476 kb
Host smart-661087e5-22bf-47cd-90c7-da35d00c1be4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628530419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.1628530419
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.1810364854
Short name T956
Test name
Test status
Simulation time 163885200 ps
CPU time 665.02 seconds
Started Jun 07 06:59:33 PM PDT 24
Finished Jun 07 07:10:38 PM PDT 24
Peak memory 284404 kb
Host smart-bb3989eb-5535-4649-934a-0946173668d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810364854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1810364854
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.4045064824
Short name T524
Test name
Test status
Simulation time 719887000 ps
CPU time 147.58 seconds
Started Jun 07 06:59:31 PM PDT 24
Finished Jun 07 07:01:59 PM PDT 24
Peak memory 263072 kb
Host smart-cb7c4622-c997-44fa-8241-da886109e867
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4045064824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.4045064824
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.4035763137
Short name T590
Test name
Test status
Simulation time 68265100 ps
CPU time 32.89 seconds
Started Jun 07 06:59:52 PM PDT 24
Finished Jun 07 07:00:26 PM PDT 24
Peak memory 276236 kb
Host smart-dd5e63b7-51d2-4d50-a0f9-bba6f3af6e4a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035763137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.4035763137
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.1102805555
Short name T525
Test name
Test status
Simulation time 248517500 ps
CPU time 38.64 seconds
Started Jun 07 06:59:55 PM PDT 24
Finished Jun 07 07:00:35 PM PDT 24
Peak memory 273480 kb
Host smart-daeea0b4-e1f5-47da-8550-493a4278fe19
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102805555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_re_evict.1102805555
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.2560149221
Short name T237
Test name
Test status
Simulation time 19222100 ps
CPU time 22.74 seconds
Started Jun 07 06:59:43 PM PDT 24
Finished Jun 07 07:00:07 PM PDT 24
Peak memory 265348 kb
Host smart-fa993795-e9ff-4c0a-acb7-b656ba27c461
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560149221 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.2560149221
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.3169581380
Short name T764
Test name
Test status
Simulation time 22894800 ps
CPU time 22.78 seconds
Started Jun 07 06:59:43 PM PDT 24
Finished Jun 07 07:00:07 PM PDT 24
Peak memory 265212 kb
Host smart-106f9fab-bd5c-4da9-b72f-31b5566bf00b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169581380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_read_word_sweep_serr.3169581380
Directory /workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.770280427
Short name T160
Test name
Test status
Simulation time 159325611000 ps
CPU time 912.76 seconds
Started Jun 07 06:59:52 PM PDT 24
Finished Jun 07 07:15:06 PM PDT 24
Peak memory 261392 kb
Host smart-27e34622-2e50-4f96-8f52-1bb8273a2d7c
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770280427 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.770280427
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.1922867741
Short name T1004
Test name
Test status
Simulation time 1096091800 ps
CPU time 128.94 seconds
Started Jun 07 06:59:43 PM PDT 24
Finished Jun 07 07:01:53 PM PDT 24
Peak memory 282192 kb
Host smart-223d1027-bb8a-4d69-a984-f9fd7082e596
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922867741 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_ro.1922867741
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.4075920561
Short name T981
Test name
Test status
Simulation time 2959340200 ps
CPU time 135.06 seconds
Started Jun 07 06:59:44 PM PDT 24
Finished Jun 07 07:02:00 PM PDT 24
Peak memory 295388 kb
Host smart-0820e087-9549-47a5-a4d4-addc10f5d2da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075920561 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.4075920561
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.4280532189
Short name T749
Test name
Test status
Simulation time 9410885100 ps
CPU time 661.25 seconds
Started Jun 07 06:59:48 PM PDT 24
Finished Jun 07 07:10:50 PM PDT 24
Peak memory 312488 kb
Host smart-efbd2fbd-9d45-4e16-ac40-fd4bebf6eb0f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280532189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.flash_ctrl_rw.4280532189
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.3799627907
Short name T108
Test name
Test status
Simulation time 18793330700 ps
CPU time 714.83 seconds
Started Jun 07 06:59:44 PM PDT 24
Finished Jun 07 07:11:40 PM PDT 24
Peak memory 347072 kb
Host smart-e76b6d59-8801-4f77-b2cc-88b6ee5cfddf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799627907 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_rw_derr.3799627907
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict.1966939630
Short name T858
Test name
Test status
Simulation time 90491600 ps
CPU time 31.11 seconds
Started Jun 07 06:59:45 PM PDT 24
Finished Jun 07 07:00:17 PM PDT 24
Peak memory 275852 kb
Host smart-b77e5862-17d9-46d2-854a-e95c3a135011
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966939630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_rw_evict.1966939630
Directory /workspace/2.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_evict_all_en.216612526
Short name T874
Test name
Test status
Simulation time 31668200 ps
CPU time 30.75 seconds
Started Jun 07 06:59:44 PM PDT 24
Finished Jun 07 07:00:16 PM PDT 24
Peak memory 275732 kb
Host smart-baaac028-0439-4066-95ff-f34aff60a34a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216612526 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict_all_en.216612526
Directory /workspace/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_serr.2007414568
Short name T310
Test name
Test status
Simulation time 13241753200 ps
CPU time 491.8 seconds
Started Jun 07 06:59:44 PM PDT 24
Finished Jun 07 07:07:57 PM PDT 24
Peak memory 321100 kb
Host smart-19f983a4-8a55-4d09-a957-1b36102fe565
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007414568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_s
err.2007414568
Directory /workspace/2.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.2097145090
Short name T929
Test name
Test status
Simulation time 831601300 ps
CPU time 82.56 seconds
Started Jun 07 06:59:52 PM PDT 24
Finished Jun 07 07:01:16 PM PDT 24
Peak memory 264872 kb
Host smart-34d584c2-416a-4495-9920-bb940b7a7402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097145090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.2097145090
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.1611107011
Short name T50
Test name
Test status
Simulation time 1478730900 ps
CPU time 74.21 seconds
Started Jun 07 06:59:45 PM PDT 24
Finished Jun 07 07:01:01 PM PDT 24
Peak memory 265768 kb
Host smart-fe346b81-a3bf-4d88-a17b-0a8b0b006636
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611107011 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.1611107011
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.119701418
Short name T922
Test name
Test status
Simulation time 1514803500 ps
CPU time 70.59 seconds
Started Jun 07 06:59:44 PM PDT 24
Finished Jun 07 07:00:55 PM PDT 24
Peak memory 274380 kb
Host smart-71a1728b-fea1-4fcd-826c-f870a359cabb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119701418 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_counter.119701418
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.357344036
Short name T284
Test name
Test status
Simulation time 114503500 ps
CPU time 120.67 seconds
Started Jun 07 06:59:30 PM PDT 24
Finished Jun 07 07:01:32 PM PDT 24
Peak memory 276708 kb
Host smart-332e0be5-31ee-4333-bec9-0e161ee93f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357344036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.357344036
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.483884654
Short name T581
Test name
Test status
Simulation time 45309400 ps
CPU time 23.77 seconds
Started Jun 07 06:59:31 PM PDT 24
Finished Jun 07 06:59:56 PM PDT 24
Peak memory 259940 kb
Host smart-5251b9c6-a65b-43b8-a555-704cf4304333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483884654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.483884654
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.4133903735
Short name T795
Test name
Test status
Simulation time 1568393500 ps
CPU time 1191.01 seconds
Started Jun 07 06:59:55 PM PDT 24
Finished Jun 07 07:19:47 PM PDT 24
Peak memory 287116 kb
Host smart-f5f3001b-5e81-406d-b921-09b91fd60ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133903735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.4133903735
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.1771614614
Short name T688
Test name
Test status
Simulation time 41373900 ps
CPU time 26.38 seconds
Started Jun 07 06:59:32 PM PDT 24
Finished Jun 07 06:59:59 PM PDT 24
Peak memory 262556 kb
Host smart-32cf6c5f-62d7-4273-b6a4-0889e4a9882f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771614614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.1771614614
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.3993049775
Short name T763
Test name
Test status
Simulation time 9351088800 ps
CPU time 201.52 seconds
Started Jun 07 06:59:43 PM PDT 24
Finished Jun 07 07:03:06 PM PDT 24
Peak memory 260256 kb
Host smart-323d165c-4764-4823-af9f-a9cc179e9d71
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993049775 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_wo.3993049775
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.2758822616
Short name T9
Test name
Test status
Simulation time 47120500 ps
CPU time 14.74 seconds
Started Jun 07 06:59:54 PM PDT 24
Finished Jun 07 07:00:09 PM PDT 24
Peak memory 261532 kb
Host smart-a9c9f97c-677b-454f-a838-d3983042fecf
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758822616 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.2758822616
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.2772208566
Short name T455
Test name
Test status
Simulation time 161513300 ps
CPU time 13.65 seconds
Started Jun 07 07:05:00 PM PDT 24
Finished Jun 07 07:05:15 PM PDT 24
Peak memory 258516 kb
Host smart-0e45ed30-a76b-488c-9444-b186960f0d93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772208566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
2772208566
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.4115044041
Short name T219
Test name
Test status
Simulation time 51099200 ps
CPU time 15.79 seconds
Started Jun 07 07:05:02 PM PDT 24
Finished Jun 07 07:05:19 PM PDT 24
Peak memory 275008 kb
Host smart-db6882a5-2830-405f-aa4f-f171ef02fcc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115044041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.4115044041
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.2875242109
Short name T74
Test name
Test status
Simulation time 15408500 ps
CPU time 21.75 seconds
Started Jun 07 07:05:00 PM PDT 24
Finished Jun 07 07:05:23 PM PDT 24
Peak memory 265832 kb
Host smart-7f8ef44d-c86f-4c63-a177-a10b47935d92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875242109 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.2875242109
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.3830357601
Short name T1086
Test name
Test status
Simulation time 25358478500 ps
CPU time 104.49 seconds
Started Jun 07 07:04:54 PM PDT 24
Finished Jun 07 07:06:39 PM PDT 24
Peak memory 263452 kb
Host smart-4a6b0d1c-d0c6-4e78-bf44-83444319abe0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830357601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.3830357601
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.3064424356
Short name T391
Test name
Test status
Simulation time 7947821900 ps
CPU time 208.39 seconds
Started Jun 07 07:04:56 PM PDT 24
Finished Jun 07 07:08:25 PM PDT 24
Peak memory 291664 kb
Host smart-5d7a52ea-f791-4c65-aef4-27d994ff1951
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064424356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.3064424356
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.2188962187
Short name T864
Test name
Test status
Simulation time 24228242700 ps
CPU time 327.62 seconds
Started Jun 07 07:05:01 PM PDT 24
Finished Jun 07 07:10:30 PM PDT 24
Peak memory 291348 kb
Host smart-bf2eb6e4-4e76-453a-b672-e8fceab26c13
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188962187 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.2188962187
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.3693691160
Short name T156
Test name
Test status
Simulation time 41191200 ps
CPU time 131.44 seconds
Started Jun 07 07:04:55 PM PDT 24
Finished Jun 07 07:07:07 PM PDT 24
Peak memory 260052 kb
Host smart-515d643f-1a64-4bfa-82e3-130b859e7884
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693691160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.3693691160
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.1059055487
Short name T421
Test name
Test status
Simulation time 33530800 ps
CPU time 30.96 seconds
Started Jun 07 07:05:01 PM PDT 24
Finished Jun 07 07:05:33 PM PDT 24
Peak memory 276052 kb
Host smart-1e9443c2-d5a7-443e-b0ce-68f63b6c7412
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059055487 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.1059055487
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.3850865534
Short name T635
Test name
Test status
Simulation time 896066800 ps
CPU time 62.38 seconds
Started Jun 07 07:05:02 PM PDT 24
Finished Jun 07 07:06:05 PM PDT 24
Peak memory 264316 kb
Host smart-128d9515-daff-4cf1-abc8-fa10460524f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850865534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.3850865534
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.1870339273
Short name T104
Test name
Test status
Simulation time 21870700 ps
CPU time 98.39 seconds
Started Jun 07 07:04:57 PM PDT 24
Finished Jun 07 07:06:36 PM PDT 24
Peak memory 277232 kb
Host smart-45b88415-fcef-438a-8a99-023616e2496a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870339273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.1870339273
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.3580207004
Short name T580
Test name
Test status
Simulation time 108331900 ps
CPU time 13.66 seconds
Started Jun 07 07:05:09 PM PDT 24
Finished Jun 07 07:05:23 PM PDT 24
Peak memory 265516 kb
Host smart-b9891009-c8a1-4db5-8da3-ef8c4f3ba15b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580207004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
3580207004
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.3094127202
Short name T1007
Test name
Test status
Simulation time 93207600 ps
CPU time 15.71 seconds
Started Jun 07 07:05:02 PM PDT 24
Finished Jun 07 07:05:18 PM PDT 24
Peak memory 275108 kb
Host smart-9569848c-4857-4c09-ade4-d520a6fe6b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094127202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.3094127202
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2134672642
Short name T725
Test name
Test status
Simulation time 2285815700 ps
CPU time 46.11 seconds
Started Jun 07 07:05:01 PM PDT 24
Finished Jun 07 07:05:49 PM PDT 24
Peak memory 263248 kb
Host smart-e2438be3-c0dc-483f-bae3-5dee7ec6dc1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134672642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.2134672642
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.1038849933
Short name T743
Test name
Test status
Simulation time 1005271600 ps
CPU time 125.1 seconds
Started Jun 07 07:05:00 PM PDT 24
Finished Jun 07 07:07:06 PM PDT 24
Peak memory 294364 kb
Host smart-bcde9942-d018-4397-9705-94b15f4d0ef9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038849933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla
sh_ctrl_intr_rd.1038849933
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.1662389903
Short name T1038
Test name
Test status
Simulation time 8729518700 ps
CPU time 245.96 seconds
Started Jun 07 07:04:59 PM PDT 24
Finished Jun 07 07:09:06 PM PDT 24
Peak memory 291356 kb
Host smart-bcb1215e-f7e0-424d-84fa-cd9132d82c4f
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662389903 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.1662389903
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.2390069632
Short name T797
Test name
Test status
Simulation time 299040500 ps
CPU time 131.91 seconds
Started Jun 07 07:05:02 PM PDT 24
Finished Jun 07 07:07:15 PM PDT 24
Peak memory 260192 kb
Host smart-ef69ec7e-894a-47ca-9fc8-f4bd73d60a9a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390069632 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.2390069632
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.913773336
Short name T107
Test name
Test status
Simulation time 7814165200 ps
CPU time 178.96 seconds
Started Jun 07 07:05:03 PM PDT 24
Finished Jun 07 07:08:02 PM PDT 24
Peak memory 261568 kb
Host smart-0459e619-4368-4b48-8b9d-75c6b870b06c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913773336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_res
et.913773336
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.3770268848
Short name T723
Test name
Test status
Simulation time 35194000 ps
CPU time 31.08 seconds
Started Jun 07 07:05:03 PM PDT 24
Finished Jun 07 07:05:35 PM PDT 24
Peak memory 274000 kb
Host smart-4893c53c-022f-46e6-9247-60f1c57d7c8d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770268848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl
ash_ctrl_rw_evict.3770268848
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.3581468302
Short name T381
Test name
Test status
Simulation time 31183400 ps
CPU time 30.71 seconds
Started Jun 07 07:05:01 PM PDT 24
Finished Jun 07 07:05:33 PM PDT 24
Peak memory 267868 kb
Host smart-bbae1ab9-e02c-42db-8e6a-46e015dba959
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581468302 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.3581468302
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.3295664070
Short name T1053
Test name
Test status
Simulation time 1327891600 ps
CPU time 71.29 seconds
Started Jun 07 07:05:03 PM PDT 24
Finished Jun 07 07:06:15 PM PDT 24
Peak memory 264844 kb
Host smart-b63bdd08-ef1f-4b3a-bed2-42bbd385c2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295664070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3295664070
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.2266259793
Short name T1029
Test name
Test status
Simulation time 75454000 ps
CPU time 74.77 seconds
Started Jun 07 07:04:58 PM PDT 24
Finished Jun 07 07:06:14 PM PDT 24
Peak memory 270088 kb
Host smart-532e3a5d-155c-4f9a-b49a-e88c82edffa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266259793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.2266259793
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.2107863672
Short name T626
Test name
Test status
Simulation time 67122400 ps
CPU time 13.76 seconds
Started Jun 07 07:05:09 PM PDT 24
Finished Jun 07 07:05:24 PM PDT 24
Peak memory 265552 kb
Host smart-dfd0d862-8c3a-4434-aad5-f861cd066d6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107863672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
2107863672
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.2087418471
Short name T919
Test name
Test status
Simulation time 28232200 ps
CPU time 15.66 seconds
Started Jun 07 07:05:11 PM PDT 24
Finished Jun 07 07:05:28 PM PDT 24
Peak memory 275224 kb
Host smart-797b7ae1-a121-4d5a-92c3-6991c23e0628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087418471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.2087418471
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.19284070
Short name T1103
Test name
Test status
Simulation time 38262900 ps
CPU time 21.67 seconds
Started Jun 07 07:05:08 PM PDT 24
Finished Jun 07 07:05:31 PM PDT 24
Peak memory 265720 kb
Host smart-e2958c8d-d0cc-4af7-9f55-b401f54b4ab8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19284070 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.flash_ctrl_disable.19284070
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.1142468439
Short name T726
Test name
Test status
Simulation time 7254867700 ps
CPU time 114.54 seconds
Started Jun 07 07:05:09 PM PDT 24
Finished Jun 07 07:07:05 PM PDT 24
Peak memory 263304 kb
Host smart-7b2c21bb-35b5-410a-943f-67d5c402a865
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142468439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_
hw_sec_otp.1142468439
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.2571320006
Short name T1097
Test name
Test status
Simulation time 2386094500 ps
CPU time 162.7 seconds
Started Jun 07 07:05:10 PM PDT 24
Finished Jun 07 07:07:54 PM PDT 24
Peak memory 294452 kb
Host smart-c0c0ad9f-89d5-4181-b438-ed7067ab2d7d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571320006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_intr_rd.2571320006
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.61836688
Short name T885
Test name
Test status
Simulation time 6915638200 ps
CPU time 126.09 seconds
Started Jun 07 07:05:10 PM PDT 24
Finished Jun 07 07:07:17 PM PDT 24
Peak memory 292928 kb
Host smart-944fc52d-d047-40ff-b949-4a2052b8cb13
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61836688 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.61836688
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.1560891105
Short name T910
Test name
Test status
Simulation time 81381200 ps
CPU time 110.07 seconds
Started Jun 07 07:05:09 PM PDT 24
Finished Jun 07 07:07:00 PM PDT 24
Peak memory 261424 kb
Host smart-43efb0c2-953f-4749-8760-a77455d4fcb4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560891105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.1560891105
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.2898702056
Short name T951
Test name
Test status
Simulation time 54916600 ps
CPU time 14.46 seconds
Started Jun 07 07:05:12 PM PDT 24
Finished Jun 07 07:05:28 PM PDT 24
Peak memory 259316 kb
Host smart-bd73fd0a-79d8-49e5-a181-6b14b5feae87
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898702056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.2898702056
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict.105597227
Short name T1080
Test name
Test status
Simulation time 30352800 ps
CPU time 31.35 seconds
Started Jun 07 07:05:10 PM PDT 24
Finished Jun 07 07:05:42 PM PDT 24
Peak memory 273420 kb
Host smart-2e70273f-17ca-4acb-9a27-084412c5eb26
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105597227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla
sh_ctrl_rw_evict.105597227
Directory /workspace/22.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.3467678032
Short name T228
Test name
Test status
Simulation time 47555500 ps
CPU time 28.31 seconds
Started Jun 07 07:05:11 PM PDT 24
Finished Jun 07 07:05:40 PM PDT 24
Peak memory 267844 kb
Host smart-716dff4b-d6e5-4b03-90c0-dfe375033ea5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467678032 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.3467678032
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.69320405
Short name T991
Test name
Test status
Simulation time 97126700 ps
CPU time 118.98 seconds
Started Jun 07 07:05:10 PM PDT 24
Finished Jun 07 07:07:09 PM PDT 24
Peak memory 276392 kb
Host smart-895423e7-e958-47c5-9e9b-29c5eb15384f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69320405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.69320405
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.1673694488
Short name T497
Test name
Test status
Simulation time 70370900 ps
CPU time 13.73 seconds
Started Jun 07 07:05:18 PM PDT 24
Finished Jun 07 07:05:32 PM PDT 24
Peak memory 258540 kb
Host smart-72b23eaf-d645-4897-8a08-1c329ccc6616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673694488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
1673694488
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.3894753303
Short name T529
Test name
Test status
Simulation time 65829400 ps
CPU time 13.37 seconds
Started Jun 07 07:05:15 PM PDT 24
Finished Jun 07 07:05:29 PM PDT 24
Peak memory 274960 kb
Host smart-724ccc5f-eaa9-4f25-b31f-1115192e80ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894753303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.3894753303
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.2199229895
Short name T270
Test name
Test status
Simulation time 32295400 ps
CPU time 20.97 seconds
Started Jun 07 07:05:15 PM PDT 24
Finished Jun 07 07:05:37 PM PDT 24
Peak memory 274080 kb
Host smart-ba3c5cbd-1035-44b6-a25d-ca8d353fd7f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199229895 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.2199229895
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.143519763
Short name T349
Test name
Test status
Simulation time 4972115900 ps
CPU time 78.17 seconds
Started Jun 07 07:05:11 PM PDT 24
Finished Jun 07 07:06:30 PM PDT 24
Peak memory 263476 kb
Host smart-adb0e51e-fb2c-4391-ad01-d519657ec7f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143519763 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_h
w_sec_otp.143519763
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.1020713602
Short name T355
Test name
Test status
Simulation time 2863059800 ps
CPU time 226.3 seconds
Started Jun 07 07:05:12 PM PDT 24
Finished Jun 07 07:08:59 PM PDT 24
Peak memory 291556 kb
Host smart-2d6e51dc-94ef-4ef1-88db-f5eb652dc4d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020713602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla
sh_ctrl_intr_rd.1020713602
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2969813643
Short name T359
Test name
Test status
Simulation time 12001189500 ps
CPU time 278.21 seconds
Started Jun 07 07:05:11 PM PDT 24
Finished Jun 07 07:09:50 PM PDT 24
Peak memory 285248 kb
Host smart-7aba7d01-97a1-4f65-bbbc-0ee07fdec04e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969813643 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2969813643
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.1573068369
Short name T3
Test name
Test status
Simulation time 147411800 ps
CPU time 130.27 seconds
Started Jun 07 07:05:11 PM PDT 24
Finished Jun 07 07:07:22 PM PDT 24
Peak memory 260196 kb
Host smart-3095ea6f-3991-43f4-a108-762eb319af89
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573068369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.1573068369
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.1263878882
Short name T916
Test name
Test status
Simulation time 32621300 ps
CPU time 14.83 seconds
Started Jun 07 07:05:08 PM PDT 24
Finished Jun 07 07:05:23 PM PDT 24
Peak memory 259840 kb
Host smart-93d277eb-c869-4200-a991-51243ef4f52f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263878882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.1263878882
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.4136928807
Short name T319
Test name
Test status
Simulation time 157767000 ps
CPU time 28.69 seconds
Started Jun 07 07:05:15 PM PDT 24
Finished Jun 07 07:05:45 PM PDT 24
Peak memory 267868 kb
Host smart-6556268f-58c2-4d77-9c11-6d31f31a9a18
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136928807 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.4136928807
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.2485228665
Short name T77
Test name
Test status
Simulation time 2672873400 ps
CPU time 135.16 seconds
Started Jun 07 07:05:10 PM PDT 24
Finished Jun 07 07:07:26 PM PDT 24
Peak memory 279980 kb
Host smart-e1ab2b2e-b762-4f34-ac28-19c2a8654168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485228665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.2485228665
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.2703464586
Short name T465
Test name
Test status
Simulation time 13687500 ps
CPU time 16.03 seconds
Started Jun 07 07:05:15 PM PDT 24
Finished Jun 07 07:05:32 PM PDT 24
Peak memory 275144 kb
Host smart-8fb016e0-0e79-49d1-b168-09ecee21b02f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703464586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.2703464586
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.2575577561
Short name T592
Test name
Test status
Simulation time 2162434400 ps
CPU time 70.56 seconds
Started Jun 07 07:05:16 PM PDT 24
Finished Jun 07 07:06:28 PM PDT 24
Peak memory 262840 kb
Host smart-58b4663a-3065-46fe-a1a6-b60dacff843f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575577561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.2575577561
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.3656673240
Short name T240
Test name
Test status
Simulation time 24791327600 ps
CPU time 200.95 seconds
Started Jun 07 07:05:15 PM PDT 24
Finished Jun 07 07:08:37 PM PDT 24
Peak memory 291720 kb
Host smart-c1696df1-65cd-4ab5-a1b9-63fa153b733b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656673240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.3656673240
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3556141718
Short name T958
Test name
Test status
Simulation time 5824140200 ps
CPU time 146.47 seconds
Started Jun 07 07:05:16 PM PDT 24
Finished Jun 07 07:07:44 PM PDT 24
Peak memory 292760 kb
Host smart-5753f426-e059-4b10-ad46-c2733d352d98
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556141718 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.3556141718
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.1728314405
Short name T103
Test name
Test status
Simulation time 75162400 ps
CPU time 129.67 seconds
Started Jun 07 07:05:14 PM PDT 24
Finished Jun 07 07:07:25 PM PDT 24
Peak memory 265392 kb
Host smart-ce42ffbc-fadb-4997-9d61-b7c8178732bf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728314405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o
tp_reset.1728314405
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.448190244
Short name T552
Test name
Test status
Simulation time 21314300 ps
CPU time 13.5 seconds
Started Jun 07 07:05:16 PM PDT 24
Finished Jun 07 07:05:30 PM PDT 24
Peak memory 258980 kb
Host smart-9ce6bbd3-fa36-4013-877a-093d0b26698a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448190244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_res
et.448190244
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.2030984734
Short name T790
Test name
Test status
Simulation time 28121900 ps
CPU time 30.41 seconds
Started Jun 07 07:05:15 PM PDT 24
Finished Jun 07 07:05:47 PM PDT 24
Peak memory 268864 kb
Host smart-b13b11ee-26c7-4958-b04f-a5810542ca25
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030984734 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.2030984734
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.2494202166
Short name T449
Test name
Test status
Simulation time 20057640200 ps
CPU time 93.84 seconds
Started Jun 07 07:05:15 PM PDT 24
Finished Jun 07 07:06:50 PM PDT 24
Peak memory 263796 kb
Host smart-e605859d-7f7f-4fb8-adb9-7ab70e60b3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494202166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.2494202166
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.1370752635
Short name T882
Test name
Test status
Simulation time 22794000 ps
CPU time 101.06 seconds
Started Jun 07 07:05:17 PM PDT 24
Finished Jun 07 07:06:59 PM PDT 24
Peak memory 276096 kb
Host smart-5888a476-cbc7-4f43-972c-0e111bd88dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370752635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.1370752635
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.3642107877
Short name T456
Test name
Test status
Simulation time 396088700 ps
CPU time 13.94 seconds
Started Jun 07 07:05:23 PM PDT 24
Finished Jun 07 07:05:38 PM PDT 24
Peak memory 258540 kb
Host smart-0e25b751-d2b0-4c64-a0ea-0fc05bc88b8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642107877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
3642107877
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.2471746748
Short name T1064
Test name
Test status
Simulation time 14818200 ps
CPU time 15.6 seconds
Started Jun 07 07:05:22 PM PDT 24
Finished Jun 07 07:05:40 PM PDT 24
Peak memory 284664 kb
Host smart-fa0fc424-e936-47e0-b7f3-23b8f2c1c957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471746748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.2471746748
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.2422188621
Short name T406
Test name
Test status
Simulation time 128637400 ps
CPU time 22.12 seconds
Started Jun 07 07:05:22 PM PDT 24
Finished Jun 07 07:05:46 PM PDT 24
Peak memory 274036 kb
Host smart-f0edabea-bcf0-4eeb-8bd1-10eef85f8ca4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422188621 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.2422188621
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.2586912019
Short name T672
Test name
Test status
Simulation time 6964777000 ps
CPU time 146.43 seconds
Started Jun 07 07:05:23 PM PDT 24
Finished Jun 07 07:07:51 PM PDT 24
Peak memory 263364 kb
Host smart-a95b4be6-003b-4812-b795-8c74c1c161ad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586912019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_
hw_sec_otp.2586912019
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3156105214
Short name T356
Test name
Test status
Simulation time 34709753200 ps
CPU time 147.96 seconds
Started Jun 07 07:05:24 PM PDT 24
Finished Jun 07 07:07:53 PM PDT 24
Peak memory 294560 kb
Host smart-8313774a-1750-4bf2-b894-8fb33b6f9afa
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156105214 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.3156105214
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.433144130
Short name T582
Test name
Test status
Simulation time 258595400 ps
CPU time 109.13 seconds
Started Jun 07 07:05:22 PM PDT 24
Finished Jun 07 07:07:13 PM PDT 24
Peak memory 260240 kb
Host smart-5ccb0898-afe6-4461-b9d9-505905f31af6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433144130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_ot
p_reset.433144130
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.1726006663
Short name T806
Test name
Test status
Simulation time 21758100 ps
CPU time 13.38 seconds
Started Jun 07 07:05:23 PM PDT 24
Finished Jun 07 07:05:38 PM PDT 24
Peak memory 259088 kb
Host smart-af75bbcf-d42e-4dc6-b3e0-e8c27c4e4ee6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726006663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_re
set.1726006663
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.2006008185
Short name T1099
Test name
Test status
Simulation time 29763100 ps
CPU time 30.51 seconds
Started Jun 07 07:05:22 PM PDT 24
Finished Jun 07 07:05:54 PM PDT 24
Peak memory 274008 kb
Host smart-76971b5c-8e21-47c2-b8bc-84eaa6f29a2d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006008185 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.2006008185
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.1222951415
Short name T830
Test name
Test status
Simulation time 921117600 ps
CPU time 51.57 seconds
Started Jun 07 07:05:23 PM PDT 24
Finished Jun 07 07:06:16 PM PDT 24
Peak memory 265128 kb
Host smart-550b40ba-d35f-4a86-9e12-a9bc905926a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222951415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1222951415
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.3766901725
Short name T285
Test name
Test status
Simulation time 62298300 ps
CPU time 146.28 seconds
Started Jun 07 07:05:23 PM PDT 24
Finished Jun 07 07:07:51 PM PDT 24
Peak memory 278476 kb
Host smart-b399b67c-dc7f-49b0-a975-30a996ee991a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766901725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.3766901725
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.51886885
Short name T606
Test name
Test status
Simulation time 42038100 ps
CPU time 13.79 seconds
Started Jun 07 07:05:39 PM PDT 24
Finished Jun 07 07:05:53 PM PDT 24
Peak memory 258600 kb
Host smart-fe94fbc8-b25d-47a7-a308-209dbfd10617
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51886885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.51886885
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.560527388
Short name T801
Test name
Test status
Simulation time 53581000 ps
CPU time 13.4 seconds
Started Jun 07 07:05:37 PM PDT 24
Finished Jun 07 07:05:51 PM PDT 24
Peak memory 275112 kb
Host smart-ff9d7f35-62e4-47db-a23d-0c5fac4d3c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560527388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.560527388
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.436216789
Short name T83
Test name
Test status
Simulation time 18040400 ps
CPU time 20.45 seconds
Started Jun 07 07:05:30 PM PDT 24
Finished Jun 07 07:05:51 PM PDT 24
Peak memory 274108 kb
Host smart-422a3ba8-9419-4da6-bb92-f65cb1d5b90f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436216789 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.436216789
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.4097899088
Short name T351
Test name
Test status
Simulation time 15281189300 ps
CPU time 161.59 seconds
Started Jun 07 07:05:23 PM PDT 24
Finished Jun 07 07:08:06 PM PDT 24
Peak memory 263400 kb
Host smart-d8e9e2d2-c562-439b-b489-620687467269
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097899088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.4097899088
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.1866971954
Short name T1034
Test name
Test status
Simulation time 725632500 ps
CPU time 153.66 seconds
Started Jun 07 07:05:30 PM PDT 24
Finished Jun 07 07:08:04 PM PDT 24
Peak memory 285568 kb
Host smart-28a8b238-dd96-4ee1-ae47-e274ca62cdbf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866971954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.1866971954
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.3248545061
Short name T681
Test name
Test status
Simulation time 19609226300 ps
CPU time 153.54 seconds
Started Jun 07 07:05:30 PM PDT 24
Finished Jun 07 07:08:05 PM PDT 24
Peak memory 291364 kb
Host smart-31a1b6b5-11ba-4af0-b651-67c9a50b01a7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248545061 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.3248545061
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.3670694027
Short name T706
Test name
Test status
Simulation time 76143900 ps
CPU time 131.41 seconds
Started Jun 07 07:05:31 PM PDT 24
Finished Jun 07 07:07:43 PM PDT 24
Peak memory 260352 kb
Host smart-8a14c066-faee-488a-8ada-a535d22f9fb3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670694027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.3670694027
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.690905099
Short name T520
Test name
Test status
Simulation time 63840700 ps
CPU time 13.48 seconds
Started Jun 07 07:05:30 PM PDT 24
Finished Jun 07 07:05:44 PM PDT 24
Peak memory 258948 kb
Host smart-eda07132-de38-4ec6-99a1-a33656dbd2fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690905099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_res
et.690905099
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict.1002942033
Short name T861
Test name
Test status
Simulation time 73546000 ps
CPU time 30.99 seconds
Started Jun 07 07:05:31 PM PDT 24
Finished Jun 07 07:06:03 PM PDT 24
Peak memory 277036 kb
Host smart-4ff14b2d-71d4-4c53-9791-a58b764ba3d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002942033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl
ash_ctrl_rw_evict.1002942033
Directory /workspace/26.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.3966005664
Short name T447
Test name
Test status
Simulation time 704124200 ps
CPU time 68.54 seconds
Started Jun 07 07:05:37 PM PDT 24
Finished Jun 07 07:06:46 PM PDT 24
Peak memory 264176 kb
Host smart-cdc006be-687b-4b45-bd3b-0ae3f245f786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966005664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.3966005664
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.1231253008
Short name T1094
Test name
Test status
Simulation time 101227100 ps
CPU time 192.95 seconds
Started Jun 07 07:05:22 PM PDT 24
Finished Jun 07 07:08:36 PM PDT 24
Peak memory 279880 kb
Host smart-b8237c80-df36-40b6-b32c-9f53012a05c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231253008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.1231253008
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.3358856640
Short name T457
Test name
Test status
Simulation time 162057100 ps
CPU time 14.47 seconds
Started Jun 07 07:05:35 PM PDT 24
Finished Jun 07 07:05:50 PM PDT 24
Peak memory 265488 kb
Host smart-720d4b9e-9802-45ea-bb36-bb59e8d4832d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358856640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.
3358856640
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.1638289596
Short name T1091
Test name
Test status
Simulation time 39890800 ps
CPU time 15.86 seconds
Started Jun 07 07:05:38 PM PDT 24
Finished Jun 07 07:05:54 PM PDT 24
Peak memory 275188 kb
Host smart-958750e9-5965-4ac8-b859-b4b87f8e1ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638289596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.1638289596
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.811909014
Short name T443
Test name
Test status
Simulation time 34051300 ps
CPU time 22.1 seconds
Started Jun 07 07:05:37 PM PDT 24
Finished Jun 07 07:05:59 PM PDT 24
Peak memory 274088 kb
Host smart-118a6e44-afe3-4855-8346-f4e299a3933c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811909014 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.811909014
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.2029424960
Short name T467
Test name
Test status
Simulation time 26736199700 ps
CPU time 228.15 seconds
Started Jun 07 07:05:36 PM PDT 24
Finished Jun 07 07:09:25 PM PDT 24
Peak memory 263432 kb
Host smart-d58b0a22-bfac-4ee3-9667-526626828bfb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029424960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.2029424960
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.4193195950
Short name T499
Test name
Test status
Simulation time 21962877300 ps
CPU time 144.33 seconds
Started Jun 07 07:05:37 PM PDT 24
Finished Jun 07 07:08:02 PM PDT 24
Peak memory 293316 kb
Host smart-ec9f48a4-88e3-47d3-b69f-33b6892d532c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193195950 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.4193195950
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.1360772242
Short name T1074
Test name
Test status
Simulation time 40146200 ps
CPU time 131.54 seconds
Started Jun 07 07:05:37 PM PDT 24
Finished Jun 07 07:07:50 PM PDT 24
Peak memory 260352 kb
Host smart-91659ac0-cd7c-496e-b731-01ba72babb08
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360772242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.1360772242
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.1618861965
Short name T931
Test name
Test status
Simulation time 20827800 ps
CPU time 13.42 seconds
Started Jun 07 07:05:35 PM PDT 24
Finished Jun 07 07:05:49 PM PDT 24
Peak memory 258916 kb
Host smart-9a2b5084-e607-4695-96f0-adb8fad2d44f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618861965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_re
set.1618861965
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict.635302153
Short name T598
Test name
Test status
Simulation time 29544300 ps
CPU time 31.17 seconds
Started Jun 07 07:05:36 PM PDT 24
Finished Jun 07 07:06:08 PM PDT 24
Peak memory 275744 kb
Host smart-6c55309d-1024-48ac-ae76-5e61aa369716
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635302153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_rw_evict.635302153
Directory /workspace/27.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.1662796121
Short name T868
Test name
Test status
Simulation time 40746100 ps
CPU time 30.73 seconds
Started Jun 07 07:05:37 PM PDT 24
Finished Jun 07 07:06:08 PM PDT 24
Peak memory 273980 kb
Host smart-5ca6e1f4-0254-4a1c-9869-bb5808d9d6bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662796121 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.1662796121
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.466041787
Short name T668
Test name
Test status
Simulation time 1931891400 ps
CPU time 56.35 seconds
Started Jun 07 07:05:38 PM PDT 24
Finished Jun 07 07:06:35 PM PDT 24
Peak memory 264348 kb
Host smart-88126215-32ce-4ddd-9fd5-7ece4d8dbe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466041787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.466041787
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.2037710277
Short name T126
Test name
Test status
Simulation time 45834300 ps
CPU time 14.03 seconds
Started Jun 07 07:05:52 PM PDT 24
Finished Jun 07 07:06:07 PM PDT 24
Peak memory 265488 kb
Host smart-2d48cc3d-dd94-45ed-a4cf-6dd7455af6a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037710277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
2037710277
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.4268313879
Short name T714
Test name
Test status
Simulation time 50679000 ps
CPU time 16.32 seconds
Started Jun 07 07:05:51 PM PDT 24
Finished Jun 07 07:06:08 PM PDT 24
Peak memory 275088 kb
Host smart-32c4c5a9-75c0-43e5-b0a4-9789ce04f5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268313879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.4268313879
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.151737087
Short name T735
Test name
Test status
Simulation time 13290800 ps
CPU time 21.9 seconds
Started Jun 07 07:05:50 PM PDT 24
Finished Jun 07 07:06:13 PM PDT 24
Peak memory 274068 kb
Host smart-94bc8566-72a6-4660-9fbc-1e19eb5a8701
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151737087 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.151737087
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.2118874423
Short name T928
Test name
Test status
Simulation time 1324419300 ps
CPU time 48.08 seconds
Started Jun 07 07:05:44 PM PDT 24
Finished Jun 07 07:06:32 PM PDT 24
Peak memory 262892 kb
Host smart-f1cd7145-9900-4e93-9d10-554b2e2f9e3d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118874423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.2118874423
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.1892579325
Short name T645
Test name
Test status
Simulation time 137953300 ps
CPU time 108.64 seconds
Started Jun 07 07:05:44 PM PDT 24
Finished Jun 07 07:07:34 PM PDT 24
Peak memory 260216 kb
Host smart-2171c1f2-7cbe-4c36-afb9-7f073edbc561
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892579325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.1892579325
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.3552524614
Short name T587
Test name
Test status
Simulation time 40051500 ps
CPU time 13.32 seconds
Started Jun 07 07:05:45 PM PDT 24
Finished Jun 07 07:05:59 PM PDT 24
Peak memory 265464 kb
Host smart-cffc8ac4-b8f0-4ac7-829d-2f396f0331c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552524614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.3552524614
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.1777297391
Short name T271
Test name
Test status
Simulation time 104206900 ps
CPU time 30.68 seconds
Started Jun 07 07:05:51 PM PDT 24
Finished Jun 07 07:06:23 PM PDT 24
Peak memory 275780 kb
Host smart-f7aecdfa-ff70-4a4d-81ae-53e917b001f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777297391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.1777297391
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.972953893
Short name T677
Test name
Test status
Simulation time 45979100 ps
CPU time 28.78 seconds
Started Jun 07 07:05:51 PM PDT 24
Finished Jun 07 07:06:21 PM PDT 24
Peak memory 276028 kb
Host smart-9994b5ea-46f1-4e54-9a8a-e3b833020cb3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972953893 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.972953893
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.2665916544
Short name T137
Test name
Test status
Simulation time 21325100 ps
CPU time 120.13 seconds
Started Jun 07 07:05:38 PM PDT 24
Finished Jun 07 07:07:39 PM PDT 24
Peak memory 277760 kb
Host smart-3ab1e45f-ce40-4bd2-a2f1-a8c4d9e972de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665916544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.2665916544
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.4193153389
Short name T133
Test name
Test status
Simulation time 57313300 ps
CPU time 13.97 seconds
Started Jun 07 07:06:00 PM PDT 24
Finished Jun 07 07:06:15 PM PDT 24
Peak memory 258516 kb
Host smart-49df1fb8-44c2-4281-beaf-4f8e1b3b99f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193153389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
4193153389
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.913467169
Short name T783
Test name
Test status
Simulation time 52770600 ps
CPU time 13.63 seconds
Started Jun 07 07:05:59 PM PDT 24
Finished Jun 07 07:06:13 PM PDT 24
Peak memory 284440 kb
Host smart-3b50ff74-2699-466a-8a78-8f2ec76f5fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913467169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.913467169
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.3780986379
Short name T791
Test name
Test status
Simulation time 18292300 ps
CPU time 21.64 seconds
Started Jun 07 07:06:02 PM PDT 24
Finished Jun 07 07:06:24 PM PDT 24
Peak memory 265852 kb
Host smart-ca50503f-f32e-47e4-be86-1a875d30bec1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780986379 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.3780986379
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.4067082836
Short name T609
Test name
Test status
Simulation time 4360229700 ps
CPU time 85.49 seconds
Started Jun 07 07:05:54 PM PDT 24
Finished Jun 07 07:07:20 PM PDT 24
Peak memory 263392 kb
Host smart-f0828d07-b00f-4ddd-8cef-b3402d94b316
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067082836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.4067082836
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.3197914790
Short name T1093
Test name
Test status
Simulation time 163848800 ps
CPU time 134.71 seconds
Started Jun 07 07:05:52 PM PDT 24
Finished Jun 07 07:08:07 PM PDT 24
Peak memory 260392 kb
Host smart-d8779782-63b1-4811-bb39-bd350fa64255
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197914790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o
tp_reset.3197914790
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.1379484174
Short name T844
Test name
Test status
Simulation time 17249923800 ps
CPU time 191.87 seconds
Started Jun 07 07:05:52 PM PDT 24
Finished Jun 07 07:09:05 PM PDT 24
Peak memory 265476 kb
Host smart-5a7a42c9-6f84-4621-97e1-db430234a597
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379484174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.1379484174
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.1887524642
Short name T267
Test name
Test status
Simulation time 32153200 ps
CPU time 31.58 seconds
Started Jun 07 07:06:00 PM PDT 24
Finished Jun 07 07:06:33 PM PDT 24
Peak memory 275788 kb
Host smart-a99e2748-d5dc-4377-8c15-0391d9011d82
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887524642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fl
ash_ctrl_rw_evict.1887524642
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.3262299622
Short name T475
Test name
Test status
Simulation time 42927500 ps
CPU time 30.86 seconds
Started Jun 07 07:05:59 PM PDT 24
Finished Jun 07 07:06:31 PM PDT 24
Peak memory 267908 kb
Host smart-fdad01b0-4e14-4839-886d-da20bb05d987
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262299622 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.3262299622
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.772377124
Short name T996
Test name
Test status
Simulation time 1456664800 ps
CPU time 54.92 seconds
Started Jun 07 07:05:58 PM PDT 24
Finished Jun 07 07:06:54 PM PDT 24
Peak memory 264208 kb
Host smart-9e61c0ac-cd5c-41de-be0b-35b1a8405989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772377124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.772377124
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.2301017107
Short name T886
Test name
Test status
Simulation time 20549100 ps
CPU time 49.52 seconds
Started Jun 07 07:05:51 PM PDT 24
Finished Jun 07 07:06:42 PM PDT 24
Peak memory 270084 kb
Host smart-09e3ace3-8a3b-48a7-99fc-746de9e15e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301017107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.2301017107
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.385511752
Short name T348
Test name
Test status
Simulation time 45672400 ps
CPU time 13.63 seconds
Started Jun 07 07:00:33 PM PDT 24
Finished Jun 07 07:00:48 PM PDT 24
Peak memory 258672 kb
Host smart-be7b102a-d4bf-4615-94ca-9fb96dc25b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385511752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.385511752
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.2291650336
Short name T287
Test name
Test status
Simulation time 73201300 ps
CPU time 13.82 seconds
Started Jun 07 07:00:32 PM PDT 24
Finished Jun 07 07:00:46 PM PDT 24
Peak memory 261864 kb
Host smart-d512b190-ed8a-4e97-bf37-fa449dfe7857
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291650336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.2291650336
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.4060110955
Short name T1045
Test name
Test status
Simulation time 46059200 ps
CPU time 16.15 seconds
Started Jun 07 07:00:25 PM PDT 24
Finished Jun 07 07:00:42 PM PDT 24
Peak memory 284564 kb
Host smart-ea71a1ce-deff-49e7-baf3-6c56ad04935c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060110955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.4060110955
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.4206913420
Short name T280
Test name
Test status
Simulation time 117914900 ps
CPU time 99.96 seconds
Started Jun 07 07:00:16 PM PDT 24
Finished Jun 07 07:01:57 PM PDT 24
Peak memory 282240 kb
Host smart-54107d28-7e2d-45af-8717-a57b843c7dcb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206913420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_derr_detect.4206913420
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.1313007108
Short name T845
Test name
Test status
Simulation time 17643600 ps
CPU time 22.05 seconds
Started Jun 07 07:00:26 PM PDT 24
Finished Jun 07 07:00:49 PM PDT 24
Peak memory 274076 kb
Host smart-d2e033ae-2280-495a-b9f2-4a365293ffec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313007108 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.1313007108
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.1232298105
Short name T178
Test name
Test status
Simulation time 8177692100 ps
CPU time 418.03 seconds
Started Jun 07 07:00:10 PM PDT 24
Finished Jun 07 07:07:09 PM PDT 24
Peak memory 263440 kb
Host smart-0bd7076f-357b-4042-8e69-6eadab25c6b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232298105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.1232298105
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.2722211213
Short name T251
Test name
Test status
Simulation time 6795418500 ps
CPU time 2248.52 seconds
Started Jun 07 07:00:16 PM PDT 24
Finished Jun 07 07:37:46 PM PDT 24
Peak memory 264692 kb
Host smart-e4d93710-1ed6-4763-8b10-7fe1b35fef32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722211213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.2722211213
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.579453812
Short name T892
Test name
Test status
Simulation time 1373838700 ps
CPU time 2643.27 seconds
Started Jun 07 07:00:18 PM PDT 24
Finished Jun 07 07:44:23 PM PDT 24
Peak memory 264784 kb
Host smart-3db3e7b5-4407-49c4-9d53-4a1ffd5c2c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579453812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.579453812
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.1639784692
Short name T1026
Test name
Test status
Simulation time 745830800 ps
CPU time 904.51 seconds
Started Jun 07 07:00:18 PM PDT 24
Finished Jun 07 07:15:23 PM PDT 24
Peak memory 272788 kb
Host smart-b65378fe-ab4e-412f-8c41-b1aaa602f8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639784692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1639784692
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.439384759
Short name T208
Test name
Test status
Simulation time 649788000 ps
CPU time 42.38 seconds
Started Jun 07 07:00:25 PM PDT 24
Finished Jun 07 07:01:09 PM PDT 24
Peak memory 263152 kb
Host smart-9324de9f-36a5-4ef1-bcca-ac46cb5c2870
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439384759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_fs_sup.439384759
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.2861067440
Short name T233
Test name
Test status
Simulation time 90005813200 ps
CPU time 2513.22 seconds
Started Jun 07 07:00:19 PM PDT 24
Finished Jun 07 07:42:14 PM PDT 24
Peak memory 265536 kb
Host smart-e3fcba24-1bbf-4566-9a37-d34a7ac74e96
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861067440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.2861067440
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.2793440648
Short name T891
Test name
Test status
Simulation time 371345692500 ps
CPU time 2493.08 seconds
Started Jun 07 07:00:08 PM PDT 24
Finished Jun 07 07:41:43 PM PDT 24
Peak memory 264388 kb
Host smart-4926df31-4589-425d-bc48-fd639827ea74
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793440648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.2793440648
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.233884968
Short name T776
Test name
Test status
Simulation time 67199900 ps
CPU time 124.72 seconds
Started Jun 07 07:00:00 PM PDT 24
Finished Jun 07 07:02:05 PM PDT 24
Peak memory 262980 kb
Host smart-7596defe-e69f-440a-a5cd-f8a718132beb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=233884968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.233884968
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1125137991
Short name T653
Test name
Test status
Simulation time 10020458700 ps
CPU time 80.98 seconds
Started Jun 07 07:00:31 PM PDT 24
Finished Jun 07 07:01:53 PM PDT 24
Peak memory 313960 kb
Host smart-ec2ad62f-070d-4757-873b-c3a6ca73c65e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125137991 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.1125137991
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.834228854
Short name T799
Test name
Test status
Simulation time 15051000 ps
CPU time 13.4 seconds
Started Jun 07 07:00:33 PM PDT 24
Finished Jun 07 07:00:48 PM PDT 24
Peak memory 258764 kb
Host smart-71ead47f-7bbf-4e58-b5ca-74d43ad7fbdf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834228854 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.834228854
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.919778634
Short name T191
Test name
Test status
Simulation time 270267760400 ps
CPU time 861.73 seconds
Started Jun 07 07:00:10 PM PDT 24
Finished Jun 07 07:14:32 PM PDT 24
Peak memory 264740 kb
Host smart-fd1d1703-2c69-4f0f-bbe4-bea069741c66
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919778634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_hw_rma_reset.919778634
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.1264208057
Short name T468
Test name
Test status
Simulation time 4770289600 ps
CPU time 158.45 seconds
Started Jun 07 07:00:09 PM PDT 24
Finished Jun 07 07:02:48 PM PDT 24
Peak memory 263332 kb
Host smart-f51efcc3-83eb-4731-86a4-a4abd2bb73a2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264208057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.1264208057
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.2159354393
Short name T1021
Test name
Test status
Simulation time 17753732700 ps
CPU time 227.57 seconds
Started Jun 07 07:00:23 PM PDT 24
Finished Jun 07 07:04:11 PM PDT 24
Peak memory 285048 kb
Host smart-bc088bf8-477d-484f-a604-b6b39f323bca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159354393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.2159354393
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.3085233167
Short name T859
Test name
Test status
Simulation time 22780233100 ps
CPU time 148.57 seconds
Started Jun 07 07:00:25 PM PDT 24
Finished Jun 07 07:02:55 PM PDT 24
Peak memory 293332 kb
Host smart-5ebc15c2-8f93-48c9-948b-d393e64bde16
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085233167 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.3085233167
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.2111422027
Short name T934
Test name
Test status
Simulation time 2794324900 ps
CPU time 71.83 seconds
Started Jun 07 07:00:22 PM PDT 24
Finished Jun 07 07:01:35 PM PDT 24
Peak memory 260824 kb
Host smart-5e482b8f-2367-4dce-abed-db59d368a4e8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111422027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.2111422027
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3480462682
Short name T34
Test name
Test status
Simulation time 41054045700 ps
CPU time 191.69 seconds
Started Jun 07 07:00:27 PM PDT 24
Finished Jun 07 07:03:40 PM PDT 24
Peak memory 265396 kb
Host smart-9205d5ce-1c7a-47bd-b510-823fb377de2d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348
0462682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.3480462682
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.1403051243
Short name T463
Test name
Test status
Simulation time 2046339700 ps
CPU time 92.07 seconds
Started Jun 07 07:00:18 PM PDT 24
Finished Jun 07 07:01:51 PM PDT 24
Peak memory 260928 kb
Host smart-5c8e8071-d233-4593-a6d6-b923d1195649
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403051243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.1403051243
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.1499091142
Short name T184
Test name
Test status
Simulation time 1830317600 ps
CPU time 69.93 seconds
Started Jun 07 07:00:24 PM PDT 24
Finished Jun 07 07:01:35 PM PDT 24
Peak memory 260524 kb
Host smart-90103f82-97df-4a3b-83c6-bc7e2ec10143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499091142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.1499091142
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.1905541151
Short name T826
Test name
Test status
Simulation time 69463877200 ps
CPU time 350.41 seconds
Started Jun 07 07:00:10 PM PDT 24
Finished Jun 07 07:06:01 PM PDT 24
Peak memory 274620 kb
Host smart-443d94a3-8292-4a0b-8650-239750d080c5
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905541151 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.1905541151
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.3277201586
Short name T151
Test name
Test status
Simulation time 40621200 ps
CPU time 131.12 seconds
Started Jun 07 07:00:08 PM PDT 24
Finished Jun 07 07:02:20 PM PDT 24
Peak memory 260484 kb
Host smart-8299bd44-5bcc-46c9-a133-87de97e0510a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277201586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot
p_reset.3277201586
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.1396529233
Short name T243
Test name
Test status
Simulation time 25282500 ps
CPU time 13.87 seconds
Started Jun 07 07:00:32 PM PDT 24
Finished Jun 07 07:00:47 PM PDT 24
Peak memory 262056 kb
Host smart-6d8fc195-1a28-412d-9f5d-556695c32846
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=1396529233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1396529233
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.4132349996
Short name T78
Test name
Test status
Simulation time 3034968800 ps
CPU time 460.27 seconds
Started Jun 07 06:59:59 PM PDT 24
Finished Jun 07 07:07:40 PM PDT 24
Peak memory 263440 kb
Host smart-05e57f07-6d95-4513-9fe1-37c6a0db03cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4132349996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.4132349996
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.1544716106
Short name T179
Test name
Test status
Simulation time 45250100 ps
CPU time 13.93 seconds
Started Jun 07 07:00:24 PM PDT 24
Finished Jun 07 07:00:39 PM PDT 24
Peak memory 266016 kb
Host smart-7be88520-d289-4410-bbdd-b180f6506cdc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544716106 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.1544716106
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.2458077969
Short name T307
Test name
Test status
Simulation time 11219818300 ps
CPU time 196.56 seconds
Started Jun 07 07:00:26 PM PDT 24
Finished Jun 07 07:03:44 PM PDT 24
Peak memory 265668 kb
Host smart-0f1f99ed-a6b3-4b56-a9e6-9344837fc710
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458077969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.2458077969
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.24950715
Short name T48
Test name
Test status
Simulation time 121348400 ps
CPU time 119.56 seconds
Started Jun 07 07:00:02 PM PDT 24
Finished Jun 07 07:02:03 PM PDT 24
Peak memory 276560 kb
Host smart-f610aaed-2914-4384-acdf-77a5e9d80c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24950715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.24950715
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.1215644594
Short name T58
Test name
Test status
Simulation time 2918343100 ps
CPU time 140.95 seconds
Started Jun 07 07:00:01 PM PDT 24
Finished Jun 07 07:02:23 PM PDT 24
Peak memory 263016 kb
Host smart-71293080-f563-45c8-97fd-a09db707c4d6
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1215644594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.1215644594
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.967989692
Short name T308
Test name
Test status
Simulation time 81086300 ps
CPU time 34.9 seconds
Started Jun 07 07:00:24 PM PDT 24
Finished Jun 07 07:01:00 PM PDT 24
Peak memory 275768 kb
Host smart-1e112660-d515-4ed4-9aa4-b5b88d66795f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967989692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_re_evict.967989692
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.3871994350
Short name T831
Test name
Test status
Simulation time 1003017900 ps
CPU time 122.76 seconds
Started Jun 07 07:00:17 PM PDT 24
Finished Jun 07 07:02:21 PM PDT 24
Peak memory 282132 kb
Host smart-1f7e8026-94ae-428d-b36d-a42368689e1b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871994350 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.3871994350
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.2229910598
Short name T607
Test name
Test status
Simulation time 465172300 ps
CPU time 114.5 seconds
Started Jun 07 07:00:18 PM PDT 24
Finished Jun 07 07:02:13 PM PDT 24
Peak memory 295460 kb
Host smart-59000d9d-f37e-483d-bc9d-549d5454ba69
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229910598 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.2229910598
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.4016170864
Short name T594
Test name
Test status
Simulation time 14073321800 ps
CPU time 541.94 seconds
Started Jun 07 07:00:19 PM PDT 24
Finished Jun 07 07:09:22 PM PDT 24
Peak memory 314848 kb
Host smart-2233baf3-1011-4762-88d4-3f81afb08c2e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016170864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.flash_ctrl_rw.4016170864
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.1721017379
Short name T986
Test name
Test status
Simulation time 14466429700 ps
CPU time 630.49 seconds
Started Jun 07 07:00:18 PM PDT 24
Finished Jun 07 07:10:49 PM PDT 24
Peak memory 337248 kb
Host smart-e6c2969f-30e1-4356-926d-0a92c715ae49
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721017379 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_rw_derr.1721017379
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.3151752185
Short name T135
Test name
Test status
Simulation time 73298200 ps
CPU time 30.92 seconds
Started Jun 07 07:00:25 PM PDT 24
Finished Jun 07 07:00:57 PM PDT 24
Peak memory 274004 kb
Host smart-e3884e4c-30d7-4094-bd82-a46e81627fcb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151752185 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.3151752185
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.2999060720
Short name T454
Test name
Test status
Simulation time 9222776000 ps
CPU time 69.92 seconds
Started Jun 07 07:00:24 PM PDT 24
Finished Jun 07 07:01:35 PM PDT 24
Peak memory 263276 kb
Host smart-b86e7d0a-594a-4dcc-9606-9c1763b500d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999060720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.2999060720
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.2338628932
Short name T488
Test name
Test status
Simulation time 3346416900 ps
CPU time 71.6 seconds
Started Jun 07 07:00:17 PM PDT 24
Finished Jun 07 07:01:29 PM PDT 24
Peak memory 265596 kb
Host smart-7fb4c49f-ee41-41e9-ad36-946b2aebabb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338628932 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.2338628932
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.3854953151
Short name T109
Test name
Test status
Simulation time 4687052100 ps
CPU time 72.2 seconds
Started Jun 07 07:00:24 PM PDT 24
Finished Jun 07 07:01:37 PM PDT 24
Peak memory 275072 kb
Host smart-a5c5cdce-4856-472c-8294-08242ff02854
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854953151 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.3854953151
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.3639020038
Short name T432
Test name
Test status
Simulation time 93039400 ps
CPU time 144.16 seconds
Started Jun 07 07:00:01 PM PDT 24
Finished Jun 07 07:02:26 PM PDT 24
Peak memory 279036 kb
Host smart-b049882d-d9ec-40d8-b3ac-fc6d9f365269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639020038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.3639020038
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.1337281620
Short name T927
Test name
Test status
Simulation time 14810500 ps
CPU time 25.62 seconds
Started Jun 07 06:59:59 PM PDT 24
Finished Jun 07 07:00:25 PM PDT 24
Peak memory 259972 kb
Host smart-e0da392f-2f69-429a-9ae5-04fef5ff02e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337281620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.1337281620
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.3524665863
Short name T1015
Test name
Test status
Simulation time 17126438300 ps
CPU time 1803.72 seconds
Started Jun 07 07:00:24 PM PDT 24
Finished Jun 07 07:30:29 PM PDT 24
Peak memory 291148 kb
Host smart-d1844227-032d-4010-86c7-bbda078dc9fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524665863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.3524665863
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.2060494934
Short name T650
Test name
Test status
Simulation time 26777200 ps
CPU time 24.49 seconds
Started Jun 07 06:59:59 PM PDT 24
Finished Jun 07 07:00:24 PM PDT 24
Peak memory 259848 kb
Host smart-08cef359-807d-4130-89e5-d41006c7dea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060494934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.2060494934
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.2368763066
Short name T670
Test name
Test status
Simulation time 1712969000 ps
CPU time 123.22 seconds
Started Jun 07 07:00:19 PM PDT 24
Finished Jun 07 07:02:23 PM PDT 24
Peak memory 259632 kb
Host smart-cc1b7529-15d2-487d-b8ef-28bb558e3a6e
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368763066 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_wo.2368763066
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.2221464600
Short name T563
Test name
Test status
Simulation time 51468500 ps
CPU time 13.67 seconds
Started Jun 07 07:06:01 PM PDT 24
Finished Jun 07 07:06:16 PM PDT 24
Peak memory 258568 kb
Host smart-aa16be73-4598-4fa3-ac43-6d25ac992d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221464600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
2221464600
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.3348416272
Short name T757
Test name
Test status
Simulation time 13791500 ps
CPU time 16.13 seconds
Started Jun 07 07:05:57 PM PDT 24
Finished Jun 07 07:06:14 PM PDT 24
Peak memory 284528 kb
Host smart-d4456ce6-7733-4b23-b5fd-34cc0ab5b158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348416272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.3348416272
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.1667050719
Short name T444
Test name
Test status
Simulation time 35594400 ps
CPU time 21.77 seconds
Started Jun 07 07:05:59 PM PDT 24
Finished Jun 07 07:06:22 PM PDT 24
Peak memory 265304 kb
Host smart-26103bc8-8454-4188-bdf1-276e121bab63
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667050719 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.1667050719
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.1697341622
Short name T839
Test name
Test status
Simulation time 7830099900 ps
CPU time 77.75 seconds
Started Jun 07 07:05:58 PM PDT 24
Finished Jun 07 07:07:17 PM PDT 24
Peak memory 262916 kb
Host smart-2be35f6c-858c-404b-a045-7f978377ab4e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697341622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.1697341622
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.2315010567
Short name T722
Test name
Test status
Simulation time 573808600 ps
CPU time 126.85 seconds
Started Jun 07 07:06:00 PM PDT 24
Finished Jun 07 07:08:08 PM PDT 24
Peak memory 294444 kb
Host smart-5b077ec4-b43c-4c7b-9373-99fa79de6c00
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315010567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.2315010567
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.4168800069
Short name T901
Test name
Test status
Simulation time 13218110300 ps
CPU time 293.48 seconds
Started Jun 07 07:05:59 PM PDT 24
Finished Jun 07 07:10:54 PM PDT 24
Peak memory 285124 kb
Host smart-6ebed8b1-7d23-42b1-ae72-19aaa02a7335
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168800069 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.4168800069
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.2388648919
Short name T778
Test name
Test status
Simulation time 325455900 ps
CPU time 145.73 seconds
Started Jun 07 07:05:59 PM PDT 24
Finished Jun 07 07:08:26 PM PDT 24
Peak memory 277020 kb
Host smart-3ad3be95-93bf-41a2-9e5f-a540a7d2326e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388648919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.2388648919
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.2084838534
Short name T564
Test name
Test status
Simulation time 38535800 ps
CPU time 13.32 seconds
Started Jun 07 07:06:05 PM PDT 24
Finished Jun 07 07:06:20 PM PDT 24
Peak memory 258516 kb
Host smart-d5ba57af-402c-454f-9f80-33427c8f8d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084838534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.
2084838534
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.1942481715
Short name T1090
Test name
Test status
Simulation time 27668500 ps
CPU time 16.19 seconds
Started Jun 07 07:06:05 PM PDT 24
Finished Jun 07 07:06:23 PM PDT 24
Peak memory 275088 kb
Host smart-af9c9668-a954-4779-93c7-012ab4b0564f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942481715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.1942481715
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.3753731568
Short name T222
Test name
Test status
Simulation time 55137700 ps
CPU time 21.75 seconds
Started Jun 07 07:06:06 PM PDT 24
Finished Jun 07 07:06:29 PM PDT 24
Peak memory 274052 kb
Host smart-47cc6fb2-acfa-444a-9bf2-673bdf487077
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753731568 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.3753731568
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.1107874591
Short name T480
Test name
Test status
Simulation time 2190629800 ps
CPU time 178.75 seconds
Started Jun 07 07:06:06 PM PDT 24
Finished Jun 07 07:09:05 PM PDT 24
Peak memory 263356 kb
Host smart-38b52821-09ab-4095-b18c-a816589324ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107874591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_
hw_sec_otp.1107874591
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd.1489223760
Short name T1016
Test name
Test status
Simulation time 1123467100 ps
CPU time 125.88 seconds
Started Jun 07 07:06:08 PM PDT 24
Finished Jun 07 07:08:15 PM PDT 24
Peak memory 292700 kb
Host smart-1d5f26e6-76bc-4522-b1a9-b6f102715561
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489223760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla
sh_ctrl_intr_rd.1489223760
Directory /workspace/31.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3851541181
Short name T211
Test name
Test status
Simulation time 12358846600 ps
CPU time 270.02 seconds
Started Jun 07 07:06:05 PM PDT 24
Finished Jun 07 07:10:36 PM PDT 24
Peak memory 293536 kb
Host smart-ec525bd7-fe98-4a8d-8186-a32ff3a1777c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851541181 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.3851541181
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.482516529
Short name T372
Test name
Test status
Simulation time 95890100 ps
CPU time 28.18 seconds
Started Jun 07 07:06:05 PM PDT 24
Finished Jun 07 07:06:34 PM PDT 24
Peak memory 267860 kb
Host smart-41d99d15-8640-4df2-8abb-bf78c3b59838
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482516529 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.482516529
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.992798539
Short name T811
Test name
Test status
Simulation time 2146957000 ps
CPU time 73.92 seconds
Started Jun 07 07:06:04 PM PDT 24
Finished Jun 07 07:07:19 PM PDT 24
Peak memory 259796 kb
Host smart-f323ba39-3051-413b-81ce-283cd6bf0f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992798539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.992798539
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.332363966
Short name T937
Test name
Test status
Simulation time 40995400 ps
CPU time 51.4 seconds
Started Jun 07 07:05:56 PM PDT 24
Finished Jun 07 07:06:49 PM PDT 24
Peak memory 271356 kb
Host smart-ee27813c-73fb-458e-ab5a-4032c15cc6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332363966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.332363966
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.3382498330
Short name T953
Test name
Test status
Simulation time 89362200 ps
CPU time 13.89 seconds
Started Jun 07 07:06:12 PM PDT 24
Finished Jun 07 07:06:26 PM PDT 24
Peak memory 258572 kb
Host smart-266b8737-fada-4d09-8671-8851f9c7cf0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382498330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
3382498330
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.3359941053
Short name T915
Test name
Test status
Simulation time 162362800 ps
CPU time 15.89 seconds
Started Jun 07 07:06:18 PM PDT 24
Finished Jun 07 07:06:35 PM PDT 24
Peak memory 284492 kb
Host smart-ea74d0aa-e4f5-4e0e-a742-92a350981b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359941053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.3359941053
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.183602217
Short name T165
Test name
Test status
Simulation time 9789300 ps
CPU time 22.3 seconds
Started Jun 07 07:06:08 PM PDT 24
Finished Jun 07 07:06:31 PM PDT 24
Peak memory 265872 kb
Host smart-cdeafaa5-7566-4e9e-9b11-8c41a6e43fd1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183602217 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.183602217
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.886968543
Short name T502
Test name
Test status
Simulation time 20530267300 ps
CPU time 194.19 seconds
Started Jun 07 07:06:05 PM PDT 24
Finished Jun 07 07:09:21 PM PDT 24
Peak memory 263440 kb
Host smart-7c70f8e8-1df8-4b85-90d6-e55562fc120b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886968543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_h
w_sec_otp.886968543
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.1458200
Short name T98
Test name
Test status
Simulation time 9058073000 ps
CPU time 214.9 seconds
Started Jun 07 07:06:09 PM PDT 24
Finished Jun 07 07:09:44 PM PDT 24
Peak memory 284896 kb
Host smart-90f0b900-0483-4a20-b934-534e0be78eea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=
flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_
ctrl_intr_rd.1458200
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.2439927193
Short name T627
Test name
Test status
Simulation time 6337761600 ps
CPU time 143.52 seconds
Started Jun 07 07:06:05 PM PDT 24
Finished Jun 07 07:08:29 PM PDT 24
Peak memory 290284 kb
Host smart-ccdc6ff9-1aa9-417e-9efa-dd32b3e6c24e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439927193 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.2439927193
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.893681676
Short name T873
Test name
Test status
Simulation time 153033100 ps
CPU time 131.19 seconds
Started Jun 07 07:06:05 PM PDT 24
Finished Jun 07 07:08:17 PM PDT 24
Peak memory 265228 kb
Host smart-d1375551-1035-4c70-87fd-71f83838feb7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893681676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ot
p_reset.893681676
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict.2481315295
Short name T798
Test name
Test status
Simulation time 44969300 ps
CPU time 30.63 seconds
Started Jun 07 07:06:04 PM PDT 24
Finished Jun 07 07:06:35 PM PDT 24
Peak memory 276788 kb
Host smart-c4c239a4-7531-419b-8249-4babbf2be613
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481315295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fl
ash_ctrl_rw_evict.2481315295
Directory /workspace/32.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.2767416698
Short name T418
Test name
Test status
Simulation time 1510205900 ps
CPU time 71.73 seconds
Started Jun 07 07:06:05 PM PDT 24
Finished Jun 07 07:07:18 PM PDT 24
Peak memory 264388 kb
Host smart-5a8a0a89-3229-4c99-a5f6-3aa4da646b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767416698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.2767416698
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.2200419280
Short name T129
Test name
Test status
Simulation time 65964700 ps
CPU time 51.32 seconds
Started Jun 07 07:06:05 PM PDT 24
Finished Jun 07 07:06:57 PM PDT 24
Peak memory 271560 kb
Host smart-88e2af3a-3b93-40d0-a2d3-3f4aca408108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200419280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.2200419280
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.4114884212
Short name T213
Test name
Test status
Simulation time 618420400 ps
CPU time 13.61 seconds
Started Jun 07 07:06:12 PM PDT 24
Finished Jun 07 07:06:27 PM PDT 24
Peak memory 258624 kb
Host smart-93ba7239-1da9-41c4-a567-2b2878f3f981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114884212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
4114884212
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.2066418560
Short name T752
Test name
Test status
Simulation time 51937600 ps
CPU time 15.58 seconds
Started Jun 07 07:06:12 PM PDT 24
Finished Jun 07 07:06:28 PM PDT 24
Peak memory 284588 kb
Host smart-5774b9dd-24c9-4a75-bdbd-f7a3a5d6c266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066418560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2066418560
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.1721435968
Short name T405
Test name
Test status
Simulation time 12697300 ps
CPU time 22.29 seconds
Started Jun 07 07:06:11 PM PDT 24
Finished Jun 07 07:06:34 PM PDT 24
Peak memory 274020 kb
Host smart-1b13f9bc-be06-41fb-be1f-1f3c3b8563e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721435968 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.1721435968
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.818235265
Short name T655
Test name
Test status
Simulation time 3726347600 ps
CPU time 120.13 seconds
Started Jun 07 07:06:12 PM PDT 24
Finished Jun 07 07:08:13 PM PDT 24
Peak memory 263348 kb
Host smart-31bc3fd7-35d3-4028-b92b-9da563faf62c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818235265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_h
w_sec_otp.818235265
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.682885082
Short name T1100
Test name
Test status
Simulation time 6170012500 ps
CPU time 124.9 seconds
Started Jun 07 07:06:11 PM PDT 24
Finished Jun 07 07:08:16 PM PDT 24
Peak memory 291716 kb
Host smart-6de0232d-0b2e-48e2-8bba-3100d9651ecd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682885082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flas
h_ctrl_intr_rd.682885082
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3703287188
Short name T51
Test name
Test status
Simulation time 28790634400 ps
CPU time 137.34 seconds
Started Jun 07 07:06:12 PM PDT 24
Finished Jun 07 07:08:31 PM PDT 24
Peak memory 293384 kb
Host smart-f9a8f767-d90d-47f5-8ab6-99a2e00f3fdb
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703287188 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.3703287188
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.816557559
Short name T961
Test name
Test status
Simulation time 41351600 ps
CPU time 110.43 seconds
Started Jun 07 07:06:12 PM PDT 24
Finished Jun 07 07:08:03 PM PDT 24
Peak memory 261460 kb
Host smart-15d867d4-f5db-4c84-9a59-87798fa31dd8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816557559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ot
p_reset.816557559
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.3644332946
Short name T225
Test name
Test status
Simulation time 28902800 ps
CPU time 31.69 seconds
Started Jun 07 07:06:12 PM PDT 24
Finished Jun 07 07:06:44 PM PDT 24
Peak memory 275892 kb
Host smart-7971f046-b5eb-4edc-98be-6303e18a540f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644332946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.3644332946
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.2690997488
Short name T384
Test name
Test status
Simulation time 31778600 ps
CPU time 28.08 seconds
Started Jun 07 07:06:12 PM PDT 24
Finished Jun 07 07:06:41 PM PDT 24
Peak memory 276024 kb
Host smart-5812582a-207e-42c8-873d-2e723ec8f48f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690997488 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.2690997488
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.3478109888
Short name T718
Test name
Test status
Simulation time 567893100 ps
CPU time 65.65 seconds
Started Jun 07 07:06:12 PM PDT 24
Finished Jun 07 07:07:19 PM PDT 24
Peak memory 263104 kb
Host smart-b771cd7a-a8f4-4c8d-961b-412353969dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478109888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.3478109888
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.1143756381
Short name T283
Test name
Test status
Simulation time 76603800 ps
CPU time 122.86 seconds
Started Jun 07 07:06:11 PM PDT 24
Finished Jun 07 07:08:15 PM PDT 24
Peak memory 277632 kb
Host smart-39cdcd04-4d95-4bfe-8429-640aad14c3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143756381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.1143756381
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.1508036482
Short name T1083
Test name
Test status
Simulation time 174925500 ps
CPU time 13.65 seconds
Started Jun 07 07:06:20 PM PDT 24
Finished Jun 07 07:06:35 PM PDT 24
Peak memory 265496 kb
Host smart-4eaee148-da97-4fac-a116-c6aa93db6a02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508036482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
1508036482
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.2305425472
Short name T772
Test name
Test status
Simulation time 47768600 ps
CPU time 15.9 seconds
Started Jun 07 07:06:20 PM PDT 24
Finished Jun 07 07:06:37 PM PDT 24
Peak memory 275192 kb
Host smart-3c925d7d-5bc8-44c9-9eb3-5612adcbf345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305425472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.2305425472
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.724795717
Short name T62
Test name
Test status
Simulation time 25692600 ps
CPU time 21.95 seconds
Started Jun 07 07:06:21 PM PDT 24
Finished Jun 07 07:06:44 PM PDT 24
Peak memory 274056 kb
Host smart-3c06e636-504a-4109-b7ce-933f6dbe368b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724795717 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.724795717
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.451996230
Short name T490
Test name
Test status
Simulation time 2901237700 ps
CPU time 116.2 seconds
Started Jun 07 07:06:12 PM PDT 24
Finished Jun 07 07:08:09 PM PDT 24
Peak memory 263300 kb
Host smart-52a0fe3e-9f60-4992-aa86-1ca1b5d9c55e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451996230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_h
w_sec_otp.451996230
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.850859155
Short name T29
Test name
Test status
Simulation time 2969081000 ps
CPU time 147.2 seconds
Started Jun 07 07:06:21 PM PDT 24
Finished Jun 07 07:08:49 PM PDT 24
Peak memory 294200 kb
Host smart-c3f5e7f3-7a55-4039-a79f-ec3832b3bafd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850859155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flas
h_ctrl_intr_rd.850859155
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.269402732
Short name T817
Test name
Test status
Simulation time 24474357600 ps
CPU time 161.51 seconds
Started Jun 07 07:06:20 PM PDT 24
Finished Jun 07 07:09:03 PM PDT 24
Peak memory 291348 kb
Host smart-c749a8e3-ab89-4cf4-ad84-b1dd116de7e5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269402732 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.269402732
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.3921374828
Short name T740
Test name
Test status
Simulation time 51223900 ps
CPU time 109.1 seconds
Started Jun 07 07:06:14 PM PDT 24
Finished Jun 07 07:08:04 PM PDT 24
Peak memory 261272 kb
Host smart-72f24831-b7ac-4074-90ce-b9ab881902f3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921374828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.3921374828
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.612966322
Short name T1023
Test name
Test status
Simulation time 35700200 ps
CPU time 30.65 seconds
Started Jun 07 07:06:21 PM PDT 24
Finished Jun 07 07:06:52 PM PDT 24
Peak memory 276912 kb
Host smart-a3ed2ccf-a117-469e-bebf-122a25105d18
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612966322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla
sh_ctrl_rw_evict.612966322
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.2610858074
Short name T711
Test name
Test status
Simulation time 85321200 ps
CPU time 30.77 seconds
Started Jun 07 07:06:22 PM PDT 24
Finished Jun 07 07:06:54 PM PDT 24
Peak memory 274016 kb
Host smart-9254eac1-9514-4522-b89f-2933d59d0d6b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610858074 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.2610858074
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.3621788152
Short name T994
Test name
Test status
Simulation time 8074461400 ps
CPU time 72.62 seconds
Started Jun 07 07:06:16 PM PDT 24
Finished Jun 07 07:07:29 PM PDT 24
Peak memory 265428 kb
Host smart-ab450f47-b549-4bf0-a641-7720faa93870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621788152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3621788152
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.2392258023
Short name T570
Test name
Test status
Simulation time 69551700 ps
CPU time 99.72 seconds
Started Jun 07 07:06:13 PM PDT 24
Finished Jun 07 07:07:54 PM PDT 24
Peak memory 276096 kb
Host smart-2486749a-71ca-4927-a829-634eb080dd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392258023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.2392258023
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.32130016
Short name T962
Test name
Test status
Simulation time 102305100 ps
CPU time 13.72 seconds
Started Jun 07 07:06:31 PM PDT 24
Finished Jun 07 07:06:46 PM PDT 24
Peak memory 265476 kb
Host smart-fd7f91d3-3b69-4ab6-8d1b-f11d4e2d6d7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32130016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.32130016
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.2299079113
Short name T469
Test name
Test status
Simulation time 82047900 ps
CPU time 15.78 seconds
Started Jun 07 07:06:28 PM PDT 24
Finished Jun 07 07:06:45 PM PDT 24
Peak memory 275188 kb
Host smart-3e87615a-ad56-4af9-8ddb-1ef2075de29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299079113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2299079113
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.2780031146
Short name T18
Test name
Test status
Simulation time 17201000 ps
CPU time 21.59 seconds
Started Jun 07 07:06:27 PM PDT 24
Finished Jun 07 07:06:49 PM PDT 24
Peak memory 274072 kb
Host smart-26d1e17a-5e3b-4555-9859-5ec7d1863b32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780031146 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.2780031146
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.1473414309
Short name T968
Test name
Test status
Simulation time 47722995200 ps
CPU time 113.71 seconds
Started Jun 07 07:06:21 PM PDT 24
Finished Jun 07 07:08:16 PM PDT 24
Peak memory 263280 kb
Host smart-28a03173-ef8c-44a5-a3e6-fb0171da0838
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473414309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.1473414309
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.524724406
Short name T948
Test name
Test status
Simulation time 8614047800 ps
CPU time 211.17 seconds
Started Jun 07 07:06:26 PM PDT 24
Finished Jun 07 07:09:58 PM PDT 24
Peak memory 292532 kb
Host smart-e6fd18a9-8004-45fe-b294-76f2c9574d20
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524724406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flas
h_ctrl_intr_rd.524724406
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.1605354653
Short name T879
Test name
Test status
Simulation time 52284453300 ps
CPU time 336.31 seconds
Started Jun 07 07:06:27 PM PDT 24
Finished Jun 07 07:12:04 PM PDT 24
Peak memory 292272 kb
Host smart-70977c06-95ab-4e8b-932f-178c2e7db429
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605354653 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.1605354653
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.739841421
Short name T820
Test name
Test status
Simulation time 47790500 ps
CPU time 112.08 seconds
Started Jun 07 07:06:21 PM PDT 24
Finished Jun 07 07:08:15 PM PDT 24
Peak memory 264232 kb
Host smart-91788d85-bac0-4847-b9c1-0f70a36cb031
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739841421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ot
p_reset.739841421
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.3879025810
Short name T68
Test name
Test status
Simulation time 74937100 ps
CPU time 28.19 seconds
Started Jun 07 07:06:28 PM PDT 24
Finished Jun 07 07:06:57 PM PDT 24
Peak memory 275776 kb
Host smart-c779ba29-b19a-47cb-8f22-f13aaa858f46
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879025810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.3879025810
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.1601166341
Short name T998
Test name
Test status
Simulation time 44176300 ps
CPU time 32.69 seconds
Started Jun 07 07:06:28 PM PDT 24
Finished Jun 07 07:07:01 PM PDT 24
Peak memory 274012 kb
Host smart-c6258c4d-f257-4b5d-8442-16815d35de9a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601166341 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.1601166341
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.238587158
Short name T36
Test name
Test status
Simulation time 8910470700 ps
CPU time 78.35 seconds
Started Jun 07 07:06:27 PM PDT 24
Finished Jun 07 07:07:46 PM PDT 24
Peak memory 264880 kb
Host smart-37ed0637-fffb-4301-a13a-13ee11663d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238587158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.238587158
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.203742337
Short name T436
Test name
Test status
Simulation time 17989400 ps
CPU time 125.31 seconds
Started Jun 07 07:06:19 PM PDT 24
Finished Jun 07 07:08:25 PM PDT 24
Peak memory 277448 kb
Host smart-d55b12ab-de0e-4543-8dfa-0344afe6b2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203742337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.203742337
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.1915562659
Short name T741
Test name
Test status
Simulation time 72581900 ps
CPU time 13.67 seconds
Started Jun 07 07:06:35 PM PDT 24
Finished Jun 07 07:06:50 PM PDT 24
Peak memory 258548 kb
Host smart-bd8e95b8-8813-40ae-afbd-b73d53c7b5cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915562659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
1915562659
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.2724117097
Short name T172
Test name
Test status
Simulation time 14172800 ps
CPU time 15.96 seconds
Started Jun 07 07:06:28 PM PDT 24
Finished Jun 07 07:06:46 PM PDT 24
Peak memory 275340 kb
Host smart-1a92aed0-7fef-4e41-99c2-b116ba85038f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724117097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.2724117097
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.1092929737
Short name T739
Test name
Test status
Simulation time 15110300 ps
CPU time 22.28 seconds
Started Jun 07 07:06:26 PM PDT 24
Finished Jun 07 07:06:49 PM PDT 24
Peak memory 274028 kb
Host smart-ed7099f2-7cd0-420b-8059-2a6ef6cb2f89
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092929737 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.1092929737
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.2338982827
Short name T877
Test name
Test status
Simulation time 5225266000 ps
CPU time 237.2 seconds
Started Jun 07 07:06:29 PM PDT 24
Finished Jun 07 07:10:27 PM PDT 24
Peak memory 263348 kb
Host smart-34a68996-1d06-4f81-a97d-7db71421e02a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338982827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.2338982827
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd.3626913347
Short name T1077
Test name
Test status
Simulation time 5761149700 ps
CPU time 194.89 seconds
Started Jun 07 07:06:30 PM PDT 24
Finished Jun 07 07:09:45 PM PDT 24
Peak memory 285268 kb
Host smart-84112bfe-4e12-4ea8-adad-6a1b0045a38d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626913347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla
sh_ctrl_intr_rd.3626913347
Directory /workspace/36.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3568542469
Short name T857
Test name
Test status
Simulation time 30293032700 ps
CPU time 295 seconds
Started Jun 07 07:06:28 PM PDT 24
Finished Jun 07 07:11:24 PM PDT 24
Peak memory 285252 kb
Host smart-47f3aa28-3b15-40f8-9935-2137522cdd7e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568542469 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.3568542469
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.3438960437
Short name T871
Test name
Test status
Simulation time 143834300 ps
CPU time 133.13 seconds
Started Jun 07 07:06:27 PM PDT 24
Finished Jun 07 07:08:41 PM PDT 24
Peak memory 260348 kb
Host smart-a23ce1f6-a1de-451d-94cc-d796616110c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438960437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.3438960437
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict.2304643946
Short name T694
Test name
Test status
Simulation time 44915900 ps
CPU time 30.66 seconds
Started Jun 07 07:06:29 PM PDT 24
Finished Jun 07 07:07:01 PM PDT 24
Peak memory 275644 kb
Host smart-2de9404f-d08d-4cc4-8e26-c91885ce4138
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304643946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl
ash_ctrl_rw_evict.2304643946
Directory /workspace/36.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.2634204643
Short name T842
Test name
Test status
Simulation time 60718500 ps
CPU time 31.2 seconds
Started Jun 07 07:06:28 PM PDT 24
Finished Jun 07 07:07:01 PM PDT 24
Peak memory 274012 kb
Host smart-6f018af4-0d6b-47a8-be84-94fed558462d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634204643 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.2634204643
Directory /workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.2575334462
Short name T1040
Test name
Test status
Simulation time 4587824400 ps
CPU time 60.36 seconds
Started Jun 07 07:06:28 PM PDT 24
Finished Jun 07 07:07:29 PM PDT 24
Peak memory 263188 kb
Host smart-e1500766-d50b-4d70-ba8a-c550fd5bb992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575334462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.2575334462
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.3246141513
Short name T425
Test name
Test status
Simulation time 58275100 ps
CPU time 170.81 seconds
Started Jun 07 07:06:27 PM PDT 24
Finished Jun 07 07:09:18 PM PDT 24
Peak memory 279452 kb
Host smart-72aeb6bb-3362-49fc-988e-596b967fe5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246141513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.3246141513
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.1668486457
Short name T624
Test name
Test status
Simulation time 51602900 ps
CPU time 13.51 seconds
Started Jun 07 07:06:37 PM PDT 24
Finished Jun 07 07:06:51 PM PDT 24
Peak memory 258580 kb
Host smart-149e3939-e50f-4785-b947-c02a4cf6c844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668486457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
1668486457
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.1887582709
Short name T504
Test name
Test status
Simulation time 47291000 ps
CPU time 15.83 seconds
Started Jun 07 07:06:38 PM PDT 24
Finished Jun 07 07:06:55 PM PDT 24
Peak memory 283776 kb
Host smart-cbe78b18-585b-4420-872f-183ede20f65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887582709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.1887582709
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.2272116090
Short name T164
Test name
Test status
Simulation time 14408600 ps
CPU time 21.44 seconds
Started Jun 07 07:06:37 PM PDT 24
Finished Jun 07 07:06:59 PM PDT 24
Peak memory 273948 kb
Host smart-d062a61e-fe1a-49ec-9d03-8fa2a28e8842
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272116090 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.2272116090
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.275984307
Short name T47
Test name
Test status
Simulation time 18730820700 ps
CPU time 138.52 seconds
Started Jun 07 07:06:34 PM PDT 24
Finished Jun 07 07:08:54 PM PDT 24
Peak memory 263256 kb
Host smart-25bdc0c7-544a-47fc-906f-5e3100b75ed0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275984307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_h
w_sec_otp.275984307
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.3487321594
Short name T493
Test name
Test status
Simulation time 43455085200 ps
CPU time 166.01 seconds
Started Jun 07 07:06:34 PM PDT 24
Finished Jun 07 07:09:21 PM PDT 24
Peak memory 292848 kb
Host smart-12c69e2d-8327-486f-9c7f-bd0f3ce8f3a2
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487321594 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.3487321594
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.31707864
Short name T924
Test name
Test status
Simulation time 75321300 ps
CPU time 108.83 seconds
Started Jun 07 07:06:35 PM PDT 24
Finished Jun 07 07:08:24 PM PDT 24
Peak memory 260324 kb
Host smart-d6023ab0-8ead-4f46-98e2-6b6ba1a9e4ef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31707864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp
_reset.31707864
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict.2707047167
Short name T815
Test name
Test status
Simulation time 35319700 ps
CPU time 28.19 seconds
Started Jun 07 07:06:35 PM PDT 24
Finished Jun 07 07:07:05 PM PDT 24
Peak memory 270588 kb
Host smart-c160b57a-a564-46a9-a7c2-0b1827580a36
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707047167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fl
ash_ctrl_rw_evict.2707047167
Directory /workspace/37.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.222962952
Short name T905
Test name
Test status
Simulation time 29648100 ps
CPU time 30.66 seconds
Started Jun 07 07:06:35 PM PDT 24
Finished Jun 07 07:07:06 PM PDT 24
Peak memory 275976 kb
Host smart-34bf2cd5-1d1f-4797-90e5-81403aaa24d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222962952 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.222962952
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.3706160086
Short name T516
Test name
Test status
Simulation time 95945600 ps
CPU time 72.7 seconds
Started Jun 07 07:06:38 PM PDT 24
Finished Jun 07 07:07:52 PM PDT 24
Peak memory 275300 kb
Host smart-b64f788a-5fd1-4f4e-b029-506815c042c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706160086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.3706160086
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.1724384749
Short name T608
Test name
Test status
Simulation time 60436900 ps
CPU time 13.68 seconds
Started Jun 07 07:06:44 PM PDT 24
Finished Jun 07 07:06:59 PM PDT 24
Peak memory 265460 kb
Host smart-d3fed26f-dc8c-42aa-a48e-84d86329134f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724384749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
1724384749
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.4227430468
Short name T973
Test name
Test status
Simulation time 47160700 ps
CPU time 15.98 seconds
Started Jun 07 07:06:45 PM PDT 24
Finished Jun 07 07:07:02 PM PDT 24
Peak memory 275004 kb
Host smart-63fc4431-d7d8-4aa5-b725-16391cb8fd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227430468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.4227430468
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.2965976515
Short name T898
Test name
Test status
Simulation time 11175400 ps
CPU time 22.04 seconds
Started Jun 07 07:06:45 PM PDT 24
Finished Jun 07 07:07:09 PM PDT 24
Peak memory 265844 kb
Host smart-4e1b944d-17c0-4b36-a98e-f33720ee933f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965976515 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.2965976515
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.1877615263
Short name T315
Test name
Test status
Simulation time 13791689800 ps
CPU time 245.73 seconds
Started Jun 07 07:06:36 PM PDT 24
Finished Jun 07 07:10:42 PM PDT 24
Peak memory 284952 kb
Host smart-4d715da6-ef50-46bf-90c1-0d1ac7fd3e83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877615263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.1877615263
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.913669728
Short name T667
Test name
Test status
Simulation time 24543732500 ps
CPU time 265.6 seconds
Started Jun 07 07:06:34 PM PDT 24
Finished Jun 07 07:11:00 PM PDT 24
Peak memory 291728 kb
Host smart-ccb3e327-8720-430b-bb69-14a1109f5c94
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913669728 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.913669728
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.1010822180
Short name T947
Test name
Test status
Simulation time 41905000 ps
CPU time 30.31 seconds
Started Jun 07 07:06:36 PM PDT 24
Finished Jun 07 07:07:07 PM PDT 24
Peak memory 276964 kb
Host smart-f461caaf-f44a-4004-8da6-bf731b1d52f7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010822180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.1010822180
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict_all_en.2916360050
Short name T314
Test name
Test status
Simulation time 78353300 ps
CPU time 28.92 seconds
Started Jun 07 07:06:35 PM PDT 24
Finished Jun 07 07:07:04 PM PDT 24
Peak memory 275984 kb
Host smart-2a20a0df-10eb-4ce5-9c0a-4c8fe323df9f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916360050 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict_all_en.2916360050
Directory /workspace/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.4283257712
Short name T1051
Test name
Test status
Simulation time 1730591200 ps
CPU time 69.51 seconds
Started Jun 07 07:06:42 PM PDT 24
Finished Jun 07 07:07:53 PM PDT 24
Peak memory 259872 kb
Host smart-b5e06138-d0b9-4ea1-956a-578c5b4fcfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283257712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.4283257712
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.928852262
Short name T942
Test name
Test status
Simulation time 20248200 ps
CPU time 122.11 seconds
Started Jun 07 07:06:35 PM PDT 24
Finished Jun 07 07:08:38 PM PDT 24
Peak memory 269996 kb
Host smart-05c0cdf4-e095-42a4-ab9d-ac200a766d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928852262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.928852262
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.77574495
Short name T596
Test name
Test status
Simulation time 35134800 ps
CPU time 14.3 seconds
Started Jun 07 07:06:51 PM PDT 24
Finished Jun 07 07:07:06 PM PDT 24
Peak memory 258576 kb
Host smart-920ff899-9069-4a3b-8d97-546b10756e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77574495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.77574495
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.631888599
Short name T940
Test name
Test status
Simulation time 15231200 ps
CPU time 16.54 seconds
Started Jun 07 07:06:51 PM PDT 24
Finished Jun 07 07:07:08 PM PDT 24
Peak memory 275192 kb
Host smart-b2cd658f-e330-4dd5-8d46-e0d3c30ad814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631888599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.631888599
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.3950466035
Short name T72
Test name
Test status
Simulation time 11235100 ps
CPU time 20.6 seconds
Started Jun 07 07:06:42 PM PDT 24
Finished Jun 07 07:07:04 PM PDT 24
Peak memory 273864 kb
Host smart-f1cec6e2-f1ec-40bd-bb9f-df94fcb6b75e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950466035 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.3950466035
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.2812805277
Short name T346
Test name
Test status
Simulation time 3700516900 ps
CPU time 143.76 seconds
Started Jun 07 07:06:42 PM PDT 24
Finished Jun 07 07:09:06 PM PDT 24
Peak memory 263372 kb
Host smart-6803196e-0412-456e-94d1-1dc610f2e6ee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812805277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.2812805277
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.3597852969
Short name T1024
Test name
Test status
Simulation time 27462100500 ps
CPU time 247.23 seconds
Started Jun 07 07:06:42 PM PDT 24
Finished Jun 07 07:10:50 PM PDT 24
Peak memory 291860 kb
Host smart-5f714cfc-0e77-47cb-a412-8081e4d990ac
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597852969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.3597852969
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3611094034
Short name T522
Test name
Test status
Simulation time 18461464300 ps
CPU time 133.02 seconds
Started Jun 07 07:06:45 PM PDT 24
Finished Jun 07 07:08:59 PM PDT 24
Peak memory 292792 kb
Host smart-e2cca36e-e9e5-4f34-b8cd-d89d8a8de8b8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611094034 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.3611094034
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.495912188
Short name T777
Test name
Test status
Simulation time 40123200 ps
CPU time 132.41 seconds
Started Jun 07 07:06:42 PM PDT 24
Finished Jun 07 07:08:55 PM PDT 24
Peak memory 260376 kb
Host smart-8c1d11f6-cb8c-47b4-a5ee-4421839701a7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495912188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_ot
p_reset.495912188
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.3538225636
Short name T426
Test name
Test status
Simulation time 29169500 ps
CPU time 28.49 seconds
Started Jun 07 07:06:45 PM PDT 24
Finished Jun 07 07:07:15 PM PDT 24
Peak memory 276896 kb
Host smart-a9fd77e9-3cee-42f1-9744-889a406abc27
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538225636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.3538225636
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.2132400893
Short name T121
Test name
Test status
Simulation time 98372200 ps
CPU time 31.35 seconds
Started Jun 07 07:06:43 PM PDT 24
Finished Jun 07 07:07:16 PM PDT 24
Peak memory 276120 kb
Host smart-00d281e2-a7c0-4a80-9127-3dd0def6104a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132400893 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.2132400893
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.1687094030
Short name T416
Test name
Test status
Simulation time 3463426200 ps
CPU time 68.31 seconds
Started Jun 07 07:06:44 PM PDT 24
Finished Jun 07 07:07:53 PM PDT 24
Peak memory 265520 kb
Host smart-1f69fe35-ab72-4adb-af87-4bf912a35adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687094030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.1687094030
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.1897212593
Short name T615
Test name
Test status
Simulation time 35183100 ps
CPU time 148.91 seconds
Started Jun 07 07:06:45 PM PDT 24
Finished Jun 07 07:09:15 PM PDT 24
Peak memory 277176 kb
Host smart-7cb5d1bd-06cf-493c-9c20-44ad51785024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897212593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1897212593
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.912598707
Short name T601
Test name
Test status
Simulation time 22397900 ps
CPU time 13.69 seconds
Started Jun 07 07:01:02 PM PDT 24
Finished Jun 07 07:01:16 PM PDT 24
Peak memory 258612 kb
Host smart-22580348-99ee-4932-b259-3913acb9c2fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912598707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.912598707
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.1434351528
Short name T404
Test name
Test status
Simulation time 32549100 ps
CPU time 13.68 seconds
Started Jun 07 07:01:06 PM PDT 24
Finished Jun 07 07:01:20 PM PDT 24
Peak memory 264624 kb
Host smart-5c12e1c3-2af9-461f-a0be-0577c659ae63
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434351528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.1434351528
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.1350133458
Short name T605
Test name
Test status
Simulation time 51649900 ps
CPU time 16.1 seconds
Started Jun 07 07:00:55 PM PDT 24
Finished Jun 07 07:01:12 PM PDT 24
Peak memory 274980 kb
Host smart-99c4884c-2e3c-4d9c-82c5-25c24858bfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350133458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.1350133458
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.1359109167
Short name T344
Test name
Test status
Simulation time 124858300 ps
CPU time 106.95 seconds
Started Jun 07 07:00:46 PM PDT 24
Finished Jun 07 07:02:35 PM PDT 24
Peak memory 275728 kb
Host smart-4bc9ae89-04a5-4717-ad63-574633731f99
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359109167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_derr_detect.1359109167
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.68904902
Short name T938
Test name
Test status
Simulation time 17312700 ps
CPU time 21.94 seconds
Started Jun 07 07:00:55 PM PDT 24
Finished Jun 07 07:01:18 PM PDT 24
Peak memory 273904 kb
Host smart-7557f2ee-cc55-4263-b1da-3a31c90a2c4a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68904902 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.flash_ctrl_disable.68904902
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.3166282605
Short name T85
Test name
Test status
Simulation time 35000118900 ps
CPU time 2214.16 seconds
Started Jun 07 07:00:46 PM PDT 24
Finished Jun 07 07:37:42 PM PDT 24
Peak memory 265596 kb
Host smart-177f5a88-f5b7-40b9-ae96-c1b033e9cec4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166282605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_err
or_mp.3166282605
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.1785640558
Short name T187
Test name
Test status
Simulation time 1653895000 ps
CPU time 2848.16 seconds
Started Jun 07 07:00:40 PM PDT 24
Finished Jun 07 07:48:09 PM PDT 24
Peak memory 264848 kb
Host smart-814870cd-cbbe-48af-9e0e-237eb4a66296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785640558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.1785640558
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.3951236294
Short name T1085
Test name
Test status
Simulation time 2776309800 ps
CPU time 772.37 seconds
Started Jun 07 07:00:49 PM PDT 24
Finished Jun 07 07:13:43 PM PDT 24
Peak memory 273836 kb
Host smart-5d01e532-7a90-40b5-87cc-98f26720aa14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951236294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.3951236294
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.1213575202
Short name T45
Test name
Test status
Simulation time 944494600 ps
CPU time 21.92 seconds
Started Jun 07 07:00:42 PM PDT 24
Finished Jun 07 07:01:05 PM PDT 24
Peak memory 262744 kb
Host smart-0abbb1ac-6c33-45bd-abc8-d55bcb9e8431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213575202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.1213575202
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.168763286
Short name T1087
Test name
Test status
Simulation time 330892200 ps
CPU time 39.12 seconds
Started Jun 07 07:00:55 PM PDT 24
Finished Jun 07 07:01:36 PM PDT 24
Peak memory 265476 kb
Host smart-b31fce9d-a89f-41ef-88c2-ebed86932935
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168763286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_fs_sup.168763286
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.1208902793
Short name T713
Test name
Test status
Simulation time 541219015400 ps
CPU time 2800.73 seconds
Started Jun 07 07:00:41 PM PDT 24
Finished Jun 07 07:47:23 PM PDT 24
Peak memory 265588 kb
Host smart-080e6ea0-68ee-4193-b3fd-1e0e06f8f938
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208902793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.1208902793
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.1111149569
Short name T82
Test name
Test status
Simulation time 388619691100 ps
CPU time 2224.59 seconds
Started Jun 07 07:00:43 PM PDT 24
Finished Jun 07 07:37:48 PM PDT 24
Peak memory 264300 kb
Host smart-063786ff-610a-45f0-84d6-7c42b8f49c45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111149569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.1111149569
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.2269515172
Short name T536
Test name
Test status
Simulation time 60453500 ps
CPU time 47.53 seconds
Started Jun 07 07:00:38 PM PDT 24
Finished Jun 07 07:01:26 PM PDT 24
Peak memory 262696 kb
Host smart-9b9aa4de-604d-4b11-8337-6dd03c3ce0aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2269515172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.2269515172
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2495220676
Short name T719
Test name
Test status
Simulation time 10025091400 ps
CPU time 63.24 seconds
Started Jun 07 07:01:02 PM PDT 24
Finished Jun 07 07:02:06 PM PDT 24
Peak memory 293668 kb
Host smart-f9a877bd-9f12-4865-a691-04de61c6a6f5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495220676 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.2495220676
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.2029465451
Short name T181
Test name
Test status
Simulation time 15532800 ps
CPU time 13.3 seconds
Started Jun 07 07:01:02 PM PDT 24
Finished Jun 07 07:01:16 PM PDT 24
Peak memory 258636 kb
Host smart-899ae9ff-0f9c-48ad-8d7f-770443d456c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029465451 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.2029465451
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.3540753009
Short name T848
Test name
Test status
Simulation time 1731462700 ps
CPU time 69.17 seconds
Started Jun 07 07:00:42 PM PDT 24
Finished Jun 07 07:01:52 PM PDT 24
Peak memory 263420 kb
Host smart-829c806f-031b-4694-a54b-792348d25421
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540753009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.3540753009
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.3526686526
Short name T496
Test name
Test status
Simulation time 776989000 ps
CPU time 148.92 seconds
Started Jun 07 07:00:57 PM PDT 24
Finished Jun 07 07:03:27 PM PDT 24
Peak memory 294220 kb
Host smart-71062d5f-bb98-42e4-a5f5-6de391bdfe42
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526686526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.3526686526
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.85292127
Short name T646
Test name
Test status
Simulation time 33641943800 ps
CPU time 211.27 seconds
Started Jun 07 07:00:56 PM PDT 24
Finished Jun 07 07:04:28 PM PDT 24
Peak memory 293616 kb
Host smart-bb6b534b-4412-453a-a3f8-ad2dc292ef2b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85292127 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.85292127
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3869518376
Short name T200
Test name
Test status
Simulation time 48454700200 ps
CPU time 198.72 seconds
Started Jun 07 07:00:56 PM PDT 24
Finished Jun 07 07:04:16 PM PDT 24
Peak memory 259992 kb
Host smart-3305b08c-8e02-4010-8681-09b586f3417a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386
9518376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.3869518376
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.3878239781
Short name T119
Test name
Test status
Simulation time 4350258400 ps
CPU time 69.8 seconds
Started Jun 07 07:00:48 PM PDT 24
Finished Jun 07 07:01:59 PM PDT 24
Peak memory 260732 kb
Host smart-f91541e3-5973-4d1e-b40e-ccc00d0894a8
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878239781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.3878239781
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.2484529794
Short name T604
Test name
Test status
Simulation time 15900500 ps
CPU time 13.46 seconds
Started Jun 07 07:01:04 PM PDT 24
Finished Jun 07 07:01:18 PM PDT 24
Peak memory 260280 kb
Host smart-28588980-241b-43ce-884c-d862f77e323a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484529794 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.2484529794
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.3543573092
Short name T92
Test name
Test status
Simulation time 25551806900 ps
CPU time 294.82 seconds
Started Jun 07 07:00:40 PM PDT 24
Finished Jun 07 07:05:35 PM PDT 24
Peak memory 274712 kb
Host smart-ec381fa9-e05a-4d2f-9908-9fab85c423dc
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543573092 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_mp_regions.3543573092
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.1209022361
Short name T1000
Test name
Test status
Simulation time 36825000 ps
CPU time 110.15 seconds
Started Jun 07 07:00:39 PM PDT 24
Finished Jun 07 07:02:29 PM PDT 24
Peak memory 260028 kb
Host smart-655c3660-0814-4e5b-9463-9d8226b9a49a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209022361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ot
p_reset.1209022361
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.3863134523
Short name T591
Test name
Test status
Simulation time 5550066900 ps
CPU time 189.91 seconds
Started Jun 07 07:00:47 PM PDT 24
Finished Jun 07 07:03:59 PM PDT 24
Peak memory 282272 kb
Host smart-86aabfd0-7f2e-4145-a003-1203f574695f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863134523 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.3863134523
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.3039269009
Short name T242
Test name
Test status
Simulation time 15906500 ps
CPU time 14.45 seconds
Started Jun 07 07:01:03 PM PDT 24
Finished Jun 07 07:01:18 PM PDT 24
Peak memory 265460 kb
Host smart-f5ab32d7-2551-4c9c-9ca2-efb15aca6108
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3039269009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.3039269009
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.1711555380
Short name T542
Test name
Test status
Simulation time 31930600 ps
CPU time 108.86 seconds
Started Jun 07 07:00:40 PM PDT 24
Finished Jun 07 07:02:29 PM PDT 24
Peak memory 263552 kb
Host smart-961b9f49-743e-44e1-adf6-463cad33ee21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711555380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1711555380
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.742505464
Short name T80
Test name
Test status
Simulation time 736974600 ps
CPU time 15.59 seconds
Started Jun 07 07:01:06 PM PDT 24
Finished Jun 07 07:01:22 PM PDT 24
Peak memory 265456 kb
Host smart-03905b22-af89-4ba3-a23e-236c1f0b3b09
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742505464 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.742505464
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.650087902
Short name T576
Test name
Test status
Simulation time 22152400 ps
CPU time 14.13 seconds
Started Jun 07 07:00:58 PM PDT 24
Finished Jun 07 07:01:12 PM PDT 24
Peak memory 265524 kb
Host smart-5c141bf1-e996-481f-af55-98ff0b9e04bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650087902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_rese
t.650087902
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.431925885
Short name T560
Test name
Test status
Simulation time 903624100 ps
CPU time 930.09 seconds
Started Jun 07 07:00:42 PM PDT 24
Finished Jun 07 07:16:13 PM PDT 24
Peak memory 286108 kb
Host smart-073c9eaa-7b52-4cd0-b265-9c5735d3807c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431925885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.431925885
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2385172297
Short name T318
Test name
Test status
Simulation time 143418500 ps
CPU time 100.07 seconds
Started Jun 07 07:00:41 PM PDT 24
Finished Jun 07 07:02:21 PM PDT 24
Peak memory 262936 kb
Host smart-71d4801f-842b-4cec-a9f5-5b971eefbcc3
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2385172297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2385172297
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.3675415840
Short name T1003
Test name
Test status
Simulation time 380971100 ps
CPU time 34.99 seconds
Started Jun 07 07:00:54 PM PDT 24
Finished Jun 07 07:01:30 PM PDT 24
Peak memory 276036 kb
Host smart-897fe3da-56bc-4405-a0c0-10f9c2225c44
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675415840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.3675415840
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.3543334524
Short name T231
Test name
Test status
Simulation time 81902900 ps
CPU time 21.68 seconds
Started Jun 07 07:00:46 PM PDT 24
Finished Jun 07 07:01:09 PM PDT 24
Peak memory 265272 kb
Host smart-98eb15b3-be52-4a9e-b91f-77608ff24df5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543334524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_read_word_sweep_serr.3543334524
Directory /workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.3626368243
Short name T549
Test name
Test status
Simulation time 504137000 ps
CPU time 125.17 seconds
Started Jun 07 07:00:46 PM PDT 24
Finished Jun 07 07:02:52 PM PDT 24
Peak memory 282196 kb
Host smart-7012bf00-577f-460b-bfb2-273ad8e68b0f
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626368243 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_ro.3626368243
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.4294779807
Short name T67
Test name
Test status
Simulation time 3025791300 ps
CPU time 144.59 seconds
Started Jun 07 07:00:47 PM PDT 24
Finished Jun 07 07:03:13 PM PDT 24
Peak memory 282252 kb
Host smart-c731c342-4c7d-4468-8edf-0d74f1eb7449
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4294779807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.4294779807
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.2591663981
Short name T618
Test name
Test status
Simulation time 591593300 ps
CPU time 145.33 seconds
Started Jun 07 07:00:48 PM PDT 24
Finished Jun 07 07:03:15 PM PDT 24
Peak memory 295672 kb
Host smart-a942c93e-cf51-4017-bfd8-0a9a34ea3453
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591663981 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.2591663981
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.2875998311
Short name T1061
Test name
Test status
Simulation time 3823245300 ps
CPU time 543.18 seconds
Started Jun 07 07:00:47 PM PDT 24
Finished Jun 07 07:09:52 PM PDT 24
Peak memory 310112 kb
Host smart-47b33003-691a-4164-b912-3bcaa256a8d8
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875998311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.flash_ctrl_rw.2875998311
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.724302418
Short name T557
Test name
Test status
Simulation time 115001600 ps
CPU time 28.67 seconds
Started Jun 07 07:00:55 PM PDT 24
Finished Jun 07 07:01:25 PM PDT 24
Peak memory 275828 kb
Host smart-996f1532-81f5-443f-9839-fd508d292b7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724302418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_rw_evict.724302418
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.2087397424
Short name T382
Test name
Test status
Simulation time 168992500 ps
CPU time 29.21 seconds
Started Jun 07 07:00:54 PM PDT 24
Finished Jun 07 07:01:24 PM PDT 24
Peak memory 275896 kb
Host smart-c38c60f9-7dc2-4997-b60b-743a8b044b85
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087397424 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.2087397424
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.936697116
Short name T914
Test name
Test status
Simulation time 9653054800 ps
CPU time 92.02 seconds
Started Jun 07 07:00:53 PM PDT 24
Finished Jun 07 07:02:25 PM PDT 24
Peak memory 265456 kb
Host smart-bc3ae2c3-e651-4d18-8721-f8c40980a3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936697116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.936697116
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.822850798
Short name T1067
Test name
Test status
Simulation time 2392849100 ps
CPU time 76.51 seconds
Started Jun 07 07:00:49 PM PDT 24
Finished Jun 07 07:02:07 PM PDT 24
Peak memory 274128 kb
Host smart-a3a13f25-fe7a-4499-a029-781caf386e49
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822850798 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_counter.822850798
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.2747072170
Short name T423
Test name
Test status
Simulation time 687102500 ps
CPU time 198.64 seconds
Started Jun 07 07:00:31 PM PDT 24
Finished Jun 07 07:03:51 PM PDT 24
Peak memory 281904 kb
Host smart-4b0be306-560d-4da0-93c6-41796d9c75af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747072170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.2747072170
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.557208664
Short name T693
Test name
Test status
Simulation time 48951700 ps
CPU time 25.76 seconds
Started Jun 07 07:00:44 PM PDT 24
Finished Jun 07 07:01:11 PM PDT 24
Peak memory 259928 kb
Host smart-d43d25f6-62f3-41d7-bf4d-42a111c9d43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557208664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.557208664
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.869518630
Short name T781
Test name
Test status
Simulation time 1766836200 ps
CPU time 1249.28 seconds
Started Jun 07 07:00:54 PM PDT 24
Finished Jun 07 07:21:44 PM PDT 24
Peak memory 288944 kb
Host smart-cdb50718-babc-41a0-886c-a6ed5d750e0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869518630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress
_all.869518630
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.3028477946
Short name T1060
Test name
Test status
Simulation time 120353900 ps
CPU time 26.39 seconds
Started Jun 07 07:00:41 PM PDT 24
Finished Jun 07 07:01:09 PM PDT 24
Peak memory 262264 kb
Host smart-87ab579e-b6c4-4ac6-9617-69095e1c4b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028477946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.3028477946
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.8522391
Short name T708
Test name
Test status
Simulation time 10275915500 ps
CPU time 180.4 seconds
Started Jun 07 07:00:47 PM PDT 24
Finished Jun 07 07:03:49 PM PDT 24
Peak memory 259700 kb
Host smart-dc23594a-8906-4f5e-83fa-5f28a697f2a5
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8522391 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_wo.8522391
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.47144613
Short name T539
Test name
Test status
Simulation time 183664300 ps
CPU time 13.73 seconds
Started Jun 07 07:06:49 PM PDT 24
Finished Jun 07 07:07:03 PM PDT 24
Peak memory 265480 kb
Host smart-5f533a7f-3d71-48b6-94fa-1c3c4f88c09c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47144613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.47144613
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.2554407751
Short name T533
Test name
Test status
Simulation time 50790200 ps
CPU time 15.81 seconds
Started Jun 07 07:06:49 PM PDT 24
Finished Jun 07 07:07:06 PM PDT 24
Peak memory 284384 kb
Host smart-0953e067-bbd1-436c-baaf-4b17e897335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554407751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.2554407751
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.1314413761
Short name T952
Test name
Test status
Simulation time 26773900 ps
CPU time 21.02 seconds
Started Jun 07 07:06:50 PM PDT 24
Finished Jun 07 07:07:12 PM PDT 24
Peak memory 274028 kb
Host smart-d5a54ff6-adb0-46cc-bc55-5c355d135fff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314413761 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.1314413761
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.2344038165
Short name T634
Test name
Test status
Simulation time 70420400 ps
CPU time 129.56 seconds
Started Jun 07 07:06:49 PM PDT 24
Finished Jun 07 07:08:59 PM PDT 24
Peak memory 265432 kb
Host smart-269dae3b-e040-4dff-8e9b-deb4321d9932
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344038165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.2344038165
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.3795051616
Short name T566
Test name
Test status
Simulation time 2676762000 ps
CPU time 75.03 seconds
Started Jun 07 07:06:52 PM PDT 24
Finished Jun 07 07:08:07 PM PDT 24
Peak memory 264232 kb
Host smart-2f6874f6-d428-478b-bc8e-4f9c70cb8ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795051616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.3795051616
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.2057293123
Short name T435
Test name
Test status
Simulation time 106037200 ps
CPU time 118.3 seconds
Started Jun 07 07:06:52 PM PDT 24
Finished Jun 07 07:08:50 PM PDT 24
Peak memory 276580 kb
Host smart-e98fbeb0-95de-47eb-b300-3703e97915ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057293123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2057293123
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.770184649
Short name T909
Test name
Test status
Simulation time 23075400 ps
CPU time 13.43 seconds
Started Jun 07 07:06:58 PM PDT 24
Finished Jun 07 07:07:13 PM PDT 24
Peak memory 258592 kb
Host smart-5fc8f4d8-46c5-429f-8b7c-a4f6f401682d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770184649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.770184649
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.2835740271
Short name T498
Test name
Test status
Simulation time 15804500 ps
CPU time 15.78 seconds
Started Jun 07 07:06:59 PM PDT 24
Finished Jun 07 07:07:15 PM PDT 24
Peak memory 275016 kb
Host smart-cf895eb9-426d-4a9c-b0aa-c91bc304fe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835740271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.2835740271
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.4292770145
Short name T1013
Test name
Test status
Simulation time 117938800 ps
CPU time 21.72 seconds
Started Jun 07 07:06:49 PM PDT 24
Finished Jun 07 07:07:11 PM PDT 24
Peak memory 265392 kb
Host smart-9cdfcd69-1430-42e7-8801-da517f1466bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292770145 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.4292770145
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3233073064
Short name T350
Test name
Test status
Simulation time 1824144300 ps
CPU time 155.93 seconds
Started Jun 07 07:06:50 PM PDT 24
Finished Jun 07 07:09:27 PM PDT 24
Peak memory 262988 kb
Host smart-85bb3954-00b1-41cb-a8fc-fc6d52358683
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233073064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.3233073064
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.640660327
Short name T162
Test name
Test status
Simulation time 255299600 ps
CPU time 130.25 seconds
Started Jun 07 07:06:52 PM PDT 24
Finished Jun 07 07:09:02 PM PDT 24
Peak memory 260172 kb
Host smart-2752d6d5-61c6-41b5-9fec-5bfea6d7d020
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640660327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ot
p_reset.640660327
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.4066937384
Short name T880
Test name
Test status
Simulation time 2681526400 ps
CPU time 65.71 seconds
Started Jun 07 07:06:59 PM PDT 24
Finished Jun 07 07:08:06 PM PDT 24
Peak memory 263900 kb
Host smart-72cc062b-da5f-4c9d-b983-978a7ffbf4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066937384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.4066937384
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.1973191437
Short name T625
Test name
Test status
Simulation time 118219000 ps
CPU time 192.92 seconds
Started Jun 07 07:06:52 PM PDT 24
Finished Jun 07 07:10:05 PM PDT 24
Peak memory 281408 kb
Host smart-29c26331-5e6f-4ff0-adbf-fdf334415855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973191437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.1973191437
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.1350426137
Short name T600
Test name
Test status
Simulation time 59165900 ps
CPU time 13.75 seconds
Started Jun 07 07:06:57 PM PDT 24
Finished Jun 07 07:07:11 PM PDT 24
Peak memory 258512 kb
Host smart-7ea6fdaf-2647-4109-9af8-e01190b8673d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350426137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
1350426137
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.84655220
Short name T971
Test name
Test status
Simulation time 200008900 ps
CPU time 16.35 seconds
Started Jun 07 07:06:57 PM PDT 24
Finished Jun 07 07:07:14 PM PDT 24
Peak memory 275156 kb
Host smart-b20264aa-f5b7-4ec7-a7e6-f1942a5da0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84655220 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.84655220
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.2179201792
Short name T408
Test name
Test status
Simulation time 14274300 ps
CPU time 21.94 seconds
Started Jun 07 07:06:57 PM PDT 24
Finished Jun 07 07:07:20 PM PDT 24
Peak memory 265792 kb
Host smart-64505a2a-ec6c-4706-aa2c-292f45097eee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179201792 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.2179201792
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.3988616328
Short name T619
Test name
Test status
Simulation time 32795866700 ps
CPU time 78.64 seconds
Started Jun 07 07:06:59 PM PDT 24
Finished Jun 07 07:08:19 PM PDT 24
Peak memory 262868 kb
Host smart-b958937b-15ea-4ffb-af42-002902d5d083
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988616328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.3988616328
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.1695460843
Short name T657
Test name
Test status
Simulation time 65948400 ps
CPU time 131.74 seconds
Started Jun 07 07:06:59 PM PDT 24
Finished Jun 07 07:09:12 PM PDT 24
Peak memory 262624 kb
Host smart-d12459a0-fbb8-442a-9bb5-278bf7602805
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695460843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.1695460843
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.325644853
Short name T99
Test name
Test status
Simulation time 533003900 ps
CPU time 63.01 seconds
Started Jun 07 07:07:03 PM PDT 24
Finished Jun 07 07:08:07 PM PDT 24
Peak memory 264192 kb
Host smart-9997365f-e711-412c-b091-25202b89d3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325644853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.325644853
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.1468442080
Short name T756
Test name
Test status
Simulation time 100064800 ps
CPU time 142.36 seconds
Started Jun 07 07:06:57 PM PDT 24
Finished Jun 07 07:09:21 PM PDT 24
Peak memory 269004 kb
Host smart-c3910c19-ed47-4305-9f41-82e28a536d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468442080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.1468442080
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.2081686447
Short name T666
Test name
Test status
Simulation time 87031400 ps
CPU time 13.69 seconds
Started Jun 07 07:06:57 PM PDT 24
Finished Jun 07 07:07:11 PM PDT 24
Peak memory 265488 kb
Host smart-4ff6e015-8f1f-4e04-aa8b-17f9c2b9ea91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081686447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
2081686447
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.3511367077
Short name T623
Test name
Test status
Simulation time 17031800 ps
CPU time 15.62 seconds
Started Jun 07 07:06:59 PM PDT 24
Finished Jun 07 07:07:16 PM PDT 24
Peak memory 284600 kb
Host smart-ef6dd555-e01e-42bd-9840-b6ded40aa66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511367077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3511367077
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.1941723636
Short name T409
Test name
Test status
Simulation time 71088200 ps
CPU time 21.97 seconds
Started Jun 07 07:06:58 PM PDT 24
Finished Jun 07 07:07:20 PM PDT 24
Peak memory 265788 kb
Host smart-94094104-2c4b-4d15-bb57-9692c88e7784
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941723636 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.1941723636
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.590058298
Short name T679
Test name
Test status
Simulation time 15673322600 ps
CPU time 115.57 seconds
Started Jun 07 07:07:03 PM PDT 24
Finished Jun 07 07:09:00 PM PDT 24
Peak memory 262772 kb
Host smart-a740dcad-0d61-4309-aa58-451854e921f4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590058298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_h
w_sec_otp.590058298
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.2288030277
Short name T190
Test name
Test status
Simulation time 168403100 ps
CPU time 129.63 seconds
Started Jun 07 07:06:58 PM PDT 24
Finished Jun 07 07:09:08 PM PDT 24
Peak memory 264876 kb
Host smart-c1d0aab7-354c-49a1-a6b1-ecd304280799
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288030277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.2288030277
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.89366218
Short name T731
Test name
Test status
Simulation time 407799500 ps
CPU time 51.98 seconds
Started Jun 07 07:06:58 PM PDT 24
Finished Jun 07 07:07:51 PM PDT 24
Peak memory 265024 kb
Host smart-1b5139f1-efa7-4b7c-86e6-7b298caac87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89366218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.89366218
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.2716997951
Short name T813
Test name
Test status
Simulation time 709535800 ps
CPU time 151.18 seconds
Started Jun 07 07:06:57 PM PDT 24
Finished Jun 07 07:09:29 PM PDT 24
Peak memory 281916 kb
Host smart-654f4f0f-8b1d-4628-9f18-472e29ba86e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716997951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.2716997951
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.3361840698
Short name T854
Test name
Test status
Simulation time 57931800 ps
CPU time 13.84 seconds
Started Jun 07 07:07:12 PM PDT 24
Finished Jun 07 07:07:27 PM PDT 24
Peak memory 258500 kb
Host smart-6c2bc85c-fa8d-4e49-b1de-be605a0cd7cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361840698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.
3361840698
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.2771744582
Short name T838
Test name
Test status
Simulation time 26390800 ps
CPU time 15.94 seconds
Started Jun 07 07:07:05 PM PDT 24
Finished Jun 07 07:07:22 PM PDT 24
Peak memory 284432 kb
Host smart-3b057672-1aba-43fc-80dd-19c9a44e2b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771744582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.2771744582
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.827168250
Short name T1006
Test name
Test status
Simulation time 27289900 ps
CPU time 21.17 seconds
Started Jun 07 07:07:03 PM PDT 24
Finished Jun 07 07:07:26 PM PDT 24
Peak memory 274028 kb
Host smart-5a3cc950-69e5-4ee9-89ee-bbb178b08741
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827168250 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.827168250
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.3278039424
Short name T1095
Test name
Test status
Simulation time 2069666500 ps
CPU time 70.74 seconds
Started Jun 07 07:07:05 PM PDT 24
Finished Jun 07 07:08:17 PM PDT 24
Peak memory 263316 kb
Host smart-e802fae2-d5e9-4bff-b9b9-1bb54c09b270
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278039424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.3278039424
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.1233004825
Short name T744
Test name
Test status
Simulation time 44983600 ps
CPU time 130.72 seconds
Started Jun 07 07:07:04 PM PDT 24
Finished Jun 07 07:09:16 PM PDT 24
Peak memory 260568 kb
Host smart-af1e7ee4-e5f5-4907-80de-07e0cf27ddf3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233004825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_o
tp_reset.1233004825
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.2277672138
Short name T807
Test name
Test status
Simulation time 10666547300 ps
CPU time 93.68 seconds
Started Jun 07 07:07:04 PM PDT 24
Finished Jun 07 07:08:39 PM PDT 24
Peak memory 263704 kb
Host smart-8a511150-ebfc-428d-a030-fda8b908b8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277672138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.2277672138
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.635144196
Short name T1098
Test name
Test status
Simulation time 698197500 ps
CPU time 146.1 seconds
Started Jun 07 07:06:57 PM PDT 24
Finished Jun 07 07:09:24 PM PDT 24
Peak memory 281728 kb
Host smart-a5d35340-3cba-495c-b1c4-1645372eaf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635144196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.635144196
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.926237730
Short name T97
Test name
Test status
Simulation time 47695800 ps
CPU time 13.67 seconds
Started Jun 07 07:07:03 PM PDT 24
Finished Jun 07 07:07:18 PM PDT 24
Peak memory 258532 kb
Host smart-baff662a-6c00-43ae-a800-0c4e53a93e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926237730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.926237730
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.2019654915
Short name T1054
Test name
Test status
Simulation time 46662500 ps
CPU time 15.99 seconds
Started Jun 07 07:07:03 PM PDT 24
Finished Jun 07 07:07:21 PM PDT 24
Peak memory 275140 kb
Host smart-1a8c9d34-83c1-46fb-b219-f06a4445a194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019654915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2019654915
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.4198528885
Short name T805
Test name
Test status
Simulation time 17086800 ps
CPU time 22.1 seconds
Started Jun 07 07:07:05 PM PDT 24
Finished Jun 07 07:07:28 PM PDT 24
Peak memory 265892 kb
Host smart-166f24b4-2db0-48fa-bf39-99fe7e33cb2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198528885 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.4198528885
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.4036075583
Short name T894
Test name
Test status
Simulation time 17071426300 ps
CPU time 144.7 seconds
Started Jun 07 07:07:04 PM PDT 24
Finished Jun 07 07:09:30 PM PDT 24
Peak memory 263272 kb
Host smart-d4dab221-3380-4d0d-823c-c063baedb08b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036075583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_
hw_sec_otp.4036075583
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.4110534487
Short name T669
Test name
Test status
Simulation time 198906900 ps
CPU time 132.27 seconds
Started Jun 07 07:07:05 PM PDT 24
Finished Jun 07 07:09:18 PM PDT 24
Peak memory 260432 kb
Host smart-456c4124-e730-4113-b3a1-2551382ac52c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110534487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.4110534487
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.1955479207
Short name T35
Test name
Test status
Simulation time 6084912100 ps
CPU time 77.82 seconds
Started Jun 07 07:07:06 PM PDT 24
Finished Jun 07 07:08:25 PM PDT 24
Peak memory 263808 kb
Host smart-27037710-d3b0-4070-94c6-8caea85304e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955479207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.1955479207
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.4051198378
Short name T589
Test name
Test status
Simulation time 100015000 ps
CPU time 77.26 seconds
Started Jun 07 07:07:04 PM PDT 24
Finished Jun 07 07:08:22 PM PDT 24
Peak memory 275824 kb
Host smart-9c407461-3ea1-4db0-9fb7-36e03aa29ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051198378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.4051198378
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.1036342690
Short name T963
Test name
Test status
Simulation time 31888700 ps
CPU time 13.66 seconds
Started Jun 07 07:07:11 PM PDT 24
Finished Jun 07 07:07:27 PM PDT 24
Peak memory 265508 kb
Host smart-0b0269b9-4148-43fe-add1-189a3244039d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036342690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
1036342690
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.3928251845
Short name T114
Test name
Test status
Simulation time 47588300 ps
CPU time 13.2 seconds
Started Jun 07 07:07:12 PM PDT 24
Finished Jun 07 07:07:27 PM PDT 24
Peak memory 275068 kb
Host smart-5a11ac44-b992-4e44-a25f-a4353e59401c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928251845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.3928251845
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.874837347
Short name T73
Test name
Test status
Simulation time 20089900 ps
CPU time 21.86 seconds
Started Jun 07 07:07:14 PM PDT 24
Finished Jun 07 07:07:37 PM PDT 24
Peak memory 273904 kb
Host smart-e5fbafe1-29a2-4a01-8faf-9cee945a5dc4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874837347 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.874837347
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.709876304
Short name T1039
Test name
Test status
Simulation time 9281495400 ps
CPU time 75.72 seconds
Started Jun 07 07:07:13 PM PDT 24
Finished Jun 07 07:08:30 PM PDT 24
Peak memory 263376 kb
Host smart-a937ca07-5bd6-4e0c-bc56-f17ce57bcdcc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709876304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_h
w_sec_otp.709876304
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.795513072
Short name T765
Test name
Test status
Simulation time 45505500 ps
CPU time 134.8 seconds
Started Jun 07 07:07:12 PM PDT 24
Finished Jun 07 07:09:28 PM PDT 24
Peak memory 260344 kb
Host smart-bc49f296-8223-45e1-835c-5879b1284d27
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795513072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_ot
p_reset.795513072
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.2082404751
Short name T448
Test name
Test status
Simulation time 6461343800 ps
CPU time 69.24 seconds
Started Jun 07 07:07:12 PM PDT 24
Finished Jun 07 07:08:23 PM PDT 24
Peak memory 265116 kb
Host smart-f4f89b03-80a2-411a-92f5-3df1f08a141f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082404751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.2082404751
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.4230759319
Short name T424
Test name
Test status
Simulation time 23612500 ps
CPU time 53.63 seconds
Started Jun 07 07:07:13 PM PDT 24
Finished Jun 07 07:08:08 PM PDT 24
Peak memory 271428 kb
Host smart-37a35baf-4776-4650-9195-826c1678610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230759319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.4230759319
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.3657005648
Short name T629
Test name
Test status
Simulation time 135799100 ps
CPU time 14.81 seconds
Started Jun 07 07:07:11 PM PDT 24
Finished Jun 07 07:07:27 PM PDT 24
Peak memory 265624 kb
Host smart-224f1f27-5531-4a8f-bcd1-d5cf22caa820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657005648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
3657005648
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.53672119
Short name T1076
Test name
Test status
Simulation time 15014800 ps
CPU time 13.34 seconds
Started Jun 07 07:07:11 PM PDT 24
Finished Jun 07 07:07:26 PM PDT 24
Peak memory 275180 kb
Host smart-32908fd9-fbbe-44e4-8e06-77a8aaad8f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53672119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.53672119
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.1084977499
Short name T75
Test name
Test status
Simulation time 30761200 ps
CPU time 21.55 seconds
Started Jun 07 07:07:13 PM PDT 24
Finished Jun 07 07:07:36 PM PDT 24
Peak memory 274060 kb
Host smart-f83e149f-7b79-41b1-ba99-d628d8905271
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084977499 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.1084977499
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.2886321958
Short name T214
Test name
Test status
Simulation time 2300607900 ps
CPU time 64.34 seconds
Started Jun 07 07:07:14 PM PDT 24
Finished Jun 07 07:08:20 PM PDT 24
Peak memory 262812 kb
Host smart-0531a0f1-1d9e-4265-bade-efc49d29328e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886321958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.2886321958
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.799881458
Short name T965
Test name
Test status
Simulation time 197868300 ps
CPU time 131.7 seconds
Started Jun 07 07:07:11 PM PDT 24
Finished Jun 07 07:09:24 PM PDT 24
Peak memory 260176 kb
Host smart-efa8a3b2-3046-4853-b0d7-84aefb9f8a2d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799881458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ot
p_reset.799881458
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.600382884
Short name T1079
Test name
Test status
Simulation time 1907773400 ps
CPU time 72.74 seconds
Started Jun 07 07:07:11 PM PDT 24
Finished Jun 07 07:08:25 PM PDT 24
Peak memory 263844 kb
Host smart-7f2dc63f-5807-478f-bc76-83fab29563be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600382884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.600382884
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.2853516661
Short name T266
Test name
Test status
Simulation time 1396762800 ps
CPU time 190.23 seconds
Started Jun 07 07:07:12 PM PDT 24
Finished Jun 07 07:10:24 PM PDT 24
Peak memory 281912 kb
Host smart-e88580be-a3bd-4877-861e-ea017275c2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853516661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.2853516661
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.1370315359
Short name T489
Test name
Test status
Simulation time 67204600 ps
CPU time 13.77 seconds
Started Jun 07 07:07:13 PM PDT 24
Finished Jun 07 07:07:28 PM PDT 24
Peak memory 258676 kb
Host smart-59e3779b-3a67-4ead-9942-bd46d82b0c0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370315359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
1370315359
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.646237225
Short name T479
Test name
Test status
Simulation time 20230000 ps
CPU time 13.53 seconds
Started Jun 07 07:07:12 PM PDT 24
Finished Jun 07 07:07:27 PM PDT 24
Peak memory 284544 kb
Host smart-18d6e228-42f9-4845-884e-889dce0debf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646237225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.646237225
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.4040717834
Short name T410
Test name
Test status
Simulation time 12721200 ps
CPU time 20.71 seconds
Started Jun 07 07:07:11 PM PDT 24
Finished Jun 07 07:07:33 PM PDT 24
Peak memory 265736 kb
Host smart-6508166c-70d1-4192-9c8e-271b6e9771a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040717834 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.4040717834
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.2385705020
Short name T733
Test name
Test status
Simulation time 11606594100 ps
CPU time 241.63 seconds
Started Jun 07 07:07:11 PM PDT 24
Finished Jun 07 07:11:14 PM PDT 24
Peak memory 263296 kb
Host smart-1f424ecc-4d82-46b2-8e7e-54f7457c4525
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385705020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.2385705020
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.1008463359
Short name T926
Test name
Test status
Simulation time 37947900 ps
CPU time 132.14 seconds
Started Jun 07 07:07:13 PM PDT 24
Finished Jun 07 07:09:26 PM PDT 24
Peak memory 260280 kb
Host smart-d3f7f44d-9beb-487d-92f5-d4d2647fca40
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008463359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o
tp_reset.1008463359
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.221574656
Short name T1070
Test name
Test status
Simulation time 34342900 ps
CPU time 75.06 seconds
Started Jun 07 07:07:12 PM PDT 24
Finished Jun 07 07:08:28 PM PDT 24
Peak memory 276640 kb
Host smart-fedaaa3a-4307-4a5e-ba4f-01d21fd90fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221574656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.221574656
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.3919936170
Short name T595
Test name
Test status
Simulation time 59158600 ps
CPU time 13.98 seconds
Started Jun 07 07:07:19 PM PDT 24
Finished Jun 07 07:07:34 PM PDT 24
Peak memory 265592 kb
Host smart-7faeebd3-17bc-486a-8bd1-500884d6e3aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919936170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.
3919936170
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.2747990993
Short name T734
Test name
Test status
Simulation time 15512900 ps
CPU time 13.12 seconds
Started Jun 07 07:07:20 PM PDT 24
Finished Jun 07 07:07:34 PM PDT 24
Peak memory 275072 kb
Host smart-7307afbc-b1dd-4c54-99e1-76413fd10040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747990993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.2747990993
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.3413225044
Short name T967
Test name
Test status
Simulation time 113186700 ps
CPU time 20.65 seconds
Started Jun 07 07:07:19 PM PDT 24
Finished Jun 07 07:07:41 PM PDT 24
Peak memory 273968 kb
Host smart-d5913191-5c43-436f-b6cc-8541dbfaebdb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413225044 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.3413225044
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.1389450899
Short name T887
Test name
Test status
Simulation time 6510197600 ps
CPU time 66 seconds
Started Jun 07 07:07:19 PM PDT 24
Finished Jun 07 07:08:27 PM PDT 24
Peak memory 263404 kb
Host smart-811d6977-cb6f-475d-aaec-e63f1a1ae7aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389450899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.1389450899
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.2986750943
Short name T441
Test name
Test status
Simulation time 336301400 ps
CPU time 134.65 seconds
Started Jun 07 07:07:20 PM PDT 24
Finished Jun 07 07:09:36 PM PDT 24
Peak memory 260172 kb
Host smart-0d41646e-9b4e-4173-85c1-c6dcf7ce78ee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986750943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.2986750943
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.3233656949
Short name T802
Test name
Test status
Simulation time 1977958400 ps
CPU time 65.71 seconds
Started Jun 07 07:07:19 PM PDT 24
Finished Jun 07 07:08:26 PM PDT 24
Peak memory 263940 kb
Host smart-c3c883a9-1dc7-4f6d-92be-5c2302ca22c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233656949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.3233656949
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.2935343315
Short name T727
Test name
Test status
Simulation time 29317700 ps
CPU time 97.84 seconds
Started Jun 07 07:07:11 PM PDT 24
Finished Jun 07 07:08:50 PM PDT 24
Peak memory 276136 kb
Host smart-042aa706-38c1-41f0-a6f6-2622a0d153d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935343315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.2935343315
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.396937283
Short name T1019
Test name
Test status
Simulation time 40341500 ps
CPU time 13.63 seconds
Started Jun 07 07:01:17 PM PDT 24
Finished Jun 07 07:01:32 PM PDT 24
Peak memory 258560 kb
Host smart-7fe4659c-79b2-4fa6-ab0a-44783e460a51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396937283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.396937283
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.3847685329
Short name T220
Test name
Test status
Simulation time 43189900 ps
CPU time 15.59 seconds
Started Jun 07 07:01:18 PM PDT 24
Finished Jun 07 07:01:35 PM PDT 24
Peak memory 274924 kb
Host smart-dcbce4df-1750-4c70-9d59-de3714ec66f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847685329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.3847685329
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.2677238102
Short name T977
Test name
Test status
Simulation time 19645300 ps
CPU time 21.7 seconds
Started Jun 07 07:01:17 PM PDT 24
Finished Jun 07 07:01:40 PM PDT 24
Peak memory 265932 kb
Host smart-ebc54d99-5fed-4217-b0db-c7a4b25cfa7d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677238102 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.2677238102
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.3348082450
Short name T523
Test name
Test status
Simulation time 6482733800 ps
CPU time 2439.22 seconds
Started Jun 07 07:01:09 PM PDT 24
Finished Jun 07 07:41:50 PM PDT 24
Peak memory 262904 kb
Host smart-8bd0b5aa-85c1-49c0-9944-d0d586a01832
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348082450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.3348082450
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.1382804233
Short name T983
Test name
Test status
Simulation time 856387500 ps
CPU time 901.94 seconds
Started Jun 07 07:01:07 PM PDT 24
Finished Jun 07 07:16:10 PM PDT 24
Peak memory 270684 kb
Host smart-d984916a-3af8-42f1-b118-0d2e79eb7c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382804233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.1382804233
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.760459455
Short name T54
Test name
Test status
Simulation time 1823020800 ps
CPU time 24.01 seconds
Started Jun 07 07:01:04 PM PDT 24
Finished Jun 07 07:01:29 PM PDT 24
Peak memory 262760 kb
Host smart-a90e0355-0617-431a-8e8c-831164449376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760459455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.760459455
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2952446793
Short name T167
Test name
Test status
Simulation time 10011950100 ps
CPU time 126.59 seconds
Started Jun 07 07:01:19 PM PDT 24
Finished Jun 07 07:03:26 PM PDT 24
Peak memory 321444 kb
Host smart-0c66a1ce-28a2-439d-87a7-beaa16807eb8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952446793 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.2952446793
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.2533607771
Short name T185
Test name
Test status
Simulation time 15592700 ps
CPU time 13.49 seconds
Started Jun 07 07:01:19 PM PDT 24
Finished Jun 07 07:01:33 PM PDT 24
Peak memory 265104 kb
Host smart-7ce7e059-8564-4039-a787-819eb55e5dec
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533607771 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.2533607771
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.697977975
Short name T959
Test name
Test status
Simulation time 6895426400 ps
CPU time 129.59 seconds
Started Jun 07 07:01:06 PM PDT 24
Finished Jun 07 07:03:16 PM PDT 24
Peak memory 262868 kb
Host smart-185259f4-3b2c-4363-a79b-ab19fdeff04b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697977975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw
_sec_otp.697977975
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.3032163854
Short name T361
Test name
Test status
Simulation time 2056361000 ps
CPU time 133.71 seconds
Started Jun 07 07:01:12 PM PDT 24
Finished Jun 07 07:03:26 PM PDT 24
Peak memory 291720 kb
Host smart-f17220db-6797-4b68-b939-7145be69fe88
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032163854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.3032163854
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.408647401
Short name T212
Test name
Test status
Simulation time 54119981700 ps
CPU time 256.12 seconds
Started Jun 07 07:01:11 PM PDT 24
Finished Jun 07 07:05:28 PM PDT 24
Peak memory 293064 kb
Host smart-c4f24ea1-e827-460b-98f7-c560214a03db
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408647401 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.408647401
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.3075523992
Short name T690
Test name
Test status
Simulation time 2412674400 ps
CPU time 73.02 seconds
Started Jun 07 07:01:11 PM PDT 24
Finished Jun 07 07:02:25 PM PDT 24
Peak memory 265716 kb
Host smart-dbc0aefc-2617-4b10-8d39-a767832ac01d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075523992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.3075523992
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.2195299183
Short name T660
Test name
Test status
Simulation time 23132716800 ps
CPU time 187.24 seconds
Started Jun 07 07:01:10 PM PDT 24
Finished Jun 07 07:04:18 PM PDT 24
Peak memory 260096 kb
Host smart-967d4c69-85ef-49de-ac40-9bd39ff96eb5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219
5299183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.2195299183
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.3648833849
Short name T526
Test name
Test status
Simulation time 6755812400 ps
CPU time 64.54 seconds
Started Jun 07 07:01:09 PM PDT 24
Finished Jun 07 07:02:14 PM PDT 24
Peak memory 263380 kb
Host smart-2d0f14f4-6fba-411b-886b-529f1fec0815
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648833849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.3648833849
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.3088475590
Short name T461
Test name
Test status
Simulation time 11351062900 ps
CPU time 209.98 seconds
Started Jun 07 07:01:03 PM PDT 24
Finished Jun 07 07:04:34 PM PDT 24
Peak memory 273892 kb
Host smart-90d68d53-e3eb-4e5c-bf9c-538d3c29abef
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088475590 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.3088475590
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.2887200027
Short name T893
Test name
Test status
Simulation time 157649400 ps
CPU time 109.16 seconds
Started Jun 07 07:01:06 PM PDT 24
Finished Jun 07 07:02:55 PM PDT 24
Peak memory 261252 kb
Host smart-4bb6c828-d6bb-4a66-b492-95e8bb40cb10
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887200027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.2887200027
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.1787671394
Short name T198
Test name
Test status
Simulation time 5513812400 ps
CPU time 671.28 seconds
Started Jun 07 07:01:03 PM PDT 24
Finished Jun 07 07:12:15 PM PDT 24
Peak memory 263504 kb
Host smart-95a90749-afd3-41ae-81d1-450df64eedf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1787671394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.1787671394
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.856846968
Short name T515
Test name
Test status
Simulation time 21004900 ps
CPU time 13.84 seconds
Started Jun 07 07:01:10 PM PDT 24
Finished Jun 07 07:01:24 PM PDT 24
Peak memory 259008 kb
Host smart-cafde9b7-706c-4055-b065-77305d8c0960
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856846968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_rese
t.856846968
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.778025715
Short name T995
Test name
Test status
Simulation time 133032800 ps
CPU time 199.36 seconds
Started Jun 07 07:01:02 PM PDT 24
Finished Jun 07 07:04:22 PM PDT 24
Peak memory 273240 kb
Host smart-4098adbb-1bc8-4a81-9347-1fb4bca77647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778025715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.778025715
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.1576108305
Short name T1062
Test name
Test status
Simulation time 160157900 ps
CPU time 35.16 seconds
Started Jun 07 07:01:17 PM PDT 24
Finished Jun 07 07:01:53 PM PDT 24
Peak memory 275704 kb
Host smart-53927d5b-48b7-4f98-b042-af215585bfa0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576108305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.1576108305
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.70008520
Short name T1056
Test name
Test status
Simulation time 1222833900 ps
CPU time 113.17 seconds
Started Jun 07 07:01:10 PM PDT 24
Finished Jun 07 07:03:03 PM PDT 24
Peak memory 291896 kb
Host smart-99da21e4-855c-48b1-b0b3-c456e08f1922
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70008520 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.flash_ctrl_ro.70008520
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.2038258354
Short name T1032
Test name
Test status
Simulation time 2324965300 ps
CPU time 133.06 seconds
Started Jun 07 07:01:11 PM PDT 24
Finished Jun 07 07:03:25 PM PDT 24
Peak memory 282268 kb
Host smart-a306aafe-7cd9-4d32-86f3-6e78c987f30e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2038258354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.2038258354
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.3614034303
Short name T742
Test name
Test status
Simulation time 1049745600 ps
CPU time 136.17 seconds
Started Jun 07 07:01:09 PM PDT 24
Finished Jun 07 07:03:26 PM PDT 24
Peak memory 282248 kb
Host smart-d2648cb9-951c-45e8-90f0-44aabcf3e30c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614034303 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.3614034303
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.2862018262
Short name T1031
Test name
Test status
Simulation time 3428185500 ps
CPU time 456.92 seconds
Started Jun 07 07:01:12 PM PDT 24
Finished Jun 07 07:08:49 PM PDT 24
Peak memory 314796 kb
Host smart-aa3dbe36-401d-42e4-baa2-f6fc0ad07a07
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862018262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.flash_ctrl_rw.2862018262
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.1623443877
Short name T235
Test name
Test status
Simulation time 7782929600 ps
CPU time 715.23 seconds
Started Jun 07 07:01:11 PM PDT 24
Finished Jun 07 07:13:07 PM PDT 24
Peak memory 338188 kb
Host smart-c3955991-e6a4-4f4e-a675-c0ac6055224b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623443877 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_rw_derr.1623443877
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict.245359768
Short name T836
Test name
Test status
Simulation time 31104000 ps
CPU time 30.95 seconds
Started Jun 07 07:01:18 PM PDT 24
Finished Jun 07 07:01:50 PM PDT 24
Peak memory 276872 kb
Host smart-bbb83b09-23b1-408f-8868-94ddd233500b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245359768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_rw_evict.245359768
Directory /workspace/5.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.4050267035
Short name T1063
Test name
Test status
Simulation time 50403100 ps
CPU time 31.06 seconds
Started Jun 07 07:01:17 PM PDT 24
Finished Jun 07 07:01:49 PM PDT 24
Peak memory 268936 kb
Host smart-84694a76-5323-465d-96a9-88162b9d2785
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050267035 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.4050267035
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.2795610041
Short name T422
Test name
Test status
Simulation time 8331248400 ps
CPU time 704.06 seconds
Started Jun 07 07:01:12 PM PDT 24
Finished Jun 07 07:12:57 PM PDT 24
Peak memory 313096 kb
Host smart-fedbe381-4587-40aa-8eca-7119348a1a49
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795610041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.2795610041
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.4172919956
Short name T450
Test name
Test status
Simulation time 840894100 ps
CPU time 63.19 seconds
Started Jun 07 07:01:17 PM PDT 24
Finished Jun 07 07:02:21 PM PDT 24
Peak memory 264268 kb
Host smart-95f952f1-ee4d-4266-89f8-6d4ef0e528ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172919956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.4172919956
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.462038380
Short name T494
Test name
Test status
Simulation time 43044700 ps
CPU time 74.27 seconds
Started Jun 07 07:01:01 PM PDT 24
Finished Jun 07 07:02:16 PM PDT 24
Peak memory 276640 kb
Host smart-774cf584-018d-4d78-9daa-a255729f2f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462038380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.462038380
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.436655881
Short name T269
Test name
Test status
Simulation time 2431127200 ps
CPU time 168.25 seconds
Started Jun 07 07:01:09 PM PDT 24
Finished Jun 07 07:03:58 PM PDT 24
Peak memory 260292 kb
Host smart-bf98452c-6661-475e-9554-4609bf462a5b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436655881 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.flash_ctrl_wo.436655881
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.3109651073
Short name T471
Test name
Test status
Simulation time 23164800 ps
CPU time 13.66 seconds
Started Jun 07 07:07:18 PM PDT 24
Finished Jun 07 07:07:33 PM PDT 24
Peak memory 275176 kb
Host smart-076faa12-0f69-40ca-93ff-a9140a386f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109651073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.3109651073
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.3187837561
Short name T785
Test name
Test status
Simulation time 224276500 ps
CPU time 134.63 seconds
Started Jun 07 07:07:18 PM PDT 24
Finished Jun 07 07:09:34 PM PDT 24
Peak memory 260340 kb
Host smart-fa760c2e-219b-4e9b-9740-3079a78fdbd8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187837561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.3187837561
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.4220685596
Short name T1068
Test name
Test status
Simulation time 17258100 ps
CPU time 13.32 seconds
Started Jun 07 07:07:19 PM PDT 24
Finished Jun 07 07:07:34 PM PDT 24
Peak memory 284396 kb
Host smart-b53559ec-290b-4734-8934-d2aa1bd14fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220685596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.4220685596
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.4252701556
Short name T159
Test name
Test status
Simulation time 155650000 ps
CPU time 133.22 seconds
Started Jun 07 07:07:19 PM PDT 24
Finished Jun 07 07:09:33 PM PDT 24
Peak memory 260260 kb
Host smart-fc92bd66-1e88-439e-98c6-ab57e936b666
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252701556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.4252701556
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.2722018896
Short name T843
Test name
Test status
Simulation time 23508800 ps
CPU time 16.15 seconds
Started Jun 07 07:07:21 PM PDT 24
Finished Jun 07 07:07:38 PM PDT 24
Peak memory 275212 kb
Host smart-63338be9-64af-474f-b2b2-f973617babba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722018896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.2722018896
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.3091111199
Short name T113
Test name
Test status
Simulation time 82010500 ps
CPU time 109.17 seconds
Started Jun 07 07:07:22 PM PDT 24
Finished Jun 07 07:09:12 PM PDT 24
Peak memory 260532 kb
Host smart-f3bf8314-e178-4c33-a1ed-61ba85311fe4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091111199 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.3091111199
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.728086378
Short name T558
Test name
Test status
Simulation time 16308000 ps
CPU time 13.63 seconds
Started Jun 07 07:07:20 PM PDT 24
Finished Jun 07 07:07:35 PM PDT 24
Peak memory 274992 kb
Host smart-b8184af2-e6d0-4c0d-aa79-e8ad390110d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728086378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.728086378
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.542497915
Short name T890
Test name
Test status
Simulation time 341335700 ps
CPU time 132.36 seconds
Started Jun 07 07:07:19 PM PDT 24
Finished Jun 07 07:09:33 PM PDT 24
Peak memory 260472 kb
Host smart-c3c32ad1-c866-477a-a9ec-ddbfe6930456
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542497915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_ot
p_reset.542497915
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.3701944535
Short name T849
Test name
Test status
Simulation time 120840100 ps
CPU time 15.71 seconds
Started Jun 07 07:07:22 PM PDT 24
Finished Jun 07 07:07:39 PM PDT 24
Peak memory 274924 kb
Host smart-e3a15eb5-5403-4939-a768-0a72ba854aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701944535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.3701944535
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.1746646950
Short name T774
Test name
Test status
Simulation time 139487800 ps
CPU time 133.46 seconds
Started Jun 07 07:07:20 PM PDT 24
Finished Jun 07 07:09:35 PM PDT 24
Peak memory 264404 kb
Host smart-d6323d5e-e206-403d-a152-8306cc7faab3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746646950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.1746646950
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.408943309
Short name T881
Test name
Test status
Simulation time 14783200 ps
CPU time 15.69 seconds
Started Jun 07 07:07:26 PM PDT 24
Finished Jun 07 07:07:44 PM PDT 24
Peak memory 275036 kb
Host smart-860784f1-8254-4d98-b4e4-f3644206f936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408943309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.408943309
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.999918404
Short name T911
Test name
Test status
Simulation time 148511400 ps
CPU time 130.32 seconds
Started Jun 07 07:07:26 PM PDT 24
Finished Jun 07 07:09:38 PM PDT 24
Peak memory 264940 kb
Host smart-103dad2e-674f-4056-86e7-83829554b9f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999918404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_ot
p_reset.999918404
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.1312537007
Short name T933
Test name
Test status
Simulation time 17328300 ps
CPU time 15.99 seconds
Started Jun 07 07:07:26 PM PDT 24
Finished Jun 07 07:07:44 PM PDT 24
Peak memory 275020 kb
Host smart-e6b46d2f-f860-41b1-ae7a-5b8d50b4ce49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312537007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.1312537007
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.997165973
Short name T602
Test name
Test status
Simulation time 138511200 ps
CPU time 132.39 seconds
Started Jun 07 07:07:26 PM PDT 24
Finished Jun 07 07:09:40 PM PDT 24
Peak memory 260676 kb
Host smart-270334c0-9f78-4a96-8b0f-5ed6d84fda57
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997165973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_ot
p_reset.997165973
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.3051637665
Short name T486
Test name
Test status
Simulation time 14238300 ps
CPU time 15.41 seconds
Started Jun 07 07:07:26 PM PDT 24
Finished Jun 07 07:07:43 PM PDT 24
Peak memory 275268 kb
Host smart-3736c952-7a21-4524-928d-7543b4b6f7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051637665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.3051637665
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.1992739089
Short name T1069
Test name
Test status
Simulation time 79154800 ps
CPU time 135.44 seconds
Started Jun 07 07:07:27 PM PDT 24
Finished Jun 07 07:09:45 PM PDT 24
Peak memory 260404 kb
Host smart-c85c55a3-f053-4120-bfe2-269d49a94289
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992739089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.1992739089
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.110994371
Short name T721
Test name
Test status
Simulation time 23166800 ps
CPU time 15.84 seconds
Started Jun 07 07:07:26 PM PDT 24
Finished Jun 07 07:07:44 PM PDT 24
Peak memory 284624 kb
Host smart-c91645b8-b954-4c3d-9f27-44b08fddab5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110994371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.110994371
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.3257035614
Short name T150
Test name
Test status
Simulation time 47975400 ps
CPU time 132.67 seconds
Started Jun 07 07:07:26 PM PDT 24
Finished Jun 07 07:09:41 PM PDT 24
Peak memory 260416 kb
Host smart-591ef4f6-c474-4533-9ac5-ce65738185e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257035614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.3257035614
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.4004302063
Short name T491
Test name
Test status
Simulation time 48479800 ps
CPU time 16.21 seconds
Started Jun 07 07:07:27 PM PDT 24
Finished Jun 07 07:07:45 PM PDT 24
Peak memory 275188 kb
Host smart-b993a91f-d706-405a-92e8-18dbbfffc4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004302063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.4004302063
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.3530499598
Short name T353
Test name
Test status
Simulation time 533563100 ps
CPU time 134.21 seconds
Started Jun 07 07:07:25 PM PDT 24
Finished Jun 07 07:09:41 PM PDT 24
Peak memory 261284 kb
Host smart-1895afa4-ed60-4d52-854f-60ed7ffe753f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530499598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.3530499598
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.2177109542
Short name T1082
Test name
Test status
Simulation time 116391400 ps
CPU time 13.76 seconds
Started Jun 07 07:01:40 PM PDT 24
Finished Jun 07 07:01:55 PM PDT 24
Peak memory 258524 kb
Host smart-045b9a77-c670-45fa-b25a-021fe77d0097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177109542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.2
177109542
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.1751425480
Short name T202
Test name
Test status
Simulation time 23326400 ps
CPU time 15.75 seconds
Started Jun 07 07:01:43 PM PDT 24
Finished Jun 07 07:02:00 PM PDT 24
Peak memory 274900 kb
Host smart-dc134280-0a53-42cb-a39f-27ba756dea05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751425480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.1751425480
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.3326702046
Short name T61
Test name
Test status
Simulation time 38476000 ps
CPU time 20.76 seconds
Started Jun 07 07:01:44 PM PDT 24
Finished Jun 07 07:02:06 PM PDT 24
Peak memory 273920 kb
Host smart-edb56fa0-affb-4354-a1c2-00b2a6c60acf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326702046 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.3326702046
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.4277778182
Short name T532
Test name
Test status
Simulation time 18020081700 ps
CPU time 2335.63 seconds
Started Jun 07 07:01:24 PM PDT 24
Finished Jun 07 07:40:20 PM PDT 24
Peak memory 263088 kb
Host smart-e1b0e2ac-746d-4881-a9d8-74c5cedd5352
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277778182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.4277778182
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.556944289
Short name T684
Test name
Test status
Simulation time 3215803800 ps
CPU time 889.83 seconds
Started Jun 07 07:01:23 PM PDT 24
Finished Jun 07 07:16:13 PM PDT 24
Peak memory 273572 kb
Host smart-655e226e-cbe3-4e7b-975e-db217344289c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556944289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.556944289
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.2368844862
Short name T941
Test name
Test status
Simulation time 753076400 ps
CPU time 26.97 seconds
Started Jun 07 07:01:25 PM PDT 24
Finished Jun 07 07:01:53 PM PDT 24
Peak memory 262496 kb
Host smart-86189a38-e75a-450d-a8e7-6c4cd48370c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368844862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.2368844862
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2943351031
Short name T152
Test name
Test status
Simulation time 10018913900 ps
CPU time 85.18 seconds
Started Jun 07 07:01:44 PM PDT 24
Finished Jun 07 07:03:11 PM PDT 24
Peak memory 292304 kb
Host smart-2c09cf0a-0dee-45b2-8130-b6dd30343268
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943351031 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.2943351031
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.1873430429
Short name T321
Test name
Test status
Simulation time 23314900 ps
CPU time 13.38 seconds
Started Jun 07 07:01:38 PM PDT 24
Finished Jun 07 07:01:52 PM PDT 24
Peak memory 258852 kb
Host smart-4a92bfcf-dcf3-4560-90df-6005826d6799
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873430429 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.1873430429
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.3497575853
Short name T637
Test name
Test status
Simulation time 160188533700 ps
CPU time 1042.1 seconds
Started Jun 07 07:01:26 PM PDT 24
Finished Jun 07 07:18:49 PM PDT 24
Peak memory 263976 kb
Host smart-7be2aa70-1ef4-4234-9c32-d684f0164a2b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497575853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_hw_rma_reset.3497575853
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.3503248616
Short name T835
Test name
Test status
Simulation time 11619991100 ps
CPU time 196.04 seconds
Started Jun 07 07:01:24 PM PDT 24
Finished Jun 07 07:04:41 PM PDT 24
Peak memory 263004 kb
Host smart-a1758494-25df-4a18-9b57-8cd090244c0e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503248616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.3503248616
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.264715917
Short name T362
Test name
Test status
Simulation time 2916509000 ps
CPU time 153.43 seconds
Started Jun 07 07:01:31 PM PDT 24
Finished Jun 07 07:04:05 PM PDT 24
Peak memory 294420 kb
Host smart-979ad091-114d-45ec-abc5-737a20ab1c34
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264715917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_intr_rd.264715917
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.2593980600
Short name T357
Test name
Test status
Simulation time 6290997500 ps
CPU time 129.9 seconds
Started Jun 07 07:01:32 PM PDT 24
Finished Jun 07 07:03:43 PM PDT 24
Peak memory 294524 kb
Host smart-810461be-8f79-4975-a4af-a28e3eb7f8e3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593980600 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.2593980600
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.4063499662
Short name T1027
Test name
Test status
Simulation time 4209992900 ps
CPU time 62.29 seconds
Started Jun 07 07:01:32 PM PDT 24
Finished Jun 07 07:02:36 PM PDT 24
Peak memory 260244 kb
Host smart-6ace17f0-78bc-4ffb-bd73-97085eef9083
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063499662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.4063499662
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.1741705092
Short name T729
Test name
Test status
Simulation time 26372408600 ps
CPU time 184.71 seconds
Started Jun 07 07:01:31 PM PDT 24
Finished Jun 07 07:04:36 PM PDT 24
Peak memory 260232 kb
Host smart-d4cf4d6a-9bb2-4cb7-8abb-d7fbb522797e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174
1705092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.1741705092
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.3743082391
Short name T814
Test name
Test status
Simulation time 8755003000 ps
CPU time 65.84 seconds
Started Jun 07 07:01:26 PM PDT 24
Finished Jun 07 07:02:32 PM PDT 24
Peak memory 260776 kb
Host smart-0ea5a99a-ce87-4287-acb1-f972f129a73b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743082391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.3743082391
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.407297008
Short name T141
Test name
Test status
Simulation time 26484700 ps
CPU time 13.98 seconds
Started Jun 07 07:01:41 PM PDT 24
Finished Jun 07 07:01:56 PM PDT 24
Peak memory 260104 kb
Host smart-feb87d53-816a-4fd9-8b66-c0d316ad9da1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407297008 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.407297008
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.2316051486
Short name T614
Test name
Test status
Simulation time 64814200 ps
CPU time 112.91 seconds
Started Jun 07 07:01:24 PM PDT 24
Finished Jun 07 07:03:17 PM PDT 24
Peak memory 265412 kb
Host smart-aa2d6eb1-e529-48b4-a919-a63179e408fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316051486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot
p_reset.2316051486
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.3926933076
Short name T993
Test name
Test status
Simulation time 33018900 ps
CPU time 151.02 seconds
Started Jun 07 07:01:20 PM PDT 24
Finished Jun 07 07:03:51 PM PDT 24
Peak memory 263528 kb
Host smart-d039c66b-90be-47fa-a9b9-6cba7b8ef1ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926933076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.3926933076
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.203540279
Short name T537
Test name
Test status
Simulation time 20138900 ps
CPU time 13.49 seconds
Started Jun 07 07:01:32 PM PDT 24
Finished Jun 07 07:01:46 PM PDT 24
Peak memory 265464 kb
Host smart-8a36d79e-3313-49dc-a375-a6e3582d77b3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203540279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_rese
t.203540279
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.2260577550
Short name T759
Test name
Test status
Simulation time 4284233700 ps
CPU time 777.93 seconds
Started Jun 07 07:01:18 PM PDT 24
Finished Jun 07 07:14:17 PM PDT 24
Peak memory 285088 kb
Host smart-8e320d0e-9ba2-4f9f-8ee5-3607096644e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260577550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.2260577550
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.1031480068
Short name T895
Test name
Test status
Simulation time 131688700 ps
CPU time 39.02 seconds
Started Jun 07 07:01:32 PM PDT 24
Finished Jun 07 07:02:12 PM PDT 24
Peak memory 276044 kb
Host smart-3e94eff3-2de0-4939-a72c-a9d02bbd9efe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031480068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_re_evict.1031480068
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.3099613755
Short name T612
Test name
Test status
Simulation time 2107944400 ps
CPU time 119.31 seconds
Started Jun 07 07:01:24 PM PDT 24
Finished Jun 07 07:03:24 PM PDT 24
Peak memory 282088 kb
Host smart-d99f67f1-36c2-4fcd-a70a-3018bc2f7cd2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099613755 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_ro.3099613755
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.406741444
Short name T980
Test name
Test status
Simulation time 1599617400 ps
CPU time 153.48 seconds
Started Jun 07 07:01:33 PM PDT 24
Finished Jun 07 07:04:07 PM PDT 24
Peak memory 282292 kb
Host smart-5fc37bab-5800-4b1a-bc94-45fccac4eb5f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
406741444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.406741444
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.1320986910
Short name T429
Test name
Test status
Simulation time 2284574300 ps
CPU time 127.05 seconds
Started Jun 07 07:01:32 PM PDT 24
Finished Jun 07 07:03:40 PM PDT 24
Peak memory 295408 kb
Host smart-b3d674a9-e708-4448-b4cb-fed9f6b77918
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320986910 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.1320986910
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.3319922138
Short name T434
Test name
Test status
Simulation time 12133830300 ps
CPU time 517.3 seconds
Started Jun 07 07:01:24 PM PDT 24
Finished Jun 07 07:10:02 PM PDT 24
Peak memory 314580 kb
Host smart-cea3f81d-9ac9-4eea-8283-1070aecefe71
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319922138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.flash_ctrl_rw.3319922138
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.913967082
Short name T100
Test name
Test status
Simulation time 3866733000 ps
CPU time 743.52 seconds
Started Jun 07 07:01:32 PM PDT 24
Finished Jun 07 07:13:56 PM PDT 24
Peak memory 335448 kb
Host smart-79b5b294-f827-4c1a-8567-5d37a163eefd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913967082 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.flash_ctrl_rw_derr.913967082
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict.3489686984
Short name T373
Test name
Test status
Simulation time 34010600 ps
CPU time 31.25 seconds
Started Jun 07 07:01:33 PM PDT 24
Finished Jun 07 07:02:05 PM PDT 24
Peak memory 275800 kb
Host smart-0ce2412b-b4ff-497d-b03e-ceeee9e34551
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489686984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_rw_evict.3489686984
Directory /workspace/6.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.2040712664
Short name T538
Test name
Test status
Simulation time 71580400 ps
CPU time 28.17 seconds
Started Jun 07 07:01:32 PM PDT 24
Finished Jun 07 07:02:01 PM PDT 24
Peak memory 276128 kb
Host smart-128a7dce-4eda-4791-a8a4-b0c8cb12d8b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040712664 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.2040712664
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.2336066981
Short name T193
Test name
Test status
Simulation time 29332461000 ps
CPU time 580.9 seconds
Started Jun 07 07:01:31 PM PDT 24
Finished Jun 07 07:11:13 PM PDT 24
Peak memory 313908 kb
Host smart-9178876d-d51a-4ea6-a51c-a41c229a4e84
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336066981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.2336066981
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.3087815202
Short name T704
Test name
Test status
Simulation time 4910620000 ps
CPU time 86.23 seconds
Started Jun 07 07:01:39 PM PDT 24
Finished Jun 07 07:03:07 PM PDT 24
Peak memory 263768 kb
Host smart-029013ff-041d-4d26-9a62-2779f7628eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087815202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.3087815202
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.2161959503
Short name T856
Test name
Test status
Simulation time 70207200 ps
CPU time 52.15 seconds
Started Jun 07 07:01:18 PM PDT 24
Finished Jun 07 07:02:11 PM PDT 24
Peak memory 271456 kb
Host smart-c0c4046d-e033-4520-aefd-503adde848cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161959503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.2161959503
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.4201476818
Short name T773
Test name
Test status
Simulation time 9401299900 ps
CPU time 204.54 seconds
Started Jun 07 07:01:24 PM PDT 24
Finished Jun 07 07:04:49 PM PDT 24
Peak memory 260340 kb
Host smart-e0b68f23-1aca-45ef-b676-baca882eac3b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201476818 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.flash_ctrl_wo.4201476818
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.3014065255
Short name T648
Test name
Test status
Simulation time 46870500 ps
CPU time 16.02 seconds
Started Jun 07 07:07:25 PM PDT 24
Finished Jun 07 07:07:43 PM PDT 24
Peak memory 275152 kb
Host smart-027e857e-f254-4a00-be45-4f313378b245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014065255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.3014065255
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.1014894224
Short name T990
Test name
Test status
Simulation time 39840200 ps
CPU time 132.3 seconds
Started Jun 07 07:07:27 PM PDT 24
Finished Jun 07 07:09:41 PM PDT 24
Peak memory 260384 kb
Host smart-a1ae223a-20a2-4e71-8b9d-70f8dba2bbfc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014894224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o
tp_reset.1014894224
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.3847756565
Short name T770
Test name
Test status
Simulation time 23619300 ps
CPU time 16.47 seconds
Started Jun 07 07:07:33 PM PDT 24
Finished Jun 07 07:07:53 PM PDT 24
Peak memory 284572 kb
Host smart-383810bf-6870-45d3-b7bc-7d7cda81c64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847756565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.3847756565
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.2626127089
Short name T636
Test name
Test status
Simulation time 356951200 ps
CPU time 132.51 seconds
Started Jun 07 07:07:32 PM PDT 24
Finished Jun 07 07:09:48 PM PDT 24
Peak memory 260216 kb
Host smart-cbd1f58a-5951-48dd-98f3-e187f1e61801
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626127089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.2626127089
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.3056686221
Short name T883
Test name
Test status
Simulation time 28658600 ps
CPU time 15.58 seconds
Started Jun 07 07:07:33 PM PDT 24
Finished Jun 07 07:07:51 PM PDT 24
Peak memory 284464 kb
Host smart-e7e2839a-4d0f-44fd-b9c1-4a20c381a0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056686221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3056686221
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.3809354014
Short name T470
Test name
Test status
Simulation time 91700200 ps
CPU time 135.64 seconds
Started Jun 07 07:07:36 PM PDT 24
Finished Jun 07 07:09:55 PM PDT 24
Peak memory 260428 kb
Host smart-933c72e7-d956-4cad-9738-b346166783b4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809354014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.3809354014
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.1510676575
Short name T561
Test name
Test status
Simulation time 21541000 ps
CPU time 13.24 seconds
Started Jun 07 07:07:33 PM PDT 24
Finished Jun 07 07:07:49 PM PDT 24
Peak memory 275084 kb
Host smart-2b862176-2971-4f92-a533-91d150f2dc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510676575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.1510676575
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.1933121087
Short name T897
Test name
Test status
Simulation time 133078300 ps
CPU time 131.31 seconds
Started Jun 07 07:07:34 PM PDT 24
Finished Jun 07 07:09:49 PM PDT 24
Peak memory 265172 kb
Host smart-2f53df98-4384-4f3c-9954-8dfde5152ae1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933121087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.1933121087
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.1407839673
Short name T1065
Test name
Test status
Simulation time 53732000 ps
CPU time 15.9 seconds
Started Jun 07 07:07:33 PM PDT 24
Finished Jun 07 07:07:51 PM PDT 24
Peak memory 275132 kb
Host smart-97bf569f-c32f-4514-83a8-3b52467b9a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407839673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.1407839673
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.2496382204
Short name T142
Test name
Test status
Simulation time 48385200 ps
CPU time 110.57 seconds
Started Jun 07 07:07:35 PM PDT 24
Finished Jun 07 07:09:28 PM PDT 24
Peak memory 260484 kb
Host smart-a37aaed1-0e6c-43ce-81c6-f5e8aa61b10f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496382204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.2496382204
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.2150237103
Short name T833
Test name
Test status
Simulation time 15301800 ps
CPU time 15.48 seconds
Started Jun 07 07:07:32 PM PDT 24
Finished Jun 07 07:07:50 PM PDT 24
Peak memory 275108 kb
Host smart-d1cf0f72-bc6d-4f2e-a5c0-6bc478e1fa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150237103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2150237103
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.776712064
Short name T322
Test name
Test status
Simulation time 48291000 ps
CPU time 133.52 seconds
Started Jun 07 07:07:34 PM PDT 24
Finished Jun 07 07:09:50 PM PDT 24
Peak memory 260056 kb
Host smart-3784f2d1-fdf8-4ff9-90a4-37bb022ac5a3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776712064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_ot
p_reset.776712064
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.717993364
Short name T827
Test name
Test status
Simulation time 89501300 ps
CPU time 13.26 seconds
Started Jun 07 07:07:35 PM PDT 24
Finished Jun 07 07:07:51 PM PDT 24
Peak memory 274988 kb
Host smart-5336cd5e-dcba-4b43-8034-5db294f06d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717993364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.717993364
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.4569431
Short name T675
Test name
Test status
Simulation time 36838800 ps
CPU time 109.33 seconds
Started Jun 07 07:07:34 PM PDT 24
Finished Jun 07 07:09:26 PM PDT 24
Peak memory 261228 kb
Host smart-ef8d8a8a-0698-455e-9a41-6bf5ab1e2041
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4569431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp_
reset.4569431
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.2997065859
Short name T593
Test name
Test status
Simulation time 13579400 ps
CPU time 15.51 seconds
Started Jun 07 07:07:40 PM PDT 24
Finished Jun 07 07:07:57 PM PDT 24
Peak memory 284664 kb
Host smart-19b345ad-2795-4ec8-b633-9ef246112dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997065859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.2997065859
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.143596793
Short name T485
Test name
Test status
Simulation time 25027200 ps
CPU time 15.68 seconds
Started Jun 07 07:07:41 PM PDT 24
Finished Jun 07 07:07:57 PM PDT 24
Peak memory 284380 kb
Host smart-df04ed3b-9bd1-45bd-a477-3f867bb263d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143596793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.143596793
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.2014647059
Short name T265
Test name
Test status
Simulation time 38548200 ps
CPU time 132.49 seconds
Started Jun 07 07:07:40 PM PDT 24
Finished Jun 07 07:09:54 PM PDT 24
Peak memory 260252 kb
Host smart-0be29055-898d-4c8c-9584-d1a9474dda30
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014647059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.2014647059
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.2013793876
Short name T847
Test name
Test status
Simulation time 14747800 ps
CPU time 15.99 seconds
Started Jun 07 07:07:42 PM PDT 24
Finished Jun 07 07:07:59 PM PDT 24
Peak memory 275068 kb
Host smart-2963131d-540d-490e-a523-ef8a8bef1b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013793876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.2013793876
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.2375785035
Short name T143
Test name
Test status
Simulation time 195289300 ps
CPU time 132.36 seconds
Started Jun 07 07:07:40 PM PDT 24
Finished Jun 07 07:09:54 PM PDT 24
Peak memory 260580 kb
Host smart-c50321a2-1576-4352-83e9-1b5744c02830
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375785035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.2375785035
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.1452989721
Short name T534
Test name
Test status
Simulation time 61710100 ps
CPU time 13.53 seconds
Started Jun 07 07:01:55 PM PDT 24
Finished Jun 07 07:02:10 PM PDT 24
Peak memory 258708 kb
Host smart-b86f5554-81fb-43bf-9156-8bc749a88909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452989721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1
452989721
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.881072861
Short name T1047
Test name
Test status
Simulation time 52384300 ps
CPU time 13.57 seconds
Started Jun 07 07:02:02 PM PDT 24
Finished Jun 07 07:02:17 PM PDT 24
Peak memory 275052 kb
Host smart-590c675e-db95-4d4b-b0b6-7ba15bd3ec16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881072861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.881072861
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.2125697481
Short name T840
Test name
Test status
Simulation time 16911000 ps
CPU time 22.11 seconds
Started Jun 07 07:01:54 PM PDT 24
Finished Jun 07 07:02:17 PM PDT 24
Peak memory 265296 kb
Host smart-6204fe21-40a0-4bfe-8318-82e641fbf257
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125697481 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.2125697481
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.2362283740
Short name T676
Test name
Test status
Simulation time 19549027200 ps
CPU time 2209.32 seconds
Started Jun 07 07:01:40 PM PDT 24
Finished Jun 07 07:38:31 PM PDT 24
Peak memory 264592 kb
Host smart-50d5fe4f-1aeb-4b0b-9400-41e5f2c0bdfe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362283740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.2362283740
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.853131176
Short name T189
Test name
Test status
Simulation time 712987500 ps
CPU time 837.23 seconds
Started Jun 07 07:01:42 PM PDT 24
Finished Jun 07 07:15:40 PM PDT 24
Peak memory 270764 kb
Host smart-b82ee246-d374-4370-b5b3-5504bdfb7df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853131176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.853131176
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.4147567530
Short name T750
Test name
Test status
Simulation time 469290000 ps
CPU time 27.2 seconds
Started Jun 07 07:01:40 PM PDT 24
Finished Jun 07 07:02:08 PM PDT 24
Peak memory 262792 kb
Host smart-20780ed0-78bb-41c0-ab04-a91accd17cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147567530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.4147567530
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2469009204
Short name T1048
Test name
Test status
Simulation time 10012221700 ps
CPU time 130.15 seconds
Started Jun 07 07:01:54 PM PDT 24
Finished Jun 07 07:04:05 PM PDT 24
Peak memory 362444 kb
Host smart-c5d1c3b8-99b5-4a13-bfc6-a0679fb243c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469009204 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.2469009204
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.1054017546
Short name T823
Test name
Test status
Simulation time 15204900 ps
CPU time 13.57 seconds
Started Jun 07 07:02:01 PM PDT 24
Finished Jun 07 07:02:16 PM PDT 24
Peak memory 258800 kb
Host smart-d49b4502-0114-47bb-9869-bf0c503945f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054017546 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.1054017546
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.142029911
Short name T949
Test name
Test status
Simulation time 160173920400 ps
CPU time 848.6 seconds
Started Jun 07 07:01:38 PM PDT 24
Finished Jun 07 07:15:48 PM PDT 24
Peak memory 264584 kb
Host smart-ee804b65-9898-479a-948c-6e00b1166deb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142029911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 7.flash_ctrl_hw_rma_reset.142029911
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.32019955
Short name T687
Test name
Test status
Simulation time 1677632600 ps
CPU time 139.59 seconds
Started Jun 07 07:01:43 PM PDT 24
Finished Jun 07 07:04:04 PM PDT 24
Peak memory 263256 kb
Host smart-ef4287a4-0a1a-4892-9631-ff87b748794d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32019955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_
sec_otp.32019955
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.2907501282
Short name T908
Test name
Test status
Simulation time 1753680400 ps
CPU time 205.12 seconds
Started Jun 07 07:01:55 PM PDT 24
Finished Jun 07 07:05:21 PM PDT 24
Peak memory 285156 kb
Host smart-505fe878-a096-4cf1-bb10-b952b15a1d26
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907501282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.2907501282
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.354531115
Short name T528
Test name
Test status
Simulation time 50720703100 ps
CPU time 141.43 seconds
Started Jun 07 07:02:00 PM PDT 24
Finished Jun 07 07:04:22 PM PDT 24
Peak memory 293416 kb
Host smart-f5ad7d0d-259c-449a-b75f-695ad08e88a5
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354531115 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.354531115
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.3288542786
Short name T767
Test name
Test status
Simulation time 3767521600 ps
CPU time 67.39 seconds
Started Jun 07 07:01:53 PM PDT 24
Finished Jun 07 07:03:01 PM PDT 24
Peak memory 265500 kb
Host smart-492b0cbc-ec2d-4d6f-8631-bb1a8e8f86af
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288542786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.3288542786
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3636120110
Short name T597
Test name
Test status
Simulation time 33608942000 ps
CPU time 209.89 seconds
Started Jun 07 07:02:00 PM PDT 24
Finished Jun 07 07:05:30 PM PDT 24
Peak memory 265480 kb
Host smart-43b9219c-d2c3-4b04-9cd2-c0e3873856fd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363
6120110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.3636120110
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.1419430855
Short name T53
Test name
Test status
Simulation time 11275720000 ps
CPU time 73.8 seconds
Started Jun 07 07:01:46 PM PDT 24
Finished Jun 07 07:03:01 PM PDT 24
Peak memory 261056 kb
Host smart-814659a1-a281-44ef-9842-7c22a111dedd
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419430855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.1419430855
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.2936540241
Short name T1022
Test name
Test status
Simulation time 16069000 ps
CPU time 13.44 seconds
Started Jun 07 07:01:54 PM PDT 24
Finished Jun 07 07:02:08 PM PDT 24
Peak memory 260212 kb
Host smart-ad0cd8d0-19d3-476f-956e-8e0ac8437100
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936540241 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.2936540241
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.4224892539
Short name T921
Test name
Test status
Simulation time 20408179900 ps
CPU time 163.87 seconds
Started Jun 07 07:01:40 PM PDT 24
Finished Jun 07 07:04:25 PM PDT 24
Peak memory 265468 kb
Host smart-843533fb-c214-4f32-a735-fddb35a27e62
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224892539 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_mp_regions.4224892539
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.719994814
Short name T154
Test name
Test status
Simulation time 40400700 ps
CPU time 110.16 seconds
Started Jun 07 07:01:40 PM PDT 24
Finished Jun 07 07:03:31 PM PDT 24
Peak memory 260560 kb
Host smart-4b03def0-929b-428c-8575-f3ea48b491fc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719994814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp
_reset.719994814
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.726839274
Short name T197
Test name
Test status
Simulation time 26419800 ps
CPU time 68.29 seconds
Started Jun 07 07:01:39 PM PDT 24
Finished Jun 07 07:02:48 PM PDT 24
Peak memory 263516 kb
Host smart-83140f9f-c2e2-4429-911b-b29c23549fc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726839274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.726839274
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.400341905
Short name T780
Test name
Test status
Simulation time 55417000 ps
CPU time 13.49 seconds
Started Jun 07 07:01:59 PM PDT 24
Finished Jun 07 07:02:13 PM PDT 24
Peak memory 259000 kb
Host smart-86bc6f50-f4ab-47a5-bfd9-b35883deb382
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400341905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_rese
t.400341905
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.497903784
Short name T794
Test name
Test status
Simulation time 83557100 ps
CPU time 281.05 seconds
Started Jun 07 07:01:40 PM PDT 24
Finished Jun 07 07:06:23 PM PDT 24
Peak memory 275460 kb
Host smart-cfebb3fa-a96d-475b-93b9-0a843afd41d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497903784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.497903784
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.507554980
Short name T808
Test name
Test status
Simulation time 118482400 ps
CPU time 36.9 seconds
Started Jun 07 07:01:55 PM PDT 24
Finished Jun 07 07:02:33 PM PDT 24
Peak memory 276040 kb
Host smart-d2a9ced3-cc01-4171-afd8-ec6edca80e68
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507554980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_re_evict.507554980
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.3688032682
Short name T701
Test name
Test status
Simulation time 578221700 ps
CPU time 135.71 seconds
Started Jun 07 07:01:48 PM PDT 24
Finished Jun 07 07:04:04 PM PDT 24
Peak memory 291752 kb
Host smart-1347be09-dc80-4c6f-b61e-671e8fe97418
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688032682 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.3688032682
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.669179744
Short name T867
Test name
Test status
Simulation time 511833500 ps
CPU time 131.48 seconds
Started Jun 07 07:01:47 PM PDT 24
Finished Jun 07 07:04:00 PM PDT 24
Peak memory 282248 kb
Host smart-6c66db5b-b1da-42fb-bc38-db1aa7c8e5e4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
669179744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.669179744
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.2683741090
Short name T234
Test name
Test status
Simulation time 2631292300 ps
CPU time 122.52 seconds
Started Jun 07 07:01:48 PM PDT 24
Finished Jun 07 07:03:51 PM PDT 24
Peak memory 282208 kb
Host smart-5441c002-de63-4534-80a5-1de77b6f44c8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683741090 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.2683741090
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.1708055530
Short name T317
Test name
Test status
Simulation time 18214244500 ps
CPU time 586.7 seconds
Started Jun 07 07:01:48 PM PDT 24
Finished Jun 07 07:11:36 PM PDT 24
Peak memory 314840 kb
Host smart-9dc99554-2b79-41cd-9d71-52704f14abeb
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708055530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.flash_ctrl_rw.1708055530
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.3761761321
Short name T622
Test name
Test status
Simulation time 36091900 ps
CPU time 29.56 seconds
Started Jun 07 07:01:54 PM PDT 24
Finished Jun 07 07:02:24 PM PDT 24
Peak memory 275816 kb
Host smart-8217106a-a97b-46f1-8dc5-eb0925e57a90
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761761321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.3761761321
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.1169695136
Short name T376
Test name
Test status
Simulation time 30458300 ps
CPU time 28.65 seconds
Started Jun 07 07:01:59 PM PDT 24
Finished Jun 07 07:02:28 PM PDT 24
Peak memory 276008 kb
Host smart-81ae03c4-d9f5-4bfd-9fde-f710ca4f5654
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169695136 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.1169695136
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.3706620439
Short name T548
Test name
Test status
Simulation time 3517496000 ps
CPU time 58.95 seconds
Started Jun 07 07:01:53 PM PDT 24
Finished Jun 07 07:02:52 PM PDT 24
Peak memory 263812 kb
Host smart-1fa755a2-39df-4295-9070-734c408b1944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706620439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.3706620439
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.18409527
Short name T578
Test name
Test status
Simulation time 18866100 ps
CPU time 99.25 seconds
Started Jun 07 07:01:43 PM PDT 24
Finished Jun 07 07:03:23 PM PDT 24
Peak memory 277008 kb
Host smart-a4b1784f-fca9-4c96-bc06-018e8a7dba45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18409527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.18409527
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.1253734603
Short name T755
Test name
Test status
Simulation time 21148400 ps
CPU time 13.34 seconds
Started Jun 07 07:07:40 PM PDT 24
Finished Jun 07 07:07:54 PM PDT 24
Peak memory 274928 kb
Host smart-f5d1ec67-3d55-42c4-98b3-b4af02fbfb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253734603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.1253734603
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.1939336832
Short name T737
Test name
Test status
Simulation time 76111600 ps
CPU time 133.72 seconds
Started Jun 07 07:07:40 PM PDT 24
Finished Jun 07 07:09:55 PM PDT 24
Peak memory 261144 kb
Host smart-4091f168-7bf8-4dc0-8e6b-8303090a6a4f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939336832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.1939336832
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.367429849
Short name T474
Test name
Test status
Simulation time 73186000 ps
CPU time 15.8 seconds
Started Jun 07 07:07:41 PM PDT 24
Finished Jun 07 07:07:57 PM PDT 24
Peak memory 275152 kb
Host smart-b6834da7-2d68-49f3-b7c0-913125bcbe0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367429849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.367429849
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.2929631694
Short name T678
Test name
Test status
Simulation time 151418700 ps
CPU time 133.57 seconds
Started Jun 07 07:07:41 PM PDT 24
Finished Jun 07 07:09:55 PM PDT 24
Peak memory 260392 kb
Host smart-90e4e53d-f43b-4867-a5e5-22bcf2db657f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929631694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o
tp_reset.2929631694
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.2379796814
Short name T1017
Test name
Test status
Simulation time 52236500 ps
CPU time 15.75 seconds
Started Jun 07 07:07:42 PM PDT 24
Finished Jun 07 07:07:58 PM PDT 24
Peak memory 275180 kb
Host smart-a029aa8f-60e7-497f-8105-8dbd74412d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379796814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.2379796814
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.3011147293
Short name T966
Test name
Test status
Simulation time 43228500 ps
CPU time 130.57 seconds
Started Jun 07 07:07:41 PM PDT 24
Finished Jun 07 07:09:52 PM PDT 24
Peak memory 260580 kb
Host smart-d27ce646-0f55-4577-9821-04e960a8d6c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011147293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.3011147293
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.1112299926
Short name T644
Test name
Test status
Simulation time 16998300 ps
CPU time 13.24 seconds
Started Jun 07 07:07:42 PM PDT 24
Finished Jun 07 07:07:56 PM PDT 24
Peak memory 275072 kb
Host smart-0caca308-9387-46e9-8ef6-275959544f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112299926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.1112299926
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.2026806992
Short name T851
Test name
Test status
Simulation time 43601900 ps
CPU time 16.01 seconds
Started Jun 07 07:07:39 PM PDT 24
Finished Jun 07 07:07:57 PM PDT 24
Peak memory 275184 kb
Host smart-636c6df3-5800-4ecf-b0f9-7d6dbcdc950f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026806992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.2026806992
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.60836676
Short name T1089
Test name
Test status
Simulation time 132283800 ps
CPU time 108.9 seconds
Started Jun 07 07:07:41 PM PDT 24
Finished Jun 07 07:09:30 PM PDT 24
Peak memory 265656 kb
Host smart-11102f07-55e6-4221-a3a0-832d7ac567da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60836676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_otp
_reset.60836676
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.2562012502
Short name T652
Test name
Test status
Simulation time 79106700 ps
CPU time 15.7 seconds
Started Jun 07 07:07:47 PM PDT 24
Finished Jun 07 07:08:04 PM PDT 24
Peak memory 275044 kb
Host smart-cb97e30f-bcab-44cc-8254-7c0ab4dd976e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562012502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.2562012502
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.3443212879
Short name T513
Test name
Test status
Simulation time 72725800 ps
CPU time 133.31 seconds
Started Jun 07 07:07:48 PM PDT 24
Finished Jun 07 07:10:02 PM PDT 24
Peak memory 260568 kb
Host smart-69739d03-cc43-4d9c-812d-397bf37a7a5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443212879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.3443212879
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.3680391871
Short name T412
Test name
Test status
Simulation time 13727900 ps
CPU time 15.58 seconds
Started Jun 07 07:07:45 PM PDT 24
Finished Jun 07 07:08:02 PM PDT 24
Peak memory 275048 kb
Host smart-353c9228-2937-48c6-8c9b-bc675ead4ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680391871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.3680391871
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.1858872125
Short name T1088
Test name
Test status
Simulation time 256428600 ps
CPU time 133.1 seconds
Started Jun 07 07:07:46 PM PDT 24
Finished Jun 07 07:10:01 PM PDT 24
Peak memory 260368 kb
Host smart-d38f6c09-327e-4c46-a6c2-238616fd0b59
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858872125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.1858872125
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.1293515596
Short name T466
Test name
Test status
Simulation time 45689700 ps
CPU time 15.31 seconds
Started Jun 07 07:07:47 PM PDT 24
Finished Jun 07 07:08:03 PM PDT 24
Peak memory 275256 kb
Host smart-c9785dcf-e612-4b02-9c0e-e1d617e56247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293515596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.1293515596
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.2785114071
Short name T171
Test name
Test status
Simulation time 485095400 ps
CPU time 131.33 seconds
Started Jun 07 07:07:49 PM PDT 24
Finished Jun 07 07:10:01 PM PDT 24
Peak memory 261396 kb
Host smart-856315c4-956a-4234-bc5c-8eb386332dc2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785114071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.2785114071
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.1527942011
Short name T736
Test name
Test status
Simulation time 42525800 ps
CPU time 15.75 seconds
Started Jun 07 07:07:46 PM PDT 24
Finished Jun 07 07:08:03 PM PDT 24
Peak memory 275040 kb
Host smart-350cecf3-204a-47cf-a28b-b8070f30ca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527942011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.1527942011
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.611208205
Short name T936
Test name
Test status
Simulation time 78964700 ps
CPU time 129.99 seconds
Started Jun 07 07:07:47 PM PDT 24
Finished Jun 07 07:09:58 PM PDT 24
Peak memory 260092 kb
Host smart-042953cb-b587-44b0-a7ec-d878b2c5578a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611208205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_ot
p_reset.611208205
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.3978609836
Short name T728
Test name
Test status
Simulation time 16966400 ps
CPU time 13.36 seconds
Started Jun 07 07:07:47 PM PDT 24
Finished Jun 07 07:08:01 PM PDT 24
Peak memory 274916 kb
Host smart-2ab5065a-71e0-4d15-8042-27b900bb220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978609836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.3978609836
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.480200981
Short name T656
Test name
Test status
Simulation time 142794900 ps
CPU time 133.36 seconds
Started Jun 07 07:07:46 PM PDT 24
Finished Jun 07 07:10:01 PM PDT 24
Peak memory 260556 kb
Host smart-dd6b3296-ff55-41b4-93d4-1a99dd00995b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480200981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_ot
p_reset.480200981
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.58391794
Short name T647
Test name
Test status
Simulation time 299634200 ps
CPU time 13.82 seconds
Started Jun 07 07:02:22 PM PDT 24
Finished Jun 07 07:02:37 PM PDT 24
Peak memory 258604 kb
Host smart-5307606f-d839-4229-b68e-c0d778f18dd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58391794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.58391794
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.1062185187
Short name T514
Test name
Test status
Simulation time 14979500 ps
CPU time 13.41 seconds
Started Jun 07 07:02:10 PM PDT 24
Finished Jun 07 07:02:25 PM PDT 24
Peak memory 274976 kb
Host smart-39e5ba2a-7b22-4f59-b445-01497c2b0978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062185187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.1062185187
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.242532203
Short name T1025
Test name
Test status
Simulation time 17646500 ps
CPU time 21.95 seconds
Started Jun 07 07:02:10 PM PDT 24
Finished Jun 07 07:02:33 PM PDT 24
Peak memory 273916 kb
Host smart-ba42e030-fb42-4be1-b8ba-75b0c9738dc2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242532203 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.242532203
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.1795253168
Short name T39
Test name
Test status
Simulation time 4753403200 ps
CPU time 2189.13 seconds
Started Jun 07 07:02:02 PM PDT 24
Finished Jun 07 07:38:33 PM PDT 24
Peak memory 264992 kb
Host smart-1a16e2f4-42de-4e83-99a3-41eee8b059b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795253168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.1795253168
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.3261481644
Short name T204
Test name
Test status
Simulation time 2468745300 ps
CPU time 820.27 seconds
Started Jun 07 07:02:01 PM PDT 24
Finished Jun 07 07:15:43 PM PDT 24
Peak memory 273808 kb
Host smart-2f2f7b25-f5a3-4b3a-b499-27e9c5ea84b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261481644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3261481644
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.214512328
Short name T572
Test name
Test status
Simulation time 581841600 ps
CPU time 26.74 seconds
Started Jun 07 07:02:02 PM PDT 24
Finished Jun 07 07:02:31 PM PDT 24
Peak memory 263848 kb
Host smart-552c9343-0583-412d-b5d7-3ca6d370e226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214512328 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.214512328
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.813594937
Short name T323
Test name
Test status
Simulation time 10012500300 ps
CPU time 111.74 seconds
Started Jun 07 07:02:09 PM PDT 24
Finished Jun 07 07:04:02 PM PDT 24
Peak memory 313656 kb
Host smart-f5e89f87-fa25-4a0b-9501-37c8aea7bcd4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813594937 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.813594937
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.4088451881
Short name T387
Test name
Test status
Simulation time 15644200 ps
CPU time 13.25 seconds
Started Jun 07 07:02:11 PM PDT 24
Finished Jun 07 07:02:26 PM PDT 24
Peak memory 265228 kb
Host smart-08b83dd8-3dd4-4929-a997-b0427e5eb0b9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088451881 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.4088451881
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.3497070845
Short name T438
Test name
Test status
Simulation time 160181080900 ps
CPU time 870.81 seconds
Started Jun 07 07:02:01 PM PDT 24
Finished Jun 07 07:16:33 PM PDT 24
Peak memory 264536 kb
Host smart-0a346dfa-bfb7-4095-8c98-b6072038db9e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497070845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.3497070845
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.902076565
Short name T889
Test name
Test status
Simulation time 9142582800 ps
CPU time 259.55 seconds
Started Jun 07 07:02:00 PM PDT 24
Finished Jun 07 07:06:20 PM PDT 24
Peak memory 263420 kb
Host smart-7bae47af-b9c7-4872-b91c-f7f0c7e6238a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902076565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw
_sec_otp.902076565
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.553196024
Short name T199
Test name
Test status
Simulation time 1497087400 ps
CPU time 232.19 seconds
Started Jun 07 07:02:09 PM PDT 24
Finished Jun 07 07:06:03 PM PDT 24
Peak memory 285348 kb
Host smart-19164a3b-9a97-4312-b6b3-cf8c47979706
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553196024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_intr_rd.553196024
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.578634811
Short name T732
Test name
Test status
Simulation time 5935965200 ps
CPU time 127.8 seconds
Started Jun 07 07:02:10 PM PDT 24
Finished Jun 07 07:04:19 PM PDT 24
Peak memory 292832 kb
Host smart-00f92926-31bc-430e-909c-ea552ce75326
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578634811 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.578634811
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.3353306638
Short name T788
Test name
Test status
Simulation time 2673203400 ps
CPU time 77.1 seconds
Started Jun 07 07:02:11 PM PDT 24
Finished Jun 07 07:03:30 PM PDT 24
Peak memory 260908 kb
Host smart-11bff01d-1b92-494b-aa0f-f84c347ef327
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353306638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_wr.3353306638
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.1392847993
Short name T917
Test name
Test status
Simulation time 23863223900 ps
CPU time 197.95 seconds
Started Jun 07 07:02:11 PM PDT 24
Finished Jun 07 07:05:30 PM PDT 24
Peak memory 265432 kb
Host smart-92682976-e8bd-459b-b8d7-9c63f0efd284
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139
2847993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.1392847993
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.418417304
Short name T575
Test name
Test status
Simulation time 59522700 ps
CPU time 13.76 seconds
Started Jun 07 07:02:09 PM PDT 24
Finished Jun 07 07:02:24 PM PDT 24
Peak memory 265208 kb
Host smart-bdb771d6-aa9c-4686-a482-463f6fc26809
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418417304 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.418417304
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.4202298196
Short name T91
Test name
Test status
Simulation time 62458383300 ps
CPU time 519.4 seconds
Started Jun 07 07:02:03 PM PDT 24
Finished Jun 07 07:10:44 PM PDT 24
Peak memory 274788 kb
Host smart-5baac75e-0b89-483d-9c51-0d0fd681ac65
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202298196 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.4202298196
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.1809172136
Short name T691
Test name
Test status
Simulation time 57394500 ps
CPU time 131.76 seconds
Started Jun 07 07:02:03 PM PDT 24
Finished Jun 07 07:04:16 PM PDT 24
Peak memory 261256 kb
Host smart-c2d29f58-1f81-4581-9d80-7d16fae4b87c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809172136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot
p_reset.1809172136
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.3542113386
Short name T603
Test name
Test status
Simulation time 40863000 ps
CPU time 148.07 seconds
Started Jun 07 07:02:01 PM PDT 24
Finished Jun 07 07:04:29 PM PDT 24
Peak memory 263512 kb
Host smart-efcafb62-5bda-4cef-ae94-8b0a3fcd581f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3542113386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3542113386
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.3583550572
Short name T186
Test name
Test status
Simulation time 37195500 ps
CPU time 13.54 seconds
Started Jun 07 07:02:10 PM PDT 24
Finished Jun 07 07:02:25 PM PDT 24
Peak memory 258952 kb
Host smart-c887943f-26ac-4a70-8ae6-713c24d2aa61
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583550572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_res
et.3583550572
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.857895926
Short name T793
Test name
Test status
Simulation time 36825400 ps
CPU time 100.09 seconds
Started Jun 07 07:02:01 PM PDT 24
Finished Jun 07 07:03:41 PM PDT 24
Peak memory 269176 kb
Host smart-aa80c943-01a1-4909-9a19-3c0e4d6c7f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857895926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.857895926
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.2482038201
Short name T437
Test name
Test status
Simulation time 266674800 ps
CPU time 35.15 seconds
Started Jun 07 07:02:10 PM PDT 24
Finished Jun 07 07:02:47 PM PDT 24
Peak memory 275628 kb
Host smart-10db22f3-0cdb-4c3f-9777-9542b330ae8b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482038201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.2482038201
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.1710334506
Short name T974
Test name
Test status
Simulation time 906086200 ps
CPU time 105.36 seconds
Started Jun 07 07:02:02 PM PDT 24
Finished Jun 07 07:03:49 PM PDT 24
Peak memory 282076 kb
Host smart-3f9246b2-34dd-4b52-88db-50e2c9b9b70b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710334506 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_ro.1710334506
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.501898230
Short name T1014
Test name
Test status
Simulation time 629730100 ps
CPU time 175.86 seconds
Started Jun 07 07:02:10 PM PDT 24
Finished Jun 07 07:05:07 PM PDT 24
Peak memory 282300 kb
Host smart-8d97a045-ed4a-4489-afcc-a56dbee3727c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
501898230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.501898230
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.3147351094
Short name T569
Test name
Test status
Simulation time 3969360300 ps
CPU time 128.92 seconds
Started Jun 07 07:02:10 PM PDT 24
Finished Jun 07 07:04:20 PM PDT 24
Peak memory 295460 kb
Host smart-af3c9df8-630b-4b4e-968b-a7d67980b6c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147351094 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.3147351094
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.2104713416
Short name T458
Test name
Test status
Simulation time 15292079800 ps
CPU time 594.31 seconds
Started Jun 07 07:02:01 PM PDT 24
Finished Jun 07 07:11:57 PM PDT 24
Peak memory 314572 kb
Host smart-2b99fc15-bfbb-43c7-91d2-0cd3eaf68254
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104713416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.flash_ctrl_rw.2104713416
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_derr.3741616604
Short name T875
Test name
Test status
Simulation time 4595856900 ps
CPU time 763.89 seconds
Started Jun 07 07:02:09 PM PDT 24
Finished Jun 07 07:14:53 PM PDT 24
Peak memory 314924 kb
Host smart-7b893a2d-8011-4efc-91ea-33301a65a405
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741616604 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 8.flash_ctrl_rw_derr.3741616604
Directory /workspace/8.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.1023191222
Short name T306
Test name
Test status
Simulation time 44148800 ps
CPU time 28.14 seconds
Started Jun 07 07:02:09 PM PDT 24
Finished Jun 07 07:02:39 PM PDT 24
Peak memory 275796 kb
Host smart-8a60bd1c-eb2d-455b-a2b3-58d80a89e815
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023191222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_rw_evict.1023191222
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.2443525594
Short name T203
Test name
Test status
Simulation time 1975035200 ps
CPU time 70.15 seconds
Started Jun 07 07:02:10 PM PDT 24
Finished Jun 07 07:03:22 PM PDT 24
Peak memory 263788 kb
Host smart-25a21555-f125-4cd7-a536-acdef2d317bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443525594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.2443525594
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.398294742
Short name T640
Test name
Test status
Simulation time 138897600 ps
CPU time 142.26 seconds
Started Jun 07 07:02:01 PM PDT 24
Finished Jun 07 07:04:25 PM PDT 24
Peak memory 277112 kb
Host smart-ef7b6fea-0537-4274-8463-ec2cc583f7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398294742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.398294742
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.948707061
Short name T105
Test name
Test status
Simulation time 5072242900 ps
CPU time 212.22 seconds
Started Jun 07 07:02:02 PM PDT 24
Finished Jun 07 07:05:35 PM PDT 24
Peak memory 265428 kb
Host smart-40cbf1e5-c6a5-4b01-acb2-1d4c7145d144
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948707061 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.flash_ctrl_wo.948707061
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.2001560645
Short name T509
Test name
Test status
Simulation time 65955100 ps
CPU time 13.4 seconds
Started Jun 07 07:02:33 PM PDT 24
Finished Jun 07 07:02:47 PM PDT 24
Peak memory 258612 kb
Host smart-23dd4804-581f-4003-9f43-1f0bec2248c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001560645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2
001560645
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.2971802851
Short name T700
Test name
Test status
Simulation time 47062500 ps
CPU time 15.71 seconds
Started Jun 07 07:02:33 PM PDT 24
Finished Jun 07 07:02:50 PM PDT 24
Peak memory 275084 kb
Host smart-da3aabdb-39e1-4d92-a0f5-9a4d89c7803a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971802851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.2971802851
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.155689119
Short name T460
Test name
Test status
Simulation time 119233900 ps
CPU time 22.55 seconds
Started Jun 07 07:02:37 PM PDT 24
Finished Jun 07 07:03:00 PM PDT 24
Peak memory 273904 kb
Host smart-c9818a5f-1d21-49b5-8ee2-966a764ead23
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155689119 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.155689119
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.2400095974
Short name T779
Test name
Test status
Simulation time 6745069100 ps
CPU time 2308.6 seconds
Started Jun 07 07:02:22 PM PDT 24
Finished Jun 07 07:40:52 PM PDT 24
Peak memory 263092 kb
Host smart-cfb3477a-da56-417c-ab37-8406edde6e42
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400095974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.2400095974
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.814781055
Short name T850
Test name
Test status
Simulation time 1257481500 ps
CPU time 777.57 seconds
Started Jun 07 07:02:21 PM PDT 24
Finished Jun 07 07:15:20 PM PDT 24
Peak memory 273028 kb
Host smart-c5727dec-b798-4907-8781-aa77e4e1670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814781055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.814781055
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.969393077
Short name T720
Test name
Test status
Simulation time 126430600 ps
CPU time 21.9 seconds
Started Jun 07 07:02:21 PM PDT 24
Finished Jun 07 07:02:43 PM PDT 24
Peak memory 263896 kb
Host smart-7a7e9d60-710f-4a7f-a226-afe5c84b8d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969393077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.969393077
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.550758820
Short name T324
Test name
Test status
Simulation time 10012073600 ps
CPU time 339.53 seconds
Started Jun 07 07:02:34 PM PDT 24
Finished Jun 07 07:08:15 PM PDT 24
Peak memory 316644 kb
Host smart-bf1b605d-23e8-42a3-aed3-9c2068429c31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550758820 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.550758820
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.209803233
Short name T473
Test name
Test status
Simulation time 26702700 ps
CPU time 13.43 seconds
Started Jun 07 07:02:33 PM PDT 24
Finished Jun 07 07:02:48 PM PDT 24
Peak memory 258732 kb
Host smart-68fa921e-d286-4927-85d7-b94720e5efad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209803233 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.209803233
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.3601518549
Short name T588
Test name
Test status
Simulation time 80142054300 ps
CPU time 953 seconds
Started Jun 07 07:02:21 PM PDT 24
Finished Jun 07 07:18:15 PM PDT 24
Peak memory 264400 kb
Host smart-e1935902-4b81-4dd5-a71a-164d990ce27a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601518549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.3601518549
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.3502760757
Short name T347
Test name
Test status
Simulation time 3932382400 ps
CPU time 171.86 seconds
Started Jun 07 07:02:21 PM PDT 24
Finished Jun 07 07:05:14 PM PDT 24
Peak memory 261316 kb
Host smart-a80c9db3-e9fa-4280-acdc-a32dc46ddfdb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502760757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.3502760757
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.3007771415
Short name T128
Test name
Test status
Simulation time 2625256900 ps
CPU time 128.39 seconds
Started Jun 07 07:02:29 PM PDT 24
Finished Jun 07 07:04:38 PM PDT 24
Peak memory 285272 kb
Host smart-9b4b8d35-e84e-4284-911c-01435697706e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007771415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_intr_rd.3007771415
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1160325518
Short name T663
Test name
Test status
Simulation time 5845950700 ps
CPU time 146.34 seconds
Started Jun 07 07:02:27 PM PDT 24
Finished Jun 07 07:04:54 PM PDT 24
Peak memory 293420 kb
Host smart-8c126654-41d9-49d0-9eda-08f79098a3c4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160325518 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.1160325518
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.37994780
Short name T982
Test name
Test status
Simulation time 3925561500 ps
CPU time 63.29 seconds
Started Jun 07 07:02:26 PM PDT 24
Finished Jun 07 07:03:31 PM PDT 24
Peak memory 265472 kb
Host smart-76fc3794-0d35-44a0-a101-18faf38f9d35
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37994780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +U
VM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.flash_ctrl_intr_wr.37994780
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1201821253
Short name T692
Test name
Test status
Simulation time 86737432900 ps
CPU time 221.48 seconds
Started Jun 07 07:02:28 PM PDT 24
Finished Jun 07 07:06:10 PM PDT 24
Peak memory 265488 kb
Host smart-fc4c0e84-ba8f-41ac-8a91-012fa1078da0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120
1821253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.1201821253
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.1521153516
Short name T620
Test name
Test status
Simulation time 1013727500 ps
CPU time 80.05 seconds
Started Jun 07 07:02:20 PM PDT 24
Finished Jun 07 07:03:40 PM PDT 24
Peak memory 260844 kb
Host smart-8f266928-1cce-4878-88ff-43d3d28bd533
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521153516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.1521153516
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1168343670
Short name T1002
Test name
Test status
Simulation time 47505400 ps
CPU time 13.61 seconds
Started Jun 07 07:02:34 PM PDT 24
Finished Jun 07 07:02:49 PM PDT 24
Peak memory 260064 kb
Host smart-49de8f16-33ff-4215-9fd9-969653af5e61
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168343670 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1168343670
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.3803368918
Short name T852
Test name
Test status
Simulation time 67535292900 ps
CPU time 478.55 seconds
Started Jun 07 07:02:26 PM PDT 24
Finished Jun 07 07:10:26 PM PDT 24
Peak memory 275748 kb
Host smart-9db4b31e-0732-4a75-883a-46e1035f73b7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803368918 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.3803368918
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.321130692
Short name T1035
Test name
Test status
Simulation time 659731700 ps
CPU time 129.91 seconds
Started Jun 07 07:02:21 PM PDT 24
Finished Jun 07 07:04:32 PM PDT 24
Peak memory 264604 kb
Host smart-d92339a7-cdb1-4d18-8e74-16a318861a27
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321130692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp
_reset.321130692
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.1383035077
Short name T747
Test name
Test status
Simulation time 738497500 ps
CPU time 384.42 seconds
Started Jun 07 07:02:20 PM PDT 24
Finished Jun 07 07:08:45 PM PDT 24
Peak memory 263444 kb
Host smart-a6430003-3f4c-46bc-9f35-46be4eda40f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1383035077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.1383035077
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.1331997902
Short name T888
Test name
Test status
Simulation time 76455600 ps
CPU time 13.31 seconds
Started Jun 07 07:02:35 PM PDT 24
Finished Jun 07 07:02:49 PM PDT 24
Peak memory 258864 kb
Host smart-9c488528-03ca-4038-ad00-0f48f949f47f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331997902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.1331997902
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.1872574052
Short name T912
Test name
Test status
Simulation time 4427625700 ps
CPU time 892.94 seconds
Started Jun 07 07:02:20 PM PDT 24
Finished Jun 07 07:17:14 PM PDT 24
Peak memory 283968 kb
Host smart-267e8e9a-adf2-440e-a6aa-3793b6fd7829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872574052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.1872574052
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.1118838858
Short name T712
Test name
Test status
Simulation time 4483079600 ps
CPU time 114.62 seconds
Started Jun 07 07:02:29 PM PDT 24
Finished Jun 07 07:04:25 PM PDT 24
Peak memory 282088 kb
Host smart-04134d2e-ed94-4ec1-8151-6bd0cbf4c844
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118838858 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_ro.1118838858
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.1860357042
Short name T698
Test name
Test status
Simulation time 587745600 ps
CPU time 131.04 seconds
Started Jun 07 07:02:30 PM PDT 24
Finished Jun 07 07:04:42 PM PDT 24
Peak memory 282292 kb
Host smart-b6e728d5-6cc3-4535-a8f6-d1353b6b3590
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1860357042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.1860357042
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.216693029
Short name T6
Test name
Test status
Simulation time 885176500 ps
CPU time 117.91 seconds
Started Jun 07 07:02:29 PM PDT 24
Finished Jun 07 07:04:28 PM PDT 24
Peak memory 295392 kb
Host smart-520ce82b-5587-4c2a-8bab-7e9152ecb9c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216693029 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.216693029
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.3043373448
Short name T194
Test name
Test status
Simulation time 15014077800 ps
CPU time 612.43 seconds
Started Jun 07 07:02:29 PM PDT 24
Finished Jun 07 07:12:42 PM PDT 24
Peak memory 309812 kb
Host smart-495764b4-2b3e-437f-9b24-1616e79ede09
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043373448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.flash_ctrl_rw.3043373448
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.2132174778
Short name T1075
Test name
Test status
Simulation time 30638700 ps
CPU time 31.31 seconds
Started Jun 07 07:02:35 PM PDT 24
Finished Jun 07 07:03:07 PM PDT 24
Peak memory 270368 kb
Host smart-6c31b280-264e-41b9-b351-7ee85a4ed610
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132174778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.2132174778
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.3251196785
Short name T30
Test name
Test status
Simulation time 129878700 ps
CPU time 30.73 seconds
Started Jun 07 07:02:34 PM PDT 24
Finished Jun 07 07:03:06 PM PDT 24
Peak memory 276120 kb
Host smart-a368019f-e223-47ba-80af-8af532caa182
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251196785 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.3251196785
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.1203542556
Short name T925
Test name
Test status
Simulation time 16953854900 ps
CPU time 578.37 seconds
Started Jun 07 07:02:31 PM PDT 24
Finished Jun 07 07:12:10 PM PDT 24
Peak memory 313232 kb
Host smart-0190512b-3bc4-4cd7-a8c9-9e6f0ecea31f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203542556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s
err.1203542556
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.2207018601
Short name T127
Test name
Test status
Simulation time 9264237800 ps
CPU time 82.84 seconds
Started Jun 07 07:02:34 PM PDT 24
Finished Jun 07 07:03:58 PM PDT 24
Peak memory 265580 kb
Host smart-74c66c88-479d-4471-b1af-6e3420e56d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207018601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.2207018601
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.2903650755
Short name T1071
Test name
Test status
Simulation time 33824100 ps
CPU time 215.33 seconds
Started Jun 07 07:02:21 PM PDT 24
Finished Jun 07 07:05:57 PM PDT 24
Peak memory 278324 kb
Host smart-e68f06ca-0c6f-436d-bd42-6f9021344cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903650755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2903650755
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.2937579786
Short name T876
Test name
Test status
Simulation time 2954496300 ps
CPU time 248.03 seconds
Started Jun 07 07:02:29 PM PDT 24
Finished Jun 07 07:06:38 PM PDT 24
Peak memory 260292 kb
Host smart-ec09221c-a332-4780-8a2b-6d06c476c99a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937579786 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.flash_ctrl_wo.2937579786
Directory /workspace/9.flash_ctrl_wo/latest
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