Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	359021	1		T2	1		T3	1		T4	2
all_values[1]	359021	1		T2	1		T3	1		T4	2
all_values[2]	359021	1		T2	1		T3	1		T4	2
all_values[3]	359021	1		T2	1		T3	1		T4	2
all_values[4]	359021	1		T2	1		T3	1		T4	2
all_values[5]	359021	1		T2	1		T3	1		T4	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	724198	1		T2	6		T3	6		T4	12
auto[1]	1429928	1		T29	6632		T33	4624		T38	28140

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1047091	1		T2	4		T3	4		T4	7
auto[1]	1107035	1		T2	2		T3	2		T4	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	358873	1		T2	1		T3	1		T4	2
all_values[0]	auto[1]	auto[1]	148	1		T282	2		T283	2		T284	3
all_values[1]	auto[0]	auto[1]	358858	1		T2	1		T3	1		T4	2
all_values[1]	auto[1]	auto[1]	163	1		T282	4		T283	5		T284	2
all_values[2]	auto[0]	auto[0]	1565	1		T2	1		T3	1		T4	2
all_values[2]	auto[0]	auto[1]	71	1		T282	1		T283	1		T284	4
all_values[2]	auto[1]	auto[0]	357337	1		T29	1658		T33	1156		T38	7035
all_values[2]	auto[1]	auto[1]	48	1		T284	1		T340	1		T341	1
all_values[3]	auto[0]	auto[0]	1569	1		T2	1		T3	1		T4	2
all_values[3]	auto[0]	auto[1]	49	1		T282	2		T283	1		T284	3
all_values[3]	auto[1]	auto[0]	74252	1		T29	1658		T33	578		T38	35
all_values[3]	auto[1]	auto[1]	283151	1		T33	578		T38	7000		T39	1588
all_values[4]	auto[0]	auto[0]	1113	1		T2	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	505	1		T4	1		T5	1		T27	1
all_values[4]	auto[1]	auto[0]	252440	1		T29	1		T33	578		T38	5285
all_values[4]	auto[1]	auto[1]	104963	1		T29	1657		T33	578		T38	1750
all_values[5]	auto[0]	auto[0]	1458	1		T2	1		T3	1		T4	2
all_values[5]	auto[0]	auto[1]	137	1		T5	1		T22	1		T40	1
all_values[5]	auto[1]	auto[0]	357357	1		T29	1658		T33	1156		T38	7035
all_values[5]	auto[1]	auto[1]	69	1		T282	1		T283	3		T339	2