Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	255933	1		T2	1		T4	17		T5	1263
auto[FlashEraseBank]	274526	1		T4	4		T5	1666		T6	3

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	261994	1		T2	1		T4	7		T5	1000
auto[FlashOpProgram]	246926	1		T4	9		T5	1929		T6	2
auto[FlashOpErase]	17539	1		T4	5		T14	1		T44	1
auto[FlashOpInvalid]	4000	1		T192	200		T92	200		T96	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	261994	1		T2	1		T4	7		T5	1000
op[FlashOpProgram]	246926	1		T4	9		T5	1929		T6	2
op[FlashOpErase]	17539	1		T4	5		T14	1		T44	1
read_erase_read	741	1		T8	2		T21	2		T26	17
read_prog_read	781	1		T4	1		T5	10		T9	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	386303	1		T4	20		T5	2417		T6	6
auto[FlashPartInfo]	140790	1		T2	1		T4	1		T5	488
auto[FlashPartInfo1]	764	1		T5	2		T21	1		T49	5
auto[FlashPartInfo2]	2602	1		T5	22		T6	2		T22	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	189664	1		T4	6		T5	665		T6	4
auto[FlashPartData]	auto[FlashOpProgram]	189013	1		T4	9		T5	1752		T6	2
auto[FlashPartData]	auto[FlashOpErase]	3718	1		T4	5		T44	1		T8	4
auto[FlashPartData]	auto[FlashOpInvalid]	3908	1		T192	200		T92	196		T96	198
auto[FlashPartInfo]	auto[FlashOpRead]	70070	1		T2	1		T4	1		T5	317
auto[FlashPartInfo]	auto[FlashOpProgram]	56844	1		T5	171		T22	37		T21	3
auto[FlashPartInfo]	auto[FlashOpErase]	13800	1		T14	1		T26	11		T32	10
auto[FlashPartInfo]	auto[FlashOpInvalid]	76	1		T92	4		T96	2		T433	4
auto[FlashPartInfo1]	auto[FlashOpRead]	591	1		T5	2		T49	5		T40	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	164	1		T21	1		T34	32		T79	1
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T310	1		T79	1		T434	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T79	2		T435	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1669	1		T5	16		T6	2		T22	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	905	1		T5	6		T29	4		T49	2
auto[FlashPartInfo2]	auto[FlashOpErase]	16	1		T120	1		T93	1		T118	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T436	2		T437	4		T435	2