Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.10	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	5	27	84.38

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	5	27	84.38	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	33971	1		T4	4		T8	9		T48	5
auto[1]	27	1		T353	3		T201	4		T354	2
auto[2]	22	1		T64	4		T127	4		T355	3
auto[3]	73	1		T6	1		T28	2		T41	3

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8520	1		T4	1		T8	2		T48	1
evic_idx[1]	8520	1		T4	1		T8	2		T48	1
evic_idx[2]	8532	1		T4	1		T8	3		T48	2
evic_idx[3]	8521	1		T4	1		T6	1		T8	2

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	33163	1		T86	568		T122	1		T192	400
evic_op[2]	340	1		T6	1		T8	1		T48	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	5	27	84.38	5

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[1] , evic_idx[2] , evic_idx[3]]	[evic_op[1]]	[auto[1]]	--	--	3

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	8287	1		T86	142		T122	1		T192	100
evic_idx[0]	evic_op[1]	auto[3]	3	1		T356	1		T357	2		-	-
evic_idx[0]	evic_op[2]	auto[0]	60	1		T121	4		T325	3		T232	2
evic_idx[0]	evic_op[2]	auto[1]	6	1		T353	1		T190	1		T358	1
evic_idx[0]	evic_op[2]	auto[2]	1	1		T359	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	15	1		T41	1		T43	1		T360	1
evic_idx[1]	evic_op[1]	auto[0]	8286	1		T86	142		T192	100		T174	156
evic_idx[1]	evic_op[1]	auto[2]	1	1		T355	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	3	1		T356	1		T357	2		-	-
evic_idx[1]	evic_op[2]	auto[0]	62	1		T121	4		T325	3		T197	1
evic_idx[1]	evic_op[2]	auto[1]	7	1		T336	1		T115	1		T361	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T94	1		T362	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	11	1		T28	1		T112	1		T191	1
evic_idx[2]	evic_op[1]	auto[0]	8285	1		T86	142		T192	100		T174	156
evic_idx[2]	evic_op[1]	auto[2]	2	1		T355	1		T237	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	5	1		T356	1		T357	2		T363	2
evic_idx[2]	evic_op[2]	auto[0]	66	1		T8	1		T48	1		T121	4
evic_idx[2]	evic_op[2]	auto[1]	8	1		T353	1		T201	2		T354	1
evic_idx[2]	evic_op[2]	auto[2]	1	1		T359	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	17	1		T28	1		T41	1		T42	1
evic_idx[3]	evic_op[1]	auto[0]	8285	1		T86	142		T192	100		T174	156
evic_idx[3]	evic_op[1]	auto[2]	1	1		T355	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	5	1		T356	1		T357	2		T363	2
evic_idx[3]	evic_op[2]	auto[0]	62	1		T121	4		T325	3		T232	2
evic_idx[3]	evic_op[2]	auto[1]	6	1		T353	1		T201	2		T354	1
evic_idx[3]	evic_op[2]	auto[2]	2	1		T362	1		T364	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	14	1		T6	1		T41	1		T43	1