Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	37411	1		T272	15512		T303	1946		T346	14334
rd_lvl[2]	42120	1		T347	1271		T272	11192		T303	1208
rd_lvl[3]	16336	1		T347	602		T348	1179		T200	290
rd_lvl[4]	48862	1		T38	5710		T347	101		T348	5863
rd_lvl[5]	14518	1		T38	1238		T347	424		T348	1147
rd_lvl[6]	19836	1		T187	2706		T347	373		T349	2396
rd_lvl[7]	11875	1		T248	1813		T187	304		T347	74
rd_lvl[8]	24997	1		T248	1507		T347	72		T350	1382
rd_lvl[9]	9243	1		T39	523		T347	71		T303	273
rd_lvl[10]	11349	1		T39	1065		T351	569		T352	1397
rd_lvl[11]	1756	1		T351	71		T352	371		T303	146
rd_lvl[12]	2143	1		T324	1637		T347	67		T303	1
rd_lvl[13]	2100	1		T33	292		T347	66		T200	2
rd_lvl[14]	3155	1		T33	173		T36	356		T37	141
rd_lvl[15]	1140	1		T36	149		T37	66		T203	556