Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	359021	1		T2	1		T3	1		T4	2
all_pins[1]	359021	1		T2	1		T3	1		T4	2
all_pins[2]	359021	1		T2	1		T3	1		T4	2
all_pins[3]	359021	1		T2	1		T3	1		T4	2
all_pins[4]	359021	1		T2	1		T3	1		T4	2
all_pins[5]	359021	1		T2	1		T3	1		T4	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1791835	1		T2	6		T3	6		T4	12
values[0x1]	362291	1		T29	1657		T33	1156		T38	8702
transitions[0x0=>0x1]	323430	1		T29	1657		T33	1156		T38	6984
transitions[0x1=>0x0]	323424	1		T29	1657		T33	1156		T38	6984

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	358873	1		T2	1		T3	1		T4	2
all_pins[0]	values[0x1]	148	1		T282	2		T283	2		T284	3
all_pins[0]	transitions[0x0=>0x1]	84	1		T283	1		T284	3		T339	4
all_pins[0]	transitions[0x1=>0x0]	99	1		T282	2		T283	4		T284	2
all_pins[1]	values[0x0]	358858	1		T2	1		T3	1		T4	2
all_pins[1]	values[0x1]	163	1		T282	4		T283	5		T284	2
all_pins[1]	transitions[0x0=>0x1]	139	1		T282	4		T283	5		T284	1
all_pins[1]	transitions[0x1=>0x0]	1620	1		T36	82		T37	45		T203	1224
all_pins[2]	values[0x0]	357377	1		T2	1		T3	1		T4	2
all_pins[2]	values[0x1]	1644	1		T36	82		T37	45		T203	1224
all_pins[2]	transitions[0x0=>0x1]	35	1		T284	1		T340	1		T341	1
all_pins[2]	transitions[0x1=>0x0]	247174	1		T33	578		T38	6948		T39	1588
all_pins[3]	values[0x0]	110238	1		T2	1		T3	1		T4	2
all_pins[3]	values[0x1]	248783	1		T33	578		T38	6948		T39	1588
all_pins[3]	transitions[0x0=>0x1]	211679	1		T33	578		T38	5230		T39	1588
all_pins[3]	transitions[0x1=>0x0]	74380	1		T29	1657		T33	578		T38	36
all_pins[4]	values[0x0]	247537	1		T2	1		T3	1		T4	2
all_pins[4]	values[0x1]	111484	1		T29	1657		T33	578		T38	1754
all_pins[4]	transitions[0x0=>0x1]	111462	1		T29	1657		T33	578		T38	1754
all_pins[4]	transitions[0x1=>0x0]	47	1		T283	3		T339	2		T340	1
all_pins[5]	values[0x0]	358952	1		T2	1		T3	1		T4	2
all_pins[5]	values[0x1]	69	1		T282	1		T283	3		T339	2
all_pins[5]	transitions[0x0=>0x1]	31	1		T283	2		T339	1		T341	2
all_pins[5]	transitions[0x1=>0x0]	104	1		T282	1		T283	2		T284	3