Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	296	1		T282	4		T283	7		T284	7
all_values[1]	296	1		T282	4		T283	7		T284	7
all_values[2]	296	1		T282	4		T283	7		T284	7
all_values[3]	296	1		T282	4		T283	7		T284	7
all_values[4]	296	1		T282	4		T283	7		T284	7
all_values[5]	296	1		T282	4		T283	7		T284	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	943	1		T282	13		T283	19		T284	32
auto[1]	833	1		T282	11		T283	23		T284	10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	614	1		T282	8		T283	12		T284	13
auto[1]	1162	1		T282	16		T283	30		T284	29

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1059	1		T282	15		T283	24		T284	20
auto[1]	717	1		T282	9		T283	18		T284	22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	91	1		T282	3		T283	2		T284	3
all_values[0]	auto[0]	auto[1]	auto[1]	67	1		T282	1		T283	1		T284	1
all_values[0]	auto[1]	auto[0]	auto[1]	84	1		T283	2		T284	2		T339	1
all_values[0]	auto[1]	auto[1]	auto[1]	54	1		T283	2		T284	1		T339	3
all_values[1]	auto[0]	auto[0]	auto[1]	91	1		T282	1		T283	2		T284	1
all_values[1]	auto[0]	auto[1]	auto[1]	88	1		T282	2		T283	3		T284	1
all_values[1]	auto[1]	auto[0]	auto[1]	64	1		T283	2		T284	5		T340	1
all_values[1]	auto[1]	auto[1]	auto[1]	53	1		T282	1		T339	1		T341	3
all_values[2]	auto[0]	auto[0]	auto[0]	100	1		T282	2		T283	3		T284	1
all_values[2]	auto[0]	auto[1]	auto[0]	77	1		T282	1		T283	3		T284	1
all_values[2]	auto[1]	auto[0]	auto[1]	74	1		T282	1		T283	1		T284	5
all_values[2]	auto[1]	auto[1]	auto[1]	45	1		T341	3		T342	2		T343	2
all_values[3]	auto[0]	auto[0]	auto[0]	97	1		T283	2		T284	3		T339	2
all_values[3]	auto[0]	auto[1]	auto[0]	95	1		T282	1		T283	1		T339	3
all_values[3]	auto[1]	auto[0]	auto[1]	54	1		T282	3		T283	1		T284	3
all_values[3]	auto[1]	auto[1]	auto[1]	50	1		T283	3		T284	1		T339	2
all_values[4]	auto[0]	auto[0]	auto[0]	60	1		T284	3		T339	2		T341	2
all_values[4]	auto[0]	auto[0]	auto[1]	28	1		T283	1		T339	2		T340	1
all_values[4]	auto[0]	auto[1]	auto[0]	68	1		T282	1		T283	1		T284	2
all_values[4]	auto[0]	auto[1]	auto[1]	22	1		T283	1		T341	1		T344	2
all_values[4]	auto[1]	auto[0]	auto[1]	64	1		T282	1		T283	2		T284	1
all_values[4]	auto[1]	auto[1]	auto[1]	54	1		T282	2		T283	2		T284	1
all_values[5]	auto[0]	auto[0]	auto[0]	44	1		T282	1		T284	1		T345	1
all_values[5]	auto[0]	auto[0]	auto[1]	25	1		T284	1		T339	2		T341	1
all_values[5]	auto[0]	auto[1]	auto[0]	73	1		T282	2		T283	2		T284	2
all_values[5]	auto[0]	auto[1]	auto[1]	33	1		T283	2		T340	1		T341	2
all_values[5]	auto[1]	auto[0]	auto[1]	67	1		T282	1		T283	1		T284	3
all_values[5]	auto[1]	auto[1]	auto[1]	54	1		T283	2		T339	2		T340	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal