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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.33 95.73 94.09 97.54 92.52 98.17 98.16 98.09


Total test records in report: 1243
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T234 /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.2269910401 Jun 09 02:43:10 PM PDT 24 Jun 09 02:43:27 PM PDT 24 988439300 ps
T1070 /workspace/coverage/default/16.flash_ctrl_wo.1775311755 Jun 09 02:52:19 PM PDT 24 Jun 09 02:54:52 PM PDT 24 7719764600 ps
T1071 /workspace/coverage/default/13.flash_ctrl_disable.3049199883 Jun 09 02:51:15 PM PDT 24 Jun 09 02:51:36 PM PDT 24 12887800 ps
T1072 /workspace/coverage/default/3.flash_ctrl_ro_serr.336418388 Jun 09 02:44:59 PM PDT 24 Jun 09 02:47:39 PM PDT 24 1375093300 ps
T1073 /workspace/coverage/default/28.flash_ctrl_smoke.1898814272 Jun 09 02:55:12 PM PDT 24 Jun 09 02:57:15 PM PDT 24 112220800 ps
T1074 /workspace/coverage/default/49.flash_ctrl_otp_reset.1528155112 Jun 09 02:57:16 PM PDT 24 Jun 09 02:59:32 PM PDT 24 278168300 ps
T1075 /workspace/coverage/default/0.flash_ctrl_read_word_sweep.3099286430 Jun 09 02:41:22 PM PDT 24 Jun 09 02:41:37 PM PDT 24 53955000 ps
T1076 /workspace/coverage/default/21.flash_ctrl_connect.714942770 Jun 09 02:54:12 PM PDT 24 Jun 09 02:54:28 PM PDT 24 28391100 ps
T1077 /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.3575082906 Jun 09 02:47:05 PM PDT 24 Jun 09 02:47:19 PM PDT 24 15783800 ps
T1078 /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.222140571 Jun 09 02:45:54 PM PDT 24 Jun 09 02:46:17 PM PDT 24 33142300 ps
T1079 /workspace/coverage/default/28.flash_ctrl_otp_reset.1421094617 Jun 09 02:55:15 PM PDT 24 Jun 09 02:57:05 PM PDT 24 36940800 ps
T1080 /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2885524210 Jun 09 02:53:45 PM PDT 24 Jun 09 02:57:03 PM PDT 24 2549172900 ps
T363 /workspace/coverage/default/14.flash_ctrl_re_evict.2952217656 Jun 09 02:51:43 PM PDT 24 Jun 09 02:52:19 PM PDT 24 151838600 ps
T1081 /workspace/coverage/default/28.flash_ctrl_sec_info_access.3868873236 Jun 09 02:55:16 PM PDT 24 Jun 09 02:56:15 PM PDT 24 346367600 ps
T1082 /workspace/coverage/default/71.flash_ctrl_connect.3796852190 Jun 09 02:57:37 PM PDT 24 Jun 09 02:57:53 PM PDT 24 16781200 ps
T1083 /workspace/coverage/default/48.flash_ctrl_connect.1393098193 Jun 09 02:57:08 PM PDT 24 Jun 09 02:57:23 PM PDT 24 24430200 ps
T432 /workspace/coverage/default/1.flash_ctrl_ro_derr.1212027004 Jun 09 02:42:50 PM PDT 24 Jun 09 02:45:49 PM PDT 24 934073400 ps
T1084 /workspace/coverage/default/25.flash_ctrl_sec_info_access.777813699 Jun 09 02:54:51 PM PDT 24 Jun 09 02:56:00 PM PDT 24 1980998800 ps
T1085 /workspace/coverage/default/24.flash_ctrl_otp_reset.2644646479 Jun 09 02:54:40 PM PDT 24 Jun 09 02:56:51 PM PDT 24 76245200 ps
T1086 /workspace/coverage/default/6.flash_ctrl_disable.2227274926 Jun 09 02:47:23 PM PDT 24 Jun 09 02:47:45 PM PDT 24 37427300 ps
T1087 /workspace/coverage/default/5.flash_ctrl_ro_derr.831228271 Jun 09 02:46:38 PM PDT 24 Jun 09 02:48:39 PM PDT 24 10622146000 ps
T414 /workspace/coverage/default/38.flash_ctrl_sec_info_access.1818051320 Jun 09 02:56:26 PM PDT 24 Jun 09 02:57:21 PM PDT 24 342894200 ps
T1088 /workspace/coverage/default/68.flash_ctrl_connect.788975386 Jun 09 02:57:32 PM PDT 24 Jun 09 02:57:48 PM PDT 24 42572100 ps
T1089 /workspace/coverage/default/39.flash_ctrl_smoke.1692797305 Jun 09 02:56:26 PM PDT 24 Jun 09 02:58:04 PM PDT 24 53454900 ps
T1090 /workspace/coverage/default/10.flash_ctrl_wo.1251219544 Jun 09 02:49:25 PM PDT 24 Jun 09 02:52:43 PM PDT 24 10060702500 ps
T1091 /workspace/coverage/default/45.flash_ctrl_alert_test.2341394174 Jun 09 02:56:56 PM PDT 24 Jun 09 02:57:10 PM PDT 24 50461700 ps
T1092 /workspace/coverage/default/59.flash_ctrl_connect.2028748012 Jun 09 02:57:23 PM PDT 24 Jun 09 02:57:37 PM PDT 24 22064200 ps
T1093 /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.441918147 Jun 09 02:48:40 PM PDT 24 Jun 09 02:50:20 PM PDT 24 10035513100 ps
T1094 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3071135058 Jun 09 01:28:26 PM PDT 24 Jun 09 01:28:40 PM PDT 24 13873900 ps
T53 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3295198733 Jun 09 01:28:00 PM PDT 24 Jun 09 01:28:20 PM PDT 24 158593800 ps
T54 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2472210241 Jun 09 01:27:52 PM PDT 24 Jun 09 01:35:29 PM PDT 24 789669900 ps
T55 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3350835539 Jun 09 01:27:29 PM PDT 24 Jun 09 01:33:48 PM PDT 24 656131100 ps
T282 /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1750828497 Jun 09 01:27:57 PM PDT 24 Jun 09 01:28:10 PM PDT 24 16952300 ps
T283 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2777479296 Jun 09 01:28:41 PM PDT 24 Jun 09 01:28:55 PM PDT 24 18532200 ps
T275 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1180737558 Jun 09 01:28:11 PM PDT 24 Jun 09 01:28:30 PM PDT 24 102299100 ps
T284 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.817406223 Jun 09 01:28:45 PM PDT 24 Jun 09 01:28:58 PM PDT 24 30363500 ps
T227 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2987529017 Jun 09 01:28:32 PM PDT 24 Jun 09 01:28:47 PM PDT 24 106467300 ps
T1095 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2559019950 Jun 09 01:27:23 PM PDT 24 Jun 09 01:27:36 PM PDT 24 24054100 ps
T339 /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3426022461 Jun 09 01:28:53 PM PDT 24 Jun 09 01:29:07 PM PDT 24 54548600 ps
T276 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3995397213 Jun 09 01:27:50 PM PDT 24 Jun 09 01:28:07 PM PDT 24 32280200 ps
T228 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3933870506 Jun 09 01:27:20 PM PDT 24 Jun 09 01:27:37 PM PDT 24 76452100 ps
T225 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.4223019915 Jun 09 01:27:59 PM PDT 24 Jun 09 01:28:17 PM PDT 24 284448900 ps
T345 /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1175657090 Jun 09 01:28:37 PM PDT 24 Jun 09 01:28:50 PM PDT 24 51103800 ps
T1096 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1392805827 Jun 09 01:27:18 PM PDT 24 Jun 09 01:27:34 PM PDT 24 40109600 ps
T1097 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1717289871 Jun 09 01:27:34 PM PDT 24 Jun 09 01:27:49 PM PDT 24 35563000 ps
T262 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1906537620 Jun 09 01:27:12 PM PDT 24 Jun 09 01:27:26 PM PDT 24 71298200 ps
T277 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.282621928 Jun 09 01:28:29 PM PDT 24 Jun 09 01:28:59 PM PDT 24 403472800 ps
T313 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2337955334 Jun 09 01:28:02 PM PDT 24 Jun 09 01:28:17 PM PDT 24 124903500 ps
T226 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1200065389 Jun 09 01:27:42 PM PDT 24 Jun 09 01:28:00 PM PDT 24 189624300 ps
T229 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1910240310 Jun 09 01:27:23 PM PDT 24 Jun 09 01:33:44 PM PDT 24 727987300 ps
T253 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2869666427 Jun 09 01:28:27 PM PDT 24 Jun 09 01:28:46 PM PDT 24 201636500 ps
T1098 /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.506453052 Jun 09 01:28:12 PM PDT 24 Jun 09 01:28:27 PM PDT 24 97090100 ps
T340 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3656071119 Jun 09 01:27:12 PM PDT 24 Jun 09 01:27:26 PM PDT 24 30247100 ps
T260 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.504028540 Jun 09 01:28:02 PM PDT 24 Jun 09 01:43:06 PM PDT 24 3312617000 ps
T1099 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.4114731407 Jun 09 01:28:00 PM PDT 24 Jun 09 01:28:15 PM PDT 24 16521700 ps
T254 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2224883035 Jun 09 01:27:54 PM PDT 24 Jun 09 01:28:12 PM PDT 24 55510000 ps
T1100 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2945529572 Jun 09 01:28:05 PM PDT 24 Jun 09 01:28:19 PM PDT 24 15043300 ps
T1101 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.697220799 Jun 09 01:27:30 PM PDT 24 Jun 09 01:27:45 PM PDT 24 18426900 ps
T341 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3822990898 Jun 09 01:28:52 PM PDT 24 Jun 09 01:29:06 PM PDT 24 73014600 ps
T342 /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1470821397 Jun 09 01:26:58 PM PDT 24 Jun 09 01:27:12 PM PDT 24 15354900 ps
T343 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3549843308 Jun 09 01:28:44 PM PDT 24 Jun 09 01:28:57 PM PDT 24 24774800 ps
T1102 /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.621984066 Jun 09 01:28:26 PM PDT 24 Jun 09 01:28:39 PM PDT 24 35579800 ps
T1103 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2673425801 Jun 09 01:28:43 PM PDT 24 Jun 09 01:28:56 PM PDT 24 99939000 ps
T255 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2306802074 Jun 09 01:28:22 PM PDT 24 Jun 09 01:28:38 PM PDT 24 100031000 ps
T256 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1235765095 Jun 09 01:28:23 PM PDT 24 Jun 09 01:35:53 PM PDT 24 415612700 ps
T1104 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3902164328 Jun 09 01:27:11 PM PDT 24 Jun 09 01:27:25 PM PDT 24 13373200 ps
T257 /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2563099153 Jun 09 01:27:41 PM PDT 24 Jun 09 01:27:58 PM PDT 24 134084300 ps
T1105 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1746059270 Jun 09 01:28:17 PM PDT 24 Jun 09 01:28:33 PM PDT 24 51216700 ps
T1106 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2303673636 Jun 09 01:28:32 PM PDT 24 Jun 09 01:28:45 PM PDT 24 42435900 ps
T1107 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.512985024 Jun 09 01:28:01 PM PDT 24 Jun 09 01:28:17 PM PDT 24 15221600 ps
T1108 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1747036355 Jun 09 01:26:59 PM PDT 24 Jun 09 01:27:15 PM PDT 24 93135700 ps
T258 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.206764289 Jun 09 01:28:24 PM PDT 24 Jun 09 01:28:42 PM PDT 24 51727900 ps
T1109 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1637758501 Jun 09 01:28:21 PM PDT 24 Jun 09 01:28:38 PM PDT 24 30181000 ps
T1110 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2918952078 Jun 09 01:27:16 PM PDT 24 Jun 09 01:27:46 PM PDT 24 482732200 ps
T259 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1771768091 Jun 09 01:27:20 PM PDT 24 Jun 09 01:27:38 PM PDT 24 85983200 ps
T344 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3920344755 Jun 09 01:28:46 PM PDT 24 Jun 09 01:28:59 PM PDT 24 19112500 ps
T1111 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3056068642 Jun 09 01:28:13 PM PDT 24 Jun 09 01:28:28 PM PDT 24 11390200 ps
T1112 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2009571977 Jun 09 01:27:28 PM PDT 24 Jun 09 01:27:44 PM PDT 24 37484000 ps
T1113 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2230269065 Jun 09 01:28:49 PM PDT 24 Jun 09 01:29:03 PM PDT 24 15473100 ps
T1114 /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4068997717 Jun 09 01:28:54 PM PDT 24 Jun 09 01:29:07 PM PDT 24 53635400 ps
T1115 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.880909937 Jun 09 01:27:49 PM PDT 24 Jun 09 01:28:03 PM PDT 24 19227700 ps
T1116 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3552337823 Jun 09 01:27:21 PM PDT 24 Jun 09 01:27:38 PM PDT 24 201194200 ps
T1117 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.156860160 Jun 09 01:27:54 PM PDT 24 Jun 09 01:28:10 PM PDT 24 17813900 ps
T1118 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1539588048 Jun 09 01:28:34 PM PDT 24 Jun 09 01:28:50 PM PDT 24 34072700 ps
T261 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1209247813 Jun 09 01:28:23 PM PDT 24 Jun 09 01:28:39 PM PDT 24 53648600 ps
T1119 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2793245652 Jun 09 01:28:21 PM PDT 24 Jun 09 01:28:36 PM PDT 24 23696000 ps
T314 /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.416198830 Jun 09 01:27:18 PM PDT 24 Jun 09 01:27:37 PM PDT 24 113272900 ps
T297 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.791088724 Jun 09 01:28:24 PM PDT 24 Jun 09 01:40:59 PM PDT 24 3299202000 ps
T1120 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1778556355 Jun 09 01:27:15 PM PDT 24 Jun 09 01:27:46 PM PDT 24 268941300 ps
T295 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3825986147 Jun 09 01:27:35 PM PDT 24 Jun 09 01:42:35 PM PDT 24 862623500 ps
T1121 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3856507472 Jun 09 01:27:23 PM PDT 24 Jun 09 01:27:41 PM PDT 24 196852700 ps
T1122 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.495840874 Jun 09 01:28:43 PM PDT 24 Jun 09 01:28:56 PM PDT 24 15293500 ps
T1123 /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.647368502 Jun 09 01:27:54 PM PDT 24 Jun 09 01:28:30 PM PDT 24 1274890200 ps
T1124 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.28159904 Jun 09 01:27:49 PM PDT 24 Jun 09 01:28:25 PM PDT 24 174724800 ps
T1125 /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.90847652 Jun 09 01:28:18 PM PDT 24 Jun 09 01:28:32 PM PDT 24 18898000 ps
T315 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.622554442 Jun 09 01:28:06 PM PDT 24 Jun 09 01:28:24 PM PDT 24 115359200 ps
T294 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2039242183 Jun 09 01:28:13 PM PDT 24 Jun 09 01:28:31 PM PDT 24 55553400 ps
T1126 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3434216423 Jun 09 01:27:20 PM PDT 24 Jun 09 01:27:34 PM PDT 24 15026900 ps
T1127 /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1128758140 Jun 09 01:28:51 PM PDT 24 Jun 09 01:29:05 PM PDT 24 29857700 ps
T1128 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3556072290 Jun 09 01:28:29 PM PDT 24 Jun 09 01:28:42 PM PDT 24 30730500 ps
T1129 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3846616006 Jun 09 01:28:22 PM PDT 24 Jun 09 01:28:38 PM PDT 24 14840500 ps
T1130 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.4141840777 Jun 09 01:28:26 PM PDT 24 Jun 09 01:28:40 PM PDT 24 25107800 ps
T1131 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3071764581 Jun 09 01:28:06 PM PDT 24 Jun 09 01:28:24 PM PDT 24 55985500 ps
T290 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4229747683 Jun 09 01:27:30 PM PDT 24 Jun 09 01:35:03 PM PDT 24 185636400 ps
T1132 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2347937668 Jun 09 01:27:00 PM PDT 24 Jun 09 01:27:14 PM PDT 24 51779900 ps
T1133 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1178548907 Jun 09 01:27:11 PM PDT 24 Jun 09 01:27:25 PM PDT 24 13917500 ps
T1134 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.169530649 Jun 09 01:28:13 PM PDT 24 Jun 09 01:28:27 PM PDT 24 19258800 ps
T1135 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4248621958 Jun 09 01:28:07 PM PDT 24 Jun 09 01:28:21 PM PDT 24 54378000 ps
T1136 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1266463370 Jun 09 01:27:05 PM PDT 24 Jun 09 01:27:19 PM PDT 24 23918400 ps
T316 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3158277409 Jun 09 01:27:15 PM PDT 24 Jun 09 01:27:36 PM PDT 24 206935200 ps
T1137 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3877243782 Jun 09 01:27:12 PM PDT 24 Jun 09 01:27:29 PM PDT 24 36116400 ps
T1138 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1025111829 Jun 09 01:28:53 PM PDT 24 Jun 09 01:29:07 PM PDT 24 31696200 ps
T1139 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1594147068 Jun 09 01:28:11 PM PDT 24 Jun 09 01:28:28 PM PDT 24 33424700 ps
T1140 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3680373388 Jun 09 01:28:55 PM PDT 24 Jun 09 01:29:08 PM PDT 24 16504200 ps
T317 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1086478151 Jun 09 01:27:01 PM PDT 24 Jun 09 01:27:18 PM PDT 24 214928800 ps
T1141 /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2253272692 Jun 09 01:28:24 PM PDT 24 Jun 09 01:28:41 PM PDT 24 18617900 ps
T279 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1734757263 Jun 09 01:28:34 PM PDT 24 Jun 09 01:28:51 PM PDT 24 40298600 ps
T1142 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2206819152 Jun 09 01:28:27 PM PDT 24 Jun 09 01:28:43 PM PDT 24 43240000 ps
T1143 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1243954531 Jun 09 01:27:00 PM PDT 24 Jun 09 01:27:17 PM PDT 24 21016400 ps
T1144 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2133844686 Jun 09 01:27:22 PM PDT 24 Jun 09 01:28:06 PM PDT 24 1150179600 ps
T318 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2474071255 Jun 09 01:27:12 PM PDT 24 Jun 09 01:28:17 PM PDT 24 2754272900 ps
T1145 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.719511699 Jun 09 01:28:20 PM PDT 24 Jun 09 01:28:33 PM PDT 24 20029200 ps
T1146 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2725781234 Jun 09 01:28:23 PM PDT 24 Jun 09 01:28:39 PM PDT 24 326125200 ps
T1147 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1756140897 Jun 09 01:27:17 PM PDT 24 Jun 09 01:27:30 PM PDT 24 20266200 ps
T1148 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.98961780 Jun 09 01:27:06 PM PDT 24 Jun 09 01:27:22 PM PDT 24 33958100 ps
T1149 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.4224893775 Jun 09 01:28:22 PM PDT 24 Jun 09 01:28:36 PM PDT 24 69101500 ps
T280 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2323036167 Jun 09 01:27:01 PM PDT 24 Jun 09 01:27:21 PM PDT 24 118369700 ps
T293 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2033582218 Jun 09 01:27:01 PM PDT 24 Jun 09 01:42:16 PM PDT 24 2719026300 ps
T281 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1574252854 Jun 09 01:27:01 PM PDT 24 Jun 09 01:27:18 PM PDT 24 78165600 ps
T1150 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3521456380 Jun 09 01:27:17 PM PDT 24 Jun 09 01:34:56 PM PDT 24 684593300 ps
T1151 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.231836613 Jun 09 01:28:43 PM PDT 24 Jun 09 01:28:57 PM PDT 24 66894500 ps
T1152 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.198007740 Jun 09 01:28:06 PM PDT 24 Jun 09 01:28:19 PM PDT 24 13590400 ps
T1153 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.903231899 Jun 09 01:27:01 PM PDT 24 Jun 09 01:27:14 PM PDT 24 12937300 ps
T1154 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3403335469 Jun 09 01:27:34 PM PDT 24 Jun 09 01:27:49 PM PDT 24 95393800 ps
T319 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1916657846 Jun 09 01:27:49 PM PDT 24 Jun 09 01:28:04 PM PDT 24 50839900 ps
T296 /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1486608729 Jun 09 01:27:08 PM PDT 24 Jun 09 01:34:39 PM PDT 24 946558900 ps
T1155 /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1460702808 Jun 09 01:28:00 PM PDT 24 Jun 09 01:28:15 PM PDT 24 41244600 ps
T1156 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3763545720 Jun 09 01:27:17 PM PDT 24 Jun 09 01:27:43 PM PDT 24 50346200 ps
T1157 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3618233170 Jun 09 01:27:06 PM PDT 24 Jun 09 01:27:22 PM PDT 24 30586300 ps
T1158 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1197780349 Jun 09 01:28:29 PM PDT 24 Jun 09 01:28:44 PM PDT 24 60264000 ps
T320 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.418849753 Jun 09 01:28:22 PM PDT 24 Jun 09 01:28:57 PM PDT 24 368643500 ps
T1159 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3837716114 Jun 09 01:28:33 PM PDT 24 Jun 09 01:36:04 PM PDT 24 339306100 ps
T1160 /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3615773121 Jun 09 01:28:55 PM PDT 24 Jun 09 01:29:08 PM PDT 24 52521500 ps
T1161 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2721039023 Jun 09 01:28:50 PM PDT 24 Jun 09 01:29:03 PM PDT 24 17024500 ps
T1162 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2949962347 Jun 09 01:27:11 PM PDT 24 Jun 09 01:27:28 PM PDT 24 55604500 ps
T1163 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1738431388 Jun 09 01:27:13 PM PDT 24 Jun 09 01:27:58 PM PDT 24 1146566800 ps
T369 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1811062137 Jun 09 01:28:02 PM PDT 24 Jun 09 01:43:16 PM PDT 24 770505600 ps
T1164 /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2732907643 Jun 09 01:28:52 PM PDT 24 Jun 09 01:29:05 PM PDT 24 34207700 ps
T321 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.4083085137 Jun 09 01:28:37 PM PDT 24 Jun 09 01:28:54 PM PDT 24 202197500 ps
T1165 /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3999749765 Jun 09 01:28:26 PM PDT 24 Jun 09 01:28:43 PM PDT 24 135834900 ps
T1166 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2501005200 Jun 09 01:28:16 PM PDT 24 Jun 09 01:28:32 PM PDT 24 39255500 ps
T1167 /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3634051392 Jun 09 01:28:53 PM PDT 24 Jun 09 01:29:07 PM PDT 24 41850700 ps
T1168 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1662617598 Jun 09 01:27:48 PM PDT 24 Jun 09 01:28:04 PM PDT 24 24779200 ps
T1169 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2606562925 Jun 09 01:27:26 PM PDT 24 Jun 09 01:27:49 PM PDT 24 218273200 ps
T1170 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2989301396 Jun 09 01:28:38 PM PDT 24 Jun 09 01:28:52 PM PDT 24 28959500 ps
T373 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3262935995 Jun 09 01:28:14 PM PDT 24 Jun 09 01:43:21 PM PDT 24 2844001400 ps
T1171 /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3293902888 Jun 09 01:28:51 PM PDT 24 Jun 09 01:29:04 PM PDT 24 156281800 ps
T1172 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2566607425 Jun 09 01:27:23 PM PDT 24 Jun 09 01:27:37 PM PDT 24 15517600 ps
T1173 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1425062942 Jun 09 01:28:40 PM PDT 24 Jun 09 01:28:54 PM PDT 24 28966400 ps
T287 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2830899186 Jun 09 01:28:11 PM PDT 24 Jun 09 01:28:30 PM PDT 24 93166400 ps
T1174 /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2266783072 Jun 09 01:27:32 PM PDT 24 Jun 09 01:27:46 PM PDT 24 79392500 ps
T1175 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.4195980268 Jun 09 01:28:12 PM PDT 24 Jun 09 01:28:26 PM PDT 24 163054400 ps
T292 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.187328173 Jun 09 01:27:11 PM PDT 24 Jun 09 01:27:31 PM PDT 24 101411400 ps
T1176 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2817923127 Jun 09 01:27:05 PM PDT 24 Jun 09 01:27:32 PM PDT 24 59255500 ps
T285 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.756995575 Jun 09 01:27:22 PM PDT 24 Jun 09 01:27:43 PM PDT 24 393865600 ps
T1177 /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2332514270 Jun 09 01:27:06 PM PDT 24 Jun 09 01:27:19 PM PDT 24 17126700 ps
T1178 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.470025932 Jun 09 01:27:00 PM PDT 24 Jun 09 01:27:35 PM PDT 24 243812800 ps
T1179 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.672372531 Jun 09 01:27:47 PM PDT 24 Jun 09 01:28:01 PM PDT 24 53866000 ps
T1180 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1954809823 Jun 09 01:27:33 PM PDT 24 Jun 09 01:27:47 PM PDT 24 32199200 ps
T286 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.222424879 Jun 09 01:28:22 PM PDT 24 Jun 09 01:28:44 PM PDT 24 434854800 ps
T1181 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.124836924 Jun 09 01:27:26 PM PDT 24 Jun 09 01:27:44 PM PDT 24 188502200 ps
T1182 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1217308669 Jun 09 01:27:36 PM PDT 24 Jun 09 01:27:52 PM PDT 24 15909600 ps
T1183 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2495911604 Jun 09 01:28:50 PM PDT 24 Jun 09 01:29:04 PM PDT 24 17841200 ps
T1184 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3078878675 Jun 09 01:27:12 PM PDT 24 Jun 09 01:27:44 PM PDT 24 687258300 ps
T1185 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2079511434 Jun 09 01:27:27 PM PDT 24 Jun 09 01:27:46 PM PDT 24 197857500 ps
T1186 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3136058706 Jun 09 01:28:18 PM PDT 24 Jun 09 01:28:35 PM PDT 24 311319800 ps
T1187 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.273865061 Jun 09 01:27:23 PM PDT 24 Jun 09 01:28:09 PM PDT 24 154767700 ps
T1188 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1252404605 Jun 09 01:27:17 PM PDT 24 Jun 09 01:27:54 PM PDT 24 337889000 ps
T1189 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2180361759 Jun 09 01:27:27 PM PDT 24 Jun 09 01:27:41 PM PDT 24 17110900 ps
T1190 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2750139879 Jun 09 01:28:18 PM PDT 24 Jun 09 01:28:37 PM PDT 24 445078900 ps
T1191 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1324997258 Jun 09 01:28:01 PM PDT 24 Jun 09 01:28:14 PM PDT 24 55364800 ps
T1192 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2215444600 Jun 09 01:27:54 PM PDT 24 Jun 09 01:28:08 PM PDT 24 69372500 ps
T288 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3473924141 Jun 09 01:27:14 PM PDT 24 Jun 09 01:27:34 PM PDT 24 370837600 ps
T1193 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.913491334 Jun 09 01:27:21 PM PDT 24 Jun 09 01:28:04 PM PDT 24 3479465900 ps
T291 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.264480278 Jun 09 01:28:12 PM PDT 24 Jun 09 01:28:32 PM PDT 24 59472500 ps
T1194 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.944841740 Jun 09 01:28:11 PM PDT 24 Jun 09 01:28:24 PM PDT 24 11339100 ps
T1195 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2314028972 Jun 09 01:28:22 PM PDT 24 Jun 09 01:28:36 PM PDT 24 63136800 ps
T1196 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1451070643 Jun 09 01:28:26 PM PDT 24 Jun 09 01:28:41 PM PDT 24 19372400 ps
T1197 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3799961953 Jun 09 01:28:50 PM PDT 24 Jun 09 01:29:04 PM PDT 24 95994000 ps
T1198 /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3787004865 Jun 09 01:28:51 PM PDT 24 Jun 09 01:29:04 PM PDT 24 58756000 ps
T1199 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1700837140 Jun 09 01:27:32 PM PDT 24 Jun 09 01:27:49 PM PDT 24 84844500 ps
T1200 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1432688461 Jun 09 01:27:05 PM PDT 24 Jun 09 01:27:20 PM PDT 24 37173200 ps
T1201 /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2280482318 Jun 09 01:28:10 PM PDT 24 Jun 09 01:28:24 PM PDT 24 16352800 ps
T1202 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.582898778 Jun 09 01:27:16 PM PDT 24 Jun 09 01:27:32 PM PDT 24 17964700 ps
T1203 /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1360740373 Jun 09 01:27:35 PM PDT 24 Jun 09 01:27:48 PM PDT 24 14732900 ps
T1204 /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3290925934 Jun 09 01:27:30 PM PDT 24 Jun 09 01:27:45 PM PDT 24 572235100 ps
T1205 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2622863324 Jun 09 01:26:59 PM PDT 24 Jun 09 01:27:25 PM PDT 24 221979400 ps
T1206 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1558346594 Jun 09 01:27:55 PM PDT 24 Jun 09 01:28:10 PM PDT 24 39465300 ps
T1207 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1154400714 Jun 09 01:27:55 PM PDT 24 Jun 09 01:28:11 PM PDT 24 114907000 ps
T1208 /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4052820932 Jun 09 01:27:26 PM PDT 24 Jun 09 01:27:42 PM PDT 24 58027300 ps
T263 /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.171002568 Jun 09 01:27:24 PM PDT 24 Jun 09 01:27:37 PM PDT 24 52774200 ps
T1209 /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2386513111 Jun 09 01:28:01 PM PDT 24 Jun 09 01:28:16 PM PDT 24 34752100 ps
T1210 /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4075854571 Jun 09 01:28:17 PM PDT 24 Jun 09 01:28:32 PM PDT 24 44614100 ps
T1211 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3661214980 Jun 09 01:27:00 PM PDT 24 Jun 09 01:28:08 PM PDT 24 650660500 ps
T1212 /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2998977624 Jun 09 01:28:06 PM PDT 24 Jun 09 01:28:22 PM PDT 24 12241200 ps
T289 /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2223822651 Jun 09 01:27:32 PM PDT 24 Jun 09 01:27:50 PM PDT 24 555947700 ps
T1213 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2851391239 Jun 09 01:28:42 PM PDT 24 Jun 09 01:29:18 PM PDT 24 810740900 ps
T1214 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.919506537 Jun 09 01:28:28 PM PDT 24 Jun 09 01:28:43 PM PDT 24 83607200 ps
T1215 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3562444384 Jun 09 01:27:33 PM PDT 24 Jun 09 01:27:51 PM PDT 24 99882500 ps
T1216 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3552636001 Jun 09 01:27:11 PM PDT 24 Jun 09 01:27:28 PM PDT 24 341406800 ps
T1217 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3807628773 Jun 09 01:28:21 PM PDT 24 Jun 09 01:28:35 PM PDT 24 12658500 ps
T1218 /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3484175018 Jun 09 01:28:43 PM PDT 24 Jun 09 01:28:57 PM PDT 24 47238500 ps
T1219 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4021001487 Jun 09 01:28:08 PM PDT 24 Jun 09 01:28:25 PM PDT 24 132271700 ps
T1220 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4277225407 Jun 09 01:28:55 PM PDT 24 Jun 09 01:29:09 PM PDT 24 55259000 ps
T264 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4010637532 Jun 09 01:27:17 PM PDT 24 Jun 09 01:27:30 PM PDT 24 124587100 ps
T1221 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1234411344 Jun 09 01:28:26 PM PDT 24 Jun 09 01:28:46 PM PDT 24 375935000 ps
T374 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2908321353 Jun 09 01:28:26 PM PDT 24 Jun 09 01:34:48 PM PDT 24 1056945100 ps
T1222 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1798987435 Jun 09 01:27:05 PM PDT 24 Jun 09 01:28:14 PM PDT 24 661811800 ps
T370 /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2310005623 Jun 09 01:28:12 PM PDT 24 Jun 09 01:35:57 PM PDT 24 427416900 ps
T1223 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2751576903 Jun 09 01:27:00 PM PDT 24 Jun 09 01:27:50 PM PDT 24 431545500 ps
T1224 /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.239376519 Jun 09 01:28:41 PM PDT 24 Jun 09 01:28:55 PM PDT 24 31246800 ps
T1225 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3774551133 Jun 09 01:27:01 PM PDT 24 Jun 09 01:27:14 PM PDT 24 35805300 ps
T1226 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3823895940 Jun 09 01:28:21 PM PDT 24 Jun 09 01:28:35 PM PDT 24 44972100 ps
T371 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.507158993 Jun 09 01:27:12 PM PDT 24 Jun 09 01:42:29 PM PDT 24 650534400 ps
T1227 /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3162605082 Jun 09 01:28:07 PM PDT 24 Jun 09 01:28:25 PM PDT 24 338400100 ps
T1228 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1848620428 Jun 09 01:28:16 PM PDT 24 Jun 09 01:28:32 PM PDT 24 346609900 ps
T1229 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3150484647 Jun 09 01:27:22 PM PDT 24 Jun 09 01:27:38 PM PDT 24 24898500 ps
T1230 /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2386739957 Jun 09 01:27:06 PM PDT 24 Jun 09 01:27:19 PM PDT 24 16961000 ps
T1231 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2905896173 Jun 09 01:28:00 PM PDT 24 Jun 09 01:28:15 PM PDT 24 39129900 ps
T1232 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.561003304 Jun 09 01:28:13 PM PDT 24 Jun 09 01:28:28 PM PDT 24 58264700 ps
T1233 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.476228676 Jun 09 01:27:38 PM PDT 24 Jun 09 01:27:56 PM PDT 24 229655600 ps
T375 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1667049803 Jun 09 01:28:17 PM PDT 24 Jun 09 01:35:52 PM PDT 24 1064909200 ps
T1234 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3115716496 Jun 09 01:27:33 PM PDT 24 Jun 09 01:27:52 PM PDT 24 426272200 ps
T1235 /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3925540474 Jun 09 01:28:33 PM PDT 24 Jun 09 01:28:47 PM PDT 24 14486300 ps
T1236 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3830066019 Jun 09 01:28:38 PM PDT 24 Jun 09 01:28:52 PM PDT 24 23456000 ps
T1237 /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2646382404 Jun 09 01:27:28 PM PDT 24 Jun 09 01:27:45 PM PDT 24 75232200 ps
T1238 /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.306000058 Jun 09 01:27:21 PM PDT 24 Jun 09 01:27:37 PM PDT 24 40170500 ps
T1239 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.4152657829 Jun 09 01:27:39 PM PDT 24 Jun 09 01:28:13 PM PDT 24 686905000 ps
T372 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.762046463 Jun 09 01:27:54 PM PDT 24 Jun 09 01:42:47 PM PDT 24 1052008900 ps
T1240 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2945202836 Jun 09 01:28:44 PM PDT 24 Jun 09 01:28:57 PM PDT 24 44899200 ps
T1241 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.924992485 Jun 09 01:28:06 PM PDT 24 Jun 09 01:35:45 PM PDT 24 2011698800 ps
T1242 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1129070087 Jun 09 01:27:12 PM PDT 24 Jun 09 01:27:51 PM PDT 24 308487300 ps
T1243 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3445307522 Jun 09 01:27:17 PM PDT 24 Jun 09 01:27:36 PM PDT 24 137662700 ps

Test location /workspace/coverage/default/4.flash_ctrl_rw_derr.1659428434
Short name T5
Test name
Test status
Simulation time 3919155900 ps
CPU time 637.72 seconds
Started Jun 09 02:45:53 PM PDT 24
Finished Jun 09 02:56:31 PM PDT 24
Peak memory 329204 kb
Host smart-9d71e2f4-ffe2-4249-a902-6e020416dd76
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659428434 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_rw_derr.1659428434
Directory /workspace/4.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2472210241
Short name T54
Test name
Test status
Simulation time 789669900 ps
CPU time 457.13 seconds
Started Jun 09 01:27:52 PM PDT 24
Finished Jun 09 01:35:29 PM PDT 24
Peak memory 263736 kb
Host smart-8fa2b905-d688-4aec-9885-1e13d958fca8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472210241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_tl_intg_err.2472210241
Directory /workspace/8.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_rma_reset.1342681656
Short name T17
Test name
Test status
Simulation time 40124590300 ps
CPU time 883.71 seconds
Started Jun 09 02:48:44 PM PDT 24
Finished Jun 09 03:03:28 PM PDT 24
Peak memory 264004 kb
Host smart-af80e7d4-4b66-44a3-bda5-d294c43106f6
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342681656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.flash_ctrl_hw_rma_reset.1342681656
Directory /workspace/9.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_phy_arb.1203505405
Short name T8
Test name
Test status
Simulation time 1467688400 ps
CPU time 527.59 seconds
Started Jun 09 02:49:55 PM PDT 24
Finished Jun 09 02:58:43 PM PDT 24
Peak memory 263432 kb
Host smart-1651bf16-5bbe-46f2-ad10-fd57dc451b87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203505405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.1203505405
Directory /workspace/11.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_mp_regions.2083045992
Short name T95
Test name
Test status
Simulation time 45652735100 ps
CPU time 393.51 seconds
Started Jun 09 02:51:03 PM PDT 24
Finished Jun 09 02:57:37 PM PDT 24
Peak memory 275028 kb
Host smart-d7d7c9da-dac3-4bf1-a1e5-0658a68e397e
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083045992 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_mp_regions.2083045992
Directory /workspace/13.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_cm.1753427005
Short name T18
Test name
Test status
Simulation time 3017776800 ps
CPU time 6359.29 seconds
Started Jun 09 02:45:16 PM PDT 24
Finished Jun 09 04:31:17 PM PDT 24
Peak memory 291140 kb
Host smart-85c5fcca-cba0-4dc6-a1a5-bae2d2eb35aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753427005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.1753427005
Directory /workspace/3.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.flash_ctrl_erase_suspend.1090634997
Short name T65
Test name
Test status
Simulation time 4175801600 ps
CPU time 396.29 seconds
Started Jun 09 02:45:33 PM PDT 24
Finished Jun 09 02:52:09 PM PDT 24
Peak memory 263716 kb
Host smart-9d72b230-561c-4767-ba6a-8b448fd84200
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090634997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.1090634997
Directory /workspace/4.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/13.flash_ctrl_otp_reset.3025849125
Short name T13
Test name
Test status
Simulation time 56390700 ps
CPU time 129.65 seconds
Started Jun 09 02:51:03 PM PDT 24
Finished Jun 09 02:53:13 PM PDT 24
Peak memory 260244 kb
Host smart-400e61e1-f68a-438a-b007-0427c59fdc23
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025849125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o
tp_reset.3025849125
Directory /workspace/13.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_wr_intg.1435106044
Short name T10
Test name
Test status
Simulation time 289089800 ps
CPU time 16.05 seconds
Started Jun 09 02:44:11 PM PDT 24
Finished Jun 09 02:44:27 PM PDT 24
Peak memory 260652 kb
Host smart-1f9631c3-2dee-4bc0-9ca1-96e3509f83c8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435106044 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.1435106044
Directory /workspace/2.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2869666427
Short name T253
Test name
Test status
Simulation time 201636500 ps
CPU time 18.21 seconds
Started Jun 09 01:28:27 PM PDT 24
Finished Jun 09 01:28:46 PM PDT 24
Peak memory 263700 kb
Host smart-96969878-12d7-4626-a469-ff1d1a027d45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869666427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.
2869666427
Directory /workspace/18.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.flash_ctrl_mid_op_rst.3475168226
Short name T122
Test name
Test status
Simulation time 1104644700 ps
CPU time 74.63 seconds
Started Jun 09 02:42:34 PM PDT 24
Finished Jun 09 02:43:49 PM PDT 24
Peak memory 260572 kb
Host smart-8b065025-45e4-4af8-8006-aebc3ad6906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475168226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.3475168226
Directory /workspace/1.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd.2769670707
Short name T38
Test name
Test status
Simulation time 1658415800 ps
CPU time 205.75 seconds
Started Jun 09 02:54:49 PM PDT 24
Finished Jun 09 02:58:15 PM PDT 24
Peak memory 291704 kb
Host smart-02366ec9-6098-43d5-b7d1-92a8fa8c16d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769670707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla
sh_ctrl_intr_rd.2769670707
Directory /workspace/25.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.2744796934
Short name T15
Test name
Test status
Simulation time 15356700 ps
CPU time 13.82 seconds
Started Jun 09 02:43:12 PM PDT 24
Finished Jun 09 02:43:26 PM PDT 24
Peak memory 266060 kb
Host smart-075dc120-69f9-4d21-9f20-34c24d53d8d4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744796934 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.2744796934
Directory /workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_sec_otp.1350771806
Short name T322
Test name
Test status
Simulation time 18197248400 ps
CPU time 146.56 seconds
Started Jun 09 02:47:07 PM PDT 24
Finished Jun 09 02:49:34 PM PDT 24
Peak memory 263464 kb
Host smart-ac44b31b-24ef-4ed9-ae8d-4408b399efab
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350771806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h
w_sec_otp.1350771806
Directory /workspace/6.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/56.flash_ctrl_otp_reset.269356655
Short name T152
Test name
Test status
Simulation time 146678100 ps
CPU time 132.54 seconds
Started Jun 09 02:57:17 PM PDT 24
Finished Jun 09 02:59:31 PM PDT 24
Peak memory 260240 kb
Host smart-940ce3a4-3057-4a4b-bf6a-ede988e38c76
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269356655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_ot
p_reset.269356655
Directory /workspace/56.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_otp_reset.1567556306
Short name T155
Test name
Test status
Simulation time 74640900 ps
CPU time 131.19 seconds
Started Jun 09 02:54:46 PM PDT 24
Finished Jun 09 02:56:57 PM PDT 24
Peak memory 261376 kb
Host smart-a2659945-e00c-4538-afaf-d4aee7797955
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567556306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o
tp_reset.1567556306
Directory /workspace/25.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.1474173009
Short name T3
Test name
Test status
Simulation time 10012241800 ps
CPU time 108.43 seconds
Started Jun 09 02:51:18 PM PDT 24
Finished Jun 09 02:53:07 PM PDT 24
Peak memory 297996 kb
Host smart-2634bbfc-32a8-4159-97b4-02a40d665866
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474173009 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.1474173009
Directory /workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_otp_reset.4041722044
Short name T145
Test name
Test status
Simulation time 69785500 ps
CPU time 131.95 seconds
Started Jun 09 02:51:24 PM PDT 24
Finished Jun 09 02:53:36 PM PDT 24
Peak memory 265320 kb
Host smart-eafd27a3-8ca1-4d22-b4fd-ec8655b2239e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041722044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o
tp_reset.4041722044
Directory /workspace/14.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.1470821397
Short name T342
Test name
Test status
Simulation time 15354900 ps
CPU time 13.32 seconds
Started Jun 09 01:26:58 PM PDT 24
Finished Jun 09 01:27:12 PM PDT 24
Peak memory 261056 kb
Host smart-c299313a-75b3-49fc-b09c-51758eab9ba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470821397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.1
470821397
Directory /workspace/0.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.504028540
Short name T260
Test name
Test status
Simulation time 3312617000 ps
CPU time 903.65 seconds
Started Jun 09 01:28:02 PM PDT 24
Finished Jun 09 01:43:06 PM PDT 24
Peak memory 263752 kb
Host smart-3d3d267f-ae85-4f54-9dcd-40b81fe5b176
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504028540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl
_tl_intg_err.504028540
Directory /workspace/10.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_derr_detect.3871142363
Short name T52
Test name
Test status
Simulation time 367882200 ps
CPU time 108.29 seconds
Started Jun 09 02:42:56 PM PDT 24
Finished Jun 09 02:44:45 PM PDT 24
Peak memory 280192 kb
Host smart-8141f389-a581-49b8-86fa-4521ad842324
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871142363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_derr_detect.3871142363
Directory /workspace/1.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_rma_err.3164947151
Short name T70
Test name
Test status
Simulation time 42014448400 ps
CPU time 899.35 seconds
Started Jun 09 02:42:09 PM PDT 24
Finished Jun 09 02:57:09 PM PDT 24
Peak memory 261456 kb
Host smart-d7bcdf52-d64c-4587-9492-13170a928130
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164947151 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.3164947151
Directory /workspace/0.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1963476495
Short name T136
Test name
Test status
Simulation time 10012052700 ps
CPU time 326.98 seconds
Started Jun 09 02:51:51 PM PDT 24
Finished Jun 09 02:57:18 PM PDT 24
Peak memory 311104 kb
Host smart-c635aef3-49d1-494a-a8fa-4bce533e4485
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963476495 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1963476495
Directory /workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/39.flash_ctrl_alert_test.3512092446
Short name T20
Test name
Test status
Simulation time 49068200 ps
CPU time 13.42 seconds
Started Jun 09 02:56:34 PM PDT 24
Finished Jun 09 02:56:48 PM PDT 24
Peak memory 258576 kb
Host smart-e88746bb-bf70-4b2b-8c56-7926ea553358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512092446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.
3512092446
Directory /workspace/39.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_info_access.909562929
Short name T233
Test name
Test status
Simulation time 703586200 ps
CPU time 54.97 seconds
Started Jun 09 02:43:00 PM PDT 24
Finished Jun 09 02:43:55 PM PDT 24
Peak memory 264904 kb
Host smart-f18da667-35da-4ee1-8daf-167591fa5431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909562929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.909562929
Directory /workspace/1.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_fetch_code.624777073
Short name T46
Test name
Test status
Simulation time 1237540700 ps
CPU time 31.22 seconds
Started Jun 09 02:47:37 PM PDT 24
Finished Jun 09 02:48:08 PM PDT 24
Peak memory 262724 kb
Host smart-bd9a67e2-4aee-45c1-b33a-4bf25210fd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624777073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.624777073
Directory /workspace/7.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.3381702789
Short name T157
Test name
Test status
Simulation time 611068288000 ps
CPU time 2286.5 seconds
Started Jun 09 02:41:18 PM PDT 24
Finished Jun 09 03:19:25 PM PDT 24
Peak memory 264520 kb
Host smart-904eeaf1-3d28-4625-ba01-71dc425d98b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381702789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 0.flash_ctrl_host_ctrl_arb.3381702789
Directory /workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.4180159769
Short name T133
Test name
Test status
Simulation time 45827100 ps
CPU time 13.74 seconds
Started Jun 09 02:42:10 PM PDT 24
Finished Jun 09 02:42:24 PM PDT 24
Peak memory 258868 kb
Host smart-880d6915-9c01-4f4c-b676-4e2ab126e45f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180159769 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.4180159769
Directory /workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_re_evict.2078187327
Short name T355
Test name
Test status
Simulation time 81120200 ps
CPU time 34.06 seconds
Started Jun 09 02:48:30 PM PDT 24
Finished Jun 09 02:49:05 PM PDT 24
Peak memory 275812 kb
Host smart-10a644b8-ae4c-4ac3-a8f6-8e403eebb85b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078187327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla
sh_ctrl_re_evict.2078187327
Directory /workspace/8.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_mid_op_rst.2501811308
Short name T123
Test name
Test status
Simulation time 2476501200 ps
CPU time 78.3 seconds
Started Jun 09 02:43:41 PM PDT 24
Finished Jun 09 02:44:59 PM PDT 24
Peak memory 260744 kb
Host smart-c0514864-6cc1-4183-9bc1-f47f4cb69c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501811308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.2501811308
Directory /workspace/2.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_stress_all.2593398711
Short name T326
Test name
Test status
Simulation time 527913500 ps
CPU time 1124.9 seconds
Started Jun 09 02:45:14 PM PDT 24
Finished Jun 09 03:03:59 PM PDT 24
Peak memory 286980 kb
Host smart-381ad347-9cda-4bb4-991a-b8b887969d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593398711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres
s_all.2593398711
Directory /workspace/3.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.flash_ctrl_invalid_op.4066947211
Short name T79
Test name
Test status
Simulation time 6781519700 ps
CPU time 77.52 seconds
Started Jun 09 02:50:03 PM PDT 24
Finished Jun 09 02:51:20 PM PDT 24
Peak memory 260844 kb
Host smart-b1a008ec-fe5c-4377-bdbc-8950885bb472
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066947211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.4
066947211
Directory /workspace/11.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb_redun.2376534261
Short name T9
Test name
Test status
Simulation time 675613200 ps
CPU time 19.02 seconds
Started Jun 09 02:44:09 PM PDT 24
Finished Jun 09 02:44:28 PM PDT 24
Peak memory 266004 kb
Host smart-b0b5bd66-b420-4d08-941d-4d36ac38c361
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376534261 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.2376534261
Directory /workspace/2.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2830899186
Short name T287
Test name
Test status
Simulation time 93166400 ps
CPU time 18.26 seconds
Started Jun 09 01:28:11 PM PDT 24
Finished Jun 09 01:28:30 PM PDT 24
Peak memory 263744 kb
Host smart-953c0d74-7cf9-46a6-a787-d6f8f1185057
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830899186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.
2830899186
Directory /workspace/14.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.2684307362
Short name T39
Test name
Test status
Simulation time 11939965900 ps
CPU time 294.5 seconds
Started Jun 09 02:56:14 PM PDT 24
Finished Jun 09 03:01:09 PM PDT 24
Peak memory 291988 kb
Host smart-cc9c2344-46ee-43a8-8a7f-5d290fd634ab
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684307362 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.2684307362
Directory /workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd.3075289420
Short name T347
Test name
Test status
Simulation time 6333240900 ps
CPU time 167.18 seconds
Started Jun 09 02:50:41 PM PDT 24
Finished Jun 09 02:53:28 PM PDT 24
Peak memory 294472 kb
Host smart-4c773277-e5b0-4249-a880-7f3af423b569
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075289420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_intr_rd.3075289420
Directory /workspace/12.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.3727084593
Short name T143
Test name
Test status
Simulation time 25966700 ps
CPU time 13.79 seconds
Started Jun 09 02:42:09 PM PDT 24
Finished Jun 09 02:42:23 PM PDT 24
Peak memory 260232 kb
Host smart-ec1293be-f855-4407-ada2-07b280267b4b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727084593 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.3727084593
Directory /workspace/0.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1906537620
Short name T262
Test name
Test status
Simulation time 71298200 ps
CPU time 13.29 seconds
Started Jun 09 01:27:12 PM PDT 24
Finished Jun 09 01:27:26 PM PDT 24
Peak memory 262088 kb
Host smart-460b114a-ddcb-44cb-a134-aa0271dd43b3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906537620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fla
sh_ctrl_mem_partial_access.1906537620
Directory /workspace/2.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2777479296
Short name T283
Test name
Test status
Simulation time 18532200 ps
CPU time 13.44 seconds
Started Jun 09 01:28:41 PM PDT 24
Finished Jun 09 01:28:55 PM PDT 24
Peak memory 261136 kb
Host smart-a342301a-d8f1-4438-9fbd-7f4f0c243324
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777479296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.
2777479296
Directory /workspace/23.flash_ctrl_intr_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw.3872117078
Short name T191
Test name
Test status
Simulation time 7187489900 ps
CPU time 567.37 seconds
Started Jun 09 02:46:33 PM PDT 24
Finished Jun 09 02:56:01 PM PDT 24
Peak memory 314980 kb
Host smart-8737f3cb-3dae-4b72-b69e-21d872a68b7c
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872117078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.flash_ctrl_rw.3872117078
Directory /workspace/5.flash_ctrl_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.791088724
Short name T297
Test name
Test status
Simulation time 3299202000 ps
CPU time 754.51 seconds
Started Jun 09 01:28:24 PM PDT 24
Finished Jun 09 01:40:59 PM PDT 24
Peak memory 263696 kb
Host smart-619751f5-49ec-4ef7-b757-a343e36b5d26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791088724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl
_tl_intg_err.791088724
Directory /workspace/16.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_oversize_error.1437767642
Short name T196
Test name
Test status
Simulation time 2742396100 ps
CPU time 220.39 seconds
Started Jun 09 02:45:06 PM PDT 24
Finished Jun 09 02:48:47 PM PDT 24
Peak memory 282268 kb
Host smart-ef6251f4-f8a9-4f91-b11a-ef36cb5ae2ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437767642 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.1437767642
Directory /workspace/3.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.109043483
Short name T158
Test name
Test status
Simulation time 10033429100 ps
CPU time 62.05 seconds
Started Jun 09 02:50:55 PM PDT 24
Finished Jun 09 02:51:57 PM PDT 24
Peak memory 293488 kb
Host smart-6e0f3b3f-4c33-4268-988c-87dbeb770ca1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109043483 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.109043483
Directory /workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.762046463
Short name T372
Test name
Test status
Simulation time 1052008900 ps
CPU time 892.34 seconds
Started Jun 09 01:27:54 PM PDT 24
Finished Jun 09 01:42:47 PM PDT 24
Peak memory 263728 kb
Host smart-5fe6eb6e-6fa1-41a2-9916-655db34d401c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762046463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_
tl_intg_err.762046463
Directory /workspace/9.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd.2564674613
Short name T36
Test name
Test status
Simulation time 2966085500 ps
CPU time 146.41 seconds
Started Jun 09 02:56:21 PM PDT 24
Finished Jun 09 02:58:48 PM PDT 24
Peak memory 294440 kb
Host smart-7e3706e1-4f21-4232-8d92-890b3235c4f0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564674613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla
sh_ctrl_intr_rd.2564674613
Directory /workspace/38.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.1446425102
Short name T354
Test name
Test status
Simulation time 42476700 ps
CPU time 30.55 seconds
Started Jun 09 02:55:01 PM PDT 24
Finished Jun 09 02:55:32 PM PDT 24
Peak memory 274044 kb
Host smart-9a1e6393-52bc-4eb1-9eca-0a342319ae05
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446425102 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.1446425102
Directory /workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_otp_reset.716661767
Short name T19
Test name
Test status
Simulation time 337173100 ps
CPU time 111.32 seconds
Started Jun 09 02:55:44 PM PDT 24
Finished Jun 09 02:57:35 PM PDT 24
Peak memory 261236 kb
Host smart-6261ed45-3f59-4425-87b3-947026e24000
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716661767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ot
p_reset.716661767
Directory /workspace/32.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb_redun.1741384897
Short name T74
Test name
Test status
Simulation time 728029000 ps
CPU time 21.56 seconds
Started Jun 09 02:46:09 PM PDT 24
Finished Jun 09 02:46:31 PM PDT 24
Peak memory 264504 kb
Host smart-ac5c2349-c58b-4a09-a9b3-147276110d60
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741384897 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.1741384897
Directory /workspace/4.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2224883035
Short name T254
Test name
Test status
Simulation time 55510000 ps
CPU time 18.02 seconds
Started Jun 09 01:27:54 PM PDT 24
Finished Jun 09 01:28:12 PM PDT 24
Peak memory 277164 kb
Host smart-11ccae6f-01a0-46e5-a730-b5e636549e09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224883035 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.2224883035
Directory /workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_re_evict.2525837373
Short name T356
Test name
Test status
Simulation time 74656600 ps
CPU time 36.38 seconds
Started Jun 09 02:50:10 PM PDT 24
Finished Jun 09 02:50:46 PM PDT 24
Peak memory 276108 kb
Host smart-f0901c89-1c90-4c81-a196-36119bf268f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525837373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_re_evict.2525837373
Directory /workspace/11.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.3663821448
Short name T45
Test name
Test status
Simulation time 16518400 ps
CPU time 14.24 seconds
Started Jun 09 02:42:02 PM PDT 24
Finished Jun 09 02:42:17 PM PDT 24
Peak memory 277436 kb
Host smart-a1ca8766-ecf5-4a08-937c-4e3dac012aff
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3663821448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.3663821448
Directory /workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_derr.1212027004
Short name T432
Test name
Test status
Simulation time 934073400 ps
CPU time 179.58 seconds
Started Jun 09 02:42:50 PM PDT 24
Finished Jun 09 02:45:49 PM PDT 24
Peak memory 282272 kb
Host smart-1f531c91-2738-4408-9c9c-6ebd8f4d3660
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
1212027004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.1212027004
Directory /workspace/1.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_dir_rd.2460105147
Short name T121
Test name
Test status
Simulation time 40872700 ps
CPU time 57.33 seconds
Started Jun 09 02:45:29 PM PDT 24
Finished Jun 09 02:46:27 PM PDT 24
Peak memory 265644 kb
Host smart-586fb58d-64bf-4aae-85ae-1e7d05e2a77d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460105147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.2460105147
Directory /workspace/4.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_connect.4252965104
Short name T214
Test name
Test status
Simulation time 51995400 ps
CPU time 13.33 seconds
Started Jun 09 02:47:54 PM PDT 24
Finished Jun 09 02:48:08 PM PDT 24
Peak memory 275060 kb
Host smart-6d57a32c-4798-4554-9093-64860b39ab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252965104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.4252965104
Directory /workspace/7.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_disable.3304154945
Short name T380
Test name
Test status
Simulation time 12181000 ps
CPU time 21.64 seconds
Started Jun 09 02:54:32 PM PDT 24
Finished Jun 09 02:54:54 PM PDT 24
Peak memory 274068 kb
Host smart-4cb49351-bb6b-4f72-81da-3190c1ad33c3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304154945 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_disable.3304154945
Directory /workspace/23.flash_ctrl_disable/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4010637532
Short name T264
Test name
Test status
Simulation time 124587100 ps
CPU time 13.38 seconds
Started Jun 09 01:27:17 PM PDT 24
Finished Jun 09 01:27:30 PM PDT 24
Peak memory 262976 kb
Host smart-bae8d80b-49b6-42fa-9e6c-ae10a07a2ced
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010637532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_mem_partial_access.4010637532
Directory /workspace/3.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_lcmgr_intg.3260138646
Short name T517
Test name
Test status
Simulation time 15224700 ps
CPU time 13.45 seconds
Started Jun 09 02:44:26 PM PDT 24
Finished Jun 09 02:44:39 PM PDT 24
Peak memory 260120 kb
Host smart-397a7903-51a9-4d4e-bae4-93c2b604b4f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260138646 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.3260138646
Directory /workspace/2.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3473924141
Short name T288
Test name
Test status
Simulation time 370837600 ps
CPU time 19.44 seconds
Started Jun 09 01:27:14 PM PDT 24
Finished Jun 09 01:27:34 PM PDT 24
Peak memory 263752 kb
Host smart-80801dfc-1536-4926-94e8-cbfe1b918690
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473924141 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.3
473924141
Directory /workspace/3.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.3061624594
Short name T365
Test name
Test status
Simulation time 46857200 ps
CPU time 13.66 seconds
Started Jun 09 02:49:48 PM PDT 24
Finished Jun 09 02:50:02 PM PDT 24
Peak memory 259776 kb
Host smart-ecc37b4c-16b7-45ac-80a8-f82278ecf639
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061624594 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.3061624594
Directory /workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_type.856818481
Short name T169
Test name
Test status
Simulation time 385124500 ps
CPU time 2403.31 seconds
Started Jun 09 02:41:16 PM PDT 24
Finished Jun 09 03:21:20 PM PDT 24
Peak memory 265084 kb
Host smart-0411760c-0611-40b9-85b1-a666d6113a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856818481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_type.856818481
Directory /workspace/0.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.840441991
Short name T63
Test name
Test status
Simulation time 835299700 ps
CPU time 20.76 seconds
Started Jun 09 02:42:05 PM PDT 24
Finished Jun 09 02:42:26 PM PDT 24
Peak memory 264484 kb
Host smart-9cd782cc-ca89-4922-9015-bfd4fb51ee32
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840441991 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.840441991
Directory /workspace/0.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/2.flash_ctrl_access_after_disable.1792381090
Short name T59
Test name
Test status
Simulation time 14149600 ps
CPU time 14.08 seconds
Started Jun 09 02:44:10 PM PDT 24
Finished Jun 09 02:44:25 PM PDT 24
Peak memory 265800 kb
Host smart-78c61f47-d1c2-45e5-9790-85cb4be8071d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792381090 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.1792381090
Directory /workspace/2.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_derr.613512283
Short name T173
Test name
Test status
Simulation time 1221338700 ps
CPU time 135 seconds
Started Jun 09 02:45:03 PM PDT 24
Finished Jun 09 02:47:19 PM PDT 24
Peak memory 282280 kb
Host smart-b1905743-c8a0-4e4f-911c-135d41b54662
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
613512283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.613512283
Directory /workspace/3.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_prog_win.44203748
Short name T743
Test name
Test status
Simulation time 1782896200 ps
CPU time 890.62 seconds
Started Jun 09 02:41:23 PM PDT 24
Finished Jun 09 02:56:13 PM PDT 24
Peak memory 273252 kb
Host smart-01092cd9-8780-483c-8a3e-f2feb57b00e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44203748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.44203748
Directory /workspace/0.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.2901765013
Short name T16
Test name
Test status
Simulation time 24392700 ps
CPU time 14 seconds
Started Jun 09 02:45:15 PM PDT 24
Finished Jun 09 02:45:29 PM PDT 24
Peak memory 262808 kb
Host smart-03602a18-6796-4de2-b944-5389100e6aa2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901765013 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.2901765013
Directory /workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_fs_sup.1260991624
Short name T190
Test name
Test status
Simulation time 324335000 ps
CPU time 41.25 seconds
Started Jun 09 02:42:04 PM PDT 24
Finished Jun 09 02:42:46 PM PDT 24
Peak memory 263192 kb
Host smart-d933f2db-5291-4304-aec2-352c78a1157b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260991624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_fs_sup.1260991624
Directory /workspace/0.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.406097669
Short name T188
Test name
Test status
Simulation time 24520600 ps
CPU time 14.12 seconds
Started Jun 09 02:44:12 PM PDT 24
Finished Jun 09 02:44:26 PM PDT 24
Peak memory 265952 kb
Host smart-7331c3c3-8400-406e-af79-71360d980375
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406097669 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.406097669
Directory /workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.2084473450
Short name T794
Test name
Test status
Simulation time 26594300 ps
CPU time 13.37 seconds
Started Jun 09 02:43:13 PM PDT 24
Finished Jun 09 02:43:27 PM PDT 24
Peak memory 265856 kb
Host smart-aceb303b-e2b7-4c6b-96b7-07586da97f67
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084473450 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.2084473450
Directory /workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.4229747683
Short name T290
Test name
Test status
Simulation time 185636400 ps
CPU time 452.41 seconds
Started Jun 09 01:27:30 PM PDT 24
Finished Jun 09 01:35:03 PM PDT 24
Peak memory 263692 kb
Host smart-3e9647ee-23a1-44e1-9ace-05d613795e3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229747683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl
_tl_intg_err.4229747683
Directory /workspace/5.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw.2323408798
Short name T362
Test name
Test status
Simulation time 4142324700 ps
CPU time 609.49 seconds
Started Jun 09 02:41:22 PM PDT 24
Finished Jun 09 02:51:32 PM PDT 24
Peak memory 314580 kb
Host smart-2af7d664-744e-4525-9c37-23faab64ffc2
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323408798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.flash_ctrl_rw.2323408798
Directory /workspace/0.flash_ctrl_rw/latest

Test location /workspace/coverage/default/0.flash_ctrl_sec_info_access.2829783305
Short name T232
Test name
Test status
Simulation time 2232435100 ps
CPU time 57.67 seconds
Started Jun 09 02:41:49 PM PDT 24
Finished Jun 09 02:42:47 PM PDT 24
Peak memory 265036 kb
Host smart-3f2cb3a8-0f5a-4ba4-a60d-58c1ba165247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829783305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.2829783305
Directory /workspace/0.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd.1302063122
Short name T303
Test name
Test status
Simulation time 4238410500 ps
CPU time 162.58 seconds
Started Jun 09 02:51:12 PM PDT 24
Finished Jun 09 02:53:55 PM PDT 24
Peak memory 294136 kb
Host smart-83a891a0-aa6a-4624-bdad-a6002438818d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302063122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_intr_rd.1302063122
Directory /workspace/13.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/13.flash_ctrl_invalid_op.978035433
Short name T437
Test name
Test status
Simulation time 6762423000 ps
CPU time 72.15 seconds
Started Jun 09 02:51:06 PM PDT 24
Finished Jun 09 02:52:18 PM PDT 24
Peak memory 261036 kb
Host smart-0b32a1aa-644c-41ff-8f1b-bbc83172405e
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978035433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.978035433
Directory /workspace/13.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.2179469201
Short name T359
Test name
Test status
Simulation time 134143600 ps
CPU time 31.24 seconds
Started Jun 09 02:56:18 PM PDT 24
Finished Jun 09 02:56:49 PM PDT 24
Peak memory 276036 kb
Host smart-64166cf0-c52d-4e42-a0d2-b2707588d3de
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179469201 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.2179469201
Directory /workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_sec_info_access.316482977
Short name T422
Test name
Test status
Simulation time 8348870700 ps
CPU time 77.81 seconds
Started Jun 09 02:56:34 PM PDT 24
Finished Jun 09 02:57:52 PM PDT 24
Peak memory 259892 kb
Host smart-e716edda-9dff-4ece-90db-1e648ca3c58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316482977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.316482977
Directory /workspace/39.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/42.flash_ctrl_sec_info_access.832078604
Short name T415
Test name
Test status
Simulation time 6840391400 ps
CPU time 72.18 seconds
Started Jun 09 02:56:45 PM PDT 24
Finished Jun 09 02:57:57 PM PDT 24
Peak memory 259724 kb
Host smart-6465fb60-b2cb-4eed-8813-780a9fa44e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832078604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.832078604
Directory /workspace/42.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_smoke.1105068868
Short name T210
Test name
Test status
Simulation time 35142100 ps
CPU time 76.24 seconds
Started Jun 09 02:47:31 PM PDT 24
Finished Jun 09 02:48:48 PM PDT 24
Peak memory 277004 kb
Host smart-8a2b6dcd-6103-40cf-8453-af47b8729ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105068868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.1105068868
Directory /workspace/7.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw.541329520
Short name T89
Test name
Test status
Simulation time 4495604100 ps
CPU time 623.73 seconds
Started Jun 09 02:44:54 PM PDT 24
Finished Jun 09 02:55:18 PM PDT 24
Peak memory 309612 kb
Host smart-e26ab886-66d3-4ce4-ba57-b5e0c1f96cb1
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541329520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.flash_ctrl_rw.541329520
Directory /workspace/3.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_disable.1605442086
Short name T385
Test name
Test status
Simulation time 16361300 ps
CPU time 20.54 seconds
Started Jun 09 02:50:44 PM PDT 24
Finished Jun 09 02:51:05 PM PDT 24
Peak memory 274084 kb
Host smart-98293b95-e739-45fd-acb1-33826a5ea908
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605442086 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_disable.1605442086
Directory /workspace/12.flash_ctrl_disable/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.206764289
Short name T258
Test name
Test status
Simulation time 51727900 ps
CPU time 18.3 seconds
Started Jun 09 01:28:24 PM PDT 24
Finished Jun 09 01:28:42 PM PDT 24
Peak memory 263756 kb
Host smart-e6b8bb17-622a-4714-b912-1fc224ac140d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206764289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.206764289
Directory /workspace/17.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.4223019915
Short name T225
Test name
Test status
Simulation time 284448900 ps
CPU time 17.25 seconds
Started Jun 09 01:27:59 PM PDT 24
Finished Jun 09 01:28:17 PM PDT 24
Peak memory 263728 kb
Host smart-7d378edb-3c2f-445a-b54f-b15159ef6ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223019915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.
4223019915
Directory /workspace/10.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_config_regwen.27942533
Short name T377
Test name
Test status
Simulation time 40460200 ps
CPU time 13.64 seconds
Started Jun 09 02:42:08 PM PDT 24
Finished Jun 09 02:42:22 PM PDT 24
Peak memory 261616 kb
Host smart-283881b5-5e8b-4051-9f49-b20007cc8921
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27942533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=
flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.f
lash_ctrl_config_regwen.27942533
Directory /workspace/0.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.flash_ctrl_disable.2129584662
Short name T826
Test name
Test status
Simulation time 25157500 ps
CPU time 21.79 seconds
Started Jun 09 02:41:49 PM PDT 24
Finished Jun 09 02:42:11 PM PDT 24
Peak memory 274036 kb
Host smart-8239b267-605c-4c5f-be92-981e9cc698fd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129584662 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_disable.2129584662
Directory /workspace/0.flash_ctrl_disable/latest

Test location /workspace/coverage/default/10.flash_ctrl_disable.2100651480
Short name T240
Test name
Test status
Simulation time 16219900 ps
CPU time 21.18 seconds
Started Jun 09 02:49:34 PM PDT 24
Finished Jun 09 02:49:55 PM PDT 24
Peak memory 273916 kb
Host smart-08f8abb1-4599-40ad-bf1a-444d877956bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100651480 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.flash_ctrl_disable.2100651480
Directory /workspace/10.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_disable.3767924813
Short name T1048
Test name
Test status
Simulation time 56199600 ps
CPU time 21.57 seconds
Started Jun 09 02:50:12 PM PDT 24
Finished Jun 09 02:50:34 PM PDT 24
Peak memory 265696 kb
Host smart-ba3e9373-ac5c-487a-b211-001cb58e499c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767924813 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_disable.3767924813
Directory /workspace/11.flash_ctrl_disable/latest

Test location /workspace/coverage/default/11.flash_ctrl_otp_reset.3525580962
Short name T635
Test name
Test status
Simulation time 46921900 ps
CPU time 107.89 seconds
Started Jun 09 02:49:59 PM PDT 24
Finished Jun 09 02:51:47 PM PDT 24
Peak memory 260272 kb
Host smart-875770af-1471-4f0b-8e49-35490b756798
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525580962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o
tp_reset.3525580962
Directory /workspace/11.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_sec_info_access.3027212454
Short name T223
Test name
Test status
Simulation time 26655232600 ps
CPU time 70.67 seconds
Started Jun 09 02:51:42 PM PDT 24
Finished Jun 09 02:52:53 PM PDT 24
Peak memory 259896 kb
Host smart-6968ddf0-7312-4d20-878a-02730ac3bad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027212454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.3027212454
Directory /workspace/14.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/18.flash_ctrl_sec_info_access.1582563011
Short name T413
Test name
Test status
Simulation time 410493200 ps
CPU time 60.26 seconds
Started Jun 09 02:53:24 PM PDT 24
Finished Jun 09 02:54:24 PM PDT 24
Peak memory 264380 kb
Host smart-1653d28c-18de-47d4-a27a-6ef88cd10905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582563011 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.1582563011
Directory /workspace/18.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_disable.4116146278
Short name T566
Test name
Test status
Simulation time 23542200 ps
CPU time 22.71 seconds
Started Jun 09 02:53:41 PM PDT 24
Finished Jun 09 02:54:04 PM PDT 24
Peak memory 273980 kb
Host smart-2460a681-beeb-4889-bbb2-4c5de2c5f47f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116146278 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_disable.4116146278
Directory /workspace/19.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_sec_info_access.3147352423
Short name T423
Test name
Test status
Simulation time 2261078000 ps
CPU time 75.35 seconds
Started Jun 09 02:44:04 PM PDT 24
Finished Jun 09 02:45:19 PM PDT 24
Peak memory 264936 kb
Host smart-bd747e0c-0c63-49b6-a4c4-69a99af21f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147352423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.3147352423
Directory /workspace/2.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_disable.2443423924
Short name T164
Test name
Test status
Simulation time 12550300 ps
CPU time 20.49 seconds
Started Jun 09 02:53:57 PM PDT 24
Finished Jun 09 02:54:17 PM PDT 24
Peak memory 265776 kb
Host smart-61994996-184c-4649-b122-c56359dfbaa9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443423924 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_disable.2443423924
Directory /workspace/20.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_sec_info_access.837491024
Short name T420
Test name
Test status
Simulation time 580049800 ps
CPU time 65.64 seconds
Started Jun 09 02:56:53 PM PDT 24
Finished Jun 09 02:57:58 PM PDT 24
Peak memory 263928 kb
Host smart-d7600914-fe34-418e-9148-ae4f5c40053d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837491024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.837491024
Directory /workspace/45.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.1724579808
Short name T503
Test name
Test status
Simulation time 27799430000 ps
CPU time 212.35 seconds
Started Jun 09 02:41:43 PM PDT 24
Finished Jun 09 02:45:16 PM PDT 24
Peak memory 260020 kb
Host smart-87cb3964-19f7-4f75-904a-1c93938dfd10
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172
4579808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.1724579808
Directory /workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_rma_reset.1563021729
Short name T147
Test name
Test status
Simulation time 40127772800 ps
CPU time 889.31 seconds
Started Jun 09 02:49:58 PM PDT 24
Finished Jun 09 03:04:47 PM PDT 24
Peak memory 264540 kb
Host smart-ffe9d161-9535-4862-b9f6-734e6c02afd7
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563021729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 11.flash_ctrl_hw_rma_reset.1563021729
Directory /workspace/11.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_derr.1836464414
Short name T172
Test name
Test status
Simulation time 15912440800 ps
CPU time 666.18 seconds
Started Jun 09 02:45:06 PM PDT 24
Finished Jun 09 02:56:13 PM PDT 24
Peak memory 338328 kb
Host smart-96babeb7-5215-431a-a6d9-dfb4d0fe0177
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836464414 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_rw_derr.1836464414
Directory /workspace/3.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2323036167
Short name T280
Test name
Test status
Simulation time 118369700 ps
CPU time 19.35 seconds
Started Jun 09 01:27:01 PM PDT 24
Finished Jun 09 01:27:21 PM PDT 24
Peak memory 263128 kb
Host smart-df1e47bf-9102-44b2-b604-1058be78096a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323036167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.2
323036167
Directory /workspace/0.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_access_after_disable.2509745398
Short name T23
Test name
Test status
Simulation time 14701200 ps
CPU time 13.51 seconds
Started Jun 09 02:41:58 PM PDT 24
Finished Jun 09 02:42:12 PM PDT 24
Peak memory 265820 kb
Host smart-6a673123-a281-4041-8d5a-52c650b167a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509745398 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.2509745398
Directory /workspace/0.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_derr.3418541402
Short name T278
Test name
Test status
Simulation time 2174492900 ps
CPU time 147.8 seconds
Started Jun 09 02:41:31 PM PDT 24
Finished Jun 09 02:43:59 PM PDT 24
Peak memory 282248 kb
Host smart-6a050e7c-03fd-40ea-ad59-fcbe55d39b74
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3418541402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.3418541402
Directory /workspace/0.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.126987056
Short name T203
Test name
Test status
Simulation time 26275766300 ps
CPU time 281.97 seconds
Started Jun 09 02:42:55 PM PDT 24
Finished Jun 09 02:47:37 PM PDT 24
Peak memory 293416 kb
Host smart-6c6a8108-9d13-4c31-b079-ef9c2a430e33
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126987056 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.126987056
Directory /workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.3670777462
Short name T246
Test name
Test status
Simulation time 28549000 ps
CPU time 13.61 seconds
Started Jun 09 02:43:11 PM PDT 24
Finished Jun 09 02:43:25 PM PDT 24
Peak memory 261556 kb
Host smart-9645c19a-eff6-45f7-b2fa-f4597b713e77
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3670777462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.3670777462
Directory /workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_rand_ops.2530883787
Short name T83
Test name
Test status
Simulation time 5938139900 ps
CPU time 1111.78 seconds
Started Jun 09 02:44:28 PM PDT 24
Finished Jun 09 03:03:00 PM PDT 24
Peak memory 289064 kb
Host smart-a9b1526d-9f56-4985-b0b0-599a082678ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530883787 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.2530883787
Directory /workspace/3.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_error_mp.56753255
Short name T21
Test name
Test status
Simulation time 9759113500 ps
CPU time 2143.64 seconds
Started Jun 09 02:41:23 PM PDT 24
Finished Jun 09 03:17:07 PM PDT 24
Peak memory 264688 kb
Host smart-3273530d-343a-4453-a9d7-ba25218df554
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56753255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error
_mp.56753255
Directory /workspace/0.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.922209527
Short name T181
Test name
Test status
Simulation time 563178184700 ps
CPU time 2648.26 seconds
Started Jun 09 02:42:30 PM PDT 24
Finished Jun 09 03:26:39 PM PDT 24
Peak memory 264160 kb
Host smart-b0590b6f-9d4b-4889-bd29-139bbbea5e45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922209527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.flash_ctrl_host_ctrl_arb.922209527
Directory /workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb_redun.2269910401
Short name T234
Test name
Test status
Simulation time 988439300 ps
CPU time 16.84 seconds
Started Jun 09 02:43:10 PM PDT 24
Finished Jun 09 02:43:27 PM PDT 24
Peak memory 263516 kb
Host smart-8f85837d-49b0-4c74-bb5a-095cd1b3aaef
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269910401 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.2269910401
Directory /workspace/1.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/1.flash_ctrl_wr_intg.4072739987
Short name T12
Test name
Test status
Simulation time 264521300 ps
CPU time 15.15 seconds
Started Jun 09 02:43:06 PM PDT 24
Finished Jun 09 02:43:21 PM PDT 24
Peak memory 265064 kb
Host smart-1c9016e4-ba9c-428a-83b9-0129112563a4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072739987 -assert nopostproc +UV
M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.4072739987
Directory /workspace/1.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.1474119571
Short name T183
Test name
Test status
Simulation time 969306961800 ps
CPU time 2275.26 seconds
Started Jun 09 02:44:44 PM PDT 24
Finished Jun 09 03:22:39 PM PDT 24
Peak memory 264252 kb
Host smart-e024d786-9160-4da1-8c08-0b5039110705
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474119571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_host_ctrl_arb.1474119571
Directory /workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_integrity.2836116624
Short name T185
Test name
Test status
Simulation time 14208007200 ps
CPU time 598.6 seconds
Started Jun 09 02:46:00 PM PDT 24
Finished Jun 09 02:55:59 PM PDT 24
Peak memory 334060 kb
Host smart-093a3c93-01dd-43d0-8e6a-af616df82e7d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836116624 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_integrity.2836116624
Directory /workspace/4.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/45.flash_ctrl_otp_reset.3860999887
Short name T230
Test name
Test status
Simulation time 527590300 ps
CPU time 135.77 seconds
Started Jun 09 02:56:55 PM PDT 24
Finished Jun 09 02:59:11 PM PDT 24
Peak memory 264260 kb
Host smart-cb0d5084-8592-45b3-b718-178b4f4a509e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860999887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o
tp_reset.3860999887
Directory /workspace/45.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2751576903
Short name T1223
Test name
Test status
Simulation time 431545500 ps
CPU time 49.9 seconds
Started Jun 09 01:27:00 PM PDT 24
Finished Jun 09 01:27:50 PM PDT 24
Peak memory 261256 kb
Host smart-d0496eac-7584-47dd-99ee-69c48097ae27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751576903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_aliasing.2751576903
Directory /workspace/0.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3661214980
Short name T1211
Test name
Test status
Simulation time 650660500 ps
CPU time 67.83 seconds
Started Jun 09 01:27:00 PM PDT 24
Finished Jun 09 01:28:08 PM PDT 24
Peak memory 261084 kb
Host smart-0e923148-b477-4a2a-9bab-6a4114912613
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661214980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_bit_bash.3661214980
Directory /workspace/0.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2622863324
Short name T1205
Test name
Test status
Simulation time 221979400 ps
CPU time 25.69 seconds
Started Jun 09 01:26:59 PM PDT 24
Finished Jun 09 01:27:25 PM PDT 24
Peak memory 261220 kb
Host smart-d19e7753-1645-4180-baf6-7db8bcbed5bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622863324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.flash_ctrl_csr_hw_reset.2622863324
Directory /workspace/0.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1086478151
Short name T317
Test name
Test status
Simulation time 214928800 ps
CPU time 16.62 seconds
Started Jun 09 01:27:01 PM PDT 24
Finished Jun 09 01:27:18 PM PDT 24
Peak memory 271964 kb
Host smart-512bedb7-f426-4503-ba61-556dc59ae88a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086478151 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.1086478151
Directory /workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1243954531
Short name T1143
Test name
Test status
Simulation time 21016400 ps
CPU time 16.49 seconds
Started Jun 09 01:27:00 PM PDT 24
Finished Jun 09 01:27:17 PM PDT 24
Peak memory 263556 kb
Host smart-8e09a192-2022-4a7d-a679-9ebfbd9c1182
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243954531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_csr_rw.1243954531
Directory /workspace/0.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2347937668
Short name T1132
Test name
Test status
Simulation time 51779900 ps
CPU time 13.6 seconds
Started Jun 09 01:27:00 PM PDT 24
Finished Jun 09 01:27:14 PM PDT 24
Peak memory 262060 kb
Host smart-9ed4ac29-c620-47b2-bf46-736741b7ff37
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347937668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_mem_partial_access.2347937668
Directory /workspace/0.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3774551133
Short name T1225
Test name
Test status
Simulation time 35805300 ps
CPU time 13.06 seconds
Started Jun 09 01:27:01 PM PDT 24
Finished Jun 09 01:27:14 PM PDT 24
Peak memory 261180 kb
Host smart-62e53632-8b0f-451b-94e5-d543a94942e9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774551133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me
m_walk.3774551133
Directory /workspace/0.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.470025932
Short name T1178
Test name
Test status
Simulation time 243812800 ps
CPU time 34.86 seconds
Started Jun 09 01:27:00 PM PDT 24
Finished Jun 09 01:27:35 PM PDT 24
Peak memory 261228 kb
Host smart-f14d8023-185a-47a3-9bab-8612c702d1ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470025932 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.470025932
Directory /workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.903231899
Short name T1153
Test name
Test status
Simulation time 12937300 ps
CPU time 13.43 seconds
Started Jun 09 01:27:01 PM PDT 24
Finished Jun 09 01:27:14 PM PDT 24
Peak memory 252912 kb
Host smart-53dc8d38-2a4e-4e75-86d4-079b47606b30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903231899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.903231899
Directory /workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1747036355
Short name T1108
Test name
Test status
Simulation time 93135700 ps
CPU time 15.55 seconds
Started Jun 09 01:26:59 PM PDT 24
Finished Jun 09 01:27:15 PM PDT 24
Peak memory 253064 kb
Host smart-77c14ed4-486f-4115-8895-804700a3b328
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747036355 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.1747036355
Directory /workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2033582218
Short name T293
Test name
Test status
Simulation time 2719026300 ps
CPU time 914.9 seconds
Started Jun 09 01:27:01 PM PDT 24
Finished Jun 09 01:42:16 PM PDT 24
Peak memory 263740 kb
Host smart-30219862-4ebe-49b8-a7a6-b3b088e5fefd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033582218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl
_tl_intg_err.2033582218
Directory /workspace/0.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2474071255
Short name T318
Test name
Test status
Simulation time 2754272900 ps
CPU time 64.38 seconds
Started Jun 09 01:27:12 PM PDT 24
Finished Jun 09 01:28:17 PM PDT 24
Peak memory 261236 kb
Host smart-47f5bbca-3626-491a-bf7f-a9797011c378
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474071255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_aliasing.2474071255
Directory /workspace/1.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1798987435
Short name T1222
Test name
Test status
Simulation time 661811800 ps
CPU time 68.44 seconds
Started Jun 09 01:27:05 PM PDT 24
Finished Jun 09 01:28:14 PM PDT 24
Peak memory 261120 kb
Host smart-87a3c557-5e2a-4ba8-99bf-5ca7356ff852
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798987435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_bit_bash.1798987435
Directory /workspace/1.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2817923127
Short name T1176
Test name
Test status
Simulation time 59255500 ps
CPU time 25.83 seconds
Started Jun 09 01:27:05 PM PDT 24
Finished Jun 09 01:27:32 PM PDT 24
Peak memory 261096 kb
Host smart-5db0cabb-432b-4c31-b091-22cc4310c34a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817923127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.flash_ctrl_csr_hw_reset.2817923127
Directory /workspace/1.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3552636001
Short name T1216
Test name
Test status
Simulation time 341406800 ps
CPU time 16.46 seconds
Started Jun 09 01:27:11 PM PDT 24
Finished Jun 09 01:27:28 PM PDT 24
Peak memory 270488 kb
Host smart-b6c60ca5-fc2b-4294-9c3c-5465c51bf4f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552636001 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.3552636001
Directory /workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1432688461
Short name T1200
Test name
Test status
Simulation time 37173200 ps
CPU time 13.96 seconds
Started Jun 09 01:27:05 PM PDT 24
Finished Jun 09 01:27:20 PM PDT 24
Peak memory 263640 kb
Host smart-05d7b40e-01d7-42f2-9622-63c3a8dc9796
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432688461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_csr_rw.1432688461
Directory /workspace/1.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2332514270
Short name T1177
Test name
Test status
Simulation time 17126700 ps
CPU time 13.43 seconds
Started Jun 09 01:27:06 PM PDT 24
Finished Jun 09 01:27:19 PM PDT 24
Peak memory 261052 kb
Host smart-301f50e3-775a-41c9-95f2-1434462e2d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332514270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.2
332514270
Directory /workspace/1.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1266463370
Short name T1136
Test name
Test status
Simulation time 23918400 ps
CPU time 13.27 seconds
Started Jun 09 01:27:05 PM PDT 24
Finished Jun 09 01:27:19 PM PDT 24
Peak memory 261884 kb
Host smart-80e1b9d8-6330-477a-8cbe-e563ece0241c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266463370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f
lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_mem_partial_access.1266463370
Directory /workspace/1.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2386739957
Short name T1230
Test name
Test status
Simulation time 16961000 ps
CPU time 13.22 seconds
Started Jun 09 01:27:06 PM PDT 24
Finished Jun 09 01:27:19 PM PDT 24
Peak memory 261052 kb
Host smart-93e084db-b2b5-4e15-a70c-990637a146c5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386739957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me
m_walk.2386739957
Directory /workspace/1.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3078878675
Short name T1184
Test name
Test status
Simulation time 687258300 ps
CPU time 31.48 seconds
Started Jun 09 01:27:12 PM PDT 24
Finished Jun 09 01:27:44 PM PDT 24
Peak memory 262992 kb
Host smart-e66f0474-b373-4a38-a833-fc9b1952b10f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078878675 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.3078878675
Directory /workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.98961780
Short name T1148
Test name
Test status
Simulation time 33958100 ps
CPU time 15.64 seconds
Started Jun 09 01:27:06 PM PDT 24
Finished Jun 09 01:27:22 PM PDT 24
Peak memory 252940 kb
Host smart-a85ec067-a0e3-4982-81b4-26c71c99d34f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98961780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.98961780
Directory /workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3618233170
Short name T1157
Test name
Test status
Simulation time 30586300 ps
CPU time 15.37 seconds
Started Jun 09 01:27:06 PM PDT 24
Finished Jun 09 01:27:22 PM PDT 24
Peak memory 252932 kb
Host smart-b9763363-af37-442e-945d-0d2acd27efa7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618233170 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.3618233170
Directory /workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1574252854
Short name T281
Test name
Test status
Simulation time 78165600 ps
CPU time 16.86 seconds
Started Jun 09 01:27:01 PM PDT 24
Finished Jun 09 01:27:18 PM PDT 24
Peak memory 263752 kb
Host smart-6a7c09d5-3969-42e8-8380-68e6d4f00e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574252854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.1
574252854
Directory /workspace/1.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1486608729
Short name T296
Test name
Test status
Simulation time 946558900 ps
CPU time 450.93 seconds
Started Jun 09 01:27:08 PM PDT 24
Finished Jun 09 01:34:39 PM PDT 24
Peak memory 263724 kb
Host smart-6f26076f-df61-4d55-8b0e-29797dd5df1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486608729 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_tl_intg_err.1486608729
Directory /workspace/1.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3295198733
Short name T53
Test name
Test status
Simulation time 158593800 ps
CPU time 19.53 seconds
Started Jun 09 01:28:00 PM PDT 24
Finished Jun 09 01:28:20 PM PDT 24
Peak memory 271996 kb
Host smart-7dc90665-408b-40fe-b071-807b8c26df79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295198733 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3295198733
Directory /workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2337955334
Short name T313
Test name
Test status
Simulation time 124903500 ps
CPU time 14.93 seconds
Started Jun 09 01:28:02 PM PDT 24
Finished Jun 09 01:28:17 PM PDT 24
Peak memory 261188 kb
Host smart-9a446535-497e-456b-9f29-a8d8e3265880
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337955334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_csr_rw.2337955334
Directory /workspace/10.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1324997258
Short name T1191
Test name
Test status
Simulation time 55364800 ps
CPU time 13.21 seconds
Started Jun 09 01:28:01 PM PDT 24
Finished Jun 09 01:28:14 PM PDT 24
Peak memory 261068 kb
Host smart-a3c2da86-a997-4375-8b89-9fbfbb288a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324997258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.
1324997258
Directory /workspace/10.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1460702808
Short name T1155
Test name
Test status
Simulation time 41244600 ps
CPU time 15.02 seconds
Started Jun 09 01:28:00 PM PDT 24
Finished Jun 09 01:28:15 PM PDT 24
Peak memory 261172 kb
Host smart-2cc86306-c9a7-4691-a5aa-21bb9162d588
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460702808 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.1460702808
Directory /workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.4114731407
Short name T1099
Test name
Test status
Simulation time 16521700 ps
CPU time 15.5 seconds
Started Jun 09 01:28:00 PM PDT 24
Finished Jun 09 01:28:15 PM PDT 24
Peak memory 252928 kb
Host smart-537a78e6-eced-4d5c-8ba0-da8b46b61dc0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114731407 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.4114731407
Directory /workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2905896173
Short name T1231
Test name
Test status
Simulation time 39129900 ps
CPU time 15.56 seconds
Started Jun 09 01:28:00 PM PDT 24
Finished Jun 09 01:28:15 PM PDT 24
Peak memory 252984 kb
Host smart-85945497-6f12-4f5b-a3ba-cba487c91e0c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905896173 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.2905896173
Directory /workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.622554442
Short name T315
Test name
Test status
Simulation time 115359200 ps
CPU time 17.57 seconds
Started Jun 09 01:28:06 PM PDT 24
Finished Jun 09 01:28:24 PM PDT 24
Peak memory 263816 kb
Host smart-ed0aea9f-bf45-433b-b7b7-3184cc179663
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622554442 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.622554442
Directory /workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3071764581
Short name T1131
Test name
Test status
Simulation time 55985500 ps
CPU time 17.74 seconds
Started Jun 09 01:28:06 PM PDT 24
Finished Jun 09 01:28:24 PM PDT 24
Peak memory 263600 kb
Host smart-0d550434-c6c7-4333-8886-b205d1976b09
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071764581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_csr_rw.3071764581
Directory /workspace/11.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4248621958
Short name T1135
Test name
Test status
Simulation time 54378000 ps
CPU time 13.45 seconds
Started Jun 09 01:28:07 PM PDT 24
Finished Jun 09 01:28:21 PM PDT 24
Peak memory 261060 kb
Host smart-a3b48d5c-014c-47d4-8180-71123d995e17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248621958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.
4248621958
Directory /workspace/11.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3162605082
Short name T1227
Test name
Test status
Simulation time 338400100 ps
CPU time 17.79 seconds
Started Jun 09 01:28:07 PM PDT 24
Finished Jun 09 01:28:25 PM PDT 24
Peak memory 261228 kb
Host smart-5770569c-c80e-48a5-8671-27d0a7d44b4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162605082 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.3162605082
Directory /workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.512985024
Short name T1107
Test name
Test status
Simulation time 15221600 ps
CPU time 15.82 seconds
Started Jun 09 01:28:01 PM PDT 24
Finished Jun 09 01:28:17 PM PDT 24
Peak memory 252988 kb
Host smart-d844d451-ade9-408b-97be-17d36d5b1f35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512985024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.512985024
Directory /workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2945529572
Short name T1100
Test name
Test status
Simulation time 15043300 ps
CPU time 12.95 seconds
Started Jun 09 01:28:05 PM PDT 24
Finished Jun 09 01:28:19 PM PDT 24
Peak memory 252984 kb
Host smart-376a4dd7-99c2-459c-ac6b-fb2f91eafcfd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945529572 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.2945529572
Directory /workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2386513111
Short name T1209
Test name
Test status
Simulation time 34752100 ps
CPU time 15.16 seconds
Started Jun 09 01:28:01 PM PDT 24
Finished Jun 09 01:28:16 PM PDT 24
Peak memory 263732 kb
Host smart-8f306b5b-28b8-427b-bb9e-22794d0c1eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386513111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.
2386513111
Directory /workspace/11.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1811062137
Short name T369
Test name
Test status
Simulation time 770505600 ps
CPU time 913.44 seconds
Started Jun 09 01:28:02 PM PDT 24
Finished Jun 09 01:43:16 PM PDT 24
Peak memory 263728 kb
Host smart-b569bbe0-d984-4ac3-90aa-40682d462ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811062137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr
l_tl_intg_err.1811062137
Directory /workspace/11.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.561003304
Short name T1232
Test name
Test status
Simulation time 58264700 ps
CPU time 15.12 seconds
Started Jun 09 01:28:13 PM PDT 24
Finished Jun 09 01:28:28 PM PDT 24
Peak memory 263796 kb
Host smart-6df65415-a54c-48cd-b1ed-5a0754cc59c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561003304 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.561003304
Directory /workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1594147068
Short name T1139
Test name
Test status
Simulation time 33424700 ps
CPU time 16.48 seconds
Started Jun 09 01:28:11 PM PDT 24
Finished Jun 09 01:28:28 PM PDT 24
Peak memory 261100 kb
Host smart-a20f5232-6637-455a-a3ae-718b8fc34b72
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594147068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_csr_rw.1594147068
Directory /workspace/12.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.4195980268
Short name T1175
Test name
Test status
Simulation time 163054400 ps
CPU time 13.47 seconds
Started Jun 09 01:28:12 PM PDT 24
Finished Jun 09 01:28:26 PM PDT 24
Peak memory 261124 kb
Host smart-48f2be0a-b066-4148-a3f6-34762434240a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195980268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.
4195980268
Directory /workspace/12.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.506453052
Short name T1098
Test name
Test status
Simulation time 97090100 ps
CPU time 14.83 seconds
Started Jun 09 01:28:12 PM PDT 24
Finished Jun 09 01:28:27 PM PDT 24
Peak memory 263688 kb
Host smart-46646857-0d72-408c-8dc7-e495bcface94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506453052 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.506453052
Directory /workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.198007740
Short name T1152
Test name
Test status
Simulation time 13590400 ps
CPU time 13.11 seconds
Started Jun 09 01:28:06 PM PDT 24
Finished Jun 09 01:28:19 PM PDT 24
Peak memory 252924 kb
Host smart-2a299884-c46d-4490-9e01-e9612f24a5bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198007740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.198007740
Directory /workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2998977624
Short name T1212
Test name
Test status
Simulation time 12241200 ps
CPU time 15.35 seconds
Started Jun 09 01:28:06 PM PDT 24
Finished Jun 09 01:28:22 PM PDT 24
Peak memory 253072 kb
Host smart-9cdaec46-e19f-42a9-b4ec-012bce1ad607
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998977624 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.2998977624
Directory /workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.4021001487
Short name T1219
Test name
Test status
Simulation time 132271700 ps
CPU time 16.14 seconds
Started Jun 09 01:28:08 PM PDT 24
Finished Jun 09 01:28:25 PM PDT 24
Peak memory 263760 kb
Host smart-e86799c8-0a87-45d2-96e2-1645d041381c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021001487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.
4021001487
Directory /workspace/12.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.924992485
Short name T1241
Test name
Test status
Simulation time 2011698800 ps
CPU time 458.77 seconds
Started Jun 09 01:28:06 PM PDT 24
Finished Jun 09 01:35:45 PM PDT 24
Peak memory 263736 kb
Host smart-d6591b9b-c49c-42e8-80ff-805d855894b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924992485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl
_tl_intg_err.924992485
Directory /workspace/12.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2039242183
Short name T294
Test name
Test status
Simulation time 55553400 ps
CPU time 17.6 seconds
Started Jun 09 01:28:13 PM PDT 24
Finished Jun 09 01:28:31 PM PDT 24
Peak memory 271992 kb
Host smart-d6f45586-8e3d-4594-b460-6e05fabe40be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039242183 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.2039242183
Directory /workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.169530649
Short name T1134
Test name
Test status
Simulation time 19258800 ps
CPU time 13.86 seconds
Started Jun 09 01:28:13 PM PDT 24
Finished Jun 09 01:28:27 PM PDT 24
Peak memory 263636 kb
Host smart-5ee23df8-dd7e-4d00-953a-471be9478c11
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169530649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.flash_ctrl_csr_rw.169530649
Directory /workspace/13.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2280482318
Short name T1201
Test name
Test status
Simulation time 16352800 ps
CPU time 13.27 seconds
Started Jun 09 01:28:10 PM PDT 24
Finished Jun 09 01:28:24 PM PDT 24
Peak memory 261068 kb
Host smart-2e876436-46ef-4beb-ab67-ab9ff5e24f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280482318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.
2280482318
Directory /workspace/13.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1180737558
Short name T275
Test name
Test status
Simulation time 102299100 ps
CPU time 18.23 seconds
Started Jun 09 01:28:11 PM PDT 24
Finished Jun 09 01:28:30 PM PDT 24
Peak memory 262964 kb
Host smart-89b6b604-d585-491f-8f00-a878d179a28f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180737558 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.1180737558
Directory /workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3056068642
Short name T1111
Test name
Test status
Simulation time 11390200 ps
CPU time 15.29 seconds
Started Jun 09 01:28:13 PM PDT 24
Finished Jun 09 01:28:28 PM PDT 24
Peak memory 252916 kb
Host smart-826faf41-5e42-4caf-90b5-aa067b182d24
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056068642 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.3056068642
Directory /workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.944841740
Short name T1194
Test name
Test status
Simulation time 11339100 ps
CPU time 13.15 seconds
Started Jun 09 01:28:11 PM PDT 24
Finished Jun 09 01:28:24 PM PDT 24
Peak memory 252948 kb
Host smart-286713f5-afe4-41fe-a07e-53b35dc7c089
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944841740 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.944841740
Directory /workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.264480278
Short name T291
Test name
Test status
Simulation time 59472500 ps
CPU time 20.03 seconds
Started Jun 09 01:28:12 PM PDT 24
Finished Jun 09 01:28:32 PM PDT 24
Peak memory 263744 kb
Host smart-7be85e25-2cd6-4f19-bf26-8af3fd84ec98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264480278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.264480278
Directory /workspace/13.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2310005623
Short name T370
Test name
Test status
Simulation time 427416900 ps
CPU time 464.36 seconds
Started Jun 09 01:28:12 PM PDT 24
Finished Jun 09 01:35:57 PM PDT 24
Peak memory 263748 kb
Host smart-0deae187-a359-4e0a-af32-9ef0599a3059
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310005623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr
l_tl_intg_err.2310005623
Directory /workspace/13.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3136058706
Short name T1186
Test name
Test status
Simulation time 311319800 ps
CPU time 17.15 seconds
Started Jun 09 01:28:18 PM PDT 24
Finished Jun 09 01:28:35 PM PDT 24
Peak memory 272012 kb
Host smart-29411a22-69f8-49ad-afe2-6354dbf9955a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136058706 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3136058706
Directory /workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2501005200
Short name T1166
Test name
Test status
Simulation time 39255500 ps
CPU time 16.34 seconds
Started Jun 09 01:28:16 PM PDT 24
Finished Jun 09 01:28:32 PM PDT 24
Peak memory 261328 kb
Host smart-398d5f0e-642b-4a2c-a97c-bebec971d5fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501005200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_csr_rw.2501005200
Directory /workspace/14.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.90847652
Short name T1125
Test name
Test status
Simulation time 18898000 ps
CPU time 14.01 seconds
Started Jun 09 01:28:18 PM PDT 24
Finished Jun 09 01:28:32 PM PDT 24
Peak memory 261068 kb
Host smart-206b9d7f-01d9-40b2-ad1d-20d92983ba05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90847652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.90847652
Directory /workspace/14.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2750139879
Short name T1190
Test name
Test status
Simulation time 445078900 ps
CPU time 18.86 seconds
Started Jun 09 01:28:18 PM PDT 24
Finished Jun 09 01:28:37 PM PDT 24
Peak memory 261164 kb
Host smart-06b88056-e097-4260-a9ec-c596c7b9e5b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750139879 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.2750139879
Directory /workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1746059270
Short name T1105
Test name
Test status
Simulation time 51216700 ps
CPU time 15.65 seconds
Started Jun 09 01:28:17 PM PDT 24
Finished Jun 09 01:28:33 PM PDT 24
Peak memory 252928 kb
Host smart-8df39c7f-dbc9-4018-a77e-f6a2014ba4e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746059270 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.1746059270
Directory /workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.4075854571
Short name T1210
Test name
Test status
Simulation time 44614100 ps
CPU time 15.41 seconds
Started Jun 09 01:28:17 PM PDT 24
Finished Jun 09 01:28:32 PM PDT 24
Peak memory 253064 kb
Host smart-b342a444-67ad-4c55-979d-c5d26342bd77
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075854571 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.4075854571
Directory /workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3262935995
Short name T373
Test name
Test status
Simulation time 2844001400 ps
CPU time 906.8 seconds
Started Jun 09 01:28:14 PM PDT 24
Finished Jun 09 01:43:21 PM PDT 24
Peak memory 263740 kb
Host smart-cd9bf5e4-8838-4006-a650-01fc68e86d25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262935995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr
l_tl_intg_err.3262935995
Directory /workspace/14.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1209247813
Short name T261
Test name
Test status
Simulation time 53648600 ps
CPU time 15.33 seconds
Started Jun 09 01:28:23 PM PDT 24
Finished Jun 09 01:28:39 PM PDT 24
Peak memory 277096 kb
Host smart-28923ce7-997b-49ae-9655-80e292125af2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209247813 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.1209247813
Directory /workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1637758501
Short name T1109
Test name
Test status
Simulation time 30181000 ps
CPU time 16.55 seconds
Started Jun 09 01:28:21 PM PDT 24
Finished Jun 09 01:28:38 PM PDT 24
Peak memory 261012 kb
Host smart-7b2cf21f-34ae-469b-a3eb-5846ab6c3490
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637758501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_csr_rw.1637758501
Directory /workspace/15.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3823895940
Short name T1226
Test name
Test status
Simulation time 44972100 ps
CPU time 13.5 seconds
Started Jun 09 01:28:21 PM PDT 24
Finished Jun 09 01:28:35 PM PDT 24
Peak memory 261056 kb
Host smart-28aef1f1-f7c2-405e-8193-22f99609169a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823895940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.
3823895940
Directory /workspace/15.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2725781234
Short name T1146
Test name
Test status
Simulation time 326125200 ps
CPU time 15.65 seconds
Started Jun 09 01:28:23 PM PDT 24
Finished Jun 09 01:28:39 PM PDT 24
Peak memory 262988 kb
Host smart-a5904cb6-1706-4124-877a-298ccfcc6639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725781234 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.2725781234
Directory /workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3807628773
Short name T1217
Test name
Test status
Simulation time 12658500 ps
CPU time 13.11 seconds
Started Jun 09 01:28:21 PM PDT 24
Finished Jun 09 01:28:35 PM PDT 24
Peak memory 252868 kb
Host smart-aa36ac7c-62dd-4cc1-9cd1-05b148cab481
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807628773 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.3807628773
Directory /workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.719511699
Short name T1145
Test name
Test status
Simulation time 20029200 ps
CPU time 13.11 seconds
Started Jun 09 01:28:20 PM PDT 24
Finished Jun 09 01:28:33 PM PDT 24
Peak memory 253176 kb
Host smart-acbf33a8-77ce-4f60-a723-0d9520a1a402
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719511699 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.719511699
Directory /workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1848620428
Short name T1228
Test name
Test status
Simulation time 346609900 ps
CPU time 15.96 seconds
Started Jun 09 01:28:16 PM PDT 24
Finished Jun 09 01:28:32 PM PDT 24
Peak memory 263748 kb
Host smart-451522fe-dff9-4192-97e4-203d00447f18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848620428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.
1848620428
Directory /workspace/15.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1667049803
Short name T375
Test name
Test status
Simulation time 1064909200 ps
CPU time 454.74 seconds
Started Jun 09 01:28:17 PM PDT 24
Finished Jun 09 01:35:52 PM PDT 24
Peak memory 263952 kb
Host smart-36c375dd-a102-44ef-8e7d-681ce6716907
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667049803 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctr
l_tl_intg_err.1667049803
Directory /workspace/15.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2306802074
Short name T255
Test name
Test status
Simulation time 100031000 ps
CPU time 14.93 seconds
Started Jun 09 01:28:22 PM PDT 24
Finished Jun 09 01:28:38 PM PDT 24
Peak memory 275940 kb
Host smart-7d8a4e0c-75ac-4fba-b3d4-e305c1921711
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306802074 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.2306802074
Directory /workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2253272692
Short name T1141
Test name
Test status
Simulation time 18617900 ps
CPU time 15.94 seconds
Started Jun 09 01:28:24 PM PDT 24
Finished Jun 09 01:28:41 PM PDT 24
Peak memory 263624 kb
Host smart-40486bfb-5fdb-4ac5-9c93-e556d27dcc29
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253272692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_csr_rw.2253272692
Directory /workspace/16.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2314028972
Short name T1195
Test name
Test status
Simulation time 63136800 ps
CPU time 13.19 seconds
Started Jun 09 01:28:22 PM PDT 24
Finished Jun 09 01:28:36 PM PDT 24
Peak memory 261068 kb
Host smart-ad02a4bf-0f51-4aae-b2f0-f28999e7d606
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314028972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.
2314028972
Directory /workspace/16.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.418849753
Short name T320
Test name
Test status
Simulation time 368643500 ps
CPU time 35.29 seconds
Started Jun 09 01:28:22 PM PDT 24
Finished Jun 09 01:28:57 PM PDT 24
Peak memory 263692 kb
Host smart-142052c9-b77f-4e82-86bf-6738bd13a77a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418849753 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.418849753
Directory /workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.4224893775
Short name T1149
Test name
Test status
Simulation time 69101500 ps
CPU time 13.19 seconds
Started Jun 09 01:28:22 PM PDT 24
Finished Jun 09 01:28:36 PM PDT 24
Peak memory 252844 kb
Host smart-afec1790-8e49-4df4-b587-646967665876
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224893775 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.4224893775
Directory /workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2793245652
Short name T1119
Test name
Test status
Simulation time 23696000 ps
CPU time 15.47 seconds
Started Jun 09 01:28:21 PM PDT 24
Finished Jun 09 01:28:36 PM PDT 24
Peak memory 252924 kb
Host smart-e5296d08-dee2-4438-8a41-36f019d707ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793245652 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.2793245652
Directory /workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.222424879
Short name T286
Test name
Test status
Simulation time 434854800 ps
CPU time 21.26 seconds
Started Jun 09 01:28:22 PM PDT 24
Finished Jun 09 01:28:44 PM PDT 24
Peak memory 263756 kb
Host smart-06988d3e-11ba-4e97-b4d7-9eb9e9f52ada
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222424879 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.222424879
Directory /workspace/16.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1234411344
Short name T1221
Test name
Test status
Simulation time 375935000 ps
CPU time 19.34 seconds
Started Jun 09 01:28:26 PM PDT 24
Finished Jun 09 01:28:46 PM PDT 24
Peak memory 272008 kb
Host smart-1cae1ac8-203c-4370-977c-88f9a6b89a21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234411344 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1234411344
Directory /workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.4141840777
Short name T1130
Test name
Test status
Simulation time 25107800 ps
CPU time 14.09 seconds
Started Jun 09 01:28:26 PM PDT 24
Finished Jun 09 01:28:40 PM PDT 24
Peak memory 263628 kb
Host smart-736f9c9d-3f6b-45a7-9fcb-ea69c11b3c63
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141840777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_csr_rw.4141840777
Directory /workspace/17.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.621984066
Short name T1102
Test name
Test status
Simulation time 35579800 ps
CPU time 13.3 seconds
Started Jun 09 01:28:26 PM PDT 24
Finished Jun 09 01:28:39 PM PDT 24
Peak memory 261068 kb
Host smart-7eb50216-0d94-4561-9e3e-40c6ed127605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621984066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.621984066
Directory /workspace/17.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.282621928
Short name T277
Test name
Test status
Simulation time 403472800 ps
CPU time 29.99 seconds
Started Jun 09 01:28:29 PM PDT 24
Finished Jun 09 01:28:59 PM PDT 24
Peak memory 261156 kb
Host smart-f6a86700-315a-4b8f-acaf-9575fe78e3a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282621928 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.282621928
Directory /workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3846616006
Short name T1129
Test name
Test status
Simulation time 14840500 ps
CPU time 15.96 seconds
Started Jun 09 01:28:22 PM PDT 24
Finished Jun 09 01:28:38 PM PDT 24
Peak memory 252896 kb
Host smart-2eb5caa6-f3d4-4ece-b65f-a01114855d4d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846616006 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.3846616006
Directory /workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2206819152
Short name T1142
Test name
Test status
Simulation time 43240000 ps
CPU time 15.58 seconds
Started Jun 09 01:28:27 PM PDT 24
Finished Jun 09 01:28:43 PM PDT 24
Peak memory 252936 kb
Host smart-f815f3b2-c5a7-4e3d-98fb-8d7ecbead581
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206819152 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.2206819152
Directory /workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1235765095
Short name T256
Test name
Test status
Simulation time 415612700 ps
CPU time 449.41 seconds
Started Jun 09 01:28:23 PM PDT 24
Finished Jun 09 01:35:53 PM PDT 24
Peak memory 263736 kb
Host smart-1cd09905-9c6b-46a1-ae07-71b388d63356
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235765095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr
l_tl_intg_err.1235765095
Directory /workspace/17.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3999749765
Short name T1165
Test name
Test status
Simulation time 135834900 ps
CPU time 17.08 seconds
Started Jun 09 01:28:26 PM PDT 24
Finished Jun 09 01:28:43 PM PDT 24
Peak memory 274532 kb
Host smart-38207ab6-e1b0-4aba-8c3d-d54ec8620d5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999749765 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.3999749765
Directory /workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1197780349
Short name T1158
Test name
Test status
Simulation time 60264000 ps
CPU time 14.63 seconds
Started Jun 09 01:28:29 PM PDT 24
Finished Jun 09 01:28:44 PM PDT 24
Peak memory 263656 kb
Host smart-6fa1f8e6-71a3-48f6-82e7-d8914e5de1ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197780349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_csr_rw.1197780349
Directory /workspace/18.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3556072290
Short name T1128
Test name
Test status
Simulation time 30730500 ps
CPU time 13.1 seconds
Started Jun 09 01:28:29 PM PDT 24
Finished Jun 09 01:28:42 PM PDT 24
Peak memory 261080 kb
Host smart-fee3937c-e3bb-4f9e-984e-edf0b4d5a3ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556072290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.
3556072290
Directory /workspace/18.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.919506537
Short name T1214
Test name
Test status
Simulation time 83607200 ps
CPU time 15.48 seconds
Started Jun 09 01:28:28 PM PDT 24
Finished Jun 09 01:28:43 PM PDT 24
Peak memory 263676 kb
Host smart-e217a8b7-a7c5-4be9-8e86-b50b7c3bc3c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919506537 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.919506537
Directory /workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3071135058
Short name T1094
Test name
Test status
Simulation time 13873900 ps
CPU time 13.59 seconds
Started Jun 09 01:28:26 PM PDT 24
Finished Jun 09 01:28:40 PM PDT 24
Peak memory 252916 kb
Host smart-87920daa-0fff-42a2-beac-103e91461e99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071135058 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.3071135058
Directory /workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1451070643
Short name T1196
Test name
Test status
Simulation time 19372400 ps
CPU time 15.36 seconds
Started Jun 09 01:28:26 PM PDT 24
Finished Jun 09 01:28:41 PM PDT 24
Peak memory 252796 kb
Host smart-426ebbf0-d4cb-45b5-b95a-f2ed68df29c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451070643 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.1451070643
Directory /workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2908321353
Short name T374
Test name
Test status
Simulation time 1056945100 ps
CPU time 381.1 seconds
Started Jun 09 01:28:26 PM PDT 24
Finished Jun 09 01:34:48 PM PDT 24
Peak memory 263756 kb
Host smart-25663068-2e7d-4e26-87ef-a7f053cb82ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908321353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctr
l_tl_intg_err.2908321353
Directory /workspace/18.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.4083085137
Short name T321
Test name
Test status
Simulation time 202197500 ps
CPU time 17.03 seconds
Started Jun 09 01:28:37 PM PDT 24
Finished Jun 09 01:28:54 PM PDT 24
Peak memory 275052 kb
Host smart-94e733bb-a653-41c4-a58e-32a6262c86b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083085137 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.4083085137
Directory /workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2987529017
Short name T227
Test name
Test status
Simulation time 106467300 ps
CPU time 14.73 seconds
Started Jun 09 01:28:32 PM PDT 24
Finished Jun 09 01:28:47 PM PDT 24
Peak memory 263652 kb
Host smart-8b9b3734-fd6e-46cd-ad56-72d11d8b101d
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987529017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_csr_rw.2987529017
Directory /workspace/19.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3925540474
Short name T1235
Test name
Test status
Simulation time 14486300 ps
CPU time 13.36 seconds
Started Jun 09 01:28:33 PM PDT 24
Finished Jun 09 01:28:47 PM PDT 24
Peak memory 261128 kb
Host smart-9c4adfc5-5b4f-484e-ada1-f1c62f31dd5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925540474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.
3925540474
Directory /workspace/19.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2851391239
Short name T1213
Test name
Test status
Simulation time 810740900 ps
CPU time 35.3 seconds
Started Jun 09 01:28:42 PM PDT 24
Finished Jun 09 01:29:18 PM PDT 24
Peak memory 263164 kb
Host smart-f5342b67-0a14-4029-90a1-caf39b3cf094
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851391239 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.2851391239
Directory /workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1539588048
Short name T1118
Test name
Test status
Simulation time 34072700 ps
CPU time 15.15 seconds
Started Jun 09 01:28:34 PM PDT 24
Finished Jun 09 01:28:50 PM PDT 24
Peak memory 253040 kb
Host smart-f0343d0c-4e72-4018-b019-497ebfe75a11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539588048 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.1539588048
Directory /workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2303673636
Short name T1106
Test name
Test status
Simulation time 42435900 ps
CPU time 13.22 seconds
Started Jun 09 01:28:32 PM PDT 24
Finished Jun 09 01:28:45 PM PDT 24
Peak memory 253064 kb
Host smart-2530103d-ae14-42e5-b5cf-835356ca54d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303673636 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.2303673636
Directory /workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1734757263
Short name T279
Test name
Test status
Simulation time 40298600 ps
CPU time 16.51 seconds
Started Jun 09 01:28:34 PM PDT 24
Finished Jun 09 01:28:51 PM PDT 24
Peak memory 263748 kb
Host smart-4927581f-ed1f-4675-847a-f1a235fc6c15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734757263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.
1734757263
Directory /workspace/19.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3837716114
Short name T1159
Test name
Test status
Simulation time 339306100 ps
CPU time 450.7 seconds
Started Jun 09 01:28:33 PM PDT 24
Finished Jun 09 01:36:04 PM PDT 24
Peak memory 263736 kb
Host smart-97dafe48-083e-46e6-9ba5-b91e55f0d4eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837716114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr
l_tl_intg_err.3837716114
Directory /workspace/19.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1778556355
Short name T1120
Test name
Test status
Simulation time 268941300 ps
CPU time 30.38 seconds
Started Jun 09 01:27:15 PM PDT 24
Finished Jun 09 01:27:46 PM PDT 24
Peak memory 261172 kb
Host smart-98e8b19c-e467-4af7-bf9f-33cf590db809
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778556355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_aliasing.1778556355
Directory /workspace/2.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1738431388
Short name T1163
Test name
Test status
Simulation time 1146566800 ps
CPU time 44.94 seconds
Started Jun 09 01:27:13 PM PDT 24
Finished Jun 09 01:27:58 PM PDT 24
Peak memory 260968 kb
Host smart-40aa552f-e1ce-4774-8948-d164d1563969
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738431388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_bit_bash.1738431388
Directory /workspace/2.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1129070087
Short name T1242
Test name
Test status
Simulation time 308487300 ps
CPU time 38.45 seconds
Started Jun 09 01:27:12 PM PDT 24
Finished Jun 09 01:27:51 PM PDT 24
Peak memory 261032 kb
Host smart-98147df3-d88d-414e-ad79-67fc11c5c5e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129070087 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.flash_ctrl_csr_hw_reset.1129070087
Directory /workspace/2.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3445307522
Short name T1243
Test name
Test status
Simulation time 137662700 ps
CPU time 18.54 seconds
Started Jun 09 01:27:17 PM PDT 24
Finished Jun 09 01:27:36 PM PDT 24
Peak memory 271432 kb
Host smart-b2d13f10-120b-4fb2-b8a8-e4777d18ad80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445307522 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.3445307522
Directory /workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3877243782
Short name T1137
Test name
Test status
Simulation time 36116400 ps
CPU time 16.38 seconds
Started Jun 09 01:27:12 PM PDT 24
Finished Jun 09 01:27:29 PM PDT 24
Peak memory 263612 kb
Host smart-31a04f14-df07-49e5-9a84-0b94cc8d3f6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877243782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_csr_rw.3877243782
Directory /workspace/2.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3656071119
Short name T340
Test name
Test status
Simulation time 30247100 ps
CPU time 13.37 seconds
Started Jun 09 01:27:12 PM PDT 24
Finished Jun 09 01:27:26 PM PDT 24
Peak memory 261152 kb
Host smart-942c25aa-387a-4687-9dac-696470bc0e12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656071119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.3
656071119
Directory /workspace/2.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1178548907
Short name T1133
Test name
Test status
Simulation time 13917500 ps
CPU time 13.3 seconds
Started Jun 09 01:27:11 PM PDT 24
Finished Jun 09 01:27:25 PM PDT 24
Peak memory 260884 kb
Host smart-9f4d00f4-9271-419d-8ecc-38ae503f531f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178548907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me
m_walk.1178548907
Directory /workspace/2.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.416198830
Short name T314
Test name
Test status
Simulation time 113272900 ps
CPU time 19.01 seconds
Started Jun 09 01:27:18 PM PDT 24
Finished Jun 09 01:27:37 PM PDT 24
Peak memory 261052 kb
Host smart-6783d7d7-e6ec-46c0-801f-c20301a6139e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416198830 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.416198830
Directory /workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3902164328
Short name T1104
Test name
Test status
Simulation time 13373200 ps
CPU time 13.07 seconds
Started Jun 09 01:27:11 PM PDT 24
Finished Jun 09 01:27:25 PM PDT 24
Peak memory 252916 kb
Host smart-055b6bee-033d-4922-84e1-1caad62acf13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902164328 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.3902164328
Directory /workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2949962347
Short name T1162
Test name
Test status
Simulation time 55604500 ps
CPU time 15.77 seconds
Started Jun 09 01:27:11 PM PDT 24
Finished Jun 09 01:27:28 PM PDT 24
Peak memory 252988 kb
Host smart-57129d61-203d-44cb-94e3-a35cae8b423e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949962347 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.2949962347
Directory /workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.187328173
Short name T292
Test name
Test status
Simulation time 101411400 ps
CPU time 19.71 seconds
Started Jun 09 01:27:11 PM PDT 24
Finished Jun 09 01:27:31 PM PDT 24
Peak memory 263736 kb
Host smart-6950114f-6722-4949-8a3c-30cc876d0434
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187328173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.187328173
Directory /workspace/2.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.507158993
Short name T371
Test name
Test status
Simulation time 650534400 ps
CPU time 916.62 seconds
Started Jun 09 01:27:12 PM PDT 24
Finished Jun 09 01:42:29 PM PDT 24
Peak memory 263676 kb
Host smart-64df3b6f-2e98-4652-a6d8-561425656542
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507158993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_
tl_intg_err.507158993
Directory /workspace/2.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3830066019
Short name T1236
Test name
Test status
Simulation time 23456000 ps
CPU time 13.36 seconds
Started Jun 09 01:28:38 PM PDT 24
Finished Jun 09 01:28:52 PM PDT 24
Peak memory 261068 kb
Host smart-0b7d6c1d-042f-4806-ac45-0615524911c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830066019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.
3830066019
Directory /workspace/20.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2989301396
Short name T1170
Test name
Test status
Simulation time 28959500 ps
CPU time 13.58 seconds
Started Jun 09 01:28:38 PM PDT 24
Finished Jun 09 01:28:52 PM PDT 24
Peak memory 261056 kb
Host smart-6bedfb37-a5ad-4b26-b454-b677f0b1f235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989301396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.
2989301396
Directory /workspace/21.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1175657090
Short name T345
Test name
Test status
Simulation time 51103800 ps
CPU time 13.35 seconds
Started Jun 09 01:28:37 PM PDT 24
Finished Jun 09 01:28:50 PM PDT 24
Peak memory 261088 kb
Host smart-60574af1-3164-4506-936d-d19f0364f8bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175657090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.
1175657090
Directory /workspace/22.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.239376519
Short name T1224
Test name
Test status
Simulation time 31246800 ps
CPU time 13.42 seconds
Started Jun 09 01:28:41 PM PDT 24
Finished Jun 09 01:28:55 PM PDT 24
Peak memory 261068 kb
Host smart-e48e1504-efc7-4b58-8111-a89a3569c828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239376519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.239376519
Directory /workspace/24.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1425062942
Short name T1173
Test name
Test status
Simulation time 28966400 ps
CPU time 13.25 seconds
Started Jun 09 01:28:40 PM PDT 24
Finished Jun 09 01:28:54 PM PDT 24
Peak memory 261088 kb
Host smart-deb3d7c3-f74f-49de-a401-aee359491a6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425062942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.
1425062942
Directory /workspace/25.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.495840874
Short name T1122
Test name
Test status
Simulation time 15293500 ps
CPU time 13.34 seconds
Started Jun 09 01:28:43 PM PDT 24
Finished Jun 09 01:28:56 PM PDT 24
Peak memory 260896 kb
Host smart-db5311a4-47a3-4ab7-8a6f-e7b4a7f576fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495840874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.495840874
Directory /workspace/26.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2673425801
Short name T1103
Test name
Test status
Simulation time 99939000 ps
CPU time 13.13 seconds
Started Jun 09 01:28:43 PM PDT 24
Finished Jun 09 01:28:56 PM PDT 24
Peak memory 261072 kb
Host smart-924087b0-9258-4690-a481-0628ff917b6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673425801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.
2673425801
Directory /workspace/27.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2945202836
Short name T1240
Test name
Test status
Simulation time 44899200 ps
CPU time 13.29 seconds
Started Jun 09 01:28:44 PM PDT 24
Finished Jun 09 01:28:57 PM PDT 24
Peak memory 261200 kb
Host smart-5eaa109d-af82-45ed-84c9-f4b6bf3e6c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945202836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.
2945202836
Directory /workspace/28.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3549843308
Short name T343
Test name
Test status
Simulation time 24774800 ps
CPU time 13.29 seconds
Started Jun 09 01:28:44 PM PDT 24
Finished Jun 09 01:28:57 PM PDT 24
Peak memory 261208 kb
Host smart-2e9186c3-d29f-4ed8-80f1-11a0ec4688d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549843308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.
3549843308
Directory /workspace/29.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2918952078
Short name T1110
Test name
Test status
Simulation time 482732200 ps
CPU time 29.91 seconds
Started Jun 09 01:27:16 PM PDT 24
Finished Jun 09 01:27:46 PM PDT 24
Peak memory 260972 kb
Host smart-f7cd8e5a-2b60-4443-a083-fde65739bab4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918952078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_aliasing.2918952078
Directory /workspace/3.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1252404605
Short name T1188
Test name
Test status
Simulation time 337889000 ps
CPU time 37.29 seconds
Started Jun 09 01:27:17 PM PDT 24
Finished Jun 09 01:27:54 PM PDT 24
Peak memory 261104 kb
Host smart-f0710c8d-6dc8-4071-9ca3-1718a98abf65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252404605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_bit_bash.1252404605
Directory /workspace/3.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3763545720
Short name T1156
Test name
Test status
Simulation time 50346200 ps
CPU time 25.81 seconds
Started Jun 09 01:27:17 PM PDT 24
Finished Jun 09 01:27:43 PM PDT 24
Peak memory 261100 kb
Host smart-65092dfa-a4a6-44ab-98c5-8aecbbaebd41
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763545720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_csr_hw_reset.3763545720
Directory /workspace/3.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1771768091
Short name T259
Test name
Test status
Simulation time 85983200 ps
CPU time 17.51 seconds
Started Jun 09 01:27:20 PM PDT 24
Finished Jun 09 01:27:38 PM PDT 24
Peak memory 277368 kb
Host smart-b544abe1-6953-4904-8940-58521f7fb286
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771768091 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.1771768091
Directory /workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3933870506
Short name T228
Test name
Test status
Simulation time 76452100 ps
CPU time 16.42 seconds
Started Jun 09 01:27:20 PM PDT 24
Finished Jun 09 01:27:37 PM PDT 24
Peak memory 261240 kb
Host smart-640d3261-269d-4f03-a3a0-a3c1aff77c7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933870506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_csr_rw.3933870506
Directory /workspace/3.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1756140897
Short name T1147
Test name
Test status
Simulation time 20266200 ps
CPU time 13.3 seconds
Started Jun 09 01:27:17 PM PDT 24
Finished Jun 09 01:27:30 PM PDT 24
Peak memory 261076 kb
Host smart-f1d50505-7848-4931-ab50-0c2be1b60d41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756140897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.1
756140897
Directory /workspace/3.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3434216423
Short name T1126
Test name
Test status
Simulation time 15026900 ps
CPU time 13.84 seconds
Started Jun 09 01:27:20 PM PDT 24
Finished Jun 09 01:27:34 PM PDT 24
Peak memory 261112 kb
Host smart-e2a74334-bb49-407a-ba4f-f21a5a3fb2d6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434216423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me
m_walk.3434216423
Directory /workspace/3.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3158277409
Short name T316
Test name
Test status
Simulation time 206935200 ps
CPU time 20.62 seconds
Started Jun 09 01:27:15 PM PDT 24
Finished Jun 09 01:27:36 PM PDT 24
Peak memory 262148 kb
Host smart-e18bba69-c494-4cbd-a55c-e7e23fd88e79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158277409 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.3158277409
Directory /workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1392805827
Short name T1096
Test name
Test status
Simulation time 40109600 ps
CPU time 15.85 seconds
Started Jun 09 01:27:18 PM PDT 24
Finished Jun 09 01:27:34 PM PDT 24
Peak memory 252940 kb
Host smart-ced8a585-234a-494e-ad8f-7dcbf5dfb540
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392805827 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.1392805827
Directory /workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.582898778
Short name T1202
Test name
Test status
Simulation time 17964700 ps
CPU time 15.78 seconds
Started Jun 09 01:27:16 PM PDT 24
Finished Jun 09 01:27:32 PM PDT 24
Peak memory 252908 kb
Host smart-6979a486-0625-46c2-9bd3-3e1afabc870a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582898778 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.582898778
Directory /workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3521456380
Short name T1150
Test name
Test status
Simulation time 684593300 ps
CPU time 459.14 seconds
Started Jun 09 01:27:17 PM PDT 24
Finished Jun 09 01:34:56 PM PDT 24
Peak memory 263736 kb
Host smart-8100e611-8872-4715-a208-f509a7e44e03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521456380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl
_tl_intg_err.3521456380
Directory /workspace/3.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.817406223
Short name T284
Test name
Test status
Simulation time 30363500 ps
CPU time 13.36 seconds
Started Jun 09 01:28:45 PM PDT 24
Finished Jun 09 01:28:58 PM PDT 24
Peak memory 261072 kb
Host smart-aea11e59-31f0-43e5-8dfa-5a7e3a8f6111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817406223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.817406223
Directory /workspace/30.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3484175018
Short name T1218
Test name
Test status
Simulation time 47238500 ps
CPU time 13.54 seconds
Started Jun 09 01:28:43 PM PDT 24
Finished Jun 09 01:28:57 PM PDT 24
Peak memory 261216 kb
Host smart-ce005e7a-91e7-4373-9874-933ee0b80ebf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484175018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.
3484175018
Directory /workspace/31.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3920344755
Short name T344
Test name
Test status
Simulation time 19112500 ps
CPU time 13.24 seconds
Started Jun 09 01:28:46 PM PDT 24
Finished Jun 09 01:28:59 PM PDT 24
Peak memory 261068 kb
Host smart-65be076c-766b-41fe-8258-2d7875cdac83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920344755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.
3920344755
Directory /workspace/32.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.231836613
Short name T1151
Test name
Test status
Simulation time 66894500 ps
CPU time 13.21 seconds
Started Jun 09 01:28:43 PM PDT 24
Finished Jun 09 01:28:57 PM PDT 24
Peak memory 261204 kb
Host smart-693bd36c-a2ea-44f0-a8fe-d9c556928d4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231836613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.231836613
Directory /workspace/33.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2732907643
Short name T1164
Test name
Test status
Simulation time 34207700 ps
CPU time 13.38 seconds
Started Jun 09 01:28:52 PM PDT 24
Finished Jun 09 01:29:05 PM PDT 24
Peak memory 261072 kb
Host smart-36846c7a-7dd2-44e4-b46d-42c6ab44d423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732907643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.
2732907643
Directory /workspace/34.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3787004865
Short name T1198
Test name
Test status
Simulation time 58756000 ps
CPU time 13.43 seconds
Started Jun 09 01:28:51 PM PDT 24
Finished Jun 09 01:29:04 PM PDT 24
Peak memory 261140 kb
Host smart-7edac3cd-e967-421e-b50e-c7ada58a476b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787004865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.
3787004865
Directory /workspace/35.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3822990898
Short name T341
Test name
Test status
Simulation time 73014600 ps
CPU time 13.44 seconds
Started Jun 09 01:28:52 PM PDT 24
Finished Jun 09 01:29:06 PM PDT 24
Peak memory 261052 kb
Host smart-c5d0611f-a50d-4079-941b-197854085183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822990898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.
3822990898
Directory /workspace/36.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3293902888
Short name T1171
Test name
Test status
Simulation time 156281800 ps
CPU time 13.27 seconds
Started Jun 09 01:28:51 PM PDT 24
Finished Jun 09 01:29:04 PM PDT 24
Peak memory 261056 kb
Host smart-99eefcbe-fe3c-448b-bfb3-a4d526693736
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293902888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.
3293902888
Directory /workspace/37.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1128758140
Short name T1127
Test name
Test status
Simulation time 29857700 ps
CPU time 13.34 seconds
Started Jun 09 01:28:51 PM PDT 24
Finished Jun 09 01:29:05 PM PDT 24
Peak memory 261204 kb
Host smart-01b65139-0083-4574-88ec-eb5618ce306f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128758140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.
1128758140
Directory /workspace/38.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2495911604
Short name T1183
Test name
Test status
Simulation time 17841200 ps
CPU time 13.43 seconds
Started Jun 09 01:28:50 PM PDT 24
Finished Jun 09 01:29:04 PM PDT 24
Peak memory 261140 kb
Host smart-c5aa72ab-5e72-4021-ab1d-895d10d4ae33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495911604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.
2495911604
Directory /workspace/39.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.913491334
Short name T1193
Test name
Test status
Simulation time 3479465900 ps
CPU time 42.44 seconds
Started Jun 09 01:27:21 PM PDT 24
Finished Jun 09 01:28:04 PM PDT 24
Peak memory 261140 kb
Host smart-6100d07d-1aa3-4b3c-81cd-bc47fb237f83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913491334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_aliasing.913491334
Directory /workspace/4.flash_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2133844686
Short name T1144
Test name
Test status
Simulation time 1150179600 ps
CPU time 44.11 seconds
Started Jun 09 01:27:22 PM PDT 24
Finished Jun 09 01:28:06 PM PDT 24
Peak memory 261244 kb
Host smart-186158fb-452d-4b7d-a193-1a2e4d6c806e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133844686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_csr_bit_bash.2133844686
Directory /workspace/4.flash_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.273865061
Short name T1187
Test name
Test status
Simulation time 154767700 ps
CPU time 45.89 seconds
Started Jun 09 01:27:23 PM PDT 24
Finished Jun 09 01:28:09 PM PDT 24
Peak memory 261248 kb
Host smart-10ce5796-468f-4844-aa5a-89adf1b3b5d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273865061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.flash_ctrl_csr_hw_reset.273865061
Directory /workspace/4.flash_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.124836924
Short name T1181
Test name
Test status
Simulation time 188502200 ps
CPU time 17.86 seconds
Started Jun 09 01:27:26 PM PDT 24
Finished Jun 09 01:27:44 PM PDT 24
Peak memory 271968 kb
Host smart-dbe2959f-c49e-46ae-8594-03d2df1b26e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124836924 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.124836924
Directory /workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3552337823
Short name T1116
Test name
Test status
Simulation time 201194200 ps
CPU time 16.48 seconds
Started Jun 09 01:27:21 PM PDT 24
Finished Jun 09 01:27:38 PM PDT 24
Peak memory 263620 kb
Host smart-9b3070cd-baa3-486d-826b-97cde8963bd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552337823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_csr_rw.3552337823
Directory /workspace/4.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2566607425
Short name T1172
Test name
Test status
Simulation time 15517600 ps
CPU time 13.37 seconds
Started Jun 09 01:27:23 PM PDT 24
Finished Jun 09 01:27:37 PM PDT 24
Peak memory 260936 kb
Host smart-d48d317b-68c5-4fb2-8804-03b1e0dadf45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566607425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2
566607425
Directory /workspace/4.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.171002568
Short name T263
Test name
Test status
Simulation time 52774200 ps
CPU time 13.37 seconds
Started Jun 09 01:27:24 PM PDT 24
Finished Jun 09 01:27:37 PM PDT 24
Peak memory 262652 kb
Host smart-fa67e947-3da8-42d8-873f-b35f34b415bb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171002568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_mem_partial_access.171002568
Directory /workspace/4.flash_ctrl_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2559019950
Short name T1095
Test name
Test status
Simulation time 24054100 ps
CPU time 13.1 seconds
Started Jun 09 01:27:23 PM PDT 24
Finished Jun 09 01:27:36 PM PDT 24
Peak memory 261128 kb
Host smart-a00860c2-64a9-4748-bee2-39b3596cc1eb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559019950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me
m_walk.2559019950
Directory /workspace/4.flash_ctrl_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3856507472
Short name T1121
Test name
Test status
Simulation time 196852700 ps
CPU time 18.01 seconds
Started Jun 09 01:27:23 PM PDT 24
Finished Jun 09 01:27:41 PM PDT 24
Peak memory 262672 kb
Host smart-6714096e-e869-4241-9ddf-47fd24a2b09d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856507472 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.3856507472
Directory /workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.306000058
Short name T1238
Test name
Test status
Simulation time 40170500 ps
CPU time 15.81 seconds
Started Jun 09 01:27:21 PM PDT 24
Finished Jun 09 01:27:37 PM PDT 24
Peak memory 253156 kb
Host smart-0f853951-c394-48ab-a82a-0412e03d98bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306000058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.306000058
Directory /workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3150484647
Short name T1229
Test name
Test status
Simulation time 24898500 ps
CPU time 15.82 seconds
Started Jun 09 01:27:22 PM PDT 24
Finished Jun 09 01:27:38 PM PDT 24
Peak memory 252948 kb
Host smart-90a31ca7-dcfb-4c75-8848-5055f617fd81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150484647 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.3150484647
Directory /workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.756995575
Short name T285
Test name
Test status
Simulation time 393865600 ps
CPU time 20.53 seconds
Started Jun 09 01:27:22 PM PDT 24
Finished Jun 09 01:27:43 PM PDT 24
Peak memory 263744 kb
Host smart-3167c68a-6135-43dc-af02-70dc05022fd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756995575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.756995575
Directory /workspace/4.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1910240310
Short name T229
Test name
Test status
Simulation time 727987300 ps
CPU time 381.64 seconds
Started Jun 09 01:27:23 PM PDT 24
Finished Jun 09 01:33:44 PM PDT 24
Peak memory 263716 kb
Host smart-f093ef9c-119f-4cbe-af9e-1e791bd6edea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910240310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_tl_intg_err.1910240310
Directory /workspace/4.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2721039023
Short name T1161
Test name
Test status
Simulation time 17024500 ps
CPU time 13.26 seconds
Started Jun 09 01:28:50 PM PDT 24
Finished Jun 09 01:29:03 PM PDT 24
Peak memory 261088 kb
Host smart-76e58b50-b623-43a1-b783-28a835427e3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721039023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.
2721039023
Directory /workspace/40.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2230269065
Short name T1113
Test name
Test status
Simulation time 15473100 ps
CPU time 13.61 seconds
Started Jun 09 01:28:49 PM PDT 24
Finished Jun 09 01:29:03 PM PDT 24
Peak memory 261304 kb
Host smart-cbee066a-7836-4bf0-8a05-15acb9ec32a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230269065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.
2230269065
Directory /workspace/41.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3799961953
Short name T1197
Test name
Test status
Simulation time 95994000 ps
CPU time 13.4 seconds
Started Jun 09 01:28:50 PM PDT 24
Finished Jun 09 01:29:04 PM PDT 24
Peak memory 260960 kb
Host smart-8b1026bc-d2b2-4251-ac58-fde6f5d021b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799961953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.
3799961953
Directory /workspace/42.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.4277225407
Short name T1220
Test name
Test status
Simulation time 55259000 ps
CPU time 13.42 seconds
Started Jun 09 01:28:55 PM PDT 24
Finished Jun 09 01:29:09 PM PDT 24
Peak memory 261152 kb
Host smart-4ce4f49a-0305-4d22-86df-55556e34cd1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277225407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.
4277225407
Directory /workspace/43.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1025111829
Short name T1138
Test name
Test status
Simulation time 31696200 ps
CPU time 13.64 seconds
Started Jun 09 01:28:53 PM PDT 24
Finished Jun 09 01:29:07 PM PDT 24
Peak memory 261084 kb
Host smart-8b1f7454-7f3f-4026-94cd-a3c8a9ca3ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025111829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.
1025111829
Directory /workspace/44.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3426022461
Short name T339
Test name
Test status
Simulation time 54548600 ps
CPU time 13.44 seconds
Started Jun 09 01:28:53 PM PDT 24
Finished Jun 09 01:29:07 PM PDT 24
Peak memory 261084 kb
Host smart-d7bfed35-58e7-4cb7-b9f1-f1ebe6ccc68b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426022461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.
3426022461
Directory /workspace/45.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3634051392
Short name T1167
Test name
Test status
Simulation time 41850700 ps
CPU time 13.77 seconds
Started Jun 09 01:28:53 PM PDT 24
Finished Jun 09 01:29:07 PM PDT 24
Peak memory 261056 kb
Host smart-d6f0ef59-c0c9-44eb-924a-c96eb66a7517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634051392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.
3634051392
Directory /workspace/46.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.4068997717
Short name T1114
Test name
Test status
Simulation time 53635400 ps
CPU time 13.37 seconds
Started Jun 09 01:28:54 PM PDT 24
Finished Jun 09 01:29:07 PM PDT 24
Peak memory 261124 kb
Host smart-45dbf5f2-75eb-4bdb-a77c-6cb8a788aca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068997717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.
4068997717
Directory /workspace/47.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3680373388
Short name T1140
Test name
Test status
Simulation time 16504200 ps
CPU time 13.31 seconds
Started Jun 09 01:28:55 PM PDT 24
Finished Jun 09 01:29:08 PM PDT 24
Peak memory 261136 kb
Host smart-efd0612d-484a-4774-b14d-de5988a190f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680373388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.
3680373388
Directory /workspace/48.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3615773121
Short name T1160
Test name
Test status
Simulation time 52521500 ps
CPU time 13.49 seconds
Started Jun 09 01:28:55 PM PDT 24
Finished Jun 09 01:29:08 PM PDT 24
Peak memory 261148 kb
Host smart-54a375e7-4615-45b9-8195-d1734319f035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615773121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.
3615773121
Directory /workspace/49.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2079511434
Short name T1185
Test name
Test status
Simulation time 197857500 ps
CPU time 19.42 seconds
Started Jun 09 01:27:27 PM PDT 24
Finished Jun 09 01:27:46 PM PDT 24
Peak memory 271452 kb
Host smart-3edfcddd-6d9c-46c3-a729-12379d0d3a1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079511434 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.2079511434
Directory /workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3290925934
Short name T1204
Test name
Test status
Simulation time 572235100 ps
CPU time 14.32 seconds
Started Jun 09 01:27:30 PM PDT 24
Finished Jun 09 01:27:45 PM PDT 24
Peak memory 263848 kb
Host smart-ea5e00eb-8849-47c7-a3f1-8f3589bf378f
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290925934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_csr_rw.3290925934
Directory /workspace/5.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2180361759
Short name T1189
Test name
Test status
Simulation time 17110900 ps
CPU time 13.51 seconds
Started Jun 09 01:27:27 PM PDT 24
Finished Jun 09 01:27:41 PM PDT 24
Peak memory 261084 kb
Host smart-b85ca1ac-6fbb-4631-a529-2bf32b2b96fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180361759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2
180361759
Directory /workspace/5.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2606562925
Short name T1169
Test name
Test status
Simulation time 218273200 ps
CPU time 21.87 seconds
Started Jun 09 01:27:26 PM PDT 24
Finished Jun 09 01:27:49 PM PDT 24
Peak memory 262588 kb
Host smart-d679df42-1cbd-4f95-9b39-fc987a6c4f24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606562925 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.2606562925
Directory /workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4052820932
Short name T1208
Test name
Test status
Simulation time 58027300 ps
CPU time 15.36 seconds
Started Jun 09 01:27:26 PM PDT 24
Finished Jun 09 01:27:42 PM PDT 24
Peak memory 253284 kb
Host smart-f9e3ede8-ef30-4c63-ad1b-d80035858654
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052820932 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.4052820932
Directory /workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2009571977
Short name T1112
Test name
Test status
Simulation time 37484000 ps
CPU time 15.27 seconds
Started Jun 09 01:27:28 PM PDT 24
Finished Jun 09 01:27:44 PM PDT 24
Peak memory 253052 kb
Host smart-073966c2-44af-4e89-9e42-4f171ecb6a2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009571977 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.2009571977
Directory /workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2646382404
Short name T1237
Test name
Test status
Simulation time 75232200 ps
CPU time 16.12 seconds
Started Jun 09 01:27:28 PM PDT 24
Finished Jun 09 01:27:45 PM PDT 24
Peak memory 263744 kb
Host smart-4abd312b-50f0-475d-89f1-ccced793c293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646382404 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.2
646382404
Directory /workspace/5.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3403335469
Short name T1154
Test name
Test status
Simulation time 95393800 ps
CPU time 14.88 seconds
Started Jun 09 01:27:34 PM PDT 24
Finished Jun 09 01:27:49 PM PDT 24
Peak memory 263756 kb
Host smart-9acde266-9c44-4b0c-aa5b-e12de57aa77b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403335469 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.3403335469
Directory /workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3562444384
Short name T1215
Test name
Test status
Simulation time 99882500 ps
CPU time 17.77 seconds
Started Jun 09 01:27:33 PM PDT 24
Finished Jun 09 01:27:51 PM PDT 24
Peak memory 263648 kb
Host smart-4f72a293-11a2-46a1-9f9b-81b5cadd649e
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562444384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_csr_rw.3562444384
Directory /workspace/6.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1360740373
Short name T1203
Test name
Test status
Simulation time 14732900 ps
CPU time 13.18 seconds
Started Jun 09 01:27:35 PM PDT 24
Finished Jun 09 01:27:48 PM PDT 24
Peak memory 261040 kb
Host smart-d3329c4d-1ea4-4d5b-b749-b302d7e05c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360740373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.1
360740373
Directory /workspace/6.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3115716496
Short name T1234
Test name
Test status
Simulation time 426272200 ps
CPU time 18.34 seconds
Started Jun 09 01:27:33 PM PDT 24
Finished Jun 09 01:27:52 PM PDT 24
Peak memory 262472 kb
Host smart-f5fc759c-b930-4693-93f6-b6a7282f2e2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115716496 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.3115716496
Directory /workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.697220799
Short name T1101
Test name
Test status
Simulation time 18426900 ps
CPU time 15.52 seconds
Started Jun 09 01:27:30 PM PDT 24
Finished Jun 09 01:27:45 PM PDT 24
Peak memory 253196 kb
Host smart-3db1f3fb-3419-46b4-89de-cb7fcb0195b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697220799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.697220799
Directory /workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1954809823
Short name T1180
Test name
Test status
Simulation time 32199200 ps
CPU time 13.12 seconds
Started Jun 09 01:27:33 PM PDT 24
Finished Jun 09 01:27:47 PM PDT 24
Peak memory 252868 kb
Host smart-4b75678f-5894-4df0-8ec8-0a89728f990d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954809823 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.1954809823
Directory /workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1700837140
Short name T1199
Test name
Test status
Simulation time 84844500 ps
CPU time 16.01 seconds
Started Jun 09 01:27:32 PM PDT 24
Finished Jun 09 01:27:49 PM PDT 24
Peak memory 263712 kb
Host smart-21de28de-5392-4c5d-a555-4ad3953ea560
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700837140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.1
700837140
Directory /workspace/6.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3350835539
Short name T55
Test name
Test status
Simulation time 656131100 ps
CPU time 379.48 seconds
Started Jun 09 01:27:29 PM PDT 24
Finished Jun 09 01:33:48 PM PDT 24
Peak memory 263648 kb
Host smart-f2ad28cd-8729-4a99-804c-a56772af3efd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350835539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl
_tl_intg_err.3350835539
Directory /workspace/6.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1200065389
Short name T226
Test name
Test status
Simulation time 189624300 ps
CPU time 17.79 seconds
Started Jun 09 01:27:42 PM PDT 24
Finished Jun 09 01:28:00 PM PDT 24
Peak memory 271852 kb
Host smart-3a0eaf07-582c-40ba-82e3-92fd46f279d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200065389 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.1200065389
Directory /workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.476228676
Short name T1233
Test name
Test status
Simulation time 229655600 ps
CPU time 17.63 seconds
Started Jun 09 01:27:38 PM PDT 24
Finished Jun 09 01:27:56 PM PDT 24
Peak memory 263644 kb
Host smart-3d36c4ce-6630-408c-ab46-e8caaa547ecc
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476228676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_csr_rw.476228676
Directory /workspace/7.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2266783072
Short name T1174
Test name
Test status
Simulation time 79392500 ps
CPU time 13.48 seconds
Started Jun 09 01:27:32 PM PDT 24
Finished Jun 09 01:27:46 PM PDT 24
Peak memory 261020 kb
Host smart-7ace1011-0d67-4433-b40c-273a08fd95ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266783072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.2
266783072
Directory /workspace/7.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.4152657829
Short name T1239
Test name
Test status
Simulation time 686905000 ps
CPU time 34.27 seconds
Started Jun 09 01:27:39 PM PDT 24
Finished Jun 09 01:28:13 PM PDT 24
Peak memory 261240 kb
Host smart-0a9c9dd3-8a51-48f4-8cf0-5f728490cacf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152657829 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.4152657829
Directory /workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1217308669
Short name T1182
Test name
Test status
Simulation time 15909600 ps
CPU time 15.88 seconds
Started Jun 09 01:27:36 PM PDT 24
Finished Jun 09 01:27:52 PM PDT 24
Peak memory 252924 kb
Host smart-845f00e5-57a8-4bfc-a682-1f743a389584
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217308669 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.1217308669
Directory /workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1717289871
Short name T1097
Test name
Test status
Simulation time 35563000 ps
CPU time 15.29 seconds
Started Jun 09 01:27:34 PM PDT 24
Finished Jun 09 01:27:49 PM PDT 24
Peak memory 253068 kb
Host smart-8b65c2fe-cb41-441e-b670-65bdc036e0fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717289871 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.1717289871
Directory /workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2223822651
Short name T289
Test name
Test status
Simulation time 555947700 ps
CPU time 18.49 seconds
Started Jun 09 01:27:32 PM PDT 24
Finished Jun 09 01:27:50 PM PDT 24
Peak memory 263948 kb
Host smart-11565862-6eb0-4dda-9052-3a5108968597
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223822651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2
223822651
Directory /workspace/7.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3825986147
Short name T295
Test name
Test status
Simulation time 862623500 ps
CPU time 899.86 seconds
Started Jun 09 01:27:35 PM PDT 24
Finished Jun 09 01:42:35 PM PDT 24
Peak memory 263764 kb
Host smart-f7211c98-6f98-43b2-a4e6-1c969e0ff91d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825986147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl
_tl_intg_err.3825986147
Directory /workspace/7.flash_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1916657846
Short name T319
Test name
Test status
Simulation time 50839900 ps
CPU time 14.5 seconds
Started Jun 09 01:27:49 PM PDT 24
Finished Jun 09 01:28:04 PM PDT 24
Peak memory 270288 kb
Host smart-b7fb9ec7-dea7-4faf-a959-6d5e0eccd45a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916657846 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.1916657846
Directory /workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3995397213
Short name T276
Test name
Test status
Simulation time 32280200 ps
CPU time 16.48 seconds
Started Jun 09 01:27:50 PM PDT 24
Finished Jun 09 01:28:07 PM PDT 24
Peak memory 263600 kb
Host smart-ba9aa753-9280-4c2e-b7cd-1d841f30fb74
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995397213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_csr_rw.3995397213
Directory /workspace/8.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.672372531
Short name T1179
Test name
Test status
Simulation time 53866000 ps
CPU time 13.4 seconds
Started Jun 09 01:27:47 PM PDT 24
Finished Jun 09 01:28:01 PM PDT 24
Peak memory 261056 kb
Host smart-c3d86da5-e51f-426c-a921-3c20877efe8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672372531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.672372531
Directory /workspace/8.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.28159904
Short name T1124
Test name
Test status
Simulation time 174724800 ps
CPU time 35.55 seconds
Started Jun 09 01:27:49 PM PDT 24
Finished Jun 09 01:28:25 PM PDT 24
Peak memory 262288 kb
Host smart-6e36ca5f-879c-4e44-9975-71047154b21c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28159904 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.28159904
Directory /workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1662617598
Short name T1168
Test name
Test status
Simulation time 24779200 ps
CPU time 15.39 seconds
Started Jun 09 01:27:48 PM PDT 24
Finished Jun 09 01:28:04 PM PDT 24
Peak memory 253060 kb
Host smart-31e43c98-b253-46d0-b766-31e0c31765b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662617598 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.1662617598
Directory /workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.880909937
Short name T1115
Test name
Test status
Simulation time 19227700 ps
CPU time 12.99 seconds
Started Jun 09 01:27:49 PM PDT 24
Finished Jun 09 01:28:03 PM PDT 24
Peak memory 253000 kb
Host smart-8c06fa51-dfc4-4396-a0b1-4e946cc305d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880909937 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.880909937
Directory /workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2563099153
Short name T257
Test name
Test status
Simulation time 134084300 ps
CPU time 16.12 seconds
Started Jun 09 01:27:41 PM PDT 24
Finished Jun 09 01:27:58 PM PDT 24
Peak memory 263752 kb
Host smart-6af00f2b-fb6b-4308-bb4e-47db2a64a1aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563099153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.2
563099153
Directory /workspace/8.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2215444600
Short name T1192
Test name
Test status
Simulation time 69372500 ps
CPU time 13.98 seconds
Started Jun 09 01:27:54 PM PDT 24
Finished Jun 09 01:28:08 PM PDT 24
Peak memory 261104 kb
Host smart-774949d4-4150-4efd-b50d-840c120434d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215444600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_csr_rw.2215444600
Directory /workspace/9.flash_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1750828497
Short name T282
Test name
Test status
Simulation time 16952300 ps
CPU time 13.2 seconds
Started Jun 09 01:27:57 PM PDT 24
Finished Jun 09 01:28:10 PM PDT 24
Peak memory 261064 kb
Host smart-b7363e1c-8ba4-4e1a-aa1f-08396841fd9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750828497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1
750828497
Directory /workspace/9.flash_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.647368502
Short name T1123
Test name
Test status
Simulation time 1274890200 ps
CPU time 35.74 seconds
Started Jun 09 01:27:54 PM PDT 24
Finished Jun 09 01:28:30 PM PDT 24
Peak memory 261292 kb
Host smart-d5cb55d2-49b0-47c8-b45f-f5a36f1de7c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647368502 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.647368502
Directory /workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.156860160
Short name T1117
Test name
Test status
Simulation time 17813900 ps
CPU time 15.54 seconds
Started Jun 09 01:27:54 PM PDT 24
Finished Jun 09 01:28:10 PM PDT 24
Peak memory 253060 kb
Host smart-07301a4c-946a-4ace-b115-fdf480bda37a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156860160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.156860160
Directory /workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1558346594
Short name T1206
Test name
Test status
Simulation time 39465300 ps
CPU time 15.67 seconds
Started Jun 09 01:27:55 PM PDT 24
Finished Jun 09 01:28:10 PM PDT 24
Peak memory 252952 kb
Host smart-f475c01d-c181-4cea-8bb9-2260642aee15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558346594 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.1558346594
Directory /workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1154400714
Short name T1207
Test name
Test status
Simulation time 114907000 ps
CPU time 16.05 seconds
Started Jun 09 01:27:55 PM PDT 24
Finished Jun 09 01:28:11 PM PDT 24
Peak memory 262796 kb
Host smart-655e7d9b-c075-4808-bd31-243e79885e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154400714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.1
154400714
Directory /workspace/9.flash_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.flash_ctrl_alert_test.2732899167
Short name T868
Test name
Test status
Simulation time 77814800 ps
CPU time 13.81 seconds
Started Jun 09 02:42:15 PM PDT 24
Finished Jun 09 02:42:29 PM PDT 24
Peak memory 265684 kb
Host smart-d35209a4-dba2-4b45-830d-6e52400cb393
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732899167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.2
732899167
Directory /workspace/0.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.flash_ctrl_connect.2223645016
Short name T660
Test name
Test status
Simulation time 50221600 ps
CPU time 15.97 seconds
Started Jun 09 02:41:47 PM PDT 24
Finished Jun 09 02:42:03 PM PDT 24
Peak memory 284572 kb
Host smart-084b8232-e1ee-4aeb-89bc-89ea55345551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223645016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2223645016
Directory /workspace/0.flash_ctrl_connect/latest

Test location /workspace/coverage/default/0.flash_ctrl_derr_detect.378120194
Short name T860
Test name
Test status
Simulation time 123838300 ps
CPU time 102.26 seconds
Started Jun 09 02:41:40 PM PDT 24
Finished Jun 09 02:43:22 PM PDT 24
Peak memory 276124 kb
Host smart-4c003f13-3fb7-42a1-8953-2e1753613e09
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378120194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_derr_detect.378120194
Directory /workspace/0.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/0.flash_ctrl_erase_suspend.2991513222
Short name T127
Test name
Test status
Simulation time 21056318600 ps
CPU time 624.12 seconds
Started Jun 09 02:41:11 PM PDT 24
Finished Jun 09 02:51:36 PM PDT 24
Peak memory 263640 kb
Host smart-908b4fb0-0538-4e96-8ee5-55b85191297b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2991513222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.2991513222
Directory /workspace/0.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/0.flash_ctrl_fetch_code.2861965593
Short name T950
Test name
Test status
Simulation time 2287488300 ps
CPU time 24.02 seconds
Started Jun 09 02:41:15 PM PDT 24
Finished Jun 09 02:41:40 PM PDT 24
Peak memory 262700 kb
Host smart-c4561777-2630-4985-9222-6dcf515f090c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861965593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.2861965593
Directory /workspace/0.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/0.flash_ctrl_full_mem_access.3593773186
Short name T82
Test name
Test status
Simulation time 101740069900 ps
CPU time 4631.73 seconds
Started Jun 09 02:41:16 PM PDT 24
Finished Jun 09 03:58:29 PM PDT 24
Peak memory 265500 kb
Host smart-4993b2f2-f407-43d9-8a45-c48f01e3c5c0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593773186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_full_mem_access.3593773186
Directory /workspace/0.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/0.flash_ctrl_host_dir_rd.1456740837
Short name T392
Test name
Test status
Simulation time 115539900 ps
CPU time 45.59 seconds
Started Jun 09 02:41:07 PM PDT 24
Finished Jun 09 02:41:53 PM PDT 24
Peak memory 265676 kb
Host smart-f2f7b9d4-568d-4867-b552-82eb0395c04f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1456740837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.1456740837
Directory /workspace/0.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1613810903
Short name T305
Test name
Test status
Simulation time 10024614800 ps
CPU time 67.41 seconds
Started Jun 09 02:42:09 PM PDT 24
Finished Jun 09 02:43:16 PM PDT 24
Peak memory 299432 kb
Host smart-e4f8dae3-93f5-4fc1-9f57-3a0b21e945fa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613810903 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.1613810903
Directory /workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma.1379315108
Short name T819
Test name
Test status
Simulation time 110953992200 ps
CPU time 2096.26 seconds
Started Jun 09 02:41:13 PM PDT 24
Finished Jun 09 03:16:09 PM PDT 24
Peak memory 265356 kb
Host smart-24f20168-2b6f-47e5-98d4-d5189af43efb
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379315108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 0.flash_ctrl_hw_rma.1379315108
Directory /workspace/0.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.3210549245
Short name T135
Test name
Test status
Simulation time 160184583900 ps
CPU time 942.19 seconds
Started Jun 09 02:41:12 PM PDT 24
Finished Jun 09 02:56:54 PM PDT 24
Peak memory 264708 kb
Host smart-38e68c7f-51c2-4a9c-b34a-bfa7cf19344b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210549245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.flash_ctrl_hw_rma_reset.3210549245
Directory /workspace/0.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.1489049734
Short name T966
Test name
Test status
Simulation time 2818516900 ps
CPU time 75.06 seconds
Started Jun 09 02:41:12 PM PDT 24
Finished Jun 09 02:42:27 PM PDT 24
Peak memory 263320 kb
Host smart-693654b7-1534-4e3c-bcbe-dde3dec4d72a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489049734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_h
w_sec_otp.1489049734
Directory /workspace/0.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/0.flash_ctrl_integrity.460997941
Short name T274
Test name
Test status
Simulation time 15528337100 ps
CPU time 717.22 seconds
Started Jun 09 02:41:37 PM PDT 24
Finished Jun 09 02:53:34 PM PDT 24
Peak memory 338192 kb
Host smart-81a5de47-389c-4cd9-b6ca-63d11f8c773e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460997941 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.flash_ctrl_integrity.460997941
Directory /workspace/0.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd.1237976857
Short name T747
Test name
Test status
Simulation time 568127000 ps
CPU time 145.72 seconds
Started Jun 09 02:41:38 PM PDT 24
Finished Jun 09 02:44:04 PM PDT 24
Peak memory 294156 kb
Host smart-d4785e1d-f731-4688-b619-a710c179fe5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237976857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_intr_rd.1237976857
Directory /workspace/0.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.1403819770
Short name T844
Test name
Test status
Simulation time 12266255500 ps
CPU time 149.39 seconds
Started Jun 09 02:41:44 PM PDT 24
Finished Jun 09 02:44:14 PM PDT 24
Peak memory 294448 kb
Host smart-d88c0ae9-95c8-4329-8f6f-577145f0f18e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403819770 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.1403819770
Directory /workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/0.flash_ctrl_intr_wr.3230442173
Short name T862
Test name
Test status
Simulation time 2874613600 ps
CPU time 84.58 seconds
Started Jun 09 02:41:38 PM PDT 24
Finished Jun 09 02:43:03 PM PDT 24
Peak memory 260852 kb
Host smart-553cfaa5-cbac-4247-a22c-832f4ccef696
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230442173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_wr.3230442173
Directory /workspace/0.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/0.flash_ctrl_invalid_op.4262330049
Short name T888
Test name
Test status
Simulation time 1945392300 ps
CPU time 95.59 seconds
Started Jun 09 02:41:19 PM PDT 24
Finished Jun 09 02:42:55 PM PDT 24
Peak memory 260836 kb
Host smart-a12757e2-7662-49d3-92bb-70817637420e
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262330049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.4262330049
Directory /workspace/0.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_mid_op_rst.2483060564
Short name T126
Test name
Test status
Simulation time 3953869500 ps
CPU time 71.21 seconds
Started Jun 09 02:41:22 PM PDT 24
Finished Jun 09 02:42:34 PM PDT 24
Peak memory 260728 kb
Host smart-2571bcce-39fe-4e16-82ab-a77f579032a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483060564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2483060564
Directory /workspace/0.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/0.flash_ctrl_mp_regions.2330744523
Short name T821
Test name
Test status
Simulation time 17310514000 ps
CPU time 395.82 seconds
Started Jun 09 02:41:17 PM PDT 24
Finished Jun 09 02:47:53 PM PDT 24
Peak memory 275144 kb
Host smart-41929cae-33b9-4b92-bf64-f7d10431b8c7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330744523 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_mp_regions.2330744523
Directory /workspace/0.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/0.flash_ctrl_otp_reset.2631412152
Short name T570
Test name
Test status
Simulation time 71258400 ps
CPU time 129.72 seconds
Started Jun 09 02:41:23 PM PDT 24
Finished Jun 09 02:43:33 PM PDT 24
Peak memory 261216 kb
Host smart-def96744-43be-43e4-8377-3e11aea615a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631412152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ot
p_reset.2631412152
Directory /workspace/0.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_oversize_error.3148121207
Short name T583
Test name
Test status
Simulation time 7104657100 ps
CPU time 198.42 seconds
Started Jun 09 02:41:38 PM PDT 24
Finished Jun 09 02:44:57 PM PDT 24
Peak memory 295660 kb
Host smart-da914005-db00-452e-856a-d8b36d224753
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148121207 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.3148121207
Directory /workspace/0.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_arb.1188053466
Short name T861
Test name
Test status
Simulation time 1482582800 ps
CPU time 457.96 seconds
Started Jun 09 02:41:12 PM PDT 24
Finished Jun 09 02:48:50 PM PDT 24
Peak memory 263584 kb
Host smart-cab6dd10-f76a-462d-a1fb-2a1a6fd828a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1188053466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.1188053466
Directory /workspace/0.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.4004300272
Short name T245
Test name
Test status
Simulation time 15444800 ps
CPU time 14.39 seconds
Started Jun 09 02:42:06 PM PDT 24
Finished Jun 09 02:42:20 PM PDT 24
Peak memory 265952 kb
Host smart-699156a3-ea1a-4331-8750-92c1d62076e0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004300272 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.4004300272
Directory /workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/0.flash_ctrl_prog_reset.1109680946
Short name T641
Test name
Test status
Simulation time 9375290300 ps
CPU time 213.05 seconds
Started Jun 09 02:41:46 PM PDT 24
Finished Jun 09 02:45:19 PM PDT 24
Peak memory 260508 kb
Host smart-cb757af2-c1c6-4521-acd0-cc9d6aa640c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109680946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_res
et.1109680946
Directory /workspace/0.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/0.flash_ctrl_rand_ops.3679605372
Short name T106
Test name
Test status
Simulation time 831885100 ps
CPU time 1046.11 seconds
Started Jun 09 02:41:07 PM PDT 24
Finished Jun 09 02:58:33 PM PDT 24
Peak memory 286516 kb
Host smart-0068c835-92b8-41b0-8858-bfec2b394e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679605372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3679605372
Directory /workspace/0.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_buff_evict.1862463569
Short name T224
Test name
Test status
Simulation time 2050173600 ps
CPU time 256.83 seconds
Started Jun 09 02:41:09 PM PDT 24
Finished Jun 09 02:45:26 PM PDT 24
Peak memory 263080 kb
Host smart-a8e1fc03-a8cb-4385-a2dc-d1b18523d781
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1862463569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.1862463569
Directory /workspace/0.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_intg.2065197009
Short name T366
Test name
Test status
Simulation time 218327400 ps
CPU time 32.97 seconds
Started Jun 09 02:41:54 PM PDT 24
Finished Jun 09 02:42:27 PM PDT 24
Peak memory 276276 kb
Host smart-dad90863-1656-4d3a-ab03-34b7c079dc91
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065197009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_rd_intg.2065197009
Directory /workspace/0.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_rd_ooo.2901632589
Short name T84
Test name
Test status
Simulation time 217672100 ps
CPU time 46.58 seconds
Started Jun 09 02:42:12 PM PDT 24
Finished Jun 09 02:42:59 PM PDT 24
Peak memory 275732 kb
Host smart-363973f6-1d25-4e1f-abe1-471b231548f8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901632589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_rd_ooo.2901632589
Directory /workspace/0.flash_ctrl_rd_ooo/latest

Test location /workspace/coverage/default/0.flash_ctrl_re_evict.3849497721
Short name T707
Test name
Test status
Simulation time 120437400 ps
CPU time 36.05 seconds
Started Jun 09 02:41:49 PM PDT 24
Finished Jun 09 02:42:25 PM PDT 24
Peak memory 270820 kb
Host smart-4c492bd9-b79f-4c07-909a-3657d4964025
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849497721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_re_evict.3849497721
Directory /workspace/0.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep.3099286430
Short name T1075
Test name
Test status
Simulation time 53955000 ps
CPU time 14.3 seconds
Started Jun 09 02:41:22 PM PDT 24
Finished Jun 09 02:41:37 PM PDT 24
Peak memory 258688 kb
Host smart-b105b666-2408-44db-bd3f-bc54e4dd396a
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=3099286430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep
.3099286430
Directory /workspace/0.flash_ctrl_read_word_sweep/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.1221580653
Short name T1026
Test name
Test status
Simulation time 59022100 ps
CPU time 22.73 seconds
Started Jun 09 02:41:33 PM PDT 24
Finished Jun 09 02:41:56 PM PDT 24
Peak memory 265752 kb
Host smart-a1e9b876-a665-403f-9c38-540c3d41075a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221580653 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.1221580653
Directory /workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.1300001757
Short name T807
Test name
Test status
Simulation time 86399400 ps
CPU time 22.25 seconds
Started Jun 09 02:41:29 PM PDT 24
Finished Jun 09 02:41:52 PM PDT 24
Peak memory 265776 kb
Host smart-5f4bcfa6-a6b8-49b9-9ee2-16ad1cb9b004
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300001757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_read_word_sweep_serr.1300001757
Directory /workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro.1604491263
Short name T677
Test name
Test status
Simulation time 2351080200 ps
CPU time 165.72 seconds
Started Jun 09 02:41:21 PM PDT 24
Finished Jun 09 02:44:07 PM PDT 24
Peak memory 291872 kb
Host smart-f6bef861-c692-4320-9c2f-f38da156b2fa
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604491263 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_ro.1604491263
Directory /workspace/0.flash_ctrl_ro/latest

Test location /workspace/coverage/default/0.flash_ctrl_ro_serr.1166449656
Short name T806
Test name
Test status
Simulation time 5698537200 ps
CPU time 156.34 seconds
Started Jun 09 02:41:28 PM PDT 24
Finished Jun 09 02:44:04 PM PDT 24
Peak memory 282244 kb
Host smart-27e24dc7-7187-4be0-ba40-4de31dfb5109
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166449656 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.1166449656
Directory /workspace/0.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_derr.2113955722
Short name T177
Test name
Test status
Simulation time 3997844600 ps
CPU time 782.41 seconds
Started Jun 09 02:41:35 PM PDT 24
Finished Jun 09 02:54:38 PM PDT 24
Peak memory 339496 kb
Host smart-fd560a99-5ee7-4af4-b70f-52ebdc53b691
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113955722 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.flash_ctrl_rw_derr.2113955722
Directory /workspace/0.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict.318906863
Short name T43
Test name
Test status
Simulation time 33081600 ps
CPU time 31.49 seconds
Started Jun 09 02:41:43 PM PDT 24
Finished Jun 09 02:42:15 PM PDT 24
Peak memory 275808 kb
Host smart-ae1d190f-68a0-4b8c-899d-2b83cdf71035
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318906863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_rw_evict.318906863
Directory /workspace/0.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/0.flash_ctrl_rw_evict_all_en.1710463190
Short name T112
Test name
Test status
Simulation time 42546300 ps
CPU time 31.21 seconds
Started Jun 09 02:41:45 PM PDT 24
Finished Jun 09 02:42:16 PM PDT 24
Peak memory 276040 kb
Host smart-36a2f46f-fe0c-44f7-9028-785c99e8f46c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710463190 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.1710463190
Directory /workspace/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_address.4256839858
Short name T997
Test name
Test status
Simulation time 5307283100 ps
CPU time 112.97 seconds
Started Jun 09 02:41:35 PM PDT 24
Finished Jun 09 02:43:28 PM PDT 24
Peak memory 274000 kb
Host smart-72598eef-09d7-4bd8-a075-99a5dce825ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256839858 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 0.flash_ctrl_serr_address.4256839858
Directory /workspace/0.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/0.flash_ctrl_serr_counter.3200457998
Short name T723
Test name
Test status
Simulation time 4388791500 ps
CPU time 61.13 seconds
Started Jun 09 02:41:27 PM PDT 24
Finished Jun 09 02:42:28 PM PDT 24
Peak memory 275740 kb
Host smart-33c8fb76-89da-4e3b-8557-3aa5182e07ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200457998 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_serr_counter.3200457998
Directory /workspace/0.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke.2034832793
Short name T98
Test name
Test status
Simulation time 64935600 ps
CPU time 99.44 seconds
Started Jun 09 02:41:03 PM PDT 24
Finished Jun 09 02:42:43 PM PDT 24
Peak memory 270036 kb
Host smart-c6e67dbf-2e68-4389-b1ed-a0f4a9fb2f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034832793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.2034832793
Directory /workspace/0.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/0.flash_ctrl_smoke_hw.2039353519
Short name T855
Test name
Test status
Simulation time 27872700 ps
CPU time 26.54 seconds
Started Jun 09 02:41:03 PM PDT 24
Finished Jun 09 02:41:29 PM PDT 24
Peak memory 259844 kb
Host smart-74db1d02-fd44-4f18-9020-f1706431d296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039353519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.2039353519
Directory /workspace/0.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/0.flash_ctrl_stress_all.4266304318
Short name T749
Test name
Test status
Simulation time 1546831300 ps
CPU time 1568.24 seconds
Started Jun 09 02:41:50 PM PDT 24
Finished Jun 09 03:07:59 PM PDT 24
Peak memory 291444 kb
Host smart-ca36b626-aeb5-405b-80fb-95fda5e9c1a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266304318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stres
s_all.4266304318
Directory /workspace/0.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.flash_ctrl_sw_op.574586315
Short name T829
Test name
Test status
Simulation time 25474600 ps
CPU time 25.9 seconds
Started Jun 09 02:41:07 PM PDT 24
Finished Jun 09 02:41:34 PM PDT 24
Peak memory 262596 kb
Host smart-51bff3b7-2117-4b46-a118-95d55086a319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574586315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.574586315
Directory /workspace/0.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/0.flash_ctrl_wo.2163388920
Short name T405
Test name
Test status
Simulation time 8157422000 ps
CPU time 168.08 seconds
Started Jun 09 02:41:24 PM PDT 24
Finished Jun 09 02:44:13 PM PDT 24
Peak memory 260244 kb
Host smart-ff3dd093-55a3-4d1a-ad57-323eabff9d2a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163388920 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.flash_ctrl_wo.2163388920
Directory /workspace/0.flash_ctrl_wo/latest

Test location /workspace/coverage/default/0.flash_ctrl_wr_intg.470332954
Short name T11
Test name
Test status
Simulation time 155083900 ps
CPU time 14.82 seconds
Started Jun 09 02:41:54 PM PDT 24
Finished Jun 09 02:42:09 PM PDT 24
Peak memory 261212 kb
Host smart-958a08a0-bb90-4440-b5e7-c13098854692
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470332954 -assert nopostproc +UVM
_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wr_intg.470332954
Directory /workspace/0.flash_ctrl_wr_intg/latest

Test location /workspace/coverage/default/0.flash_ctrl_write_word_sweep.2227708152
Short name T852
Test name
Test status
Simulation time 240292000 ps
CPU time 16.63 seconds
Started Jun 09 02:41:22 PM PDT 24
Finished Jun 09 02:41:39 PM PDT 24
Peak memory 258872 kb
Host smart-78c6144b-d6a8-4e4d-bc01-ea6e756b1393
User root
Command /workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t
op/hw/dv/tools/sim.tcl +ntb_random_seed=2227708152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe
ep.2227708152
Directory /workspace/0.flash_ctrl_write_word_sweep/latest

Test location /workspace/coverage/default/1.flash_ctrl_access_after_disable.1289263586
Short name T60
Test name
Test status
Simulation time 17474900 ps
CPU time 13.38 seconds
Started Jun 09 02:43:04 PM PDT 24
Finished Jun 09 02:43:18 PM PDT 24
Peak memory 261832 kb
Host smart-f80c52ce-7c07-48d1-adde-605d3672d26a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289263586 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.1289263586
Directory /workspace/1.flash_ctrl_access_after_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_alert_test.227468600
Short name T1031
Test name
Test status
Simulation time 30631600 ps
CPU time 14.47 seconds
Started Jun 09 02:43:19 PM PDT 24
Finished Jun 09 02:43:33 PM PDT 24
Peak memory 258484 kb
Host smart-cec9e3ae-e9cf-400e-9020-2a1377889886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227468600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.227468600
Directory /workspace/1.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.flash_ctrl_config_regwen.4235355004
Short name T970
Test name
Test status
Simulation time 69395600 ps
CPU time 13.97 seconds
Started Jun 09 02:43:13 PM PDT 24
Finished Jun 09 02:43:28 PM PDT 24
Peak memory 265140 kb
Host smart-17fa28f1-2f47-44ca-97d0-9ca4b6141fdd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235355004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.flash_ctrl_config_regwen.4235355004
Directory /workspace/1.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.flash_ctrl_connect.4094521043
Short name T440
Test name
Test status
Simulation time 39387300 ps
CPU time 15.98 seconds
Started Jun 09 02:43:04 PM PDT 24
Finished Jun 09 02:43:20 PM PDT 24
Peak memory 284576 kb
Host smart-74db9342-f994-4433-8c02-5d536fca57c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094521043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.4094521043
Directory /workspace/1.flash_ctrl_connect/latest

Test location /workspace/coverage/default/1.flash_ctrl_disable.1936558617
Short name T681
Test name
Test status
Simulation time 22959300 ps
CPU time 21.8 seconds
Started Jun 09 02:43:02 PM PDT 24
Finished Jun 09 02:43:24 PM PDT 24
Peak memory 265404 kb
Host smart-c3ca77ab-4ce8-4760-95c8-525a6d73a0bd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936558617 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_disable.1936558617
Directory /workspace/1.flash_ctrl_disable/latest

Test location /workspace/coverage/default/1.flash_ctrl_erase_suspend.2457683896
Short name T446
Test name
Test status
Simulation time 12671497900 ps
CPU time 380.55 seconds
Started Jun 09 02:42:24 PM PDT 24
Finished Jun 09 02:48:45 PM PDT 24
Peak memory 263724 kb
Host smart-b5874ac8-9698-4a30-9ff8-30b95d57c089
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457683896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.2457683896
Directory /workspace/1.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_mp.3263507663
Short name T739
Test name
Test status
Simulation time 7411643000 ps
CPU time 2433.62 seconds
Started Jun 09 02:42:34 PM PDT 24
Finished Jun 09 03:23:08 PM PDT 24
Peak memory 265076 kb
Host smart-29e8351e-1594-4f6b-adca-5e34551960a9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263507663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_err
or_mp.3263507663
Directory /workspace/1.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_type.3747471323
Short name T202
Test name
Test status
Simulation time 492006700 ps
CPU time 2053.62 seconds
Started Jun 09 02:42:29 PM PDT 24
Finished Jun 09 03:16:43 PM PDT 24
Peak memory 262572 kb
Host smart-0cb95edb-863b-401e-98d6-f2afd247e8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747471323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.3747471323
Directory /workspace/1.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/1.flash_ctrl_error_prog_win.2020543462
Short name T701
Test name
Test status
Simulation time 1830915100 ps
CPU time 737.32 seconds
Started Jun 09 02:42:31 PM PDT 24
Finished Jun 09 02:54:48 PM PDT 24
Peak memory 274260 kb
Host smart-d87bf623-9606-4d23-83bb-96b69f202f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020543462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2020543462
Directory /workspace/1.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/1.flash_ctrl_fetch_code.2133029482
Short name T442
Test name
Test status
Simulation time 912471600 ps
CPU time 26.25 seconds
Started Jun 09 02:42:29 PM PDT 24
Finished Jun 09 02:42:55 PM PDT 24
Peak memory 262828 kb
Host smart-26a8d2ab-25f2-4d23-89f7-c80d423e737b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133029482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.2133029482
Directory /workspace/1.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/1.flash_ctrl_fs_sup.3428605012
Short name T911
Test name
Test status
Simulation time 315056400 ps
CPU time 41.71 seconds
Started Jun 09 02:43:05 PM PDT 24
Finished Jun 09 02:43:47 PM PDT 24
Peak memory 265612 kb
Host smart-f806e9bb-3a60-4c93-9a9a-3d95b6df3e32
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428605012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 1.flash_ctrl_fs_sup.3428605012
Directory /workspace/1.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/1.flash_ctrl_full_mem_access.1836182720
Short name T100
Test name
Test status
Simulation time 78260387100 ps
CPU time 2820.16 seconds
Started Jun 09 02:42:30 PM PDT 24
Finished Jun 09 03:29:31 PM PDT 24
Peak memory 265516 kb
Host smart-a03b96de-4369-4589-b68e-b5b759f09abb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836182720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_full_mem_access.1836182720
Directory /workspace/1.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/1.flash_ctrl_host_dir_rd.3156120020
Short name T299
Test name
Test status
Simulation time 52991400 ps
CPU time 90.87 seconds
Started Jun 09 02:42:20 PM PDT 24
Finished Jun 09 02:43:51 PM PDT 24
Peak memory 262972 kb
Host smart-46b54c42-e872-4120-955b-6cc6916b4c0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156120020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3156120020
Directory /workspace/1.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.3464168016
Short name T968
Test name
Test status
Simulation time 10020369000 ps
CPU time 92.6 seconds
Started Jun 09 02:43:16 PM PDT 24
Finished Jun 09 02:44:49 PM PDT 24
Peak memory 322872 kb
Host smart-c639b021-b641-492a-afb0-c490ce44352a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464168016 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.3464168016
Directory /workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma.1010609043
Short name T212
Test name
Test status
Simulation time 1589715379800 ps
CPU time 2480.95 seconds
Started Jun 09 02:42:24 PM PDT 24
Finished Jun 09 03:23:46 PM PDT 24
Peak memory 260952 kb
Host smart-0bc07e86-de5c-483d-bbb2-f4945d22302a
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010609043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 1.flash_ctrl_hw_rma.1010609043
Directory /workspace/1.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_rma_reset.3984534201
Short name T167
Test name
Test status
Simulation time 200229604000 ps
CPU time 1009.24 seconds
Started Jun 09 02:42:24 PM PDT 24
Finished Jun 09 02:59:14 PM PDT 24
Peak memory 264184 kb
Host smart-c250d042-f434-4d93-9acc-bb73a2d49975
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984534201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_hw_rma_reset.3984534201
Directory /workspace/1.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_hw_sec_otp.95746156
Short name T109
Test name
Test status
Simulation time 3459144900 ps
CPU time 153.56 seconds
Started Jun 09 02:42:23 PM PDT 24
Finished Jun 09 02:44:57 PM PDT 24
Peak memory 261884 kb
Host smart-49dc3afb-23c1-499f-81a8-34f638708742
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95746156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_
sec_otp.95746156
Directory /workspace/1.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/1.flash_ctrl_integrity.2146605482
Short name T273
Test name
Test status
Simulation time 4754819500 ps
CPU time 795.4 seconds
Started Jun 09 02:42:53 PM PDT 24
Finished Jun 09 02:56:09 PM PDT 24
Peak memory 343508 kb
Host smart-bd86d181-4b94-4f97-92b8-35bdf2fc5445
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146605482 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_integrity.2146605482
Directory /workspace/1.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_rd.1470608896
Short name T1034
Test name
Test status
Simulation time 5240161700 ps
CPU time 217.49 seconds
Started Jun 09 02:42:57 PM PDT 24
Finished Jun 09 02:46:35 PM PDT 24
Peak memory 285160 kb
Host smart-1cdf2319-f56c-4770-aad4-4269132568b6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470608896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_intr_rd.1470608896
Directory /workspace/1.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr.4024018995
Short name T972
Test name
Test status
Simulation time 2339674000 ps
CPU time 85.41 seconds
Started Jun 09 02:42:54 PM PDT 24
Finished Jun 09 02:44:20 PM PDT 24
Peak memory 261852 kb
Host smart-42559d67-1873-4f11-a0c6-c24d504e5768
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024018995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_wr.4024018995
Directory /workspace/1.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.4153944760
Short name T599
Test name
Test status
Simulation time 68347542100 ps
CPU time 245.92 seconds
Started Jun 09 02:42:55 PM PDT 24
Finished Jun 09 02:47:01 PM PDT 24
Peak memory 260280 kb
Host smart-934cf14a-af50-4ad3-bf70-c69df555cc9d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415
3944760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.4153944760
Directory /workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/1.flash_ctrl_invalid_op.3012107272
Short name T575
Test name
Test status
Simulation time 4229655000 ps
CPU time 77.04 seconds
Started Jun 09 02:42:35 PM PDT 24
Finished Jun 09 02:43:52 PM PDT 24
Peak memory 260828 kb
Host smart-5cace042-3b95-426c-b9a5-d9767465cd96
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012107272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.3012107272
Directory /workspace/1.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/1.flash_ctrl_lcmgr_intg.3863434884
Short name T702
Test name
Test status
Simulation time 47178900 ps
CPU time 13.31 seconds
Started Jun 09 02:43:11 PM PDT 24
Finished Jun 09 02:43:25 PM PDT 24
Peak memory 260176 kb
Host smart-f5409cf8-1c4f-4372-a320-ae103122c35e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863434884 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.3863434884
Directory /workspace/1.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_otp_reset.42642357
Short name T489
Test name
Test status
Simulation time 209113500 ps
CPU time 108.88 seconds
Started Jun 09 02:42:30 PM PDT 24
Finished Jun 09 02:44:19 PM PDT 24
Peak memory 261552 kb
Host smart-705d1db6-8a74-4e8a-940b-73e6e16af62d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42642357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_
reset.42642357
Directory /workspace/1.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_oversize_error.437573854
Short name T56
Test name
Test status
Simulation time 2431690200 ps
CPU time 209.99 seconds
Started Jun 09 02:42:57 PM PDT 24
Finished Jun 09 02:46:27 PM PDT 24
Peak memory 282268 kb
Host smart-39c78db6-f7af-43fc-a251-95864ba81a19
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437573854 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.437573854
Directory /workspace/1.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/1.flash_ctrl_phy_arb.1534941600
Short name T783
Test name
Test status
Simulation time 11702816700 ps
CPU time 281.99 seconds
Started Jun 09 02:42:20 PM PDT 24
Finished Jun 09 02:47:03 PM PDT 24
Peak memory 263600 kb
Host smart-6d14bdca-1431-46c2-8825-41a0bfb733e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1534941600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.1534941600
Directory /workspace/1.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/1.flash_ctrl_prog_reset.3418922762
Short name T849
Test name
Test status
Simulation time 64326800 ps
CPU time 13.92 seconds
Started Jun 09 02:42:56 PM PDT 24
Finished Jun 09 02:43:10 PM PDT 24
Peak memory 258960 kb
Host smart-0378af71-5546-4c90-b64f-54211067af8a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418922762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_res
et.3418922762
Directory /workspace/1.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/1.flash_ctrl_rand_ops.2056101429
Short name T91
Test name
Test status
Simulation time 34180200 ps
CPU time 76.97 seconds
Started Jun 09 02:42:12 PM PDT 24
Finished Jun 09 02:43:30 PM PDT 24
Peak memory 277656 kb
Host smart-7ac6400a-812e-4b96-8f5d-cb4d9a6121a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056101429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.2056101429
Directory /workspace/1.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_buff_evict.3184031874
Short name T1000
Test name
Test status
Simulation time 1440446500 ps
CPU time 145.13 seconds
Started Jun 09 02:42:19 PM PDT 24
Finished Jun 09 02:44:44 PM PDT 24
Peak memory 263128 kb
Host smart-030acc97-8883-43f9-8686-3b7d1835bf23
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3184031874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.3184031874
Directory /workspace/1.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rd_intg.4231670171
Short name T899
Test name
Test status
Simulation time 66599000 ps
CPU time 32.53 seconds
Started Jun 09 02:43:09 PM PDT 24
Finished Jun 09 02:43:42 PM PDT 24
Peak memory 276268 kb
Host smart-b4ff7a2c-8d4a-4066-93df-b371d804f928
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231670171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.flash_ctrl_rd_intg.4231670171
Directory /workspace/1.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/1.flash_ctrl_re_evict.2871028954
Short name T1011
Test name
Test status
Simulation time 147274800 ps
CPU time 34.77 seconds
Started Jun 09 02:42:59 PM PDT 24
Finished Jun 09 02:43:34 PM PDT 24
Peak memory 275756 kb
Host smart-754bfed3-09bd-43cf-9119-5a2e446a82c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871028954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_re_evict.2871028954
Directory /workspace/1.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.3089398946
Short name T175
Test name
Test status
Simulation time 39398300 ps
CPU time 21.35 seconds
Started Jun 09 02:42:50 PM PDT 24
Finished Jun 09 02:43:12 PM PDT 24
Peak memory 265848 kb
Host smart-ae3ba1cf-8a75-456d-b884-1b84c789885c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089398946 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.3089398946
Directory /workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.1995264014
Short name T864
Test name
Test status
Simulation time 25671500 ps
CPU time 22.54 seconds
Started Jun 09 02:42:43 PM PDT 24
Finished Jun 09 02:43:06 PM PDT 24
Peak memory 265728 kb
Host smart-fd1201ce-55e5-45fa-9e24-92027720f2a1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995264014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_read_word_sweep_serr.1995264014
Directory /workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rma_err.1795358834
Short name T160
Test name
Test status
Simulation time 41996344500 ps
CPU time 953.37 seconds
Started Jun 09 02:43:12 PM PDT 24
Finished Jun 09 02:59:06 PM PDT 24
Peak memory 265352 kb
Host smart-7356ad9c-e43a-41f5-980d-ba163e927366
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795358834 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.1795358834
Directory /workspace/1.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro.1466591839
Short name T853
Test name
Test status
Simulation time 561223800 ps
CPU time 145.53 seconds
Started Jun 09 02:42:39 PM PDT 24
Finished Jun 09 02:45:05 PM PDT 24
Peak memory 282124 kb
Host smart-3c4883ef-e5d8-461d-ba8c-c7bca4c9e9d9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466591839 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_ro.1466591839
Directory /workspace/1.flash_ctrl_ro/latest

Test location /workspace/coverage/default/1.flash_ctrl_ro_serr.2172722319
Short name T735
Test name
Test status
Simulation time 1924460000 ps
CPU time 142.38 seconds
Started Jun 09 02:42:43 PM PDT 24
Finished Jun 09 02:45:06 PM PDT 24
Peak memory 297216 kb
Host smart-32e766e8-7e4e-4e4e-a081-28ff48a56eb4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172722319 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.2172722319
Directory /workspace/1.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw.2340505628
Short name T808
Test name
Test status
Simulation time 7887177400 ps
CPU time 682.13 seconds
Started Jun 09 02:42:39 PM PDT 24
Finished Jun 09 02:54:01 PM PDT 24
Peak memory 309748 kb
Host smart-f6835a81-1bc9-4bcd-9248-c17e48cee84f
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340505628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.flash_ctrl_rw.2340505628
Directory /workspace/1.flash_ctrl_rw/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict.1418510753
Short name T763
Test name
Test status
Simulation time 54603900 ps
CPU time 31.11 seconds
Started Jun 09 02:43:01 PM PDT 24
Finished Jun 09 02:43:32 PM PDT 24
Peak memory 277944 kb
Host smart-6b752055-c217-4608-89f6-25ecc165dd0c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418510753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_rw_evict.1418510753
Directory /workspace/1.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.2484688788
Short name T937
Test name
Test status
Simulation time 56749600 ps
CPU time 31.13 seconds
Started Jun 09 02:43:02 PM PDT 24
Finished Jun 09 02:43:33 PM PDT 24
Peak memory 274044 kb
Host smart-3ec9ec45-760b-4d5e-8934-e7a592d94bfe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484688788 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.2484688788
Directory /workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/1.flash_ctrl_sec_cm.2226117364
Short name T25
Test name
Test status
Simulation time 2734541100 ps
CPU time 6337.03 seconds
Started Jun 09 02:43:00 PM PDT 24
Finished Jun 09 04:28:38 PM PDT 24
Peak memory 284768 kb
Host smart-cc722e55-7cfd-475d-b040-befd4c572ccb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226117364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.2226117364
Directory /workspace/1.flash_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_address.1486297851
Short name T906
Test name
Test status
Simulation time 5029464000 ps
CPU time 80.13 seconds
Started Jun 09 02:42:50 PM PDT 24
Finished Jun 09 02:44:10 PM PDT 24
Peak memory 273984 kb
Host smart-9e519fb0-14c2-4c02-aeee-f127cfb215d2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486297851 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_address.1486297851
Directory /workspace/1.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/1.flash_ctrl_serr_counter.237087392
Short name T302
Test name
Test status
Simulation time 3753671300 ps
CPU time 76.71 seconds
Started Jun 09 02:42:43 PM PDT 24
Finished Jun 09 02:44:00 PM PDT 24
Peak memory 274712 kb
Host smart-863fbb10-6c5f-4bc4-8a79-f8bce3ff46f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237087392 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_serr_counter.237087392
Directory /workspace/1.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke.3739007906
Short name T630
Test name
Test status
Simulation time 72461800 ps
CPU time 98.56 seconds
Started Jun 09 02:42:12 PM PDT 24
Finished Jun 09 02:43:51 PM PDT 24
Peak memory 276124 kb
Host smart-70a62f4d-0e67-443c-abc9-1a5bfaaf4adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739007906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.3739007906
Directory /workspace/1.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/1.flash_ctrl_smoke_hw.841491653
Short name T551
Test name
Test status
Simulation time 49076700 ps
CPU time 23.98 seconds
Started Jun 09 02:42:12 PM PDT 24
Finished Jun 09 02:42:36 PM PDT 24
Peak memory 259824 kb
Host smart-9a036878-982c-4955-be30-1e6914325a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841491653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.841491653
Directory /workspace/1.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/1.flash_ctrl_stress_all.1711824996
Short name T590
Test name
Test status
Simulation time 72689000 ps
CPU time 316.82 seconds
Started Jun 09 02:43:00 PM PDT 24
Finished Jun 09 02:48:17 PM PDT 24
Peak memory 274780 kb
Host smart-318ede51-fd76-4b88-9fa0-c66652ab786e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711824996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres
s_all.1711824996
Directory /workspace/1.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.flash_ctrl_sw_op.445416465
Short name T569
Test name
Test status
Simulation time 86603200 ps
CPU time 26.3 seconds
Started Jun 09 02:42:15 PM PDT 24
Finished Jun 09 02:42:41 PM PDT 24
Peak memory 262596 kb
Host smart-9a2972d9-d915-4d34-b54c-a3d977db729a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445416465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.445416465
Directory /workspace/1.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_alert_test.3212692101
Short name T615
Test name
Test status
Simulation time 72657700 ps
CPU time 14.19 seconds
Started Jun 09 02:49:49 PM PDT 24
Finished Jun 09 02:50:04 PM PDT 24
Peak memory 265664 kb
Host smart-9f2b59a2-888e-4f4c-aefc-f8686880dd0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212692101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.
3212692101
Directory /workspace/10.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.flash_ctrl_connect.569064270
Short name T934
Test name
Test status
Simulation time 20270100 ps
CPU time 15.79 seconds
Started Jun 09 02:49:43 PM PDT 24
Finished Jun 09 02:49:59 PM PDT 24
Peak memory 275252 kb
Host smart-1778ebb3-1797-4ff9-b1a0-b0a11659acef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569064270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.569064270
Directory /workspace/10.flash_ctrl_connect/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.3212726675
Short name T628
Test name
Test status
Simulation time 10020455400 ps
CPU time 73.14 seconds
Started Jun 09 02:49:48 PM PDT 24
Finished Jun 09 02:51:02 PM PDT 24
Peak memory 277956 kb
Host smart-609496c0-9698-4573-9087-223618b23cdb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212726675 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.3212726675
Directory /workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_rma_reset.57559270
Short name T168
Test name
Test status
Simulation time 320267225700 ps
CPU time 1063.9 seconds
Started Jun 09 02:49:25 PM PDT 24
Finished Jun 09 03:07:09 PM PDT 24
Peak memory 264356 kb
Host smart-1494df3a-35f5-416f-9b38-84a75a4013b4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57559270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul
l -cm_name 10.flash_ctrl_hw_rma_reset.57559270
Directory /workspace/10.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.1196479362
Short name T1013
Test name
Test status
Simulation time 8054268500 ps
CPU time 143.99 seconds
Started Jun 09 02:49:21 PM PDT 24
Finished Jun 09 02:51:46 PM PDT 24
Peak memory 263396 kb
Host smart-5c006a6c-2e88-47b5-86a3-d8d89c58375b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196479362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
hw_sec_otp.1196479362
Directory /workspace/10.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd.810924583
Short name T1068
Test name
Test status
Simulation time 7444800700 ps
CPU time 231.2 seconds
Started Jun 09 02:49:31 PM PDT 24
Finished Jun 09 02:53:22 PM PDT 24
Peak memory 285264 kb
Host smart-239bd127-15d8-439a-a1d5-5c2aa7577716
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810924583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flas
h_ctrl_intr_rd.810924583
Directory /workspace/10.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.3135886393
Short name T580
Test name
Test status
Simulation time 5601318500 ps
CPU time 141.85 seconds
Started Jun 09 02:49:35 PM PDT 24
Finished Jun 09 02:51:57 PM PDT 24
Peak memory 292796 kb
Host smart-ace11e91-a99a-4ed3-860b-7d073d0d82e9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135886393 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.3135886393
Directory /workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/10.flash_ctrl_invalid_op.3250286930
Short name T1001
Test name
Test status
Simulation time 2143154100 ps
CPU time 76.71 seconds
Started Jun 09 02:49:26 PM PDT 24
Finished Jun 09 02:50:43 PM PDT 24
Peak memory 260792 kb
Host smart-7d15296c-4ff3-4c2b-96fe-4af85d8719ec
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250286930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.3
250286930
Directory /workspace/10.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.852386711
Short name T495
Test name
Test status
Simulation time 65601300 ps
CPU time 14.07 seconds
Started Jun 09 02:49:44 PM PDT 24
Finished Jun 09 02:49:58 PM PDT 24
Peak memory 265284 kb
Host smart-b32a63e3-abd9-4553-af61-65a9fe325273
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852386711 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.852386711
Directory /workspace/10.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/10.flash_ctrl_mp_regions.1235160599
Short name T625
Test name
Test status
Simulation time 23834130500 ps
CPU time 185.47 seconds
Started Jun 09 02:49:23 PM PDT 24
Finished Jun 09 02:52:29 PM PDT 24
Peak memory 265528 kb
Host smart-7c3ba1c6-647f-4565-8c7a-fb710cf70e55
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235160599 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_mp_regions.1235160599
Directory /workspace/10.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/10.flash_ctrl_otp_reset.1119116408
Short name T1040
Test name
Test status
Simulation time 74132500 ps
CPU time 130.14 seconds
Started Jun 09 02:49:25 PM PDT 24
Finished Jun 09 02:51:35 PM PDT 24
Peak memory 261196 kb
Host smart-ae3dfaa6-7958-41f3-828b-1c7ff3e30d8c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119116408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_o
tp_reset.1119116408
Directory /workspace/10.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_phy_arb.2109440891
Short name T542
Test name
Test status
Simulation time 53121200 ps
CPU time 278.4 seconds
Started Jun 09 02:49:20 PM PDT 24
Finished Jun 09 02:53:59 PM PDT 24
Peak memory 263376 kb
Host smart-134fca10-9b0d-447d-8eec-c97274fe3076
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2109440891 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.2109440891
Directory /workspace/10.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/10.flash_ctrl_prog_reset.2546399155
Short name T521
Test name
Test status
Simulation time 45620100 ps
CPU time 13.87 seconds
Started Jun 09 02:49:34 PM PDT 24
Finished Jun 09 02:49:48 PM PDT 24
Peak memory 259216 kb
Host smart-578a4866-2364-4791-8980-47bd93feacad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546399155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_re
set.2546399155
Directory /workspace/10.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/10.flash_ctrl_rand_ops.1217038354
Short name T598
Test name
Test status
Simulation time 412902100 ps
CPU time 221.28 seconds
Started Jun 09 02:49:20 PM PDT 24
Finished Jun 09 02:53:01 PM PDT 24
Peak memory 279452 kb
Host smart-e7a2cf72-8ddb-4751-befa-a662a22a0d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217038354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.1217038354
Directory /workspace/10.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/10.flash_ctrl_re_evict.1909315124
Short name T716
Test name
Test status
Simulation time 163153400 ps
CPU time 32.97 seconds
Started Jun 09 02:49:34 PM PDT 24
Finished Jun 09 02:50:07 PM PDT 24
Peak memory 275824 kb
Host smart-bfc80999-8e2c-491d-a674-3124a35d7d43
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909315124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_re_evict.1909315124
Directory /workspace/10.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_ro.968124738
Short name T877
Test name
Test status
Simulation time 450006800 ps
CPU time 124.02 seconds
Started Jun 09 02:49:30 PM PDT 24
Finished Jun 09 02:51:34 PM PDT 24
Peak memory 282164 kb
Host smart-10e8aaf7-1397-4cc1-9c43-4f7a66fc88d8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968124738 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.flash_ctrl_ro.968124738
Directory /workspace/10.flash_ctrl_ro/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw.1868116192
Short name T573
Test name
Test status
Simulation time 18673327500 ps
CPU time 552.39 seconds
Started Jun 09 02:49:29 PM PDT 24
Finished Jun 09 02:58:41 PM PDT 24
Peak memory 314920 kb
Host smart-a674e0fd-d771-4446-910d-de48521588f1
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868116192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.flash_ctrl_rw.1868116192
Directory /workspace/10.flash_ctrl_rw/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict.2361172684
Short name T854
Test name
Test status
Simulation time 29414800 ps
CPU time 31.46 seconds
Started Jun 09 02:49:34 PM PDT 24
Finished Jun 09 02:50:06 PM PDT 24
Peak memory 275728 kb
Host smart-d9d865d0-facf-44f6-a2fa-9398f579561c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361172684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl
ash_ctrl_rw_evict.2361172684
Directory /workspace/10.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.87814622
Short name T473
Test name
Test status
Simulation time 29365500 ps
CPU time 30.9 seconds
Started Jun 09 02:49:36 PM PDT 24
Finished Jun 09 02:50:07 PM PDT 24
Peak memory 276008 kb
Host smart-173aadd2-fcfa-4ab1-b395-a3a39515a433
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87814622 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.87814622
Directory /workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/10.flash_ctrl_sec_info_access.343481582
Short name T874
Test name
Test status
Simulation time 9839078300 ps
CPU time 87.73 seconds
Started Jun 09 02:49:38 PM PDT 24
Finished Jun 09 02:51:06 PM PDT 24
Peak memory 263808 kb
Host smart-35b70b14-7d49-40f9-b5c0-76b835124f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343481582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.343481582
Directory /workspace/10.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/10.flash_ctrl_smoke.1965864247
Short name T895
Test name
Test status
Simulation time 17700200 ps
CPU time 75.38 seconds
Started Jun 09 02:49:19 PM PDT 24
Finished Jun 09 02:50:35 PM PDT 24
Peak memory 276712 kb
Host smart-a63bb2e7-52cf-4be0-ad17-c57a46b55621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965864247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.1965864247
Directory /workspace/10.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/10.flash_ctrl_wo.1251219544
Short name T1090
Test name
Test status
Simulation time 10060702500 ps
CPU time 197.78 seconds
Started Jun 09 02:49:25 PM PDT 24
Finished Jun 09 02:52:43 PM PDT 24
Peak memory 265680 kb
Host smart-a7759c28-5c67-47ad-8c21-e850559baedc
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251219544 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.flash_ctrl_wo.1251219544
Directory /workspace/10.flash_ctrl_wo/latest

Test location /workspace/coverage/default/11.flash_ctrl_alert_test.4004248245
Short name T673
Test name
Test status
Simulation time 127716900 ps
CPU time 13.55 seconds
Started Jun 09 02:50:31 PM PDT 24
Finished Jun 09 02:50:45 PM PDT 24
Peak memory 258568 kb
Host smart-7dc5952d-7871-4e10-ae70-a7376fd4ba5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004248245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.
4004248245
Directory /workspace/11.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.flash_ctrl_connect.2958915624
Short name T389
Test name
Test status
Simulation time 15002900 ps
CPU time 15.6 seconds
Started Jun 09 02:50:15 PM PDT 24
Finished Jun 09 02:50:31 PM PDT 24
Peak memory 275160 kb
Host smart-d82e778b-9d20-4980-9cf2-b09a2350d5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958915624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.2958915624
Directory /workspace/11.flash_ctrl_connect/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3265866894
Short name T307
Test name
Test status
Simulation time 10014579400 ps
CPU time 262.01 seconds
Started Jun 09 02:50:20 PM PDT 24
Finished Jun 09 02:54:42 PM PDT 24
Peak memory 309516 kb
Host smart-0455b9a6-bbdc-488a-97e4-c4a2614b409f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265866894 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.3265866894
Directory /workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.1228355170
Short name T368
Test name
Test status
Simulation time 25548000 ps
CPU time 13.33 seconds
Started Jun 09 02:50:18 PM PDT 24
Finished Jun 09 02:50:32 PM PDT 24
Peak memory 259808 kb
Host smart-cf481257-6dd6-4789-8266-d8e8fa104924
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228355170 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.1228355170
Directory /workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/11.flash_ctrl_hw_sec_otp.4008575936
Short name T663
Test name
Test status
Simulation time 15572663400 ps
CPU time 94.05 seconds
Started Jun 09 02:49:53 PM PDT 24
Finished Jun 09 02:51:27 PM PDT 24
Peak memory 263260 kb
Host smart-7f7a55c0-f8ab-4e26-9492-1ee216d61f35
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008575936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
hw_sec_otp.4008575936
Directory /workspace/11.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd.1737713332
Short name T348
Test name
Test status
Simulation time 3352798400 ps
CPU time 298 seconds
Started Jun 09 02:50:06 PM PDT 24
Finished Jun 09 02:55:05 PM PDT 24
Peak memory 292756 kb
Host smart-b42e8ebb-166c-4e9d-bc89-fec02a65c67f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737713332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_intr_rd.1737713332
Directory /workspace/11.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.1457029586
Short name T811
Test name
Test status
Simulation time 11314682700 ps
CPU time 269.35 seconds
Started Jun 09 02:50:08 PM PDT 24
Finished Jun 09 02:54:38 PM PDT 24
Peak memory 285240 kb
Host smart-c8a78fb7-bea7-4e5f-8c32-ad75c2dae650
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457029586 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.1457029586
Directory /workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/11.flash_ctrl_lcmgr_intg.82802263
Short name T545
Test name
Test status
Simulation time 15428600 ps
CPU time 13.31 seconds
Started Jun 09 02:50:16 PM PDT 24
Finished Jun 09 02:50:30 PM PDT 24
Peak memory 261132 kb
Host smart-040f28c6-0a7e-4db3-bb1b-913f10ce694e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82802263 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.82802263
Directory /workspace/11.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/11.flash_ctrl_mp_regions.3508263378
Short name T105
Test name
Test status
Simulation time 15290406200 ps
CPU time 352.89 seconds
Started Jun 09 02:50:04 PM PDT 24
Finished Jun 09 02:55:57 PM PDT 24
Peak memory 274892 kb
Host smart-f00e69df-fe4c-4e39-97ef-c4fc86b8b90a
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508263378 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_mp_regions.3508263378
Directory /workspace/11.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/11.flash_ctrl_prog_reset.3710219389
Short name T499
Test name
Test status
Simulation time 1899772500 ps
CPU time 179.57 seconds
Started Jun 09 02:50:08 PM PDT 24
Finished Jun 09 02:53:08 PM PDT 24
Peak memory 265216 kb
Host smart-47b935b9-ae0f-47bd-80cb-1ad074004ef5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710219389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_re
set.3710219389
Directory /workspace/11.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/11.flash_ctrl_rand_ops.554464180
Short name T49
Test name
Test status
Simulation time 428076400 ps
CPU time 692.09 seconds
Started Jun 09 02:49:55 PM PDT 24
Finished Jun 09 03:01:28 PM PDT 24
Peak memory 284084 kb
Host smart-eb00604b-22d8-47ce-9ccc-2416df555ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554464180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.554464180
Directory /workspace/11.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/11.flash_ctrl_ro.2509013542
Short name T194
Test name
Test status
Simulation time 919028100 ps
CPU time 128.96 seconds
Started Jun 09 02:50:07 PM PDT 24
Finished Jun 09 02:52:16 PM PDT 24
Peak memory 290364 kb
Host smart-7dbb33b2-0ff8-4d72-ab6e-1ab51abdbcc4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509013542 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 11.flash_ctrl_ro.2509013542
Directory /workspace/11.flash_ctrl_ro/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw.524563890
Short name T1036
Test name
Test status
Simulation time 6481654000 ps
CPU time 525.97 seconds
Started Jun 09 02:50:08 PM PDT 24
Finished Jun 09 02:58:54 PM PDT 24
Peak memory 310396 kb
Host smart-89cc77c3-4710-47ad-8656-d3c7cb7d0579
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524563890 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.flash_ctrl_rw.524563890
Directory /workspace/11.flash_ctrl_rw/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict.2818172905
Short name T750
Test name
Test status
Simulation time 33689300 ps
CPU time 31.22 seconds
Started Jun 09 02:50:07 PM PDT 24
Finished Jun 09 02:50:39 PM PDT 24
Peak memory 277948 kb
Host smart-783fbff2-5846-4220-9d8b-ca4d3d71e6d3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818172905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_rw_evict.2818172905
Directory /workspace/11.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.1904672833
Short name T41
Test name
Test status
Simulation time 32500500 ps
CPU time 31.48 seconds
Started Jun 09 02:50:08 PM PDT 24
Finished Jun 09 02:50:40 PM PDT 24
Peak memory 276052 kb
Host smart-59f2497b-e9e7-4e33-9c70-d03651922394
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904672833 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.1904672833
Directory /workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/11.flash_ctrl_sec_info_access.1484137344
Short name T416
Test name
Test status
Simulation time 1374377900 ps
CPU time 62.88 seconds
Started Jun 09 02:50:17 PM PDT 24
Finished Jun 09 02:51:20 PM PDT 24
Peak memory 265092 kb
Host smart-cb5272bf-d801-4b78-a48f-03d64ff9c9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484137344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.1484137344
Directory /workspace/11.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/11.flash_ctrl_smoke.3438794850
Short name T916
Test name
Test status
Simulation time 37673800 ps
CPU time 120.89 seconds
Started Jun 09 02:49:47 PM PDT 24
Finished Jun 09 02:51:48 PM PDT 24
Peak memory 271132 kb
Host smart-da00647c-e6f2-45ec-a93c-ed9dc7a0fe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438794850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.3438794850
Directory /workspace/11.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/11.flash_ctrl_wo.3147897976
Short name T923
Test name
Test status
Simulation time 3404709100 ps
CPU time 266.48 seconds
Started Jun 09 02:50:03 PM PDT 24
Finished Jun 09 02:54:30 PM PDT 24
Peak memory 265476 kb
Host smart-fe4feff8-7c63-4e39-8ef1-58edde64e47c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147897976 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.flash_ctrl_wo.3147897976
Directory /workspace/11.flash_ctrl_wo/latest

Test location /workspace/coverage/default/12.flash_ctrl_alert_test.3248173693
Short name T655
Test name
Test status
Simulation time 171506000 ps
CPU time 13.93 seconds
Started Jun 09 02:50:53 PM PDT 24
Finished Jun 09 02:51:07 PM PDT 24
Peak memory 258512 kb
Host smart-a4432c4e-31fe-47af-bbdc-52da47c200f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248173693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.
3248173693
Directory /workspace/12.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.flash_ctrl_connect.349292490
Short name T497
Test name
Test status
Simulation time 12959600 ps
CPU time 15.82 seconds
Started Jun 09 02:50:50 PM PDT 24
Finished Jun 09 02:51:06 PM PDT 24
Peak memory 275268 kb
Host smart-808c9f14-9cfa-4337-9664-604d2cf0bde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349292490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.349292490
Directory /workspace/12.flash_ctrl_connect/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.1906086604
Short name T367
Test name
Test status
Simulation time 25287800 ps
CPU time 13.65 seconds
Started Jun 09 02:50:59 PM PDT 24
Finished Jun 09 02:51:13 PM PDT 24
Peak memory 265224 kb
Host smart-b48ea4ed-5092-4637-8ebd-d0c0434b19ad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906086604 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.1906086604
Directory /workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.1649763295
Short name T166
Test name
Test status
Simulation time 40121210900 ps
CPU time 802.99 seconds
Started Jun 09 02:50:36 PM PDT 24
Finished Jun 09 03:03:59 PM PDT 24
Peak memory 264512 kb
Host smart-dea7ea12-2965-46c7-91bf-d0f48188c1a4
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649763295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 12.flash_ctrl_hw_rma_reset.1649763295
Directory /workspace/12.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.425782493
Short name T670
Test name
Test status
Simulation time 4515370900 ps
CPU time 245.94 seconds
Started Jun 09 02:50:33 PM PDT 24
Finished Jun 09 02:54:40 PM PDT 24
Peak memory 262896 kb
Host smart-09aac0b6-0114-42de-8b16-415ec54c63c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425782493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_h
w_sec_otp.425782493
Directory /workspace/12.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3601231191
Short name T898
Test name
Test status
Simulation time 5775367800 ps
CPU time 145.18 seconds
Started Jun 09 02:50:40 PM PDT 24
Finished Jun 09 02:53:05 PM PDT 24
Peak memory 293452 kb
Host smart-3fab76fb-d4b7-4e1d-ba94-1dd4e1ed603c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601231191 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.3601231191
Directory /workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/12.flash_ctrl_invalid_op.850847779
Short name T192
Test name
Test status
Simulation time 3684536900 ps
CPU time 61.64 seconds
Started Jun 09 02:50:35 PM PDT 24
Finished Jun 09 02:51:37 PM PDT 24
Peak memory 263168 kb
Host smart-c5109c77-7054-4938-b590-63ee58d1bb72
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850847779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.850847779
Directory /workspace/12.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/12.flash_ctrl_lcmgr_intg.52931305
Short name T622
Test name
Test status
Simulation time 22346600 ps
CPU time 13.37 seconds
Started Jun 09 02:50:48 PM PDT 24
Finished Jun 09 02:51:01 PM PDT 24
Peak memory 265184 kb
Host smart-f7d5a9cc-8053-4001-9d06-4da480d97f88
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52931305 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.52931305
Directory /workspace/12.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/12.flash_ctrl_mp_regions.3134977395
Short name T77
Test name
Test status
Simulation time 7950686400 ps
CPU time 269.19 seconds
Started Jun 09 02:50:35 PM PDT 24
Finished Jun 09 02:55:04 PM PDT 24
Peak memory 274596 kb
Host smart-209f4b45-5c60-48f0-9ce3-196d9e0773bb
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134977395 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_mp_regions.3134977395
Directory /workspace/12.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/12.flash_ctrl_otp_reset.872605680
Short name T1045
Test name
Test status
Simulation time 175260400 ps
CPU time 109.16 seconds
Started Jun 09 02:50:34 PM PDT 24
Finished Jun 09 02:52:23 PM PDT 24
Peak memory 261364 kb
Host smart-b97868e4-44c9-4294-a803-638c3b5c4619
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872605680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ot
p_reset.872605680
Directory /workspace/12.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_phy_arb.1116400052
Short name T999
Test name
Test status
Simulation time 946622800 ps
CPU time 377.29 seconds
Started Jun 09 02:50:33 PM PDT 24
Finished Jun 09 02:56:50 PM PDT 24
Peak memory 263420 kb
Host smart-1d0ce362-fde6-47f3-8809-a52e72042de5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1116400052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1116400052
Directory /workspace/12.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/12.flash_ctrl_prog_reset.2406893075
Short name T528
Test name
Test status
Simulation time 44396100 ps
CPU time 13.8 seconds
Started Jun 09 02:50:39 PM PDT 24
Finished Jun 09 02:50:53 PM PDT 24
Peak memory 265720 kb
Host smart-f238b51e-3dd6-498a-89e5-bbdc20c441d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406893075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_re
set.2406893075
Directory /workspace/12.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/12.flash_ctrl_rand_ops.415532570
Short name T725
Test name
Test status
Simulation time 78398400 ps
CPU time 252.73 seconds
Started Jun 09 02:50:31 PM PDT 24
Finished Jun 09 02:54:44 PM PDT 24
Peak memory 275184 kb
Host smart-a03dc975-41ff-412a-9fb9-461f9f7bbff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415532570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.415532570
Directory /workspace/12.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/12.flash_ctrl_re_evict.2510465718
Short name T237
Test name
Test status
Simulation time 83440000 ps
CPU time 35.91 seconds
Started Jun 09 02:50:47 PM PDT 24
Finished Jun 09 02:51:23 PM PDT 24
Peak memory 275712 kb
Host smart-545de7b4-dfb8-4dd9-ae87-ac3d1c2577a8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510465718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_re_evict.2510465718
Directory /workspace/12.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_ro.2409450554
Short name T494
Test name
Test status
Simulation time 2172567500 ps
CPU time 124.78 seconds
Started Jun 09 02:50:41 PM PDT 24
Finished Jun 09 02:52:46 PM PDT 24
Peak memory 282312 kb
Host smart-a162ed44-2bd7-494f-be4f-4f59d5239ff7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409450554 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_ro.2409450554
Directory /workspace/12.flash_ctrl_ro/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw.3080216737
Short name T696
Test name
Test status
Simulation time 3414973200 ps
CPU time 571.24 seconds
Started Jun 09 02:50:40 PM PDT 24
Finished Jun 09 03:00:11 PM PDT 24
Peak memory 314572 kb
Host smart-5cd8c0ca-e153-493a-998b-506474785bb0
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080216737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.flash_ctrl_rw.3080216737
Directory /workspace/12.flash_ctrl_rw/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict.2705977322
Short name T820
Test name
Test status
Simulation time 40659200 ps
CPU time 31.21 seconds
Started Jun 09 02:50:41 PM PDT 24
Finished Jun 09 02:51:12 PM PDT 24
Peak memory 275808 kb
Host smart-b3d07ef1-b53d-4f2e-93ba-58a05e578d71
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705977322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl
ash_ctrl_rw_evict.2705977322
Directory /workspace/12.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.4148008872
Short name T869
Test name
Test status
Simulation time 163900000 ps
CPU time 28.91 seconds
Started Jun 09 02:50:41 PM PDT 24
Finished Jun 09 02:51:10 PM PDT 24
Peak memory 276020 kb
Host smart-78b22367-4742-4218-8458-62e4d0f38eb3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148008872 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict_all_en.4148008872
Directory /workspace/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/12.flash_ctrl_sec_info_access.2067561498
Short name T527
Test name
Test status
Simulation time 2715536800 ps
CPU time 61.47 seconds
Started Jun 09 02:50:50 PM PDT 24
Finished Jun 09 02:51:51 PM PDT 24
Peak memory 259916 kb
Host smart-5165c063-0fb9-44c9-80d5-7394a1588ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067561498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.2067561498
Directory /workspace/12.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/12.flash_ctrl_smoke.1968286162
Short name T268
Test name
Test status
Simulation time 42186400 ps
CPU time 146.49 seconds
Started Jun 09 02:50:33 PM PDT 24
Finished Jun 09 02:52:59 PM PDT 24
Peak memory 277216 kb
Host smart-8682873b-e25b-4238-8add-fa5045255751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968286162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1968286162
Directory /workspace/12.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/12.flash_ctrl_wo.4094184225
Short name T88
Test name
Test status
Simulation time 4599527100 ps
CPU time 208.81 seconds
Started Jun 09 02:50:35 PM PDT 24
Finished Jun 09 02:54:04 PM PDT 24
Peak memory 265708 kb
Host smart-bec73639-572f-4df4-9ac8-4a9d36c3bcc1
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094184225 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.flash_ctrl_wo.4094184225
Directory /workspace/12.flash_ctrl_wo/latest

Test location /workspace/coverage/default/13.flash_ctrl_alert_test.769739621
Short name T1053
Test name
Test status
Simulation time 56416800 ps
CPU time 13.57 seconds
Started Jun 09 02:51:16 PM PDT 24
Finished Jun 09 02:51:29 PM PDT 24
Peak memory 258540 kb
Host smart-42d72b51-a5e5-4fd2-b832-680ade539360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769739621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.769739621
Directory /workspace/13.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.flash_ctrl_connect.503774290
Short name T448
Test name
Test status
Simulation time 42650700 ps
CPU time 15.95 seconds
Started Jun 09 02:51:17 PM PDT 24
Finished Jun 09 02:51:33 PM PDT 24
Peak memory 275248 kb
Host smart-fe177af1-aea9-4710-9808-0fdcd25aae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503774290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.503774290
Directory /workspace/13.flash_ctrl_connect/latest

Test location /workspace/coverage/default/13.flash_ctrl_disable.3049199883
Short name T1071
Test name
Test status
Simulation time 12887800 ps
CPU time 21.48 seconds
Started Jun 09 02:51:15 PM PDT 24
Finished Jun 09 02:51:36 PM PDT 24
Peak memory 265272 kb
Host smart-269b99ba-67e7-419c-8116-d7d77a5c5410
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049199883 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_disable.3049199883
Directory /workspace/13.flash_ctrl_disable/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.1959353130
Short name T951
Test name
Test status
Simulation time 29166000 ps
CPU time 13.69 seconds
Started Jun 09 02:51:18 PM PDT 24
Finished Jun 09 02:51:32 PM PDT 24
Peak memory 265156 kb
Host smart-37622c44-1e38-43fe-a7d1-a37fae76b59f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959353130 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.1959353130
Directory /workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_rma_reset.1571406651
Short name T556
Test name
Test status
Simulation time 230210966500 ps
CPU time 885.28 seconds
Started Jun 09 02:50:59 PM PDT 24
Finished Jun 09 03:05:44 PM PDT 24
Peak memory 264768 kb
Host smart-1ffb7ec6-fb50-4ced-833b-3ffd2ea102b8
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571406651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 13.flash_ctrl_hw_rma_reset.1571406651
Directory /workspace/13.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_hw_sec_otp.4043754934
Short name T174
Test name
Test status
Simulation time 7043552900 ps
CPU time 131.04 seconds
Started Jun 09 02:50:58 PM PDT 24
Finished Jun 09 02:53:09 PM PDT 24
Peak memory 262832 kb
Host smart-a179ded4-5c75-4413-8001-c22768d8b61e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043754934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
hw_sec_otp.4043754934
Directory /workspace/13.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2076927029
Short name T876
Test name
Test status
Simulation time 25430913900 ps
CPU time 290.61 seconds
Started Jun 09 02:51:10 PM PDT 24
Finished Jun 09 02:56:01 PM PDT 24
Peak memory 292332 kb
Host smart-5b2b0ca6-9b8d-4b46-b1fc-5a0d8138c3c7
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076927029 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.2076927029
Directory /workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2052925637
Short name T535
Test name
Test status
Simulation time 25881800 ps
CPU time 13.66 seconds
Started Jun 09 02:51:14 PM PDT 24
Finished Jun 09 02:51:27 PM PDT 24
Peak memory 265280 kb
Host smart-e0dd4ca4-f890-4541-bd2e-df4bb889ec30
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052925637 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2052925637
Directory /workspace/13.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/13.flash_ctrl_phy_arb.744992818
Short name T935
Test name
Test status
Simulation time 51272600 ps
CPU time 226.76 seconds
Started Jun 09 02:50:58 PM PDT 24
Finished Jun 09 02:54:45 PM PDT 24
Peak memory 263300 kb
Host smart-e4373645-dea9-4f5b-ad4d-5a7d6d556750
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=744992818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.744992818
Directory /workspace/13.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/13.flash_ctrl_prog_reset.590024182
Short name T130
Test name
Test status
Simulation time 32047600 ps
CPU time 13.81 seconds
Started Jun 09 02:51:10 PM PDT 24
Finished Jun 09 02:51:24 PM PDT 24
Peak memory 259112 kb
Host smart-ed48ec4e-798d-43d7-beff-38b56d51df1f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590024182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_res
et.590024182
Directory /workspace/13.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/13.flash_ctrl_rand_ops.2262751194
Short name T251
Test name
Test status
Simulation time 18578561500 ps
CPU time 1181.57 seconds
Started Jun 09 02:50:58 PM PDT 24
Finished Jun 09 03:10:40 PM PDT 24
Peak memory 286448 kb
Host smart-f8af99b3-c402-4b35-9471-ec4671d92cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262751194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.2262751194
Directory /workspace/13.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/13.flash_ctrl_re_evict.2995311184
Short name T796
Test name
Test status
Simulation time 120551000 ps
CPU time 35.52 seconds
Started Jun 09 02:51:13 PM PDT 24
Finished Jun 09 02:51:48 PM PDT 24
Peak memory 278328 kb
Host smart-70de354a-3651-43f1-81dc-f97dffe09e2b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995311184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_re_evict.2995311184
Directory /workspace/13.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_ro.1562225382
Short name T705
Test name
Test status
Simulation time 643502600 ps
CPU time 145.41 seconds
Started Jun 09 02:51:02 PM PDT 24
Finished Jun 09 02:53:27 PM PDT 24
Peak memory 281296 kb
Host smart-ccf1f84f-3a40-406f-ae64-0558ed685ca6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562225382 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.flash_ctrl_ro.1562225382
Directory /workspace/13.flash_ctrl_ro/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw.1187316860
Short name T235
Test name
Test status
Simulation time 3993199400 ps
CPU time 625.48 seconds
Started Jun 09 02:51:08 PM PDT 24
Finished Jun 09 03:01:34 PM PDT 24
Peak memory 309832 kb
Host smart-8a23b07d-e82c-4569-9b25-ebd0809645a4
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187316860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.flash_ctrl_rw.1187316860
Directory /workspace/13.flash_ctrl_rw/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict.2862511117
Short name T353
Test name
Test status
Simulation time 181282800 ps
CPU time 28.91 seconds
Started Jun 09 02:51:08 PM PDT 24
Finished Jun 09 02:51:38 PM PDT 24
Peak memory 277924 kb
Host smart-4ae406f5-399e-4dfa-9012-28dd4dd006eb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862511117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl
ash_ctrl_rw_evict.2862511117
Directory /workspace/13.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.1152124390
Short name T28
Test name
Test status
Simulation time 294384400 ps
CPU time 31.25 seconds
Started Jun 09 02:51:15 PM PDT 24
Finished Jun 09 02:51:47 PM PDT 24
Peak memory 276060 kb
Host smart-fbe48b78-9c77-4f98-849d-850219cd187a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152124390 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.1152124390
Directory /workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/13.flash_ctrl_sec_info_access.771421200
Short name T919
Test name
Test status
Simulation time 2758773300 ps
CPU time 71.99 seconds
Started Jun 09 02:51:14 PM PDT 24
Finished Jun 09 02:52:26 PM PDT 24
Peak memory 263944 kb
Host smart-4f0f0cb3-3bfa-4f76-8303-679e99ffdf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771421200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.771421200
Directory /workspace/13.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/13.flash_ctrl_smoke.839666110
Short name T554
Test name
Test status
Simulation time 696468900 ps
CPU time 199.45 seconds
Started Jun 09 02:50:55 PM PDT 24
Finished Jun 09 02:54:14 PM PDT 24
Peak memory 281884 kb
Host smart-ccbf8433-f293-487f-8f9c-9f15276b2582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839666110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.839666110
Directory /workspace/13.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/13.flash_ctrl_wo.4281237157
Short name T547
Test name
Test status
Simulation time 10633482900 ps
CPU time 237.91 seconds
Started Jun 09 02:51:03 PM PDT 24
Finished Jun 09 02:55:01 PM PDT 24
Peak memory 260348 kb
Host smart-ff9890d9-c40d-4df3-8d56-7a4460ae8cb6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281237157 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.flash_ctrl_wo.4281237157
Directory /workspace/13.flash_ctrl_wo/latest

Test location /workspace/coverage/default/14.flash_ctrl_alert_test.1767207928
Short name T562
Test name
Test status
Simulation time 40717600 ps
CPU time 13.63 seconds
Started Jun 09 02:51:47 PM PDT 24
Finished Jun 09 02:52:01 PM PDT 24
Peak memory 258592 kb
Host smart-06a1758a-6da5-422b-a59f-951cced3cca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767207928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.
1767207928
Directory /workspace/14.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.flash_ctrl_connect.3027249098
Short name T461
Test name
Test status
Simulation time 14944500 ps
CPU time 16.27 seconds
Started Jun 09 02:51:40 PM PDT 24
Finished Jun 09 02:51:57 PM PDT 24
Peak memory 275344 kb
Host smart-015bc6d7-f375-4c9f-8f3b-ff43a44d3f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027249098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.3027249098
Directory /workspace/14.flash_ctrl_connect/latest

Test location /workspace/coverage/default/14.flash_ctrl_disable.3553305861
Short name T387
Test name
Test status
Simulation time 19889300 ps
CPU time 21.82 seconds
Started Jun 09 02:51:42 PM PDT 24
Finished Jun 09 02:52:04 PM PDT 24
Peak memory 265704 kb
Host smart-27e07f1f-ab82-411e-9611-73f6e13e9014
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553305861 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_disable.3553305861
Directory /workspace/14.flash_ctrl_disable/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.1321513051
Short name T219
Test name
Test status
Simulation time 34708400 ps
CPU time 13.74 seconds
Started Jun 09 02:51:48 PM PDT 24
Finished Jun 09 02:52:02 PM PDT 24
Peak memory 258860 kb
Host smart-e81b3855-8b6a-41ba-84b5-e79c4a572681
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321513051 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.1321513051
Directory /workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_rma_reset.951875954
Short name T148
Test name
Test status
Simulation time 480332359400 ps
CPU time 972.83 seconds
Started Jun 09 02:51:21 PM PDT 24
Finished Jun 09 03:07:35 PM PDT 24
Peak memory 265092 kb
Host smart-17831a7f-2587-4805-a2b9-7bcfaa2d4999
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951875954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 14.flash_ctrl_hw_rma_reset.951875954
Directory /workspace/14.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_hw_sec_otp.2054105865
Short name T1019
Test name
Test status
Simulation time 7457599700 ps
CPU time 67.77 seconds
Started Jun 09 02:51:23 PM PDT 24
Finished Jun 09 02:52:31 PM PDT 24
Peak memory 262896 kb
Host smart-7c54f27e-b723-4070-baae-284b4badef3d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054105865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
hw_sec_otp.2054105865
Directory /workspace/14.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd.30355885
Short name T961
Test name
Test status
Simulation time 3506575000 ps
CPU time 232.52 seconds
Started Jun 09 02:51:40 PM PDT 24
Finished Jun 09 02:55:33 PM PDT 24
Peak memory 285228 kb
Host smart-1099f5cd-1c8b-4453-8843-d4dd8930bfad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30355885 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash
_ctrl_intr_rd.30355885
Directory /workspace/14.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.2322757136
Short name T431
Test name
Test status
Simulation time 25502912200 ps
CPU time 286.29 seconds
Started Jun 09 02:51:38 PM PDT 24
Finished Jun 09 02:56:24 PM PDT 24
Peak memory 291368 kb
Host smart-fb23715e-2d73-4076-a8e8-7c72c0d03218
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322757136 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.2322757136
Directory /workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/14.flash_ctrl_invalid_op.311620887
Short name T433
Test name
Test status
Simulation time 1701305800 ps
CPU time 64.91 seconds
Started Jun 09 02:51:32 PM PDT 24
Finished Jun 09 02:52:37 PM PDT 24
Peak memory 263876 kb
Host smart-a865a992-c7ab-4c79-b868-b19db55fc309
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311620887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.311620887
Directory /workspace/14.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2884789121
Short name T144
Test name
Test status
Simulation time 24918600 ps
CPU time 13.45 seconds
Started Jun 09 02:51:42 PM PDT 24
Finished Jun 09 02:51:56 PM PDT 24
Peak memory 265420 kb
Host smart-a5e35a2c-0d1a-4b68-981a-b4ad2431a86d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884789121 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.2884789121
Directory /workspace/14.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/14.flash_ctrl_mp_regions.1559153662
Short name T1003
Test name
Test status
Simulation time 14318814200 ps
CPU time 541.22 seconds
Started Jun 09 02:51:30 PM PDT 24
Finished Jun 09 03:00:31 PM PDT 24
Peak memory 274636 kb
Host smart-95c09db0-941b-444d-a585-d2de756c5be7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559153662 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_mp_regions.1559153662
Directory /workspace/14.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/14.flash_ctrl_phy_arb.3330448526
Short name T87
Test name
Test status
Simulation time 253197700 ps
CPU time 272.32 seconds
Started Jun 09 02:51:23 PM PDT 24
Finished Jun 09 02:55:55 PM PDT 24
Peak memory 263304 kb
Host smart-37b7afdf-dfd7-4077-b51f-5dd3ac4d4c3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3330448526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.3330448526
Directory /workspace/14.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/14.flash_ctrl_prog_reset.3233841665
Short name T928
Test name
Test status
Simulation time 2300556000 ps
CPU time 212.51 seconds
Started Jun 09 02:51:39 PM PDT 24
Finished Jun 09 02:55:11 PM PDT 24
Peak memory 260496 kb
Host smart-b61c4627-d72b-44fb-afab-58f3c9fa405b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233841665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_re
set.3233841665
Directory /workspace/14.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/14.flash_ctrl_rand_ops.1797402117
Short name T90
Test name
Test status
Simulation time 3078517100 ps
CPU time 716.72 seconds
Started Jun 09 02:51:22 PM PDT 24
Finished Jun 09 03:03:19 PM PDT 24
Peak memory 286272 kb
Host smart-8a410fab-f0ba-419d-8d05-171102046c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797402117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.1797402117
Directory /workspace/14.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/14.flash_ctrl_re_evict.2952217656
Short name T363
Test name
Test status
Simulation time 151838600 ps
CPU time 36.23 seconds
Started Jun 09 02:51:43 PM PDT 24
Finished Jun 09 02:52:19 PM PDT 24
Peak memory 277840 kb
Host smart-d8666346-44fb-4e1a-a037-c481f92fe21c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952217656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_re_evict.2952217656
Directory /workspace/14.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_ro.3115919180
Short name T610
Test name
Test status
Simulation time 567472100 ps
CPU time 125.9 seconds
Started Jun 09 02:51:32 PM PDT 24
Finished Jun 09 02:53:39 PM PDT 24
Peak memory 282208 kb
Host smart-575e10ed-e3ad-4187-96db-f7a20856b3c4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115919180 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 14.flash_ctrl_ro.3115919180
Directory /workspace/14.flash_ctrl_ro/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw.2836102270
Short name T1017
Test name
Test status
Simulation time 3264249900 ps
CPU time 576.09 seconds
Started Jun 09 02:51:34 PM PDT 24
Finished Jun 09 03:01:10 PM PDT 24
Peak memory 310084 kb
Host smart-4aba1269-be2d-4c95-b4e5-fd04f21cb88d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836102270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.flash_ctrl_rw.2836102270
Directory /workspace/14.flash_ctrl_rw/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict.1051572977
Short name T1064
Test name
Test status
Simulation time 70554400 ps
CPU time 30.57 seconds
Started Jun 09 02:51:43 PM PDT 24
Finished Jun 09 02:52:14 PM PDT 24
Peak memory 276088 kb
Host smart-d30a72f0-0817-4ba9-9ccc-f2dfe48864bc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051572977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_rw_evict.1051572977
Directory /workspace/14.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.3312930404
Short name T524
Test name
Test status
Simulation time 44737700 ps
CPU time 31.1 seconds
Started Jun 09 02:51:43 PM PDT 24
Finished Jun 09 02:52:14 PM PDT 24
Peak memory 267848 kb
Host smart-39b9dc19-163a-4cc7-b27a-bdbbe1ef4e72
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312930404 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.3312930404
Directory /workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/14.flash_ctrl_smoke.127364731
Short name T921
Test name
Test status
Simulation time 25476600 ps
CPU time 120.77 seconds
Started Jun 09 02:51:19 PM PDT 24
Finished Jun 09 02:53:20 PM PDT 24
Peak memory 279028 kb
Host smart-9437cd3c-4b05-4afd-b3d6-8af860569f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127364731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.127364731
Directory /workspace/14.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/14.flash_ctrl_wo.4148848353
Short name T642
Test name
Test status
Simulation time 2580856200 ps
CPU time 207.57 seconds
Started Jun 09 02:51:34 PM PDT 24
Finished Jun 09 02:55:02 PM PDT 24
Peak memory 265552 kb
Host smart-86b798ec-9215-4601-813a-12084dcc572b
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148848353 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.flash_ctrl_wo.4148848353
Directory /workspace/14.flash_ctrl_wo/latest

Test location /workspace/coverage/default/15.flash_ctrl_alert_test.2524885530
Short name T979
Test name
Test status
Simulation time 201892700 ps
CPU time 14.21 seconds
Started Jun 09 02:52:09 PM PDT 24
Finished Jun 09 02:52:24 PM PDT 24
Peak memory 258820 kb
Host smart-91a7ebc0-de20-4ae7-b92c-eecabcb071a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524885530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.
2524885530
Directory /workspace/15.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.flash_ctrl_connect.2972757687
Short name T613
Test name
Test status
Simulation time 104172400 ps
CPU time 15.64 seconds
Started Jun 09 02:52:05 PM PDT 24
Finished Jun 09 02:52:21 PM PDT 24
Peak memory 275028 kb
Host smart-87868dd3-8296-4399-bc02-6b0572e29166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972757687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.2972757687
Directory /workspace/15.flash_ctrl_connect/latest

Test location /workspace/coverage/default/15.flash_ctrl_disable.2274099184
Short name T644
Test name
Test status
Simulation time 21291300 ps
CPU time 21.53 seconds
Started Jun 09 02:52:07 PM PDT 24
Finished Jun 09 02:52:28 PM PDT 24
Peak memory 274048 kb
Host smart-2d4600a2-3a6d-407e-a55b-d54ddbffd8b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274099184 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_disable.2274099184
Directory /workspace/15.flash_ctrl_disable/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2611224995
Short name T516
Test name
Test status
Simulation time 10030795800 ps
CPU time 60.66 seconds
Started Jun 09 02:52:10 PM PDT 24
Finished Jun 09 02:53:11 PM PDT 24
Peak memory 276728 kb
Host smart-c0160d8a-b118-4204-8598-e7a1ed281392
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611224995 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.2611224995
Directory /workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.2110353024
Short name T304
Test name
Test status
Simulation time 22672600 ps
CPU time 13.23 seconds
Started Jun 09 02:52:10 PM PDT 24
Finished Jun 09 02:52:23 PM PDT 24
Peak memory 258892 kb
Host smart-20588b40-2688-449f-beef-766d108556db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110353024 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.2110353024
Directory /workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_rma_reset.1306927684
Short name T1014
Test name
Test status
Simulation time 160176148800 ps
CPU time 945.45 seconds
Started Jun 09 02:51:52 PM PDT 24
Finished Jun 09 03:07:38 PM PDT 24
Peak memory 264592 kb
Host smart-c98578d4-8863-49f7-8a0e-7cd784c2a54f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306927684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.flash_ctrl_hw_rma_reset.1306927684
Directory /workspace/15.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_hw_sec_otp.2703684432
Short name T858
Test name
Test status
Simulation time 6367950100 ps
CPU time 130.14 seconds
Started Jun 09 02:51:47 PM PDT 24
Finished Jun 09 02:53:57 PM PDT 24
Peak memory 263332 kb
Host smart-088c0195-d420-4614-ba71-2cb9a49e034d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703684432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_
hw_sec_otp.2703684432
Directory /workspace/15.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd.3725649478
Short name T947
Test name
Test status
Simulation time 1354341900 ps
CPU time 201.18 seconds
Started Jun 09 02:52:00 PM PDT 24
Finished Jun 09 02:55:22 PM PDT 24
Peak memory 291608 kb
Host smart-881daffe-294f-4e02-9dc6-960251515d4a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725649478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_intr_rd.3725649478
Directory /workspace/15.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.88535589
Short name T905
Test name
Test status
Simulation time 8319223300 ps
CPU time 208.61 seconds
Started Jun 09 02:52:02 PM PDT 24
Finished Jun 09 02:55:31 PM PDT 24
Peak memory 293400 kb
Host smart-f3e61edf-52b2-43a3-a877-ba4dd9b05ec3
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88535589 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.88535589
Directory /workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/15.flash_ctrl_invalid_op.334272344
Short name T953
Test name
Test status
Simulation time 3192193500 ps
CPU time 73.77 seconds
Started Jun 09 02:51:57 PM PDT 24
Finished Jun 09 02:53:11 PM PDT 24
Peak memory 261036 kb
Host smart-afc65b60-39b3-4bcd-b3be-0ad7ab83de21
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334272344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.334272344
Directory /workspace/15.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3369833513
Short name T142
Test name
Test status
Simulation time 15754500 ps
CPU time 13.62 seconds
Started Jun 09 02:52:08 PM PDT 24
Finished Jun 09 02:52:22 PM PDT 24
Peak memory 265300 kb
Host smart-8276668e-81c5-4878-a885-088c12219b45
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369833513 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3369833513
Directory /workspace/15.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/15.flash_ctrl_mp_regions.1746339487
Short name T252
Test name
Test status
Simulation time 33166742800 ps
CPU time 692.07 seconds
Started Jun 09 02:51:56 PM PDT 24
Finished Jun 09 03:03:29 PM PDT 24
Peak memory 275320 kb
Host smart-4c6f8f2e-5c6a-4b40-9508-012c215817a7
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746339487 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_mp_regions.1746339487
Directory /workspace/15.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/15.flash_ctrl_otp_reset.2843490102
Short name T69
Test name
Test status
Simulation time 37102800 ps
CPU time 108.71 seconds
Started Jun 09 02:51:52 PM PDT 24
Finished Jun 09 02:53:41 PM PDT 24
Peak memory 260260 kb
Host smart-fd7a5715-27f3-49db-9888-1e4a1019a2fe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843490102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_o
tp_reset.2843490102
Directory /workspace/15.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_phy_arb.2436542509
Short name T647
Test name
Test status
Simulation time 108338000 ps
CPU time 152.25 seconds
Started Jun 09 02:51:49 PM PDT 24
Finished Jun 09 02:54:22 PM PDT 24
Peak memory 263400 kb
Host smart-179cf9ed-5c07-450a-a283-0394cdae5afc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2436542509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2436542509
Directory /workspace/15.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/15.flash_ctrl_prog_reset.2687004717
Short name T1018
Test name
Test status
Simulation time 7109055700 ps
CPU time 159.36 seconds
Started Jun 09 02:52:02 PM PDT 24
Finished Jun 09 02:54:42 PM PDT 24
Peak memory 260492 kb
Host smart-e067b64b-d031-4097-954a-1e9e35e1c0c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687004717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_re
set.2687004717
Directory /workspace/15.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/15.flash_ctrl_rand_ops.3360298437
Short name T93
Test name
Test status
Simulation time 756516500 ps
CPU time 539.85 seconds
Started Jun 09 02:51:48 PM PDT 24
Finished Jun 09 03:00:48 PM PDT 24
Peak memory 281904 kb
Host smart-31dc0b0c-c7fb-446a-a179-4a46ae51bbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360298437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.3360298437
Directory /workspace/15.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/15.flash_ctrl_re_evict.4184835400
Short name T478
Test name
Test status
Simulation time 223125300 ps
CPU time 35.55 seconds
Started Jun 09 02:52:05 PM PDT 24
Finished Jun 09 02:52:41 PM PDT 24
Peak memory 276048 kb
Host smart-5c489f89-643c-410e-9238-6901fc908b5b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184835400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_re_evict.4184835400
Directory /workspace/15.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/15.flash_ctrl_ro.3643780415
Short name T182
Test name
Test status
Simulation time 708025700 ps
CPU time 155.23 seconds
Started Jun 09 02:51:56 PM PDT 24
Finished Jun 09 02:54:31 PM PDT 24
Peak memory 290468 kb
Host smart-d76529c7-9375-4084-a5c1-43a562c94961
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643780415 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_ro.3643780415
Directory /workspace/15.flash_ctrl_ro/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw.1875439081
Short name T617
Test name
Test status
Simulation time 15872089700 ps
CPU time 566.59 seconds
Started Jun 09 02:51:55 PM PDT 24
Finished Jun 09 03:01:22 PM PDT 24
Peak memory 314844 kb
Host smart-891329c7-db2e-4665-80f7-bca8521a578e
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875439081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.flash_ctrl_rw.1875439081
Directory /workspace/15.flash_ctrl_rw/latest

Test location /workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.4173192408
Short name T786
Test name
Test status
Simulation time 77697200 ps
CPU time 30.79 seconds
Started Jun 09 02:52:01 PM PDT 24
Finished Jun 09 02:52:32 PM PDT 24
Peak memory 276012 kb
Host smart-c0088214-5da7-4ca1-b872-1831a0a0eed7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173192408 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict_all_en.4173192408
Directory /workspace/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/15.flash_ctrl_sec_info_access.3703288232
Short name T546
Test name
Test status
Simulation time 1736972900 ps
CPU time 60.95 seconds
Started Jun 09 02:52:06 PM PDT 24
Finished Jun 09 02:53:07 PM PDT 24
Peak memory 264324 kb
Host smart-80425a98-6f19-4fcd-8d63-fcf56e98b023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703288232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3703288232
Directory /workspace/15.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/15.flash_ctrl_smoke.3748619212
Short name T684
Test name
Test status
Simulation time 26781000 ps
CPU time 122.41 seconds
Started Jun 09 02:51:51 PM PDT 24
Finished Jun 09 02:53:54 PM PDT 24
Peak memory 276856 kb
Host smart-dbbf4067-1036-43cb-b519-2fd396a0b3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748619212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.3748619212
Directory /workspace/15.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/15.flash_ctrl_wo.611945345
Short name T909
Test name
Test status
Simulation time 5461037100 ps
CPU time 195.85 seconds
Started Jun 09 02:51:54 PM PDT 24
Finished Jun 09 02:55:10 PM PDT 24
Peak memory 261308 kb
Host smart-fa0c148f-e534-4338-a486-efe41bfcd9bf
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611945345 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.flash_ctrl_wo.611945345
Directory /workspace/15.flash_ctrl_wo/latest

Test location /workspace/coverage/default/16.flash_ctrl_alert_test.3915047806
Short name T459
Test name
Test status
Simulation time 96016100 ps
CPU time 13.56 seconds
Started Jun 09 02:52:34 PM PDT 24
Finished Jun 09 02:52:47 PM PDT 24
Peak memory 258540 kb
Host smart-acb22751-b17f-4252-b741-46963bd53aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915047806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.
3915047806
Directory /workspace/16.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.flash_ctrl_connect.2945225965
Short name T717
Test name
Test status
Simulation time 49677400 ps
CPU time 16.15 seconds
Started Jun 09 02:52:33 PM PDT 24
Finished Jun 09 02:52:50 PM PDT 24
Peak memory 284588 kb
Host smart-5aaaf95e-fdbd-445d-97f4-cec572366f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945225965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.2945225965
Directory /workspace/16.flash_ctrl_connect/latest

Test location /workspace/coverage/default/16.flash_ctrl_disable.1510220469
Short name T863
Test name
Test status
Simulation time 18428300 ps
CPU time 22.58 seconds
Started Jun 09 02:52:29 PM PDT 24
Finished Jun 09 02:52:51 PM PDT 24
Peak memory 265824 kb
Host smart-01658125-0d1d-4c95-bf27-4d7f9b4ed1c7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510220469 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_disable.1510220469
Directory /workspace/16.flash_ctrl_disable/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2284997372
Short name T151
Test name
Test status
Simulation time 10032408700 ps
CPU time 63.21 seconds
Started Jun 09 02:52:32 PM PDT 24
Finished Jun 09 02:53:36 PM PDT 24
Peak memory 272260 kb
Host smart-fd6c231c-d94d-4f9f-bb88-02386b05e21e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284997372 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.2284997372
Directory /workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.3004934790
Short name T231
Test name
Test status
Simulation time 31929700 ps
CPU time 13.5 seconds
Started Jun 09 02:52:33 PM PDT 24
Finished Jun 09 02:52:46 PM PDT 24
Peak memory 265360 kb
Host smart-606ba32d-8e34-404e-a06c-73bf6a1bcc92
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004934790 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.3004934790
Directory /workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.1513470094
Short name T815
Test name
Test status
Simulation time 80153547200 ps
CPU time 970.22 seconds
Started Jun 09 02:52:10 PM PDT 24
Finished Jun 09 03:08:20 PM PDT 24
Peak memory 264572 kb
Host smart-2b0511f3-4fc6-421e-bdda-254bd6a91083
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513470094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.flash_ctrl_hw_rma_reset.1513470094
Directory /workspace/16.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_hw_sec_otp.3787707907
Short name T686
Test name
Test status
Simulation time 2533936800 ps
CPU time 113.01 seconds
Started Jun 09 02:52:10 PM PDT 24
Finished Jun 09 02:54:03 PM PDT 24
Peak memory 263296 kb
Host smart-e5335df2-f2d2-46c9-abc3-9bbec2d27091
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787707907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_
hw_sec_otp.3787707907
Directory /workspace/16.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd.2103679142
Short name T669
Test name
Test status
Simulation time 1174801600 ps
CPU time 132.93 seconds
Started Jun 09 02:52:25 PM PDT 24
Finished Jun 09 02:54:38 PM PDT 24
Peak memory 294320 kb
Host smart-cc3ec675-97a7-4083-9b0e-179459f874dc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103679142 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_intr_rd.2103679142
Directory /workspace/16.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3847993263
Short name T857
Test name
Test status
Simulation time 25365693300 ps
CPU time 323.06 seconds
Started Jun 09 02:52:24 PM PDT 24
Finished Jun 09 02:57:47 PM PDT 24
Peak memory 285224 kb
Host smart-915813c2-d15d-43fd-a0c8-89108edfb9db
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847993263 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.3847993263
Directory /workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/16.flash_ctrl_invalid_op.3468220859
Short name T1005
Test name
Test status
Simulation time 3376216900 ps
CPU time 71.37 seconds
Started Jun 09 02:52:16 PM PDT 24
Finished Jun 09 02:53:28 PM PDT 24
Peak memory 260832 kb
Host smart-377ad34f-7362-4523-be7b-097a43a1c6ca
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468220859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.3
468220859
Directory /workspace/16.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/16.flash_ctrl_lcmgr_intg.2102856434
Short name T309
Test name
Test status
Simulation time 47379400 ps
CPU time 13.47 seconds
Started Jun 09 02:52:33 PM PDT 24
Finished Jun 09 02:52:46 PM PDT 24
Peak memory 265280 kb
Host smart-05cf4a6a-7bf3-4f8d-a670-d35a1ead1604
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102856434 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.2102856434
Directory /workspace/16.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/16.flash_ctrl_mp_regions.1195411153
Short name T102
Test name
Test status
Simulation time 5690831400 ps
CPU time 434.86 seconds
Started Jun 09 02:52:15 PM PDT 24
Finished Jun 09 02:59:31 PM PDT 24
Peak memory 274416 kb
Host smart-4a170b0a-0bf6-48ab-8f83-c3b8205a85ee
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195411153 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_mp_regions.1195411153
Directory /workspace/16.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/16.flash_ctrl_otp_reset.1861689987
Short name T141
Test name
Test status
Simulation time 37903100 ps
CPU time 108.43 seconds
Started Jun 09 02:52:16 PM PDT 24
Finished Jun 09 02:54:05 PM PDT 24
Peak memory 260536 kb
Host smart-2bbd3a64-f65e-4d8c-ad71-7c4e1608d299
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861689987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o
tp_reset.1861689987
Directory /workspace/16.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_phy_arb.72373351
Short name T731
Test name
Test status
Simulation time 154653600 ps
CPU time 153.51 seconds
Started Jun 09 02:52:09 PM PDT 24
Finished Jun 09 02:54:43 PM PDT 24
Peak memory 263496 kb
Host smart-c2e036aa-cd59-4715-a2b9-06b53a7bafed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=72373351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.72373351
Directory /workspace/16.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/16.flash_ctrl_prog_reset.2125807105
Short name T776
Test name
Test status
Simulation time 81988200 ps
CPU time 18.56 seconds
Started Jun 09 02:52:22 PM PDT 24
Finished Jun 09 02:52:41 PM PDT 24
Peak memory 265580 kb
Host smart-32cb27a4-f3e5-4547-a8bc-fe68af5b8405
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125807105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_re
set.2125807105
Directory /workspace/16.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/16.flash_ctrl_rand_ops.578684802
Short name T738
Test name
Test status
Simulation time 32122900 ps
CPU time 124.8 seconds
Started Jun 09 02:52:10 PM PDT 24
Finished Jun 09 02:54:15 PM PDT 24
Peak memory 269880 kb
Host smart-a08503bb-6eed-41bb-84e0-a150768bbdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578684802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.578684802
Directory /workspace/16.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/16.flash_ctrl_re_evict.939195687
Short name T357
Test name
Test status
Simulation time 162816800 ps
CPU time 37.2 seconds
Started Jun 09 02:52:26 PM PDT 24
Finished Jun 09 02:53:03 PM PDT 24
Peak memory 278224 kb
Host smart-14768281-363b-406e-984d-42dd5b2d571a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939195687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_re_evict.939195687
Directory /workspace/16.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_ro.1995327873
Short name T204
Test name
Test status
Simulation time 2437993900 ps
CPU time 141.17 seconds
Started Jun 09 02:52:20 PM PDT 24
Finished Jun 09 02:54:42 PM PDT 24
Peak memory 289628 kb
Host smart-99a300be-6e68-468e-a8f1-cc4c810c5132
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995327873 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_ro.1995327873
Directory /workspace/16.flash_ctrl_ro/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw.3248187389
Short name T753
Test name
Test status
Simulation time 3757545600 ps
CPU time 604.9 seconds
Started Jun 09 02:52:20 PM PDT 24
Finished Jun 09 03:02:25 PM PDT 24
Peak memory 309696 kb
Host smart-f8e75964-33c7-4915-aa33-8ab9d62c754d
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248187389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.flash_ctrl_rw.3248187389
Directory /workspace/16.flash_ctrl_rw/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict.2926056654
Short name T582
Test name
Test status
Simulation time 30997700 ps
CPU time 30.08 seconds
Started Jun 09 02:52:24 PM PDT 24
Finished Jun 09 02:52:54 PM PDT 24
Peak memory 275828 kb
Host smart-77c69995-1640-44b4-aa1e-5f7648724979
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926056654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl
ash_ctrl_rw_evict.2926056654
Directory /workspace/16.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.699852791
Short name T6
Test name
Test status
Simulation time 48307000 ps
CPU time 31.83 seconds
Started Jun 09 02:52:22 PM PDT 24
Finished Jun 09 02:52:54 PM PDT 24
Peak memory 276008 kb
Host smart-66e7ad85-0a92-488c-a883-c581e7f778c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699852791 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.699852791
Directory /workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/16.flash_ctrl_sec_info_access.253063945
Short name T412
Test name
Test status
Simulation time 3548187400 ps
CPU time 73.3 seconds
Started Jun 09 02:52:29 PM PDT 24
Finished Jun 09 02:53:43 PM PDT 24
Peak memory 263840 kb
Host smart-8ea46699-2f18-4255-9b31-caf96e307576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253063945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.253063945
Directory /workspace/16.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/16.flash_ctrl_smoke.1918562410
Short name T1055
Test name
Test status
Simulation time 705451300 ps
CPU time 145.65 seconds
Started Jun 09 02:52:10 PM PDT 24
Finished Jun 09 02:54:36 PM PDT 24
Peak memory 272796 kb
Host smart-525014df-e46c-40d2-8a65-430a8ec07349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918562410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.1918562410
Directory /workspace/16.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/16.flash_ctrl_wo.1775311755
Short name T1070
Test name
Test status
Simulation time 7719764600 ps
CPU time 152.29 seconds
Started Jun 09 02:52:19 PM PDT 24
Finished Jun 09 02:54:52 PM PDT 24
Peak memory 260240 kb
Host smart-4c180d4c-f57a-437a-8dfa-aac4e7dbd1f6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775311755 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.flash_ctrl_wo.1775311755
Directory /workspace/16.flash_ctrl_wo/latest

Test location /workspace/coverage/default/17.flash_ctrl_alert_test.270776852
Short name T430
Test name
Test status
Simulation time 46967600 ps
CPU time 13.54 seconds
Started Jun 09 02:52:59 PM PDT 24
Finished Jun 09 02:53:13 PM PDT 24
Peak memory 258596 kb
Host smart-b56210ec-4f8e-4131-9249-9007a1ebcd42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270776852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.270776852
Directory /workspace/17.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.flash_ctrl_connect.1120268192
Short name T1033
Test name
Test status
Simulation time 23531300 ps
CPU time 15.86 seconds
Started Jun 09 02:53:00 PM PDT 24
Finished Jun 09 02:53:16 PM PDT 24
Peak memory 275236 kb
Host smart-44c951ca-58aa-4bdc-b6eb-e2a86ed83585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120268192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.1120268192
Directory /workspace/17.flash_ctrl_connect/latest

Test location /workspace/coverage/default/17.flash_ctrl_disable.4183990287
Short name T1057
Test name
Test status
Simulation time 20441000 ps
CPU time 22.05 seconds
Started Jun 09 02:52:55 PM PDT 24
Finished Jun 09 02:53:17 PM PDT 24
Peak memory 265944 kb
Host smart-3ef220d2-9e08-40dc-a24f-a0d2e68d421b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183990287 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_disable.4183990287
Directory /workspace/17.flash_ctrl_disable/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.4294378387
Short name T306
Test name
Test status
Simulation time 10034704700 ps
CPU time 48.69 seconds
Started Jun 09 02:52:59 PM PDT 24
Finished Jun 09 02:53:48 PM PDT 24
Peak memory 266952 kb
Host smart-672480c2-9d84-4b96-bfe8-0dad8632acc6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294378387 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.4294378387
Directory /workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.114939924
Short name T298
Test name
Test status
Simulation time 45517300 ps
CPU time 13.47 seconds
Started Jun 09 02:52:59 PM PDT 24
Finished Jun 09 02:53:13 PM PDT 24
Peak memory 265856 kb
Host smart-ce46311d-c930-472c-842c-a167fb958877
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114939924 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.114939924
Directory /workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_rma_reset.762553963
Short name T645
Test name
Test status
Simulation time 80153476400 ps
CPU time 968.53 seconds
Started Jun 09 02:52:38 PM PDT 24
Finished Jun 09 03:08:47 PM PDT 24
Peak memory 261244 kb
Host smart-1ad63a8e-cb59-4687-a7f2-87680e44aece
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762553963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 17.flash_ctrl_hw_rma_reset.762553963
Directory /workspace/17.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_hw_sec_otp.1063043119
Short name T922
Test name
Test status
Simulation time 8855426600 ps
CPU time 192.06 seconds
Started Jun 09 02:52:35 PM PDT 24
Finished Jun 09 02:55:48 PM PDT 24
Peak memory 263168 kb
Host smart-07a1f48b-4c59-40bf-a633-b2f9e4565634
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063043119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_
hw_sec_otp.1063043119
Directory /workspace/17.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd.3470239189
Short name T954
Test name
Test status
Simulation time 1759134100 ps
CPU time 225.8 seconds
Started Jun 09 02:52:52 PM PDT 24
Finished Jun 09 02:56:38 PM PDT 24
Peak memory 285228 kb
Host smart-8057c6d7-380c-46fa-89fa-44568d4b07be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470239189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_intr_rd.3470239189
Directory /workspace/17.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.106917919
Short name T944
Test name
Test status
Simulation time 8342559400 ps
CPU time 194.11 seconds
Started Jun 09 02:52:49 PM PDT 24
Finished Jun 09 02:56:04 PM PDT 24
Peak memory 292352 kb
Host smart-17670ff3-8aaf-4274-a614-c1569a533097
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106917919 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.106917919
Directory /workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/17.flash_ctrl_invalid_op.3088706959
Short name T436
Test name
Test status
Simulation time 4627606000 ps
CPU time 95.7 seconds
Started Jun 09 02:52:45 PM PDT 24
Finished Jun 09 02:54:21 PM PDT 24
Peak memory 263436 kb
Host smart-86e231f6-8c79-4389-a646-48f5aafbe67c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088706959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.3
088706959
Directory /workspace/17.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/17.flash_ctrl_lcmgr_intg.3061041646
Short name T880
Test name
Test status
Simulation time 26655200 ps
CPU time 13.51 seconds
Started Jun 09 02:52:59 PM PDT 24
Finished Jun 09 02:53:13 PM PDT 24
Peak memory 260244 kb
Host smart-019d030a-2811-4224-9044-89aa544b4adc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061041646 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.3061041646
Directory /workspace/17.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/17.flash_ctrl_mp_regions.2032655075
Short name T1028
Test name
Test status
Simulation time 45795865400 ps
CPU time 362.55 seconds
Started Jun 09 02:52:40 PM PDT 24
Finished Jun 09 02:58:43 PM PDT 24
Peak memory 275380 kb
Host smart-5f330a95-a1f7-4653-b7ad-20e9a1bf6053
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032655075 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_mp_regions.2032655075
Directory /workspace/17.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/17.flash_ctrl_otp_reset.748131183
Short name T67
Test name
Test status
Simulation time 589382500 ps
CPU time 132.51 seconds
Started Jun 09 02:52:41 PM PDT 24
Finished Jun 09 02:54:54 PM PDT 24
Peak memory 265320 kb
Host smart-a7138c35-d689-4cb6-8fad-044d0da0eae3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748131183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ot
p_reset.748131183
Directory /workspace/17.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_phy_arb.62658853
Short name T4
Test name
Test status
Simulation time 1393479700 ps
CPU time 566.59 seconds
Started Jun 09 02:52:37 PM PDT 24
Finished Jun 09 03:02:04 PM PDT 24
Peak memory 263508 kb
Host smart-1099b6d2-1390-4489-84c5-b6e6b4fd383c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=62658853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.62658853
Directory /workspace/17.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/17.flash_ctrl_prog_reset.1101246232
Short name T85
Test name
Test status
Simulation time 66923100 ps
CPU time 13.79 seconds
Started Jun 09 02:52:50 PM PDT 24
Finished Jun 09 02:53:04 PM PDT 24
Peak memory 265532 kb
Host smart-755d7e87-2da7-43c8-8bec-42bb6fd831f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101246232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_re
set.1101246232
Directory /workspace/17.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/17.flash_ctrl_rand_ops.2119772283
Short name T767
Test name
Test status
Simulation time 82468200 ps
CPU time 577.09 seconds
Started Jun 09 02:52:37 PM PDT 24
Finished Jun 09 03:02:15 PM PDT 24
Peak memory 285764 kb
Host smart-30a4d80b-baac-450f-9e68-01bf5520c935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119772283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2119772283
Directory /workspace/17.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/17.flash_ctrl_re_evict.2362533656
Short name T772
Test name
Test status
Simulation time 113218300 ps
CPU time 34.38 seconds
Started Jun 09 02:52:54 PM PDT 24
Finished Jun 09 02:53:29 PM PDT 24
Peak memory 275636 kb
Host smart-d1882ddf-98c4-484b-873f-25aaea7493f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362533656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_re_evict.2362533656
Directory /workspace/17.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_ro.3778320547
Short name T654
Test name
Test status
Simulation time 900580800 ps
CPU time 99.8 seconds
Started Jun 09 02:52:50 PM PDT 24
Finished Jun 09 02:54:30 PM PDT 24
Peak memory 282084 kb
Host smart-661a14ea-8c26-4951-bfe0-08d0518a21c6
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778320547 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 17.flash_ctrl_ro.3778320547
Directory /workspace/17.flash_ctrl_ro/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw.3256943599
Short name T178
Test name
Test status
Simulation time 41186700800 ps
CPU time 748.99 seconds
Started Jun 09 02:52:50 PM PDT 24
Finished Jun 09 03:05:20 PM PDT 24
Peak memory 310184 kb
Host smart-e1aa44de-f9ba-4fc9-b1bf-49a7a4f590cf
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256943599 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.flash_ctrl_rw.3256943599
Directory /workspace/17.flash_ctrl_rw/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict.224022255
Short name T757
Test name
Test status
Simulation time 29292300 ps
CPU time 28.23 seconds
Started Jun 09 02:52:55 PM PDT 24
Finished Jun 09 02:53:23 PM PDT 24
Peak memory 276988 kb
Host smart-37ecae30-2db7-4580-8398-c65fd291defe
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224022255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_rw_evict.224022255
Directory /workspace/17.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.3284168809
Short name T816
Test name
Test status
Simulation time 55049700 ps
CPU time 31.45 seconds
Started Jun 09 02:52:55 PM PDT 24
Finished Jun 09 02:53:26 PM PDT 24
Peak memory 267904 kb
Host smart-62a62f88-2c51-4f98-885c-6e5170fc3462
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284168809 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.3284168809
Directory /workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/17.flash_ctrl_sec_info_access.1074109354
Short name T837
Test name
Test status
Simulation time 1243560900 ps
CPU time 71.03 seconds
Started Jun 09 02:52:53 PM PDT 24
Finished Jun 09 02:54:05 PM PDT 24
Peak memory 265220 kb
Host smart-a5aeba25-cbe4-4102-aad8-3071f343adeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074109354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1074109354
Directory /workspace/17.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/17.flash_ctrl_smoke.758428107
Short name T584
Test name
Test status
Simulation time 101530600 ps
CPU time 50.91 seconds
Started Jun 09 02:52:37 PM PDT 24
Finished Jun 09 02:53:28 PM PDT 24
Peak memory 271408 kb
Host smart-efaf061f-0705-40fb-81fe-43ff128ec3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758428107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.758428107
Directory /workspace/17.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/17.flash_ctrl_wo.518715810
Short name T977
Test name
Test status
Simulation time 2282128300 ps
CPU time 178.23 seconds
Started Jun 09 02:52:45 PM PDT 24
Finished Jun 09 02:55:43 PM PDT 24
Peak memory 265548 kb
Host smart-e2b35ff7-f4af-4f19-b39a-ee477ed14e52
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518715810 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.flash_ctrl_wo.518715810
Directory /workspace/17.flash_ctrl_wo/latest

Test location /workspace/coverage/default/18.flash_ctrl_alert_test.3494862230
Short name T721
Test name
Test status
Simulation time 393001900 ps
CPU time 14.54 seconds
Started Jun 09 02:53:23 PM PDT 24
Finished Jun 09 02:53:38 PM PDT 24
Peak memory 258604 kb
Host smart-dc1a8b45-8123-4632-aff9-c19e10b5e8bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494862230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.
3494862230
Directory /workspace/18.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.flash_ctrl_connect.1548888108
Short name T774
Test name
Test status
Simulation time 163240400 ps
CPU time 16.23 seconds
Started Jun 09 02:53:23 PM PDT 24
Finished Jun 09 02:53:39 PM PDT 24
Peak memory 284440 kb
Host smart-9820962c-da41-408b-b82a-901cd1854ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548888108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.1548888108
Directory /workspace/18.flash_ctrl_connect/latest

Test location /workspace/coverage/default/18.flash_ctrl_disable.1372170877
Short name T572
Test name
Test status
Simulation time 55441600 ps
CPU time 21.98 seconds
Started Jun 09 02:53:18 PM PDT 24
Finished Jun 09 02:53:40 PM PDT 24
Peak memory 274068 kb
Host smart-b7583230-1954-4f54-a8d5-06674e5c5317
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372170877 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.flash_ctrl_disable.1372170877
Directory /workspace/18.flash_ctrl_disable/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.3157042594
Short name T526
Test name
Test status
Simulation time 10018673400 ps
CPU time 89.37 seconds
Started Jun 09 02:53:22 PM PDT 24
Finished Jun 09 02:54:52 PM PDT 24
Peak memory 332380 kb
Host smart-3758d39e-034d-477e-9f2f-0a2f8754bfa9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157042594 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.3157042594
Directory /workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.844252386
Short name T605
Test name
Test status
Simulation time 15414500 ps
CPU time 13.54 seconds
Started Jun 09 02:53:21 PM PDT 24
Finished Jun 09 02:53:35 PM PDT 24
Peak memory 265356 kb
Host smart-73ea32c7-2456-4d9d-86cb-392fca42d290
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844252386 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.844252386
Directory /workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_rma_reset.3539251194
Short name T838
Test name
Test status
Simulation time 40130519600 ps
CPU time 922.27 seconds
Started Jun 09 02:53:05 PM PDT 24
Finished Jun 09 03:08:27 PM PDT 24
Peak memory 264388 kb
Host smart-340d5861-d171-4c86-8f7d-a15b97574981
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539251194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.flash_ctrl_hw_rma_reset.3539251194
Directory /workspace/18.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_hw_sec_otp.2055284709
Short name T335
Test name
Test status
Simulation time 4312615300 ps
CPU time 90.87 seconds
Started Jun 09 02:53:02 PM PDT 24
Finished Jun 09 02:54:34 PM PDT 24
Peak memory 262908 kb
Host smart-a5d93d55-06c5-44fb-b1b8-8082d1a6c97f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055284709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_
hw_sec_otp.2055284709
Directory /workspace/18.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd.1580856232
Short name T892
Test name
Test status
Simulation time 1832629100 ps
CPU time 334.7 seconds
Started Jun 09 02:53:17 PM PDT 24
Finished Jun 09 02:58:52 PM PDT 24
Peak memory 285076 kb
Host smart-2340b2da-80ec-4448-9f99-9421f969a9ef
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580856232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_intr_rd.1580856232
Directory /workspace/18.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1891393541
Short name T867
Test name
Test status
Simulation time 5848313100 ps
CPU time 150.89 seconds
Started Jun 09 02:53:16 PM PDT 24
Finished Jun 09 02:55:48 PM PDT 24
Peak memory 292836 kb
Host smart-041c21dd-8d08-4eda-8a27-7f0f66d122f4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891393541 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.1891393541
Directory /workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/18.flash_ctrl_invalid_op.2809375819
Short name T623
Test name
Test status
Simulation time 3892472200 ps
CPU time 97.42 seconds
Started Jun 09 02:53:11 PM PDT 24
Finished Jun 09 02:54:49 PM PDT 24
Peak memory 263708 kb
Host smart-69aeaae6-e203-4afa-9aa7-9707a02a693c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809375819 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.2
809375819
Directory /workspace/18.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/18.flash_ctrl_lcmgr_intg.2120045707
Short name T1024
Test name
Test status
Simulation time 15605000 ps
CPU time 13.41 seconds
Started Jun 09 02:53:23 PM PDT 24
Finished Jun 09 02:53:37 PM PDT 24
Peak memory 265260 kb
Host smart-79d66d86-2d3b-4c2c-9a84-bdd695125bf0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120045707 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.2120045707
Directory /workspace/18.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/18.flash_ctrl_mp_regions.122923807
Short name T81
Test name
Test status
Simulation time 19744736800 ps
CPU time 636.54 seconds
Started Jun 09 02:53:10 PM PDT 24
Finished Jun 09 03:03:47 PM PDT 24
Peak memory 274936 kb
Host smart-de0059da-4437-4512-aa53-15314c9f1bd4
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122923807 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 18.flash_ctrl_mp_regions.122923807
Directory /workspace/18.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/18.flash_ctrl_otp_reset.1680978227
Short name T967
Test name
Test status
Simulation time 153347800 ps
CPU time 133.25 seconds
Started Jun 09 02:53:03 PM PDT 24
Finished Jun 09 02:55:16 PM PDT 24
Peak memory 261252 kb
Host smart-46f05b58-8d9b-4652-9a2a-a7367050b85a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680978227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o
tp_reset.1680978227
Directory /workspace/18.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_phy_arb.3907490865
Short name T661
Test name
Test status
Simulation time 306223300 ps
CPU time 195.57 seconds
Started Jun 09 02:53:04 PM PDT 24
Finished Jun 09 02:56:20 PM PDT 24
Peak memory 263496 kb
Host smart-05e57e6a-989f-4f1d-851f-31638d458bee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3907490865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.3907490865
Directory /workspace/18.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/18.flash_ctrl_prog_reset.3128242829
Short name T671
Test name
Test status
Simulation time 66500500 ps
CPU time 13.51 seconds
Started Jun 09 02:53:19 PM PDT 24
Finished Jun 09 02:53:32 PM PDT 24
Peak memory 259116 kb
Host smart-11558796-de32-4668-a189-c2a861a67281
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128242829 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_re
set.3128242829
Directory /workspace/18.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/18.flash_ctrl_rand_ops.3249055839
Short name T116
Test name
Test status
Simulation time 725684100 ps
CPU time 511.46 seconds
Started Jun 09 02:53:01 PM PDT 24
Finished Jun 09 03:01:32 PM PDT 24
Peak memory 281936 kb
Host smart-efa1dac2-8e70-4950-b04a-f32d40803065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249055839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.3249055839
Directory /workspace/18.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/18.flash_ctrl_re_evict.4044752534
Short name T813
Test name
Test status
Simulation time 195226300 ps
CPU time 31.83 seconds
Started Jun 09 02:53:17 PM PDT 24
Finished Jun 09 02:53:49 PM PDT 24
Peak memory 275764 kb
Host smart-7f1c37cf-abc7-44c9-8558-2e0c934fbd73
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044752534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_re_evict.4044752534
Directory /workspace/18.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/18.flash_ctrl_ro.294463975
Short name T402
Test name
Test status
Simulation time 2405494300 ps
CPU time 134.42 seconds
Started Jun 09 02:53:18 PM PDT 24
Finished Jun 09 02:55:33 PM PDT 24
Peak memory 291656 kb
Host smart-cf86bf81-79bb-4936-bd84-87b71e3a8a91
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294463975 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.flash_ctrl_ro.294463975
Directory /workspace/18.flash_ctrl_ro/latest

Test location /workspace/coverage/default/18.flash_ctrl_rw.2496034140
Short name T1063
Test name
Test status
Simulation time 21355915400 ps
CPU time 625.33 seconds
Started Jun 09 02:53:17 PM PDT 24
Finished Jun 09 03:03:43 PM PDT 24
Peak memory 317904 kb
Host smart-1d033709-88ba-45b9-b3ca-46c31270309b
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496034140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.flash_ctrl_rw.2496034140
Directory /workspace/18.flash_ctrl_rw/latest

Test location /workspace/coverage/default/18.flash_ctrl_smoke.2035232802
Short name T577
Test name
Test status
Simulation time 24899300 ps
CPU time 96.58 seconds
Started Jun 09 02:52:58 PM PDT 24
Finished Jun 09 02:54:35 PM PDT 24
Peak memory 276308 kb
Host smart-e9ed5f39-92f0-454f-8c3c-0d6ed66d5f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035232802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2035232802
Directory /workspace/18.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/18.flash_ctrl_wo.2229362267
Short name T646
Test name
Test status
Simulation time 3491382300 ps
CPU time 154.03 seconds
Started Jun 09 02:53:18 PM PDT 24
Finished Jun 09 02:55:52 PM PDT 24
Peak memory 265640 kb
Host smart-f7eb58c4-b9f9-44db-8949-c7c830928b32
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229362267 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.flash_ctrl_wo.2229362267
Directory /workspace/18.flash_ctrl_wo/latest

Test location /workspace/coverage/default/19.flash_ctrl_alert_test.1894846679
Short name T666
Test name
Test status
Simulation time 23198000 ps
CPU time 13.46 seconds
Started Jun 09 02:53:45 PM PDT 24
Finished Jun 09 02:53:59 PM PDT 24
Peak memory 265456 kb
Host smart-eda18936-0d48-4f26-983e-f9d28082e59f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894846679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.
1894846679
Directory /workspace/19.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.flash_ctrl_connect.2084997522
Short name T924
Test name
Test status
Simulation time 43001900 ps
CPU time 13.96 seconds
Started Jun 09 02:53:47 PM PDT 24
Finished Jun 09 02:54:01 PM PDT 24
Peak memory 275176 kb
Host smart-1a403615-0e35-4923-acad-1930f5f18c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084997522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.2084997522
Directory /workspace/19.flash_ctrl_connect/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3107119647
Short name T159
Test name
Test status
Simulation time 10032016700 ps
CPU time 59.54 seconds
Started Jun 09 02:53:48 PM PDT 24
Finished Jun 09 02:54:47 PM PDT 24
Peak memory 294560 kb
Host smart-5146a59a-3f92-4ba1-b6c0-b3e154372e29
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107119647 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.3107119647
Directory /workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.1545586455
Short name T682
Test name
Test status
Simulation time 45076300 ps
CPU time 13.36 seconds
Started Jun 09 02:53:48 PM PDT 24
Finished Jun 09 02:54:02 PM PDT 24
Peak memory 258888 kb
Host smart-3be69cb0-4f83-4d5a-b5b3-03d558d8b58d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545586455 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.1545586455
Directory /workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.3334931538
Short name T218
Test name
Test status
Simulation time 80139890800 ps
CPU time 846.95 seconds
Started Jun 09 02:53:29 PM PDT 24
Finished Jun 09 03:07:36 PM PDT 24
Peak memory 264044 kb
Host smart-71a507f1-ea84-4612-950c-7b67a9e22c4c
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334931538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.flash_ctrl_hw_rma_reset.3334931538
Directory /workspace/19.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_hw_sec_otp.1253619396
Short name T841
Test name
Test status
Simulation time 15000187300 ps
CPU time 141.93 seconds
Started Jun 09 02:53:27 PM PDT 24
Finished Jun 09 02:55:50 PM PDT 24
Peak memory 262884 kb
Host smart-12451909-0dc4-478e-b234-742e534b786f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253619396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_
hw_sec_otp.1253619396
Directory /workspace/19.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd.1834332668
Short name T959
Test name
Test status
Simulation time 3639541700 ps
CPU time 338.86 seconds
Started Jun 09 02:53:36 PM PDT 24
Finished Jun 09 02:59:15 PM PDT 24
Peak memory 285088 kb
Host smart-5676b31d-658b-4925-b8ec-5b9da13debce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834332668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_intr_rd.1834332668
Directory /workspace/19.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.2953105984
Short name T883
Test name
Test status
Simulation time 5862112500 ps
CPU time 144.59 seconds
Started Jun 09 02:53:37 PM PDT 24
Finished Jun 09 02:56:02 PM PDT 24
Peak memory 292848 kb
Host smart-97df775f-4ee9-4bad-8792-4ddf86481be0
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953105984 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.2953105984
Directory /workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/19.flash_ctrl_invalid_op.3739490326
Short name T515
Test name
Test status
Simulation time 4353030000 ps
CPU time 76.82 seconds
Started Jun 09 02:53:30 PM PDT 24
Finished Jun 09 02:54:47 PM PDT 24
Peak memory 260904 kb
Host smart-87aa7920-54d2-481a-b088-a67d2b50b00e
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739490326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.3
739490326
Directory /workspace/19.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/19.flash_ctrl_lcmgr_intg.2505617930
Short name T831
Test name
Test status
Simulation time 61036000 ps
CPU time 13.52 seconds
Started Jun 09 02:53:47 PM PDT 24
Finished Jun 09 02:54:00 PM PDT 24
Peak memory 265280 kb
Host smart-fd3d6911-f59f-46e6-9737-20fb3f3bd083
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505617930 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.2505617930
Directory /workspace/19.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/19.flash_ctrl_mp_regions.213032742
Short name T913
Test name
Test status
Simulation time 98486845800 ps
CPU time 815.14 seconds
Started Jun 09 02:53:33 PM PDT 24
Finished Jun 09 03:07:08 PM PDT 24
Peak memory 274632 kb
Host smart-e8f8dd7c-318b-4f3d-942c-de513480186c
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213032742 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 19.flash_ctrl_mp_regions.213032742
Directory /workspace/19.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/19.flash_ctrl_otp_reset.3400249399
Short name T108
Test name
Test status
Simulation time 40393800 ps
CPU time 130.95 seconds
Started Jun 09 02:53:30 PM PDT 24
Finished Jun 09 02:55:41 PM PDT 24
Peak memory 260384 kb
Host smart-d675550e-59cf-48f3-b13e-45a0ce16204f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400249399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o
tp_reset.3400249399
Directory /workspace/19.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_phy_arb.4067248133
Short name T500
Test name
Test status
Simulation time 2846444500 ps
CPU time 210.36 seconds
Started Jun 09 02:53:29 PM PDT 24
Finished Jun 09 02:57:00 PM PDT 24
Peak memory 263388 kb
Host smart-6d47dcaf-61f1-4432-8d8b-1b4ac310d346
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4067248133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.4067248133
Directory /workspace/19.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/19.flash_ctrl_prog_reset.3074478712
Short name T401
Test name
Test status
Simulation time 7654401500 ps
CPU time 169.97 seconds
Started Jun 09 02:53:37 PM PDT 24
Finished Jun 09 02:56:27 PM PDT 24
Peak memory 265620 kb
Host smart-7487dd73-0111-479b-acf4-28f3bfa998b0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074478712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_re
set.3074478712
Directory /workspace/19.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/19.flash_ctrl_rand_ops.3108120091
Short name T887
Test name
Test status
Simulation time 101118300 ps
CPU time 466.53 seconds
Started Jun 09 02:53:28 PM PDT 24
Finished Jun 09 03:01:15 PM PDT 24
Peak memory 281912 kb
Host smart-36c663cb-362c-441e-96f6-f4d2e1d6aed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108120091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.3108120091
Directory /workspace/19.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/19.flash_ctrl_re_evict.846473300
Short name T464
Test name
Test status
Simulation time 61399000 ps
CPU time 31.83 seconds
Started Jun 09 02:53:40 PM PDT 24
Finished Jun 09 02:54:12 PM PDT 24
Peak memory 278048 kb
Host smart-b3cc897a-f20c-4325-82c6-644f22f888bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846473300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_re_evict.846473300
Directory /workspace/19.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_ro.3738470283
Short name T789
Test name
Test status
Simulation time 562119900 ps
CPU time 114.82 seconds
Started Jun 09 02:53:37 PM PDT 24
Finished Jun 09 02:55:32 PM PDT 24
Peak memory 282252 kb
Host smart-ec5ffcc2-b9fe-40df-94a7-6539ed92821a
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738470283 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 19.flash_ctrl_ro.3738470283
Directory /workspace/19.flash_ctrl_ro/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw.1532073502
Short name T220
Test name
Test status
Simulation time 14111605500 ps
CPU time 655.24 seconds
Started Jun 09 02:53:38 PM PDT 24
Finished Jun 09 03:04:34 PM PDT 24
Peak memory 310180 kb
Host smart-aa713493-6f22-4be5-8354-178c25b9bd12
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532073502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.flash_ctrl_rw.1532073502
Directory /workspace/19.flash_ctrl_rw/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict.1790443194
Short name T1047
Test name
Test status
Simulation time 40347500 ps
CPU time 28.26 seconds
Started Jun 09 02:53:41 PM PDT 24
Finished Jun 09 02:54:10 PM PDT 24
Peak memory 275836 kb
Host smart-797e4926-3de7-41a8-a949-62add264fc46
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790443194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_rw_evict.1790443194
Directory /workspace/19.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.2539932253
Short name T638
Test name
Test status
Simulation time 27153900 ps
CPU time 30.9 seconds
Started Jun 09 02:53:41 PM PDT 24
Finished Jun 09 02:54:12 PM PDT 24
Peak memory 274012 kb
Host smart-888b99f8-f223-41f8-a5d8-821266769e50
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539932253 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.2539932253
Directory /workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/19.flash_ctrl_sec_info_access.1152346924
Short name T32
Test name
Test status
Simulation time 8474634900 ps
CPU time 74.26 seconds
Started Jun 09 02:53:40 PM PDT 24
Finished Jun 09 02:54:54 PM PDT 24
Peak memory 265440 kb
Host smart-ba12776c-1cfc-4a0d-a2e6-b447bac06760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152346924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.1152346924
Directory /workspace/19.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/19.flash_ctrl_smoke.1566220474
Short name T1042
Test name
Test status
Simulation time 62628800 ps
CPU time 49.44 seconds
Started Jun 09 02:53:23 PM PDT 24
Finished Jun 09 02:54:13 PM PDT 24
Peak memory 271456 kb
Host smart-d448facb-b219-4d3a-bda4-53264fd721fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566220474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1566220474
Directory /workspace/19.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/19.flash_ctrl_wo.446970203
Short name T768
Test name
Test status
Simulation time 9222223000 ps
CPU time 173.95 seconds
Started Jun 09 02:53:33 PM PDT 24
Finished Jun 09 02:56:27 PM PDT 24
Peak memory 260240 kb
Host smart-a000e565-10de-44e5-a295-c359761771c9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446970203 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.flash_ctrl_wo.446970203
Directory /workspace/19.flash_ctrl_wo/latest

Test location /workspace/coverage/default/2.flash_ctrl_alert_test.2731092350
Short name T476
Test name
Test status
Simulation time 43101300 ps
CPU time 13.83 seconds
Started Jun 09 02:44:27 PM PDT 24
Finished Jun 09 02:44:41 PM PDT 24
Peak memory 258696 kb
Host smart-ee75ffc3-5813-4b4a-9a0a-4bf0ddc70181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731092350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.2
731092350
Directory /workspace/2.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.flash_ctrl_config_regwen.1109974300
Short name T376
Test name
Test status
Simulation time 23007500 ps
CPU time 13.81 seconds
Started Jun 09 02:44:18 PM PDT 24
Finished Jun 09 02:44:32 PM PDT 24
Peak memory 261868 kb
Host smart-b07df49f-3ab1-4135-a594-47a038402c9e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109974300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.flash_ctrl_config_regwen.1109974300
Directory /workspace/2.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.flash_ctrl_connect.3359098680
Short name T870
Test name
Test status
Simulation time 14157800 ps
CPU time 14 seconds
Started Jun 09 02:44:09 PM PDT 24
Finished Jun 09 02:44:23 PM PDT 24
Peak memory 275020 kb
Host smart-1c396ecf-ba5a-4016-921d-8f7722a3b2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359098680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.3359098680
Directory /workspace/2.flash_ctrl_connect/latest

Test location /workspace/coverage/default/2.flash_ctrl_derr_detect.115961500
Short name T439
Test name
Test status
Simulation time 194136200 ps
CPU time 107.04 seconds
Started Jun 09 02:43:55 PM PDT 24
Finished Jun 09 02:45:42 PM PDT 24
Peak memory 282288 kb
Host smart-ec92d4d9-ff4e-49c7-9a2e-1e92f892997d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115961500 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_derr_detect.115961500
Directory /workspace/2.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/2.flash_ctrl_disable.2686392481
Short name T754
Test name
Test status
Simulation time 17057900 ps
CPU time 22.53 seconds
Started Jun 09 02:44:07 PM PDT 24
Finished Jun 09 02:44:30 PM PDT 24
Peak memory 274076 kb
Host smart-18ab29d5-ed83-49f7-8464-abc16682a930
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686392481 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_disable.2686392481
Directory /workspace/2.flash_ctrl_disable/latest

Test location /workspace/coverage/default/2.flash_ctrl_erase_suspend.1388869910
Short name T453
Test name
Test status
Simulation time 13405400600 ps
CPU time 565.94 seconds
Started Jun 09 02:43:21 PM PDT 24
Finished Jun 09 02:52:47 PM PDT 24
Peak memory 263776 kb
Host smart-27aabe8a-285d-47c2-a871-9f453887cd7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388869910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.1388869910
Directory /workspace/2.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_mp.3447008916
Short name T627
Test name
Test status
Simulation time 19553059500 ps
CPU time 2247.78 seconds
Started Jun 09 02:43:42 PM PDT 24
Finished Jun 09 03:21:10 PM PDT 24
Peak memory 265072 kb
Host smart-62aa50a6-bcb9-46d1-9ee6-122c11969963
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447008916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_err
or_mp.3447008916
Directory /workspace/2.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_type.3220028923
Short name T170
Test name
Test status
Simulation time 1054018600 ps
CPU time 1989.48 seconds
Started Jun 09 02:43:34 PM PDT 24
Finished Jun 09 03:16:44 PM PDT 24
Peak memory 265568 kb
Host smart-940eeee8-d106-4420-9cc2-72c0a890e7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220028923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.3220028923
Directory /workspace/2.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/2.flash_ctrl_error_prog_win.4265568419
Short name T171
Test name
Test status
Simulation time 1671356700 ps
CPU time 810.09 seconds
Started Jun 09 02:43:43 PM PDT 24
Finished Jun 09 02:57:13 PM PDT 24
Peak memory 270688 kb
Host smart-73f725b3-a44e-4d4b-be29-eae2c7a3aa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265568419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.4265568419
Directory /workspace/2.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/2.flash_ctrl_fetch_code.3411477522
Short name T47
Test name
Test status
Simulation time 1254455700 ps
CPU time 25.07 seconds
Started Jun 09 02:43:33 PM PDT 24
Finished Jun 09 02:43:59 PM PDT 24
Peak memory 262828 kb
Host smart-a8bf8fcd-0f23-4683-9033-862625edaa82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411477522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.3411477522
Directory /workspace/2.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/2.flash_ctrl_fs_sup.1718340410
Short name T201
Test name
Test status
Simulation time 1181734400 ps
CPU time 38.73 seconds
Started Jun 09 02:44:09 PM PDT 24
Finished Jun 09 02:44:48 PM PDT 24
Peak memory 265688 kb
Host smart-fb6a1b69-1b5e-4205-b7fd-e3d36e4c1d5d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718340410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 2.flash_ctrl_fs_sup.1718340410
Directory /workspace/2.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/2.flash_ctrl_full_mem_access.977448435
Short name T1027
Test name
Test status
Simulation time 48914801000 ps
CPU time 4435.79 seconds
Started Jun 09 02:43:35 PM PDT 24
Finished Jun 09 03:57:32 PM PDT 24
Peak memory 265420 kb
Host smart-06dc6553-4ca2-44fe-9764-d0b8349dda9b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977448435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_full_mem_access.977448435
Directory /workspace/2.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.211313054
Short name T72
Test name
Test status
Simulation time 509277838300 ps
CPU time 1812.94 seconds
Started Jun 09 02:43:31 PM PDT 24
Finished Jun 09 03:13:45 PM PDT 24
Peak memory 264320 kb
Host smart-324fe9a5-2215-48fe-9260-88fe05577e2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211313054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TES
T_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.flash_ctrl_host_ctrl_arb.211313054
Directory /workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_host_dir_rd.33376006
Short name T325
Test name
Test status
Simulation time 79735100 ps
CPU time 49.93 seconds
Started Jun 09 02:43:21 PM PDT 24
Finished Jun 09 02:44:12 PM PDT 24
Peak memory 265652 kb
Host smart-e308aff9-8c73-4795-ae85-4970d5318979
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=33376006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.33376006
Directory /workspace/2.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.2874488916
Short name T24
Test name
Test status
Simulation time 10012467200 ps
CPU time 341.69 seconds
Started Jun 09 02:44:28 PM PDT 24
Finished Jun 09 02:50:10 PM PDT 24
Peak memory 333104 kb
Host smart-d937eb81-813d-48ae-9dcc-60d7d2baf540
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874488916 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.2874488916
Directory /workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.1943083886
Short name T695
Test name
Test status
Simulation time 33174000 ps
CPU time 13.77 seconds
Started Jun 09 02:44:22 PM PDT 24
Finished Jun 09 02:44:36 PM PDT 24
Peak memory 265228 kb
Host smart-123e1d05-36fc-45d9-8eea-95921eb1d7f4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943083886 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.1943083886
Directory /workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma.1163049600
Short name T699
Test name
Test status
Simulation time 169169207300 ps
CPU time 2030.38 seconds
Started Jun 09 02:43:25 PM PDT 24
Finished Jun 09 03:17:16 PM PDT 24
Peak memory 264844 kb
Host smart-d93e2f5e-964e-445b-be89-5de26d5e897f
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163049600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.flash_ctrl_hw_rma.1163049600
Directory /workspace/2.flash_ctrl_hw_rma/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_rma_reset.2441316506
Short name T650
Test name
Test status
Simulation time 160195753300 ps
CPU time 988.51 seconds
Started Jun 09 02:43:25 PM PDT 24
Finished Jun 09 02:59:54 PM PDT 24
Peak memory 264652 kb
Host smart-2511bfc4-18b0-4cac-966d-eee3b18ee2ce
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441316506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.flash_ctrl_hw_rma_reset.2441316506
Directory /workspace/2.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_hw_sec_otp.947595336
Short name T331
Test name
Test status
Simulation time 18732395200 ps
CPU time 223 seconds
Started Jun 09 02:43:21 PM PDT 24
Finished Jun 09 02:47:04 PM PDT 24
Peak memory 263396 kb
Host smart-f43d738c-6036-403a-bde2-56de9b01c97d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947595336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw
_sec_otp.947595336
Directory /workspace/2.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/2.flash_ctrl_integrity.2280782096
Short name T265
Test name
Test status
Simulation time 16736424600 ps
CPU time 667.88 seconds
Started Jun 09 02:44:02 PM PDT 24
Finished Jun 09 02:55:11 PM PDT 24
Peak memory 332956 kb
Host smart-d1af2674-4009-4491-9c8c-3967ad392b72
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280782096 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_integrity.2280782096
Directory /workspace/2.flash_ctrl_integrity/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd.2244342256
Short name T248
Test name
Test status
Simulation time 6970492000 ps
CPU time 239.37 seconds
Started Jun 09 02:43:59 PM PDT 24
Finished Jun 09 02:47:59 PM PDT 24
Peak memory 285200 kb
Host smart-00e8dbfb-2f4d-4c41-9b7e-5ee361563348
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244342256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_intr_rd.2244342256
Directory /workspace/2.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3935666176
Short name T272
Test name
Test status
Simulation time 24662353800 ps
CPU time 480.75 seconds
Started Jun 09 02:44:01 PM PDT 24
Finished Jun 09 02:52:02 PM PDT 24
Peak memory 285224 kb
Host smart-869aa776-67e7-4535-aafe-af33944c7f8a
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935666176 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.3935666176
Directory /workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr.1671319382
Short name T778
Test name
Test status
Simulation time 1843058200 ps
CPU time 63.22 seconds
Started Jun 09 02:44:01 PM PDT 24
Finished Jun 09 02:45:04 PM PDT 24
Peak memory 260588 kb
Host smart-219d75e4-c9e9-49dc-8605-d1e50d75c562
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671319382 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_wr.1671319382
Directory /workspace/2.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1911000576
Short name T827
Test name
Test status
Simulation time 102931302100 ps
CPU time 267.98 seconds
Started Jun 09 02:43:58 PM PDT 24
Finished Jun 09 02:48:27 PM PDT 24
Peak memory 260692 kb
Host smart-7943c535-b4ce-47b7-ab88-25d943b17f68
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191
1000576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1911000576
Directory /workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/2.flash_ctrl_invalid_op.730592640
Short name T96
Test name
Test status
Simulation time 1949640700 ps
CPU time 95.71 seconds
Started Jun 09 02:43:40 PM PDT 24
Finished Jun 09 02:45:15 PM PDT 24
Peak memory 263684 kb
Host smart-dd38efdf-6d63-42df-b1ef-8be44ddb9989
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730592640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.730592640
Directory /workspace/2.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_mp_regions.3870631677
Short name T250
Test name
Test status
Simulation time 3601489700 ps
CPU time 185.63 seconds
Started Jun 09 02:43:30 PM PDT 24
Finished Jun 09 02:46:35 PM PDT 24
Peak memory 265524 kb
Host smart-7ef063a9-538d-41eb-ace6-f7e4de851a48
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870631677 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_mp_regions.3870631677
Directory /workspace/2.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/2.flash_ctrl_otp_reset.2010642283
Short name T563
Test name
Test status
Simulation time 139373800 ps
CPU time 129.99 seconds
Started Jun 09 02:43:29 PM PDT 24
Finished Jun 09 02:45:40 PM PDT 24
Peak memory 260272 kb
Host smart-ad21b7f3-74a4-47b1-ab89-6a9b63413c7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010642283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot
p_reset.2010642283
Directory /workspace/2.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_oversize_error.478129708
Short name T558
Test name
Test status
Simulation time 3675169600 ps
CPU time 231.28 seconds
Started Jun 09 02:43:56 PM PDT 24
Finished Jun 09 02:47:47 PM PDT 24
Peak memory 282260 kb
Host smart-4188c44a-2fd9-4f7a-8a4d-ad2c31e7b80a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478129708 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.478129708
Directory /workspace/2.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.3593019722
Short name T221
Test name
Test status
Simulation time 87537100 ps
CPU time 15.02 seconds
Started Jun 09 02:44:18 PM PDT 24
Finished Jun 09 02:44:33 PM PDT 24
Peak memory 262036 kb
Host smart-ece06d99-31f6-4265-b787-d0e2c7428d84
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=3593019722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.3593019722
Directory /workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/2.flash_ctrl_phy_arb.1898426915
Short name T987
Test name
Test status
Simulation time 696066600 ps
CPU time 196.23 seconds
Started Jun 09 02:43:21 PM PDT 24
Finished Jun 09 02:46:37 PM PDT 24
Peak memory 263344 kb
Host smart-d286773f-6406-4ded-8f39-f29c2ae1adcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1898426915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.1898426915
Directory /workspace/2.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/2.flash_ctrl_prog_reset.2595924693
Short name T762
Test name
Test status
Simulation time 2257924100 ps
CPU time 190.34 seconds
Started Jun 09 02:44:03 PM PDT 24
Finished Jun 09 02:47:13 PM PDT 24
Peak memory 259912 kb
Host smart-df1423f8-b073-40be-aaa1-6ade50e164ea
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595924693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_res
et.2595924693
Directory /workspace/2.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/2.flash_ctrl_rand_ops.4069125571
Short name T998
Test name
Test status
Simulation time 9257958600 ps
CPU time 497.19 seconds
Started Jun 09 02:43:16 PM PDT 24
Finished Jun 09 02:51:33 PM PDT 24
Peak memory 283432 kb
Host smart-899e694e-a5ce-40ca-95bb-224255cd6161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069125571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.4069125571
Directory /workspace/2.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_buff_evict.2349879520
Short name T949
Test name
Test status
Simulation time 2826701900 ps
CPU time 199.38 seconds
Started Jun 09 02:43:22 PM PDT 24
Finished Jun 09 02:46:41 PM PDT 24
Peak memory 263032 kb
Host smart-c9d6789a-f987-44cd-81a4-f7f9bc44ced6
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2349879520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.2349879520
Directory /workspace/2.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_rd_intg.3085529287
Short name T676
Test name
Test status
Simulation time 209606200 ps
CPU time 32.87 seconds
Started Jun 09 02:44:07 PM PDT 24
Finished Jun 09 02:44:40 PM PDT 24
Peak memory 280720 kb
Host smart-bf74de9c-9301-4425-918c-b39966585e06
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085529287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_rd_intg.3085529287
Directory /workspace/2.flash_ctrl_rd_intg/latest

Test location /workspace/coverage/default/2.flash_ctrl_re_evict.968510329
Short name T840
Test name
Test status
Simulation time 412162400 ps
CPU time 32.95 seconds
Started Jun 09 02:44:03 PM PDT 24
Finished Jun 09 02:44:36 PM PDT 24
Peak memory 275720 kb
Host smart-2a3dc897-a4b9-4bcc-b3f6-437763d06ce3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968510329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_re_evict.968510329
Directory /workspace/2.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.2926652416
Short name T395
Test name
Test status
Simulation time 89209700 ps
CPU time 22.63 seconds
Started Jun 09 02:43:50 PM PDT 24
Finished Jun 09 02:44:12 PM PDT 24
Peak memory 265296 kb
Host smart-1de6a314-6f60-4362-8408-89abbec01259
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926652416 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.2926652416
Directory /workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rma_err.955323854
Short name T150
Test name
Test status
Simulation time 40555641100 ps
CPU time 983.34 seconds
Started Jun 09 02:44:22 PM PDT 24
Finished Jun 09 03:00:45 PM PDT 24
Peak memory 261404 kb
Host smart-df22469d-602c-4f81-ae69-ddf555079540
User root
Command /workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955323854 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.955323854
Directory /workspace/2.flash_ctrl_rma_err/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro.773116243
Short name T873
Test name
Test status
Simulation time 1796255800 ps
CPU time 141.03 seconds
Started Jun 09 02:43:46 PM PDT 24
Finished Jun 09 02:46:08 PM PDT 24
Peak memory 281328 kb
Host smart-50383005-172b-4eef-9c43-89ce0e09d367
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773116243 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.flash_ctrl_ro.773116243
Directory /workspace/2.flash_ctrl_ro/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_derr.35389162
Short name T176
Test name
Test status
Simulation time 2786584200 ps
CPU time 163.73 seconds
Started Jun 09 02:43:55 PM PDT 24
Finished Jun 09 02:46:39 PM PDT 24
Peak memory 283340 kb
Host smart-4b766e98-5564-4f14-b079-7783ac153c83
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
35389162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.35389162
Directory /workspace/2.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_ro_serr.4163482349
Short name T643
Test name
Test status
Simulation time 1062207700 ps
CPU time 153.74 seconds
Started Jun 09 02:43:46 PM PDT 24
Finished Jun 09 02:46:20 PM PDT 24
Peak memory 282188 kb
Host smart-22c38aa7-ff46-4c65-bf5a-ed749cd276a0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163482349 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.4163482349
Directory /workspace/2.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw.650888029
Short name T908
Test name
Test status
Simulation time 7208527700 ps
CPU time 665.02 seconds
Started Jun 09 02:43:45 PM PDT 24
Finished Jun 09 02:54:50 PM PDT 24
Peak memory 314688 kb
Host smart-c845db77-6d1b-45b6-bd66-2b8ec3c0e2b9
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650888029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.flash_ctrl_rw.650888029
Directory /workspace/2.flash_ctrl_rw/latest

Test location /workspace/coverage/default/2.flash_ctrl_rw_derr.1458977676
Short name T195
Test name
Test status
Simulation time 8613135300 ps
CPU time 759.48 seconds
Started Jun 09 02:43:54 PM PDT 24
Finished Jun 09 02:56:34 PM PDT 24
Peak memory 324344 kb
Host smart-2883fe42-b7f4-4c9c-b5d0-98c0f46e4b10
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458977676 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_rw_derr.1458977676
Directory /workspace/2.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_address.3134027751
Short name T559
Test name
Test status
Simulation time 3153984200 ps
CPU time 96.36 seconds
Started Jun 09 02:43:50 PM PDT 24
Finished Jun 09 02:45:27 PM PDT 24
Peak memory 265796 kb
Host smart-e4451a47-cd6d-4339-a40e-12dde6015189
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134027751 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 2.flash_ctrl_serr_address.3134027751
Directory /workspace/2.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/2.flash_ctrl_serr_counter.1442714691
Short name T22
Test name
Test status
Simulation time 826243300 ps
CPU time 57.47 seconds
Started Jun 09 02:43:50 PM PDT 24
Finished Jun 09 02:44:47 PM PDT 24
Peak memory 265948 kb
Host smart-0028c920-e16d-4810-a849-ed2ee1ba7195
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442714691 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_serr_counter.1442714691
Directory /workspace/2.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke.352051613
Short name T591
Test name
Test status
Simulation time 20926000 ps
CPU time 98.86 seconds
Started Jun 09 02:43:15 PM PDT 24
Finished Jun 09 02:44:54 PM PDT 24
Peak memory 277584 kb
Host smart-e33b8387-55c8-4edd-89ee-1aec17c6c45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352051613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.352051613
Directory /workspace/2.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/2.flash_ctrl_smoke_hw.2088239097
Short name T902
Test name
Test status
Simulation time 45947400 ps
CPU time 24.26 seconds
Started Jun 09 02:43:18 PM PDT 24
Finished Jun 09 02:43:43 PM PDT 24
Peak memory 259800 kb
Host smart-d3b2c652-e28d-4dc0-9343-31e3aa38b592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088239097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.2088239097
Directory /workspace/2.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/2.flash_ctrl_stress_all.2375366933
Short name T941
Test name
Test status
Simulation time 81499200 ps
CPU time 237.97 seconds
Started Jun 09 02:44:21 PM PDT 24
Finished Jun 09 02:48:19 PM PDT 24
Peak memory 275140 kb
Host smart-d02ce9b4-b3d8-414d-8fa5-0e8aea2cc510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375366933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stres
s_all.2375366933
Directory /workspace/2.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.flash_ctrl_sw_op.752753811
Short name T771
Test name
Test status
Simulation time 72560600 ps
CPU time 23.36 seconds
Started Jun 09 02:43:15 PM PDT 24
Finished Jun 09 02:43:39 PM PDT 24
Peak memory 262436 kb
Host smart-f9cf04dd-9120-4bd3-a840-08b718d3b47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752753811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.752753811
Directory /workspace/2.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/2.flash_ctrl_wo.2187031430
Short name T498
Test name
Test status
Simulation time 31392974000 ps
CPU time 206.06 seconds
Started Jun 09 02:43:41 PM PDT 24
Finished Jun 09 02:47:08 PM PDT 24
Peak memory 260260 kb
Host smart-07d2cabc-601c-419d-839f-11dfeb9494cb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187031430 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.flash_ctrl_wo.2187031430
Directory /workspace/2.flash_ctrl_wo/latest

Test location /workspace/coverage/default/20.flash_ctrl_alert_test.4215392647
Short name T266
Test name
Test status
Simulation time 135141000 ps
CPU time 13.87 seconds
Started Jun 09 02:54:01 PM PDT 24
Finished Jun 09 02:54:15 PM PDT 24
Peak memory 265504 kb
Host smart-957d3dca-eacb-41bf-a19b-5e571533ca51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215392647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.
4215392647
Directory /workspace/20.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.flash_ctrl_connect.2009229855
Short name T216
Test name
Test status
Simulation time 22931800 ps
CPU time 15.97 seconds
Started Jun 09 02:54:01 PM PDT 24
Finished Jun 09 02:54:17 PM PDT 24
Peak memory 275040 kb
Host smart-362bdfb8-85ff-4a9a-a7eb-5e07d435eb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009229855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.2009229855
Directory /workspace/20.flash_ctrl_connect/latest

Test location /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2885524210
Short name T1080
Test name
Test status
Simulation time 2549172900 ps
CPU time 197.61 seconds
Started Jun 09 02:53:45 PM PDT 24
Finished Jun 09 02:57:03 PM PDT 24
Peak memory 262912 kb
Host smart-e76d2a33-2147-401e-affc-5a76505c31ce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885524210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_
hw_sec_otp.2885524210
Directory /workspace/20.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd.3636900949
Short name T37
Test name
Test status
Simulation time 2594078800 ps
CPU time 124.48 seconds
Started Jun 09 02:53:49 PM PDT 24
Finished Jun 09 02:55:54 PM PDT 24
Peak memory 291608 kb
Host smart-e5081b91-c4cb-4abe-9d77-e993aafdecae
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636900949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla
sh_ctrl_intr_rd.3636900949
Directory /workspace/20.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.402920640
Short name T618
Test name
Test status
Simulation time 6292662300 ps
CPU time 149.07 seconds
Started Jun 09 02:53:50 PM PDT 24
Finished Jun 09 02:56:20 PM PDT 24
Peak memory 293432 kb
Host smart-10c46098-4b18-4b3c-8bfe-0f3b08626458
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402920640 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.402920640
Directory /workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/20.flash_ctrl_otp_reset.1698362962
Short name T522
Test name
Test status
Simulation time 256399100 ps
CPU time 131.82 seconds
Started Jun 09 02:53:50 PM PDT 24
Finished Jun 09 02:56:02 PM PDT 24
Peak memory 260228 kb
Host smart-51a20843-2717-42b4-a682-c2b6c9fc98b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698362962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_o
tp_reset.1698362962
Directory /workspace/20.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_prog_reset.4144011092
Short name T1050
Test name
Test status
Simulation time 40813000 ps
CPU time 14.35 seconds
Started Jun 09 02:53:50 PM PDT 24
Finished Jun 09 02:54:05 PM PDT 24
Peak memory 265612 kb
Host smart-5030d5e8-25e6-439c-845a-391e82544835
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144011092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_re
set.4144011092
Directory /workspace/20.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.2890234430
Short name T568
Test name
Test status
Simulation time 112002400 ps
CPU time 30.8 seconds
Started Jun 09 02:53:58 PM PDT 24
Finished Jun 09 02:54:29 PM PDT 24
Peak memory 276036 kb
Host smart-07c24633-edff-4dfe-89ba-e801c3bcc604
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890234430 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.2890234430
Directory /workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/20.flash_ctrl_sec_info_access.3404562078
Short name T418
Test name
Test status
Simulation time 2480438100 ps
CPU time 68.91 seconds
Started Jun 09 02:54:00 PM PDT 24
Finished Jun 09 02:55:09 PM PDT 24
Peak memory 264304 kb
Host smart-f5e00ff6-007f-4625-82dd-32dec86d3c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404562078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.3404562078
Directory /workspace/20.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/20.flash_ctrl_smoke.353969394
Short name T603
Test name
Test status
Simulation time 61090200 ps
CPU time 48.65 seconds
Started Jun 09 02:53:49 PM PDT 24
Finished Jun 09 02:54:37 PM PDT 24
Peak memory 271544 kb
Host smart-626bf108-a80d-427e-82b1-09527121492e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353969394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.353969394
Directory /workspace/20.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/21.flash_ctrl_alert_test.3967434931
Short name T455
Test name
Test status
Simulation time 160414600 ps
CPU time 13.64 seconds
Started Jun 09 02:54:12 PM PDT 24
Finished Jun 09 02:54:26 PM PDT 24
Peak memory 258512 kb
Host smart-ca43ab7c-14ab-4fce-a5c2-3f2713485935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967434931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.
3967434931
Directory /workspace/21.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.flash_ctrl_connect.714942770
Short name T1076
Test name
Test status
Simulation time 28391100 ps
CPU time 16.31 seconds
Started Jun 09 02:54:12 PM PDT 24
Finished Jun 09 02:54:28 PM PDT 24
Peak memory 275104 kb
Host smart-30ff2de8-d2c8-400e-8dd1-00ca0fecdf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714942770 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.714942770
Directory /workspace/21.flash_ctrl_connect/latest

Test location /workspace/coverage/default/21.flash_ctrl_disable.1206208150
Short name T889
Test name
Test status
Simulation time 29260000 ps
CPU time 20.77 seconds
Started Jun 09 02:54:12 PM PDT 24
Finished Jun 09 02:54:34 PM PDT 24
Peak memory 274084 kb
Host smart-d32f2fc7-3c2f-469f-a959-b8c0b6e2ed21
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206208150 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_disable.1206208150
Directory /workspace/21.flash_ctrl_disable/latest

Test location /workspace/coverage/default/21.flash_ctrl_hw_sec_otp.4256893330
Short name T208
Test name
Test status
Simulation time 16690211200 ps
CPU time 129.29 seconds
Started Jun 09 02:54:00 PM PDT 24
Finished Jun 09 02:56:10 PM PDT 24
Peak memory 263268 kb
Host smart-6fe9dbfb-fb7c-459f-8f8a-0b8cb05d3665
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256893330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_
hw_sec_otp.4256893330
Directory /workspace/21.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd.75250153
Short name T965
Test name
Test status
Simulation time 1787703500 ps
CPU time 224.17 seconds
Started Jun 09 02:54:04 PM PDT 24
Finished Jun 09 02:57:49 PM PDT 24
Peak memory 291728 kb
Host smart-51618c11-9acb-4c02-9fc5-4da01b92d3be
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75250153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash
_ctrl_intr_rd.75250153
Directory /workspace/21.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.2092008900
Short name T427
Test name
Test status
Simulation time 11456006600 ps
CPU time 173.68 seconds
Started Jun 09 02:54:06 PM PDT 24
Finished Jun 09 02:56:59 PM PDT 24
Peak memory 293404 kb
Host smart-bc1fe76b-58ea-478c-8161-2aad3ee2e9dd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092008900 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.2092008900
Directory /workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/21.flash_ctrl_otp_reset.1027935105
Short name T926
Test name
Test status
Simulation time 145779100 ps
CPU time 134.69 seconds
Started Jun 09 02:53:58 PM PDT 24
Finished Jun 09 02:56:13 PM PDT 24
Peak memory 261244 kb
Host smart-46872768-c2c1-4a97-b18b-476b3ab02f6f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027935105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o
tp_reset.1027935105
Directory /workspace/21.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_prog_reset.3193514174
Short name T329
Test name
Test status
Simulation time 170461200 ps
CPU time 13.49 seconds
Started Jun 09 02:54:06 PM PDT 24
Finished Jun 09 02:54:20 PM PDT 24
Peak memory 259332 kb
Host smart-ddcc58e4-fb17-4b67-8aa7-817a747507f3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193514174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_re
set.3193514174
Directory /workspace/21.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict.3614089121
Short name T1022
Test name
Test status
Simulation time 56085800 ps
CPU time 31.07 seconds
Started Jun 09 02:54:04 PM PDT 24
Finished Jun 09 02:54:35 PM PDT 24
Peak memory 276048 kb
Host smart-124cbdcb-d645-4257-9201-d896e66b3c63
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614089121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl
ash_ctrl_rw_evict.3614089121
Directory /workspace/21.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/21.flash_ctrl_rw_evict_all_en.2775304212
Short name T732
Test name
Test status
Simulation time 30270100 ps
CPU time 28.43 seconds
Started Jun 09 02:54:12 PM PDT 24
Finished Jun 09 02:54:41 PM PDT 24
Peak memory 275728 kb
Host smart-448eb9cd-28c9-4932-b82f-23f4581ca317
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775304212 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict_all_en.2775304212
Directory /workspace/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/21.flash_ctrl_sec_info_access.198985737
Short name T759
Test name
Test status
Simulation time 659188200 ps
CPU time 68.66 seconds
Started Jun 09 02:54:12 PM PDT 24
Finished Jun 09 02:55:21 PM PDT 24
Peak memory 264320 kb
Host smart-e4ecdbb5-b2ee-4d11-b054-870d21067876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198985737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.198985737
Directory /workspace/21.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/21.flash_ctrl_smoke.145924099
Short name T397
Test name
Test status
Simulation time 69880100 ps
CPU time 52.35 seconds
Started Jun 09 02:54:00 PM PDT 24
Finished Jun 09 02:54:53 PM PDT 24
Peak memory 271536 kb
Host smart-54374be1-7e41-458d-a887-aad1daaec4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145924099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.145924099
Directory /workspace/21.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/22.flash_ctrl_alert_test.4024121534
Short name T1016
Test name
Test status
Simulation time 110518300 ps
CPU time 14.26 seconds
Started Jun 09 02:54:26 PM PDT 24
Finished Jun 09 02:54:40 PM PDT 24
Peak memory 265572 kb
Host smart-511cb24d-315d-47df-93bd-985be5f9212d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024121534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.
4024121534
Directory /workspace/22.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.flash_ctrl_connect.2996405132
Short name T97
Test name
Test status
Simulation time 15681300 ps
CPU time 15.91 seconds
Started Jun 09 02:54:18 PM PDT 24
Finished Jun 09 02:54:35 PM PDT 24
Peak memory 275144 kb
Host smart-09adfe31-b97a-451e-96fe-6af4b9de0b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996405132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.2996405132
Directory /workspace/22.flash_ctrl_connect/latest

Test location /workspace/coverage/default/22.flash_ctrl_disable.24620399
Short name T138
Test name
Test status
Simulation time 37537700 ps
CPU time 22.55 seconds
Started Jun 09 02:54:22 PM PDT 24
Finished Jun 09 02:54:44 PM PDT 24
Peak memory 274052 kb
Host smart-0bdb827e-5787-4173-b559-4d353ccfaed7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24620399 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.flash_ctrl_disable.24620399
Directory /workspace/22.flash_ctrl_disable/latest

Test location /workspace/coverage/default/22.flash_ctrl_hw_sec_otp.321136540
Short name T443
Test name
Test status
Simulation time 37014286800 ps
CPU time 168.64 seconds
Started Jun 09 02:54:13 PM PDT 24
Finished Jun 09 02:57:02 PM PDT 24
Peak memory 263292 kb
Host smart-81c4267c-1132-47d6-bf2f-9110fb315874
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321136540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_h
w_sec_otp.321136540
Directory /workspace/22.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd.399190871
Short name T481
Test name
Test status
Simulation time 1458405200 ps
CPU time 153.6 seconds
Started Jun 09 02:54:14 PM PDT 24
Finished Jun 09 02:56:48 PM PDT 24
Peak memory 291740 kb
Host smart-cca85e1e-73d1-4210-8693-78206e3d206f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399190871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flas
h_ctrl_intr_rd.399190871
Directory /workspace/22.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.2044509609
Short name T616
Test name
Test status
Simulation time 11445857900 ps
CPU time 139.05 seconds
Started Jun 09 02:54:14 PM PDT 24
Finished Jun 09 02:56:33 PM PDT 24
Peak memory 293428 kb
Host smart-8201255d-23ad-43af-b4e2-b6e389febb9b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044509609 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.2044509609
Directory /workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/22.flash_ctrl_otp_reset.1601341433
Short name T726
Test name
Test status
Simulation time 37572100 ps
CPU time 132.53 seconds
Started Jun 09 02:54:14 PM PDT 24
Finished Jun 09 02:56:27 PM PDT 24
Peak memory 260104 kb
Host smart-389c1b4f-2d8e-4866-9fc1-3ce7c3de86e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601341433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o
tp_reset.1601341433
Directory /workspace/22.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_prog_reset.2340259298
Short name T1006
Test name
Test status
Simulation time 17696600 ps
CPU time 14.03 seconds
Started Jun 09 02:54:13 PM PDT 24
Finished Jun 09 02:54:28 PM PDT 24
Peak memory 265604 kb
Host smart-54fac279-7eca-43bc-8b53-8a7379e2d6d6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340259298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_re
set.2340259298
Directory /workspace/22.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.927455993
Short name T744
Test name
Test status
Simulation time 75962800 ps
CPU time 28.53 seconds
Started Jun 09 02:54:21 PM PDT 24
Finished Jun 09 02:54:50 PM PDT 24
Peak memory 276020 kb
Host smart-df2dd0f8-62fa-4581-b361-5551e64bc102
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927455993 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.927455993
Directory /workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/22.flash_ctrl_sec_info_access.3931103765
Short name T604
Test name
Test status
Simulation time 4366824400 ps
CPU time 85.33 seconds
Started Jun 09 02:54:18 PM PDT 24
Finished Jun 09 02:55:44 PM PDT 24
Peak memory 265428 kb
Host smart-e07c85ec-7b86-4be9-ae00-c9049161ef79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931103765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.3931103765
Directory /workspace/22.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/22.flash_ctrl_smoke.2187653345
Short name T338
Test name
Test status
Simulation time 144664000 ps
CPU time 147.33 seconds
Started Jun 09 02:54:10 PM PDT 24
Finished Jun 09 02:56:37 PM PDT 24
Peak memory 268980 kb
Host smart-265d4979-ab24-4954-b252-9eeb203b3e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187653345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.2187653345
Directory /workspace/22.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/23.flash_ctrl_alert_test.2954857065
Short name T803
Test name
Test status
Simulation time 32031900 ps
CPU time 13.66 seconds
Started Jun 09 02:54:42 PM PDT 24
Finished Jun 09 02:54:55 PM PDT 24
Peak memory 265464 kb
Host smart-a7e74f33-9b2e-4b2d-8de1-6ce4e60d5870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954857065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.
2954857065
Directory /workspace/23.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.flash_ctrl_connect.3502568097
Short name T571
Test name
Test status
Simulation time 67948800 ps
CPU time 15.68 seconds
Started Jun 09 02:54:37 PM PDT 24
Finished Jun 09 02:54:53 PM PDT 24
Peak memory 275116 kb
Host smart-98892c89-6429-4525-ab3a-c22a24e039dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502568097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.3502568097
Directory /workspace/23.flash_ctrl_connect/latest

Test location /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.3863724961
Short name T466
Test name
Test status
Simulation time 1435921700 ps
CPU time 50.62 seconds
Started Jun 09 02:54:31 PM PDT 24
Finished Jun 09 02:55:22 PM PDT 24
Peak memory 263396 kb
Host smart-456ea553-5e83-4da1-ac1f-9dd571c411c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863724961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_
hw_sec_otp.3863724961
Directory /workspace/23.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd.48202786
Short name T507
Test name
Test status
Simulation time 10840600900 ps
CPU time 212.53 seconds
Started Jun 09 02:54:38 PM PDT 24
Finished Jun 09 02:58:11 PM PDT 24
Peak memory 291704 kb
Host smart-586f93c1-5688-4fd3-9950-9d723d12354f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48202786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ
=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash
_ctrl_intr_rd.48202786
Directory /workspace/23.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2463069409
Short name T485
Test name
Test status
Simulation time 11951312000 ps
CPU time 295.93 seconds
Started Jun 09 02:54:33 PM PDT 24
Finished Jun 09 02:59:29 PM PDT 24
Peak memory 291364 kb
Host smart-e9351fb1-eb74-40b0-aa61-3f54c7a8b611
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463069409 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2463069409
Directory /workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/23.flash_ctrl_otp_reset.3593545265
Short name T161
Test name
Test status
Simulation time 124643000 ps
CPU time 133.49 seconds
Started Jun 09 02:54:30 PM PDT 24
Finished Jun 09 02:56:44 PM PDT 24
Peak memory 265032 kb
Host smart-e04667af-8404-4af5-874e-2aa8b26decec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593545265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_o
tp_reset.3593545265
Directory /workspace/23.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_prog_reset.1263412822
Short name T1023
Test name
Test status
Simulation time 20477200 ps
CPU time 13.47 seconds
Started Jun 09 02:54:39 PM PDT 24
Finished Jun 09 02:54:53 PM PDT 24
Peak memory 259052 kb
Host smart-931ee03c-1626-47e2-87a6-5a860e1e823c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263412822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_re
set.1263412822
Directory /workspace/23.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.3291832070
Short name T332
Test name
Test status
Simulation time 28052400 ps
CPU time 30.97 seconds
Started Jun 09 02:54:39 PM PDT 24
Finished Jun 09 02:55:10 PM PDT 24
Peak memory 276048 kb
Host smart-fe8acde1-4748-4132-9a63-fa3768ef9bf9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291832070 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.3291832070
Directory /workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/23.flash_ctrl_sec_info_access.1904805743
Short name T685
Test name
Test status
Simulation time 1026191200 ps
CPU time 55.75 seconds
Started Jun 09 02:54:44 PM PDT 24
Finished Jun 09 02:55:39 PM PDT 24
Peak memory 264400 kb
Host smart-b431bda4-b681-40b2-96de-7318711db894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904805743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.1904805743
Directory /workspace/23.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/23.flash_ctrl_smoke.4090234630
Short name T621
Test name
Test status
Simulation time 332686900 ps
CPU time 122.19 seconds
Started Jun 09 02:54:25 PM PDT 24
Finished Jun 09 02:56:28 PM PDT 24
Peak memory 277688 kb
Host smart-280de1e7-51ae-4cc2-835d-27e0c47f8cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090234630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.4090234630
Directory /workspace/23.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/24.flash_ctrl_alert_test.761124117
Short name T441
Test name
Test status
Simulation time 49348800 ps
CPU time 13.76 seconds
Started Jun 09 02:54:47 PM PDT 24
Finished Jun 09 02:55:00 PM PDT 24
Peak memory 258496 kb
Host smart-b91095c2-c174-4ffb-8fb5-9ca518216c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761124117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.761124117
Directory /workspace/24.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.flash_ctrl_connect.86138347
Short name T978
Test name
Test status
Simulation time 16014700 ps
CPU time 15.8 seconds
Started Jun 09 02:54:42 PM PDT 24
Finished Jun 09 02:54:58 PM PDT 24
Peak memory 284500 kb
Host smart-b9919c93-124f-4b88-b2e6-cbba74e38341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86138347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.86138347
Directory /workspace/24.flash_ctrl_connect/latest

Test location /workspace/coverage/default/24.flash_ctrl_disable.1349241002
Short name T469
Test name
Test status
Simulation time 24522900 ps
CPU time 21.64 seconds
Started Jun 09 02:54:36 PM PDT 24
Finished Jun 09 02:54:58 PM PDT 24
Peak memory 274012 kb
Host smart-34d6beb5-8aa1-442d-830f-d0b204607246
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349241002 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_disable.1349241002
Directory /workspace/24.flash_ctrl_disable/latest

Test location /workspace/coverage/default/24.flash_ctrl_hw_sec_otp.1330677073
Short name T463
Test name
Test status
Simulation time 12755739300 ps
CPU time 93.73 seconds
Started Jun 09 02:54:43 PM PDT 24
Finished Jun 09 02:56:17 PM PDT 24
Peak memory 263280 kb
Host smart-c4b4d025-db6a-4c80-98d8-aa3b141f0112
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330677073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_
hw_sec_otp.1330677073
Directory /workspace/24.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd.2682380839
Short name T648
Test name
Test status
Simulation time 6333037400 ps
CPU time 247.84 seconds
Started Jun 09 02:54:37 PM PDT 24
Finished Jun 09 02:58:45 PM PDT 24
Peak memory 285112 kb
Host smart-1499ab57-c0d2-44bf-af08-ad66bebcc300
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682380839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_intr_rd.2682380839
Directory /workspace/24.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.1448969459
Short name T125
Test name
Test status
Simulation time 6046717100 ps
CPU time 142.81 seconds
Started Jun 09 02:54:42 PM PDT 24
Finished Jun 09 02:57:05 PM PDT 24
Peak memory 292856 kb
Host smart-722d8201-eaa3-408f-928c-250b3190e361
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448969459 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.1448969459
Directory /workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/24.flash_ctrl_otp_reset.2644646479
Short name T1085
Test name
Test status
Simulation time 76245200 ps
CPU time 130.78 seconds
Started Jun 09 02:54:40 PM PDT 24
Finished Jun 09 02:56:51 PM PDT 24
Peak memory 260192 kb
Host smart-07a76409-dc54-4670-9edb-4bfb9cb9144f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644646479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o
tp_reset.2644646479
Directory /workspace/24.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_prog_reset.1005381725
Short name T555
Test name
Test status
Simulation time 23529800 ps
CPU time 13.49 seconds
Started Jun 09 02:54:39 PM PDT 24
Finished Jun 09 02:54:53 PM PDT 24
Peak memory 259080 kb
Host smart-e7642f6e-1a8c-4612-b030-d956e00ee480
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005381725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_re
set.1005381725
Directory /workspace/24.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict.940330411
Short name T1010
Test name
Test status
Simulation time 188178000 ps
CPU time 31.01 seconds
Started Jun 09 02:54:40 PM PDT 24
Finished Jun 09 02:55:11 PM PDT 24
Peak memory 275720 kb
Host smart-f0f4cbe3-f4fe-4838-92ea-37223bc52d21
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940330411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla
sh_ctrl_rw_evict.940330411
Directory /workspace/24.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.3452392229
Short name T361
Test name
Test status
Simulation time 29620200 ps
CPU time 27.77 seconds
Started Jun 09 02:54:39 PM PDT 24
Finished Jun 09 02:55:07 PM PDT 24
Peak memory 276036 kb
Host smart-98ab2170-f9bd-4047-b753-61d1e9b4211c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452392229 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.3452392229
Directory /workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/24.flash_ctrl_sec_info_access.4029286679
Short name T652
Test name
Test status
Simulation time 4382666900 ps
CPU time 77.58 seconds
Started Jun 09 02:54:44 PM PDT 24
Finished Jun 09 02:56:01 PM PDT 24
Peak memory 264980 kb
Host smart-f4592aac-3b26-4d59-9d0f-c46dfe368fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029286679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.4029286679
Directory /workspace/24.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/24.flash_ctrl_smoke.3161494334
Short name T398
Test name
Test status
Simulation time 9511993400 ps
CPU time 142.22 seconds
Started Jun 09 02:54:44 PM PDT 24
Finished Jun 09 02:57:07 PM PDT 24
Peak memory 281092 kb
Host smart-8d5d21c9-1437-41c3-9bd2-2b38f08bc851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161494334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.3161494334
Directory /workspace/24.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/25.flash_ctrl_alert_test.3089734126
Short name T689
Test name
Test status
Simulation time 87184800 ps
CPU time 13.63 seconds
Started Jun 09 02:54:50 PM PDT 24
Finished Jun 09 02:55:04 PM PDT 24
Peak memory 258544 kb
Host smart-65a49bf8-d47d-417e-98d3-a293c6728f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089734126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.
3089734126
Directory /workspace/25.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.flash_ctrl_connect.2462429860
Short name T724
Test name
Test status
Simulation time 15446400 ps
CPU time 15.58 seconds
Started Jun 09 02:54:52 PM PDT 24
Finished Jun 09 02:55:07 PM PDT 24
Peak memory 275136 kb
Host smart-06fbf0ef-3887-4b0d-8ec3-6b29417fac78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462429860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.2462429860
Directory /workspace/25.flash_ctrl_connect/latest

Test location /workspace/coverage/default/25.flash_ctrl_disable.3898056244
Short name T14
Test name
Test status
Simulation time 14830400 ps
CPU time 20.9 seconds
Started Jun 09 02:54:51 PM PDT 24
Finished Jun 09 02:55:12 PM PDT 24
Peak memory 265380 kb
Host smart-a7e7fa66-3824-40e5-baae-5213b7b2e985
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898056244 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.flash_ctrl_disable.3898056244
Directory /workspace/25.flash_ctrl_disable/latest

Test location /workspace/coverage/default/25.flash_ctrl_hw_sec_otp.87091411
Short name T323
Test name
Test status
Simulation time 28775701800 ps
CPU time 137.64 seconds
Started Jun 09 02:54:46 PM PDT 24
Finished Jun 09 02:57:04 PM PDT 24
Peak memory 260244 kb
Host smart-8a4264b1-08c2-4e12-8a59-3ffe4bb76cbb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87091411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw
_sec_otp.87091411
Directory /workspace/25.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3597067419
Short name T346
Test name
Test status
Simulation time 34061319100 ps
CPU time 493.26 seconds
Started Jun 09 02:54:47 PM PDT 24
Finished Jun 09 03:03:00 PM PDT 24
Peak memory 292340 kb
Host smart-74d711ec-2a9c-4648-a0db-69d2e048d123
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597067419 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.3597067419
Directory /workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/25.flash_ctrl_prog_reset.867570093
Short name T657
Test name
Test status
Simulation time 5166016300 ps
CPU time 221.62 seconds
Started Jun 09 02:54:47 PM PDT 24
Finished Jun 09 02:58:28 PM PDT 24
Peak memory 260584 kb
Host smart-587238d5-03fb-4aac-8848-a60ff2425ef6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867570093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_res
et.867570093
Directory /workspace/25.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict.3096010998
Short name T694
Test name
Test status
Simulation time 211149300 ps
CPU time 31.61 seconds
Started Jun 09 02:54:51 PM PDT 24
Finished Jun 09 02:55:23 PM PDT 24
Peak memory 276068 kb
Host smart-6d92fca4-f108-4f54-be0b-0a278e6b1b4e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096010998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fl
ash_ctrl_rw_evict.3096010998
Directory /workspace/25.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.918289484
Short name T364
Test name
Test status
Simulation time 34868700 ps
CPU time 29.21 seconds
Started Jun 09 02:54:51 PM PDT 24
Finished Jun 09 02:55:21 PM PDT 24
Peak memory 267900 kb
Host smart-0ac512b9-fabb-401b-9bc6-f2a01660b543
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918289484 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.918289484
Directory /workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/25.flash_ctrl_sec_info_access.777813699
Short name T1084
Test name
Test status
Simulation time 1980998800 ps
CPU time 68.58 seconds
Started Jun 09 02:54:51 PM PDT 24
Finished Jun 09 02:56:00 PM PDT 24
Peak memory 259844 kb
Host smart-7b6a5c2a-3418-478e-877e-cc0f9f1191ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777813699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.777813699
Directory /workspace/25.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/25.flash_ctrl_smoke.2692402525
Short name T990
Test name
Test status
Simulation time 1252023700 ps
CPU time 107.37 seconds
Started Jun 09 02:54:47 PM PDT 24
Finished Jun 09 02:56:35 PM PDT 24
Peak memory 281892 kb
Host smart-974ad4e1-0568-484e-9dc2-4e2755625ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692402525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.2692402525
Directory /workspace/25.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/26.flash_ctrl_alert_test.379763037
Short name T729
Test name
Test status
Simulation time 103460800 ps
CPU time 13.73 seconds
Started Jun 09 02:55:06 PM PDT 24
Finished Jun 09 02:55:20 PM PDT 24
Peak memory 265596 kb
Host smart-77a4157b-80da-4200-9363-cdc18b34ac1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379763037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.379763037
Directory /workspace/26.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.flash_ctrl_connect.1582465798
Short name T99
Test name
Test status
Simulation time 25787200 ps
CPU time 13.66 seconds
Started Jun 09 02:55:06 PM PDT 24
Finished Jun 09 02:55:20 PM PDT 24
Peak memory 275156 kb
Host smart-f728032d-08c7-481f-b510-5ffd2f2e093c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582465798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.1582465798
Directory /workspace/26.flash_ctrl_connect/latest

Test location /workspace/coverage/default/26.flash_ctrl_disable.2998625432
Short name T409
Test name
Test status
Simulation time 22786900 ps
CPU time 21.83 seconds
Started Jun 09 02:55:01 PM PDT 24
Finished Jun 09 02:55:23 PM PDT 24
Peak memory 274196 kb
Host smart-be743777-ec34-4b7a-9f6f-f127ccfa361b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998625432 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.flash_ctrl_disable.2998625432
Directory /workspace/26.flash_ctrl_disable/latest

Test location /workspace/coverage/default/26.flash_ctrl_hw_sec_otp.2890935615
Short name T550
Test name
Test status
Simulation time 2567772100 ps
CPU time 205.04 seconds
Started Jun 09 02:54:52 PM PDT 24
Finished Jun 09 02:58:17 PM PDT 24
Peak memory 263360 kb
Host smart-ad7f79e5-e173-4c5c-8b3f-3743356f6003
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890935615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_
hw_sec_otp.2890935615
Directory /workspace/26.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd.2302885523
Short name T350
Test name
Test status
Simulation time 1645216000 ps
CPU time 199.03 seconds
Started Jun 09 02:54:57 PM PDT 24
Finished Jun 09 02:58:16 PM PDT 24
Peak memory 285248 kb
Host smart-86726ea3-209e-4544-8e44-8f4613234519
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302885523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla
sh_ctrl_intr_rd.2302885523
Directory /workspace/26.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.436168815
Short name T324
Test name
Test status
Simulation time 25913998700 ps
CPU time 328.3 seconds
Started Jun 09 02:54:57 PM PDT 24
Finished Jun 09 03:00:25 PM PDT 24
Peak memory 291356 kb
Host smart-b20e56a3-cfa5-40f4-a471-cd5ebad89d51
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436168815 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.436168815
Directory /workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/26.flash_ctrl_otp_reset.3875742792
Short name T891
Test name
Test status
Simulation time 48159900 ps
CPU time 131.47 seconds
Started Jun 09 02:54:57 PM PDT 24
Finished Jun 09 02:57:08 PM PDT 24
Peak memory 261196 kb
Host smart-2cc03a2a-068a-41ec-8ed3-0337cc5ef4b8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875742792 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o
tp_reset.3875742792
Directory /workspace/26.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_prog_reset.156622487
Short name T942
Test name
Test status
Simulation time 19100200 ps
CPU time 13.95 seconds
Started Jun 09 02:55:02 PM PDT 24
Finished Jun 09 02:55:16 PM PDT 24
Peak memory 258984 kb
Host smart-ad9bbb76-8b50-4160-aa5a-658e9fd99625
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156622487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_res
et.156622487
Directory /workspace/26.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/26.flash_ctrl_sec_info_access.2988086185
Short name T411
Test name
Test status
Simulation time 5168972500 ps
CPU time 64.79 seconds
Started Jun 09 02:55:07 PM PDT 24
Finished Jun 09 02:56:12 PM PDT 24
Peak memory 264928 kb
Host smart-75f4ec9d-e316-43b9-bc53-bb6bec7f2f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988086185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2988086185
Directory /workspace/26.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/26.flash_ctrl_smoke.1241761073
Short name T704
Test name
Test status
Simulation time 25160100 ps
CPU time 123.57 seconds
Started Jun 09 02:54:51 PM PDT 24
Finished Jun 09 02:56:55 PM PDT 24
Peak memory 277472 kb
Host smart-e8fa0d5f-282c-45ac-abc7-7d1a4a2cf311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241761073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.1241761073
Directory /workspace/26.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/27.flash_ctrl_alert_test.750988380
Short name T477
Test name
Test status
Simulation time 24709700 ps
CPU time 13.45 seconds
Started Jun 09 02:55:12 PM PDT 24
Finished Jun 09 02:55:26 PM PDT 24
Peak memory 265564 kb
Host smart-3c692fc4-34b9-4750-967d-1cfb95e67643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750988380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.750988380
Directory /workspace/27.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.flash_ctrl_connect.2919082588
Short name T1032
Test name
Test status
Simulation time 43756500 ps
CPU time 13.45 seconds
Started Jun 09 02:55:15 PM PDT 24
Finished Jun 09 02:55:29 PM PDT 24
Peak memory 275228 kb
Host smart-6de98eda-ed6b-4873-b344-8f61d8fd44ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919082588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.2919082588
Directory /workspace/27.flash_ctrl_connect/latest

Test location /workspace/coverage/default/27.flash_ctrl_disable.2561043301
Short name T386
Test name
Test status
Simulation time 36223100 ps
CPU time 22.03 seconds
Started Jun 09 02:55:10 PM PDT 24
Finished Jun 09 02:55:32 PM PDT 24
Peak memory 274252 kb
Host smart-0bba0fdd-e39a-48f1-92c2-ddafe2e7bade
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561043301 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_disable.2561043301
Directory /workspace/27.flash_ctrl_disable/latest

Test location /workspace/coverage/default/27.flash_ctrl_hw_sec_otp.1833265530
Short name T938
Test name
Test status
Simulation time 4246452500 ps
CPU time 144.56 seconds
Started Jun 09 02:55:04 PM PDT 24
Finished Jun 09 02:57:29 PM PDT 24
Peak memory 263360 kb
Host smart-7586f072-67ba-49dc-ab6b-c2e947ac588f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833265530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_
hw_sec_otp.1833265530
Directory /workspace/27.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd.1306365276
Short name T242
Test name
Test status
Simulation time 6481047500 ps
CPU time 235.02 seconds
Started Jun 09 02:55:12 PM PDT 24
Finished Jun 09 02:59:07 PM PDT 24
Peak memory 292692 kb
Host smart-698d188d-ec23-4da2-b1f0-cb3a7a6801d7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306365276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla
sh_ctrl_intr_rd.1306365276
Directory /workspace/27.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.4270463147
Short name T349
Test name
Test status
Simulation time 12130367900 ps
CPU time 271.14 seconds
Started Jun 09 02:55:12 PM PDT 24
Finished Jun 09 02:59:43 PM PDT 24
Peak memory 285192 kb
Host smart-b57c1201-9cdc-4131-b42c-92f7f322ef5d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270463147 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.4270463147
Directory /workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/27.flash_ctrl_otp_reset.1650580211
Short name T804
Test name
Test status
Simulation time 88913800 ps
CPU time 134.08 seconds
Started Jun 09 02:55:07 PM PDT 24
Finished Jun 09 02:57:21 PM PDT 24
Peak memory 261388 kb
Host smart-bc5cbbc5-096e-4eaf-a879-1f3b9384e5be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650580211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o
tp_reset.1650580211
Directory /workspace/27.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_prog_reset.2980120261
Short name T403
Test name
Test status
Simulation time 42969300 ps
CPU time 13.77 seconds
Started Jun 09 02:55:11 PM PDT 24
Finished Jun 09 02:55:25 PM PDT 24
Peak memory 259272 kb
Host smart-fbf23a55-6276-4fc1-82e0-e9ffca3969b4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980120261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_re
set.2980120261
Directory /workspace/27.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.1160287625
Short name T115
Test name
Test status
Simulation time 29593900 ps
CPU time 28.38 seconds
Started Jun 09 02:55:11 PM PDT 24
Finished Jun 09 02:55:39 PM PDT 24
Peak memory 274004 kb
Host smart-3d1ad724-a1f3-4c76-ba1c-05e0ca6d25d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160287625 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.1160287625
Directory /workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/27.flash_ctrl_sec_info_access.2143637902
Short name T787
Test name
Test status
Simulation time 6931360900 ps
CPU time 69.78 seconds
Started Jun 09 02:55:13 PM PDT 24
Finished Jun 09 02:56:23 PM PDT 24
Peak memory 259932 kb
Host smart-765bd227-2e5e-4326-ae7a-0d70c38b13e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143637902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.2143637902
Directory /workspace/27.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/27.flash_ctrl_smoke.3120591917
Short name T674
Test name
Test status
Simulation time 1402124500 ps
CPU time 243.63 seconds
Started Jun 09 02:55:05 PM PDT 24
Finished Jun 09 02:59:09 PM PDT 24
Peak memory 281608 kb
Host smart-4b5b5d47-6da5-4366-8e16-1a2409713f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120591917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.3120591917
Directory /workspace/27.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/28.flash_ctrl_alert_test.2691572776
Short name T981
Test name
Test status
Simulation time 42195700 ps
CPU time 13.45 seconds
Started Jun 09 02:55:20 PM PDT 24
Finished Jun 09 02:55:34 PM PDT 24
Peak memory 258512 kb
Host smart-af794802-c0b2-46d7-a789-6c6cf176fa5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691572776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.
2691572776
Directory /workspace/28.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.flash_ctrl_connect.1002951008
Short name T764
Test name
Test status
Simulation time 53087800 ps
CPU time 15.65 seconds
Started Jun 09 02:55:20 PM PDT 24
Finished Jun 09 02:55:36 PM PDT 24
Peak memory 275120 kb
Host smart-02515111-44ea-4200-9011-68b27683a57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002951008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1002951008
Directory /workspace/28.flash_ctrl_connect/latest

Test location /workspace/coverage/default/28.flash_ctrl_disable.1001749345
Short name T140
Test name
Test status
Simulation time 104365700 ps
CPU time 21.77 seconds
Started Jun 09 02:55:15 PM PDT 24
Finished Jun 09 02:55:37 PM PDT 24
Peak memory 265376 kb
Host smart-975452c0-6193-4a92-b361-712e1954a342
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001749345 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_disable.1001749345
Directory /workspace/28.flash_ctrl_disable/latest

Test location /workspace/coverage/default/28.flash_ctrl_hw_sec_otp.1276374989
Short name T612
Test name
Test status
Simulation time 15832794800 ps
CPU time 146.47 seconds
Started Jun 09 02:55:10 PM PDT 24
Finished Jun 09 02:57:37 PM PDT 24
Peak memory 261084 kb
Host smart-56f1be89-ffec-4ce8-b79f-865fac6b9a1f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276374989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_
hw_sec_otp.1276374989
Directory /workspace/28.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd.1900429016
Short name T746
Test name
Test status
Simulation time 691232900 ps
CPU time 157.95 seconds
Started Jun 09 02:55:13 PM PDT 24
Finished Jun 09 02:57:52 PM PDT 24
Peak memory 294520 kb
Host smart-13d2dbf1-49ee-4148-ac6a-4b865dfd1724
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900429016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla
sh_ctrl_intr_rd.1900429016
Directory /workspace/28.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.1730189447
Short name T608
Test name
Test status
Simulation time 11922625500 ps
CPU time 136.8 seconds
Started Jun 09 02:55:13 PM PDT 24
Finished Jun 09 02:57:31 PM PDT 24
Peak memory 292752 kb
Host smart-29312ef0-5a0a-40b8-a3b6-1c24243c2f6b
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730189447 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.1730189447
Directory /workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/28.flash_ctrl_otp_reset.1421094617
Short name T1079
Test name
Test status
Simulation time 36940800 ps
CPU time 110.1 seconds
Started Jun 09 02:55:15 PM PDT 24
Finished Jun 09 02:57:05 PM PDT 24
Peak memory 260224 kb
Host smart-d707ed6a-02bb-4c2b-9190-2f3e239a3c48
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421094617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o
tp_reset.1421094617
Directory /workspace/28.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_prog_reset.3686666678
Short name T903
Test name
Test status
Simulation time 37577100 ps
CPU time 15.03 seconds
Started Jun 09 02:55:16 PM PDT 24
Finished Jun 09 02:55:31 PM PDT 24
Peak memory 259148 kb
Host smart-b7885ead-f51b-4f88-bbd2-9eb37954e210
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686666678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_re
set.3686666678
Directory /workspace/28.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict.2504989985
Short name T270
Test name
Test status
Simulation time 30815500 ps
CPU time 31.4 seconds
Started Jun 09 02:55:15 PM PDT 24
Finished Jun 09 02:55:46 PM PDT 24
Peak memory 275752 kb
Host smart-c32e79a7-1895-46bd-8587-2b96e514e5e3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504989985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl
ash_ctrl_rw_evict.2504989985
Directory /workspace/28.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.3229259167
Short name T407
Test name
Test status
Simulation time 70940400 ps
CPU time 30.63 seconds
Started Jun 09 02:55:15 PM PDT 24
Finished Jun 09 02:55:46 PM PDT 24
Peak memory 267868 kb
Host smart-c01f8ce1-fb56-4ed9-b79e-1609121ca683
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229259167 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.3229259167
Directory /workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/28.flash_ctrl_sec_info_access.3868873236
Short name T1081
Test name
Test status
Simulation time 346367600 ps
CPU time 58.41 seconds
Started Jun 09 02:55:16 PM PDT 24
Finished Jun 09 02:56:15 PM PDT 24
Peak memory 264360 kb
Host smart-180ff8d6-e689-4002-8301-d5297d81e05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868873236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.3868873236
Directory /workspace/28.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/28.flash_ctrl_smoke.1898814272
Short name T1073
Test name
Test status
Simulation time 112220800 ps
CPU time 122.43 seconds
Started Jun 09 02:55:12 PM PDT 24
Finished Jun 09 02:57:15 PM PDT 24
Peak memory 276740 kb
Host smart-dfbcda3f-6f07-43ab-a0e4-f2ae423a6a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898814272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.1898814272
Directory /workspace/28.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/29.flash_ctrl_alert_test.3049378486
Short name T236
Test name
Test status
Simulation time 99215200 ps
CPU time 13.89 seconds
Started Jun 09 02:55:27 PM PDT 24
Finished Jun 09 02:55:41 PM PDT 24
Peak memory 265548 kb
Host smart-60c89aae-0cf0-44a1-af4e-a89dd013e749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049378486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.
3049378486
Directory /workspace/29.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.flash_ctrl_connect.139942029
Short name T581
Test name
Test status
Simulation time 28497800 ps
CPU time 15.76 seconds
Started Jun 09 02:55:23 PM PDT 24
Finished Jun 09 02:55:39 PM PDT 24
Peak memory 284536 kb
Host smart-fb409881-cdb7-4633-a7b7-cfc0be5b1120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139942029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.139942029
Directory /workspace/29.flash_ctrl_connect/latest

Test location /workspace/coverage/default/29.flash_ctrl_disable.2511199741
Short name T933
Test name
Test status
Simulation time 10169300 ps
CPU time 21.52 seconds
Started Jun 09 02:55:23 PM PDT 24
Finished Jun 09 02:55:45 PM PDT 24
Peak memory 274084 kb
Host smart-542128cf-80d5-43aa-af9c-2372113d0cad
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511199741 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_disable.2511199741
Directory /workspace/29.flash_ctrl_disable/latest

Test location /workspace/coverage/default/29.flash_ctrl_hw_sec_otp.3318077743
Short name T474
Test name
Test status
Simulation time 15520056800 ps
CPU time 120.96 seconds
Started Jun 09 02:55:19 PM PDT 24
Finished Jun 09 02:57:20 PM PDT 24
Peak memory 263340 kb
Host smart-a18436df-720a-4481-b8ac-5577729f3d7c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318077743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_
hw_sec_otp.3318077743
Directory /workspace/29.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd.2634897859
Short name T1008
Test name
Test status
Simulation time 1237834100 ps
CPU time 122.77 seconds
Started Jun 09 02:55:29 PM PDT 24
Finished Jun 09 02:57:32 PM PDT 24
Peak memory 294528 kb
Host smart-d42db434-e2c0-4714-b787-338d432680ff
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634897859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_intr_rd.2634897859
Directory /workspace/29.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1479170072
Short name T352
Test name
Test status
Simulation time 52689936600 ps
CPU time 302.54 seconds
Started Jun 09 02:55:23 PM PDT 24
Finished Jun 09 03:00:25 PM PDT 24
Peak memory 290324 kb
Host smart-5a86ff6c-9427-4247-b32b-6583becbbd43
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479170072 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.1479170072
Directory /workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/29.flash_ctrl_otp_reset.421456969
Short name T269
Test name
Test status
Simulation time 44204600 ps
CPU time 131.24 seconds
Started Jun 09 02:55:19 PM PDT 24
Finished Jun 09 02:57:30 PM PDT 24
Peak memory 260132 kb
Host smart-069430ba-c57d-4ade-9f41-30c1fce854f6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421456969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ot
p_reset.421456969
Directory /workspace/29.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_prog_reset.2253180601
Short name T678
Test name
Test status
Simulation time 14125770800 ps
CPU time 217.54 seconds
Started Jun 09 02:55:25 PM PDT 24
Finished Jun 09 02:59:02 PM PDT 24
Peak memory 260552 kb
Host smart-2eea829a-764c-4122-bd05-80522581b247
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253180601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_re
set.2253180601
Directory /workspace/29.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict.228557857
Short name T358
Test name
Test status
Simulation time 89895700 ps
CPU time 27.92 seconds
Started Jun 09 02:55:25 PM PDT 24
Finished Jun 09 02:55:53 PM PDT 24
Peak memory 275796 kb
Host smart-ab1127c8-989a-4d0a-92dc-dcf92e9fdedf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228557857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla
sh_ctrl_rw_evict.228557857
Directory /workspace/29.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.3192810023
Short name T609
Test name
Test status
Simulation time 83274100 ps
CPU time 32.29 seconds
Started Jun 09 02:55:24 PM PDT 24
Finished Jun 09 02:55:57 PM PDT 24
Peak memory 276048 kb
Host smart-2b9ed51d-41e6-4fa7-b099-34347d9569da
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192810023 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.3192810023
Directory /workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/29.flash_ctrl_sec_info_access.3585964380
Short name T693
Test name
Test status
Simulation time 3576669000 ps
CPU time 73.06 seconds
Started Jun 09 02:55:23 PM PDT 24
Finished Jun 09 02:56:37 PM PDT 24
Peak memory 263788 kb
Host smart-ef56d0bd-48e1-4a56-b88c-367e3b67624a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585964380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.3585964380
Directory /workspace/29.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/29.flash_ctrl_smoke.3119428906
Short name T328
Test name
Test status
Simulation time 23882400 ps
CPU time 121.7 seconds
Started Jun 09 02:55:18 PM PDT 24
Finished Jun 09 02:57:20 PM PDT 24
Peak memory 277584 kb
Host smart-721cd22d-fbd7-4f7b-832b-8b389972a42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119428906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.3119428906
Directory /workspace/29.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_alert_test.516293336
Short name T594
Test name
Test status
Simulation time 54533800 ps
CPU time 14.26 seconds
Started Jun 09 02:45:23 PM PDT 24
Finished Jun 09 02:45:38 PM PDT 24
Peak memory 258544 kb
Host smart-a906339c-317d-457a-b5db-fa74e7d5197a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516293336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.516293336
Directory /workspace/3.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.flash_ctrl_config_regwen.3889934558
Short name T952
Test name
Test status
Simulation time 19802900 ps
CPU time 13.73 seconds
Started Jun 09 02:45:19 PM PDT 24
Finished Jun 09 02:45:33 PM PDT 24
Peak memory 261872 kb
Host smart-0bf82c8f-99bd-493f-8353-8983ce300038
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889934558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.flash_ctrl_config_regwen.3889934558
Directory /workspace/3.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.flash_ctrl_connect.3897770428
Short name T691
Test name
Test status
Simulation time 60127000 ps
CPU time 16.3 seconds
Started Jun 09 02:45:15 PM PDT 24
Finished Jun 09 02:45:31 PM PDT 24
Peak memory 275268 kb
Host smart-b18ecd43-f2d7-42ca-a64a-511335fd626b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897770428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.3897770428
Directory /workspace/3.flash_ctrl_connect/latest

Test location /workspace/coverage/default/3.flash_ctrl_derr_detect.40666796
Short name T745
Test name
Test status
Simulation time 181571000 ps
CPU time 105.62 seconds
Started Jun 09 02:45:05 PM PDT 24
Finished Jun 09 02:46:51 PM PDT 24
Peak memory 281240 kb
Host smart-259a598a-d4ad-4098-be2b-7204add088db
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40666796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t
est +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_derr_detect.40666796
Directory /workspace/3.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/3.flash_ctrl_disable.1288885768
Short name T333
Test name
Test status
Simulation time 10073400 ps
CPU time 20.23 seconds
Started Jun 09 02:45:10 PM PDT 24
Finished Jun 09 02:45:30 PM PDT 24
Peak memory 274080 kb
Host smart-4713e494-2c04-40b8-8de4-5d4e88334790
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288885768 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_disable.1288885768
Directory /workspace/3.flash_ctrl_disable/latest

Test location /workspace/coverage/default/3.flash_ctrl_erase_suspend.656647283
Short name T64
Test name
Test status
Simulation time 8182867500 ps
CPU time 399.87 seconds
Started Jun 09 02:44:39 PM PDT 24
Finished Jun 09 02:51:19 PM PDT 24
Peak memory 263644 kb
Host smart-ed4fa8d8-df71-4cb1-94a7-f6a46fbac798
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=656647283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.656647283
Directory /workspace/3.flash_ctrl_erase_suspend/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_mp.3360763108
Short name T956
Test name
Test status
Simulation time 20700405100 ps
CPU time 2581.1 seconds
Started Jun 09 02:44:47 PM PDT 24
Finished Jun 09 03:27:49 PM PDT 24
Peak memory 263224 kb
Host smart-5082cf82-f95b-4055-a453-a8a277951351
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360763108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_err
or_mp.3360763108
Directory /workspace/3.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_type.13185418
Short name T914
Test name
Test status
Simulation time 959836600 ps
CPU time 2861.49 seconds
Started Jun 09 02:44:47 PM PDT 24
Finished Jun 09 03:32:29 PM PDT 24
Peak memory 264708 kb
Host smart-1f02f93d-4ef0-467e-9a73-151dfeb0b6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13185418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_type.13185418
Directory /workspace/3.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/3.flash_ctrl_error_prog_win.1122618810
Short name T249
Test name
Test status
Simulation time 654847300 ps
CPU time 849.26 seconds
Started Jun 09 02:44:48 PM PDT 24
Finished Jun 09 02:58:57 PM PDT 24
Peak memory 270756 kb
Host smart-d7a3ca59-531a-4eda-9527-592fcea45898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122618810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.1122618810
Directory /workspace/3.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/3.flash_ctrl_fetch_code.2797774681
Short name T985
Test name
Test status
Simulation time 582045700 ps
CPU time 29.26 seconds
Started Jun 09 02:44:43 PM PDT 24
Finished Jun 09 02:45:12 PM PDT 24
Peak memory 262764 kb
Host smart-3eab76b3-9627-4ea1-9517-ac398b482206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797774681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.2797774681
Directory /workspace/3.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/3.flash_ctrl_fs_sup.3572206075
Short name T75
Test name
Test status
Simulation time 688373300 ps
CPU time 38.39 seconds
Started Jun 09 02:45:15 PM PDT 24
Finished Jun 09 02:45:54 PM PDT 24
Peak memory 263068 kb
Host smart-1b1a06f4-210a-4c14-967a-9f8d72ba61a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572206075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 3.flash_ctrl_fs_sup.3572206075
Directory /workspace/3.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/3.flash_ctrl_full_mem_access.2755942023
Short name T34
Test name
Test status
Simulation time 367755988800 ps
CPU time 2915.21 seconds
Started Jun 09 02:44:42 PM PDT 24
Finished Jun 09 03:33:18 PM PDT 24
Peak memory 265632 kb
Host smart-187c44c7-d41e-4838-8250-15e4f5367983
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755942023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_full_mem_access.2755942023
Directory /workspace/3.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_host_dir_rd.3387350736
Short name T620
Test name
Test status
Simulation time 353034100 ps
CPU time 124.99 seconds
Started Jun 09 02:44:33 PM PDT 24
Finished Jun 09 02:46:38 PM PDT 24
Peak memory 262924 kb
Host smart-5c3f87a0-be4b-466d-941a-b5a1d2cf60ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387350736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.3387350736
Directory /workspace/3.flash_ctrl_host_dir_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3879112295
Short name T267
Test name
Test status
Simulation time 10012108100 ps
CPU time 113.63 seconds
Started Jun 09 02:45:24 PM PDT 24
Finished Jun 09 02:47:18 PM PDT 24
Peak memory 313528 kb
Host smart-1e45de5a-83ae-4877-b0e4-7b25b30f0e0e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879112295 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.3879112295
Directory /workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.375466198
Short name T714
Test name
Test status
Simulation time 26499000 ps
CPU time 13.68 seconds
Started Jun 09 02:45:25 PM PDT 24
Finished Jun 09 02:45:39 PM PDT 24
Peak memory 259776 kb
Host smart-765cd350-eac8-436b-bcda-cea9863a55c6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375466198 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.375466198
Directory /workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_rma_reset.473154240
Short name T149
Test name
Test status
Simulation time 180202034100 ps
CPU time 1044.69 seconds
Started Jun 09 02:44:43 PM PDT 24
Finished Jun 09 03:02:08 PM PDT 24
Peak memory 264556 kb
Host smart-df4431e1-5f8e-4f7e-9d37-d3284d3b613b
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473154240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 3.flash_ctrl_hw_rma_reset.473154240
Directory /workspace/3.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_hw_sec_otp.1581629300
Short name T846
Test name
Test status
Simulation time 19335639500 ps
CPU time 139.05 seconds
Started Jun 09 02:44:38 PM PDT 24
Finished Jun 09 02:46:57 PM PDT 24
Peak memory 263368 kb
Host smart-3df6f2f0-6562-43c0-acb4-d27953cd5553
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581629300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h
w_sec_otp.1581629300
Directory /workspace/3.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd.1779815715
Short name T751
Test name
Test status
Simulation time 7712555000 ps
CPU time 274.96 seconds
Started Jun 09 02:45:08 PM PDT 24
Finished Jun 09 02:49:43 PM PDT 24
Peak memory 285240 kb
Host smart-891fb4bc-37f9-4344-b000-aa7a325d3573
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779815715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_intr_rd.1779815715
Directory /workspace/3.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1965275657
Short name T425
Test name
Test status
Simulation time 23525182200 ps
CPU time 175.85 seconds
Started Jun 09 02:45:09 PM PDT 24
Finished Jun 09 02:48:05 PM PDT 24
Peak memory 293148 kb
Host smart-3c92574e-53f5-4e0a-8664-ed767f416993
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965275657 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.1965275657
Directory /workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr.1138236974
Short name T850
Test name
Test status
Simulation time 2519195800 ps
CPU time 76.86 seconds
Started Jun 09 02:45:08 PM PDT 24
Finished Jun 09 02:46:25 PM PDT 24
Peak memory 265520 kb
Host smart-1ac511fd-d6be-44ee-b9c8-8a731dd1d267
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138236974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_wr.1138236974
Directory /workspace/3.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1430754668
Short name T475
Test name
Test status
Simulation time 18878545900 ps
CPU time 166.05 seconds
Started Jun 09 02:45:10 PM PDT 24
Finished Jun 09 02:47:56 PM PDT 24
Peak memory 265396 kb
Host smart-a916b1d6-e82c-47d9-b23a-49b247fc52cf
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143
0754668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.1430754668
Directory /workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/3.flash_ctrl_invalid_op.2036867963
Short name T92
Test name
Test status
Simulation time 2497564400 ps
CPU time 63.67 seconds
Started Jun 09 02:44:47 PM PDT 24
Finished Jun 09 02:45:51 PM PDT 24
Peak memory 263884 kb
Host smart-e5e044cc-b3c2-4a11-b155-ead37e2303d6
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036867963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.2036867963
Directory /workspace/3.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_lcmgr_intg.3589895081
Short name T900
Test name
Test status
Simulation time 15405000 ps
CPU time 13.42 seconds
Started Jun 09 02:45:20 PM PDT 24
Finished Jun 09 02:45:34 PM PDT 24
Peak memory 260200 kb
Host smart-f5ec6d72-b3b9-483e-bf48-7b879647603f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589895081 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.3589895081
Directory /workspace/3.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/3.flash_ctrl_mid_op_rst.2535023571
Short name T124
Test name
Test status
Simulation time 5827780500 ps
CPU time 76.45 seconds
Started Jun 09 02:44:47 PM PDT 24
Finished Jun 09 02:46:04 PM PDT 24
Peak memory 260732 kb
Host smart-7536b69e-a35d-4030-87f3-0fa947236c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535023571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.2535023571
Directory /workspace/3.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/3.flash_ctrl_mp_regions.3824102102
Short name T103
Test name
Test status
Simulation time 16494811000 ps
CPU time 257.23 seconds
Started Jun 09 02:44:42 PM PDT 24
Finished Jun 09 02:49:00 PM PDT 24
Peak memory 275220 kb
Host smart-f09f9f7a-a949-415c-b43c-724cf01c8ada
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824102102 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_mp_regions.3824102102
Directory /workspace/3.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/3.flash_ctrl_otp_reset.357143167
Short name T1056
Test name
Test status
Simulation time 138783400 ps
CPU time 109.59 seconds
Started Jun 09 02:44:43 PM PDT 24
Finished Jun 09 02:46:33 PM PDT 24
Peak memory 260384 kb
Host smart-56cbd5c6-7939-419e-8027-45a725cf48e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357143167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp
_reset.357143167
Directory /workspace/3.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.4089547474
Short name T247
Test name
Test status
Simulation time 84467700 ps
CPU time 13.93 seconds
Started Jun 09 02:45:19 PM PDT 24
Finished Jun 09 02:45:33 PM PDT 24
Peak memory 261936 kb
Host smart-65902af4-da9b-454c-8053-81066a07bc11
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=4089547474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.4089547474
Directory /workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb.1729569134
Short name T779
Test name
Test status
Simulation time 187307500 ps
CPU time 276.97 seconds
Started Jun 09 02:44:31 PM PDT 24
Finished Jun 09 02:49:08 PM PDT 24
Peak memory 263384 kb
Host smart-fa0307a5-8a60-406d-9da7-b26b5a255599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729569134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1729569134
Directory /workspace/3.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/3.flash_ctrl_phy_arb_redun.1486152304
Short name T73
Test name
Test status
Simulation time 886785000 ps
CPU time 19.04 seconds
Started Jun 09 02:45:14 PM PDT 24
Finished Jun 09 02:45:33 PM PDT 24
Peak memory 266044 kb
Host smart-1633c29f-2cd2-45c2-8794-980f709bf2b7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486152304 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.1486152304
Directory /workspace/3.flash_ctrl_phy_arb_redun/latest

Test location /workspace/coverage/default/3.flash_ctrl_prog_reset.1609299522
Short name T920
Test name
Test status
Simulation time 21550100 ps
CPU time 13.74 seconds
Started Jun 09 02:45:07 PM PDT 24
Finished Jun 09 02:45:21 PM PDT 24
Peak memory 265672 kb
Host smart-be807016-f9d2-4c44-934b-93773c1e87ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609299522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_res
et.1609299522
Directory /workspace/3.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/3.flash_ctrl_rd_buff_evict.3545775108
Short name T193
Test name
Test status
Simulation time 1435456100 ps
CPU time 154.48 seconds
Started Jun 09 02:44:33 PM PDT 24
Finished Jun 09 02:47:08 PM PDT 24
Peak memory 265612 kb
Host smart-bd409216-7784-45b7-8db1-55ca77373b0a
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3545775108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.3545775108
Directory /workspace/3.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_re_evict.3457630405
Short name T1007
Test name
Test status
Simulation time 152350500 ps
CPU time 34.66 seconds
Started Jun 09 02:45:09 PM PDT 24
Finished Jun 09 02:45:44 PM PDT 24
Peak memory 270572 kb
Host smart-dd4d381e-b4e3-4f12-aec9-a0460a50a33c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457630405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_re_evict.3457630405
Directory /workspace/3.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.2608186917
Short name T825
Test name
Test status
Simulation time 48713900 ps
CPU time 21.27 seconds
Started Jun 09 02:45:03 PM PDT 24
Finished Jun 09 02:45:25 PM PDT 24
Peak memory 265776 kb
Host smart-240c1200-b3e0-4706-b286-6ad5ac24d6f9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608186917 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.2608186917
Directory /workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.1988106623
Short name T736
Test name
Test status
Simulation time 91688300 ps
CPU time 22.87 seconds
Started Jun 09 02:44:55 PM PDT 24
Finished Jun 09 02:45:18 PM PDT 24
Peak memory 265664 kb
Host smart-490f7d35-7e9b-47a8-a76f-ae151297af23
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988106623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_read_word_sweep_serr.1988106623
Directory /workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro.2969310968
Short name T823
Test name
Test status
Simulation time 1856036100 ps
CPU time 120.96 seconds
Started Jun 09 02:44:54 PM PDT 24
Finished Jun 09 02:46:55 PM PDT 24
Peak memory 282100 kb
Host smart-0fdfb461-9786-4130-8a08-0bfc7a04f911
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969310968 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_ro.2969310968
Directory /workspace/3.flash_ctrl_ro/latest

Test location /workspace/coverage/default/3.flash_ctrl_ro_serr.336418388
Short name T1072
Test name
Test status
Simulation time 1375093300 ps
CPU time 160.28 seconds
Started Jun 09 02:44:59 PM PDT 24
Finished Jun 09 02:47:39 PM PDT 24
Peak memory 295664 kb
Host smart-1c163386-43cb-47f6-8316-f332887fc885
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336418388 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.336418388
Directory /workspace/3.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict.2269200064
Short name T336
Test name
Test status
Simulation time 27661600 ps
CPU time 29.14 seconds
Started Jun 09 02:45:08 PM PDT 24
Finished Jun 09 02:45:37 PM PDT 24
Peak memory 275696 kb
Host smart-2223b590-562d-4bd6-81e0-60064269fbb5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269200064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_rw_evict.2269200064
Directory /workspace/3.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.3839375389
Short name T1052
Test name
Test status
Simulation time 29124400 ps
CPU time 31.14 seconds
Started Jun 09 02:45:09 PM PDT 24
Finished Jun 09 02:45:41 PM PDT 24
Peak memory 276048 kb
Host smart-f266eaba-fd15-400b-9e21-f0b930e83b81
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839375389 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.3839375389
Directory /workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/3.flash_ctrl_sec_info_access.3712711050
Short name T509
Test name
Test status
Simulation time 2897486100 ps
CPU time 74.94 seconds
Started Jun 09 02:45:15 PM PDT 24
Finished Jun 09 02:46:31 PM PDT 24
Peak memory 264276 kb
Host smart-0323b1f5-fa2e-486c-9a44-b08b2db4ddab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712711050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.3712711050
Directory /workspace/3.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_address.2473901265
Short name T1069
Test name
Test status
Simulation time 1551562100 ps
CPU time 57.65 seconds
Started Jun 09 02:45:04 PM PDT 24
Finished Jun 09 02:46:02 PM PDT 24
Peak memory 273892 kb
Host smart-f4423b8a-39b4-430e-9994-d206e5fad629
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473901265 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_serr_address.2473901265
Directory /workspace/3.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/3.flash_ctrl_serr_counter.1161761291
Short name T1061
Test name
Test status
Simulation time 3263997900 ps
CPU time 95.79 seconds
Started Jun 09 02:45:00 PM PDT 24
Finished Jun 09 02:46:36 PM PDT 24
Peak memory 274092 kb
Host smart-a97fec7b-a6df-4638-9eb7-7351c591696a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161761291 -assert nopostproc +UVM_TESTNAME=flash_ctr
l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_serr_counter.1161761291
Directory /workspace/3.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke.4203130253
Short name T722
Test name
Test status
Simulation time 43146400 ps
CPU time 117.48 seconds
Started Jun 09 02:44:29 PM PDT 24
Finished Jun 09 02:46:26 PM PDT 24
Peak memory 276332 kb
Host smart-0adac15f-14be-46a5-9e93-6374f0d2cfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203130253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.4203130253
Directory /workspace/3.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/3.flash_ctrl_smoke_hw.2812188401
Short name T452
Test name
Test status
Simulation time 17047100 ps
CPU time 25.49 seconds
Started Jun 09 02:44:28 PM PDT 24
Finished Jun 09 02:44:54 PM PDT 24
Peak memory 259816 kb
Host smart-27d9c23f-e5c5-4bd2-8450-9c7e5f43d311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812188401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.2812188401
Directory /workspace/3.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/3.flash_ctrl_sw_op.1003128588
Short name T1021
Test name
Test status
Simulation time 30443800 ps
CPU time 26.63 seconds
Started Jun 09 02:44:32 PM PDT 24
Finished Jun 09 02:44:59 PM PDT 24
Peak memory 262404 kb
Host smart-43d99e1e-9838-43c2-8031-46304ec85ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003128588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.1003128588
Directory /workspace/3.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/3.flash_ctrl_wo.3675184908
Short name T634
Test name
Test status
Simulation time 12265606900 ps
CPU time 149.26 seconds
Started Jun 09 02:44:53 PM PDT 24
Finished Jun 09 02:47:22 PM PDT 24
Peak memory 260200 kb
Host smart-b798ef51-c720-4e2b-9120-c124f0119ecb
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675184908 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.flash_ctrl_wo.3675184908
Directory /workspace/3.flash_ctrl_wo/latest

Test location /workspace/coverage/default/30.flash_ctrl_alert_test.2274889466
Short name T698
Test name
Test status
Simulation time 18546600 ps
CPU time 13.77 seconds
Started Jun 09 02:55:30 PM PDT 24
Finished Jun 09 02:55:44 PM PDT 24
Peak memory 265580 kb
Host smart-ae2fa1ae-2111-4b0d-b016-e3a7b3decb14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274889466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.
2274889466
Directory /workspace/30.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.flash_ctrl_connect.1042243908
Short name T893
Test name
Test status
Simulation time 97587500 ps
CPU time 15.97 seconds
Started Jun 09 02:55:31 PM PDT 24
Finished Jun 09 02:55:47 PM PDT 24
Peak memory 274944 kb
Host smart-562c29da-36c4-47e7-bf93-2618022bc0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042243908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.1042243908
Directory /workspace/30.flash_ctrl_connect/latest

Test location /workspace/coverage/default/30.flash_ctrl_disable.1720240358
Short name T207
Test name
Test status
Simulation time 31893500 ps
CPU time 21.9 seconds
Started Jun 09 02:55:29 PM PDT 24
Finished Jun 09 02:55:51 PM PDT 24
Peak memory 274088 kb
Host smart-59f098a8-fb75-4ee8-853a-eb813c5ce565
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720240358 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_disable.1720240358
Directory /workspace/30.flash_ctrl_disable/latest

Test location /workspace/coverage/default/30.flash_ctrl_hw_sec_otp.2886925996
Short name T664
Test name
Test status
Simulation time 2642651000 ps
CPU time 70.06 seconds
Started Jun 09 02:55:29 PM PDT 24
Finished Jun 09 02:56:39 PM PDT 24
Peak memory 263364 kb
Host smart-987e9fd5-04f9-459e-8af7-3d1858bff3f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886925996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_
hw_sec_otp.2886925996
Directory /workspace/30.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd.2065228057
Short name T703
Test name
Test status
Simulation time 6222463400 ps
CPU time 278.86 seconds
Started Jun 09 02:55:32 PM PDT 24
Finished Jun 09 03:00:11 PM PDT 24
Peak memory 285232 kb
Host smart-b678b702-5fb2-4315-a4bd-87c3bb56b09e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065228057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_intr_rd.2065228057
Directory /workspace/30.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3201156564
Short name T918
Test name
Test status
Simulation time 8611254600 ps
CPU time 157.38 seconds
Started Jun 09 02:55:31 PM PDT 24
Finished Jun 09 02:58:09 PM PDT 24
Peak memory 293376 kb
Host smart-b6d27780-3377-4d76-83d9-ddab3a567e60
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201156564 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.3201156564
Directory /workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/30.flash_ctrl_otp_reset.1653922659
Short name T798
Test name
Test status
Simulation time 71890700 ps
CPU time 131.91 seconds
Started Jun 09 02:55:30 PM PDT 24
Finished Jun 09 02:57:42 PM PDT 24
Peak memory 261284 kb
Host smart-9cee2a7e-6d21-46da-ab57-1b0184078960
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653922659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_o
tp_reset.1653922659
Directory /workspace/30.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict.170553959
Short name T7
Test name
Test status
Simulation time 65672200 ps
CPU time 30.36 seconds
Started Jun 09 02:55:30 PM PDT 24
Finished Jun 09 02:56:01 PM PDT 24
Peak memory 275824 kb
Host smart-731afc16-e267-461e-8002-9e5add086463
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170553959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla
sh_ctrl_rw_evict.170553959
Directory /workspace/30.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/30.flash_ctrl_rw_evict_all_en.3906228833
Short name T1038
Test name
Test status
Simulation time 34405800 ps
CPU time 31.4 seconds
Started Jun 09 02:55:28 PM PDT 24
Finished Jun 09 02:56:00 PM PDT 24
Peak memory 276088 kb
Host smart-09b82022-304b-4c53-a7ab-83896666469d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906228833 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict_all_en.3906228833
Directory /workspace/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/30.flash_ctrl_sec_info_access.2624251081
Short name T1029
Test name
Test status
Simulation time 359101100 ps
CPU time 55.19 seconds
Started Jun 09 02:55:30 PM PDT 24
Finished Jun 09 02:56:26 PM PDT 24
Peak memory 264164 kb
Host smart-b4ebdab0-1cea-454d-b303-d05a205527a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624251081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.2624251081
Directory /workspace/30.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/30.flash_ctrl_smoke.403796110
Short name T611
Test name
Test status
Simulation time 30198900 ps
CPU time 74.79 seconds
Started Jun 09 02:55:28 PM PDT 24
Finished Jun 09 02:56:43 PM PDT 24
Peak memory 276996 kb
Host smart-110dd8f1-56c1-415c-ab04-aba37656a17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403796110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.403796110
Directory /workspace/30.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/31.flash_ctrl_alert_test.169373896
Short name T501
Test name
Test status
Simulation time 48818400 ps
CPU time 13.52 seconds
Started Jun 09 02:55:37 PM PDT 24
Finished Jun 09 02:55:51 PM PDT 24
Peak memory 258584 kb
Host smart-778c10fb-e53f-4fe9-87f9-0097980128cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169373896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.169373896
Directory /workspace/31.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.flash_ctrl_connect.3551806482
Short name T468
Test name
Test status
Simulation time 71289300 ps
CPU time 13.34 seconds
Started Jun 09 02:55:39 PM PDT 24
Finished Jun 09 02:55:53 PM PDT 24
Peak memory 284596 kb
Host smart-3b01b74a-aac0-43dc-9187-50cfbbed7a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551806482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3551806482
Directory /workspace/31.flash_ctrl_connect/latest

Test location /workspace/coverage/default/31.flash_ctrl_disable.115920594
Short name T797
Test name
Test status
Simulation time 20540900 ps
CPU time 22.22 seconds
Started Jun 09 02:55:40 PM PDT 24
Finished Jun 09 02:56:02 PM PDT 24
Peak memory 265264 kb
Host smart-2bc15177-496d-4528-bf12-bd3bf57d620a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115920594 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.flash_ctrl_disable.115920594
Directory /workspace/31.flash_ctrl_disable/latest

Test location /workspace/coverage/default/31.flash_ctrl_hw_sec_otp.654826773
Short name T712
Test name
Test status
Simulation time 3443344300 ps
CPU time 130.84 seconds
Started Jun 09 02:55:31 PM PDT 24
Finished Jun 09 02:57:42 PM PDT 24
Peak memory 263260 kb
Host smart-67c29de5-a7c6-4176-9482-f23366a5c2c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654826773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_h
w_sec_otp.654826773
Directory /workspace/31.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.2395021880
Short name T856
Test name
Test status
Simulation time 70180751300 ps
CPU time 301.98 seconds
Started Jun 09 02:55:32 PM PDT 24
Finished Jun 09 03:00:35 PM PDT 24
Peak memory 291316 kb
Host smart-fc51bbe8-2b55-4eff-958e-70b46d99b8f8
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395021880 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.2395021880
Directory /workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/31.flash_ctrl_otp_reset.3520092377
Short name T688
Test name
Test status
Simulation time 82807900 ps
CPU time 130.09 seconds
Started Jun 09 02:55:34 PM PDT 24
Finished Jun 09 02:57:44 PM PDT 24
Peak memory 261292 kb
Host smart-90bcfd8b-15d6-4f13-9258-b7cca023d3d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520092377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o
tp_reset.3520092377
Directory /workspace/31.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict.4211844421
Short name T1035
Test name
Test status
Simulation time 32743200 ps
CPU time 28.23 seconds
Started Jun 09 02:55:33 PM PDT 24
Finished Jun 09 02:56:02 PM PDT 24
Peak memory 275840 kb
Host smart-2cbfc679-0471-42d5-9b8f-1cc7f926a4e7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211844421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fl
ash_ctrl_rw_evict.4211844421
Directory /workspace/31.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.308966404
Short name T360
Test name
Test status
Simulation time 344451100 ps
CPU time 31.65 seconds
Started Jun 09 02:55:39 PM PDT 24
Finished Jun 09 02:56:11 PM PDT 24
Peak memory 276048 kb
Host smart-617bffd4-8a47-40f8-bcfa-fd8db421e9c4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308966404 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.308966404
Directory /workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/31.flash_ctrl_sec_info_access.3825245354
Short name T35
Test name
Test status
Simulation time 1641177100 ps
CPU time 77.37 seconds
Started Jun 09 02:55:39 PM PDT 24
Finished Jun 09 02:56:57 PM PDT 24
Peak memory 264428 kb
Host smart-9b99c84d-228a-4d5e-b044-461a2da51e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825245354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.3825245354
Directory /workspace/31.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/31.flash_ctrl_smoke.1646051919
Short name T1020
Test name
Test status
Simulation time 81031200 ps
CPU time 124.42 seconds
Started Jun 09 02:55:29 PM PDT 24
Finished Jun 09 02:57:34 PM PDT 24
Peak memory 278528 kb
Host smart-711f8f72-9074-4999-8884-282d2c04c3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646051919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.1646051919
Directory /workspace/31.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/32.flash_ctrl_alert_test.3861359492
Short name T632
Test name
Test status
Simulation time 49215600 ps
CPU time 13.29 seconds
Started Jun 09 02:55:45 PM PDT 24
Finished Jun 09 02:55:59 PM PDT 24
Peak memory 265756 kb
Host smart-f2036e0d-3f7c-47be-89e4-863c02e2419e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861359492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.
3861359492
Directory /workspace/32.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.flash_ctrl_connect.319574743
Short name T637
Test name
Test status
Simulation time 26925800 ps
CPU time 15.88 seconds
Started Jun 09 02:55:43 PM PDT 24
Finished Jun 09 02:55:59 PM PDT 24
Peak memory 284580 kb
Host smart-ed82853b-699b-4545-86d7-a820ded350f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319574743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.319574743
Directory /workspace/32.flash_ctrl_connect/latest

Test location /workspace/coverage/default/32.flash_ctrl_disable.3457280263
Short name T408
Test name
Test status
Simulation time 11173400 ps
CPU time 20.36 seconds
Started Jun 09 02:55:45 PM PDT 24
Finished Jun 09 02:56:06 PM PDT 24
Peak memory 274196 kb
Host smart-b8a64c10-edbc-498a-9b9d-d744b52073ca
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457280263 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_disable.3457280263
Directory /workspace/32.flash_ctrl_disable/latest

Test location /workspace/coverage/default/32.flash_ctrl_hw_sec_otp.3482368754
Short name T520
Test name
Test status
Simulation time 2856782800 ps
CPU time 202.72 seconds
Started Jun 09 02:55:38 PM PDT 24
Finished Jun 09 02:59:02 PM PDT 24
Peak memory 262996 kb
Host smart-35addb60-0b4a-4aca-98f2-15d0794c1fc9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482368754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_
hw_sec_otp.3482368754
Directory /workspace/32.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd.2576408995
Short name T1046
Test name
Test status
Simulation time 2122213400 ps
CPU time 130.82 seconds
Started Jun 09 02:55:47 PM PDT 24
Finished Jun 09 02:57:58 PM PDT 24
Peak memory 291740 kb
Host smart-d227efc8-f221-476e-92ca-aced0c158a25
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576408995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla
sh_ctrl_intr_rd.2576408995
Directory /workspace/32.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.4108604919
Short name T963
Test name
Test status
Simulation time 47888858800 ps
CPU time 307.96 seconds
Started Jun 09 02:55:42 PM PDT 24
Finished Jun 09 03:00:50 PM PDT 24
Peak memory 290348 kb
Host smart-49f9eeb2-9bd3-44d3-a3a6-d180bfac24f9
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108604919 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.4108604919
Directory /workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.1493771481
Short name T756
Test name
Test status
Simulation time 72115500 ps
CPU time 31.12 seconds
Started Jun 09 02:55:43 PM PDT 24
Finished Jun 09 02:56:15 PM PDT 24
Peak memory 267888 kb
Host smart-6c497e26-a52f-49ce-acd8-dd56ecb5fa85
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493771481 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.1493771481
Directory /workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/32.flash_ctrl_sec_info_access.3074919125
Short name T727
Test name
Test status
Simulation time 4354580000 ps
CPU time 64.65 seconds
Started Jun 09 02:55:45 PM PDT 24
Finished Jun 09 02:56:50 PM PDT 24
Peak memory 265612 kb
Host smart-a48422dd-6d10-4b92-a658-1a628f7df7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074919125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3074919125
Directory /workspace/32.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/32.flash_ctrl_smoke.637023655
Short name T907
Test name
Test status
Simulation time 52938100 ps
CPU time 148.11 seconds
Started Jun 09 02:55:39 PM PDT 24
Finished Jun 09 02:58:07 PM PDT 24
Peak memory 271104 kb
Host smart-0db5686f-1078-4d98-8082-a8fcf4aef1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637023655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.637023655
Directory /workspace/32.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/33.flash_ctrl_alert_test.2542836707
Short name T734
Test name
Test status
Simulation time 226324500 ps
CPU time 13.75 seconds
Started Jun 09 02:55:56 PM PDT 24
Finished Jun 09 02:56:10 PM PDT 24
Peak memory 265504 kb
Host smart-f85e4a31-dd4f-4192-a144-36b0258a2f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542836707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.
2542836707
Directory /workspace/33.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.flash_ctrl_connect.2465665416
Short name T390
Test name
Test status
Simulation time 40868700 ps
CPU time 15.79 seconds
Started Jun 09 02:55:52 PM PDT 24
Finished Jun 09 02:56:08 PM PDT 24
Peak memory 284428 kb
Host smart-39338f8a-3b7c-4371-aaed-62986f00af4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465665416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2465665416
Directory /workspace/33.flash_ctrl_connect/latest

Test location /workspace/coverage/default/33.flash_ctrl_disable.479064696
Short name T137
Test name
Test status
Simulation time 13650200 ps
CPU time 21.16 seconds
Started Jun 09 02:55:55 PM PDT 24
Finished Jun 09 02:56:16 PM PDT 24
Peak memory 265228 kb
Host smart-e2b8b064-2a0a-41ba-80f2-e927eec1c028
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479064696 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_disable.479064696
Directory /workspace/33.flash_ctrl_disable/latest

Test location /workspace/coverage/default/33.flash_ctrl_hw_sec_otp.3352449158
Short name T715
Test name
Test status
Simulation time 3665606200 ps
CPU time 59.56 seconds
Started Jun 09 02:55:43 PM PDT 24
Finished Jun 09 02:56:43 PM PDT 24
Peak memory 263248 kb
Host smart-df9ad732-e77f-47b9-81f4-246ba6a361d8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352449158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_
hw_sec_otp.3352449158
Directory /workspace/33.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd.4206072701
Short name T801
Test name
Test status
Simulation time 5497429700 ps
CPU time 206.68 seconds
Started Jun 09 02:55:48 PM PDT 24
Finished Jun 09 02:59:15 PM PDT 24
Peak memory 291732 kb
Host smart-44289e35-6d5a-4237-8224-d665cbe0c35b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206072701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla
sh_ctrl_intr_rd.4206072701
Directory /workspace/33.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.849440985
Short name T607
Test name
Test status
Simulation time 16487218200 ps
CPU time 299.11 seconds
Started Jun 09 02:55:48 PM PDT 24
Finished Jun 09 03:00:48 PM PDT 24
Peak memory 285136 kb
Host smart-0b649c98-7f2b-43d9-ae7c-e88574fc750c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849440985 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.849440985
Directory /workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/33.flash_ctrl_otp_reset.4093233904
Short name T1054
Test name
Test status
Simulation time 45942300 ps
CPU time 131.67 seconds
Started Jun 09 02:55:49 PM PDT 24
Finished Jun 09 02:58:01 PM PDT 24
Peak memory 265416 kb
Host smart-98e21e87-1965-4b82-a264-48efdc3013c0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093233904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o
tp_reset.4093233904
Directory /workspace/33.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict.3036477254
Short name T792
Test name
Test status
Simulation time 210691300 ps
CPU time 31.19 seconds
Started Jun 09 02:55:51 PM PDT 24
Finished Jun 09 02:56:22 PM PDT 24
Peak memory 275784 kb
Host smart-46c75842-f531-4a71-bafd-4169d4ee4515
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036477254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl
ash_ctrl_rw_evict.3036477254
Directory /workspace/33.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.2705639177
Short name T884
Test name
Test status
Simulation time 35481900 ps
CPU time 30.22 seconds
Started Jun 09 02:55:48 PM PDT 24
Finished Jun 09 02:56:18 PM PDT 24
Peak memory 276104 kb
Host smart-d8226ba4-d861-489f-97a1-69810d4cceee
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705639177 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.2705639177
Directory /workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/33.flash_ctrl_sec_info_access.1493961884
Short name T791
Test name
Test status
Simulation time 4793331600 ps
CPU time 79.7 seconds
Started Jun 09 02:55:53 PM PDT 24
Finished Jun 09 02:57:13 PM PDT 24
Peak memory 259812 kb
Host smart-d4c84647-72e2-43e9-a903-1b9305a652e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493961884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1493961884
Directory /workspace/33.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/33.flash_ctrl_smoke.2470494352
Short name T1062
Test name
Test status
Simulation time 116970500 ps
CPU time 144.18 seconds
Started Jun 09 02:55:47 PM PDT 24
Finished Jun 09 02:58:11 PM PDT 24
Peak memory 276996 kb
Host smart-d552f892-15c9-4d22-8746-4e5f0264a279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470494352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.2470494352
Directory /workspace/33.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/34.flash_ctrl_alert_test.3260713203
Short name T885
Test name
Test status
Simulation time 54636800 ps
CPU time 13.86 seconds
Started Jun 09 02:55:59 PM PDT 24
Finished Jun 09 02:56:13 PM PDT 24
Peak memory 258560 kb
Host smart-3b9e7cf6-fe1a-471d-b20b-a4c81c5db6f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260713203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.
3260713203
Directory /workspace/34.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.flash_ctrl_connect.2207552746
Short name T486
Test name
Test status
Simulation time 15864100 ps
CPU time 15.86 seconds
Started Jun 09 02:55:58 PM PDT 24
Finished Jun 09 02:56:14 PM PDT 24
Peak memory 275300 kb
Host smart-8fee3dee-ef37-4414-ba20-2025b4b4e9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207552746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.2207552746
Directory /workspace/34.flash_ctrl_connect/latest

Test location /workspace/coverage/default/34.flash_ctrl_disable.2792458479
Short name T57
Test name
Test status
Simulation time 20436200 ps
CPU time 20.22 seconds
Started Jun 09 02:55:59 PM PDT 24
Finished Jun 09 02:56:19 PM PDT 24
Peak memory 265824 kb
Host smart-d0ee951f-bc98-44df-bb92-834c7030fa7b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792458479 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_disable.2792458479
Directory /workspace/34.flash_ctrl_disable/latest

Test location /workspace/coverage/default/34.flash_ctrl_hw_sec_otp.3330927058
Short name T1043
Test name
Test status
Simulation time 29023733400 ps
CPU time 99.84 seconds
Started Jun 09 02:55:58 PM PDT 24
Finished Jun 09 02:57:38 PM PDT 24
Peak memory 263448 kb
Host smart-e09432b8-5d59-4eed-8270-ffaa7724f92d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330927058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_
hw_sec_otp.3330927058
Directory /workspace/34.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd.330472809
Short name T187
Test name
Test status
Simulation time 5656743500 ps
CPU time 199.62 seconds
Started Jun 09 02:55:57 PM PDT 24
Finished Jun 09 02:59:16 PM PDT 24
Peak memory 285040 kb
Host smart-73846287-1d27-4cb2-8811-25dfbcdca66b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330472809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flas
h_ctrl_intr_rd.330472809
Directory /workspace/34.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.1370798056
Short name T886
Test name
Test status
Simulation time 8651145700 ps
CPU time 159.82 seconds
Started Jun 09 02:55:59 PM PDT 24
Finished Jun 09 02:58:39 PM PDT 24
Peak memory 293424 kb
Host smart-a0fb12c4-9be6-4b7d-b945-f3f50baba8a4
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370798056 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.1370798056
Directory /workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/34.flash_ctrl_otp_reset.4225998738
Short name T456
Test name
Test status
Simulation time 129219100 ps
CPU time 130 seconds
Started Jun 09 02:55:56 PM PDT 24
Finished Jun 09 02:58:06 PM PDT 24
Peak memory 264504 kb
Host smart-1ad8cacc-761e-4ee2-a4f9-ca3a15c7f66c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225998738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o
tp_reset.4225998738
Directory /workspace/34.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict.1957713172
Short name T404
Test name
Test status
Simulation time 28807000 ps
CPU time 30.76 seconds
Started Jun 09 02:55:57 PM PDT 24
Finished Jun 09 02:56:28 PM PDT 24
Peak memory 269752 kb
Host smart-76a23533-8591-4f16-b525-42f05a2d1035
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957713172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fl
ash_ctrl_rw_evict.1957713172
Directory /workspace/34.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.2076230401
Short name T1066
Test name
Test status
Simulation time 45095500 ps
CPU time 29.14 seconds
Started Jun 09 02:55:58 PM PDT 24
Finished Jun 09 02:56:27 PM PDT 24
Peak memory 267812 kb
Host smart-b1cd2ca3-fd31-4214-8cf2-68d815f84965
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076230401 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.2076230401
Directory /workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/34.flash_ctrl_sec_info_access.4086401161
Short name T713
Test name
Test status
Simulation time 761160200 ps
CPU time 70.58 seconds
Started Jun 09 02:55:58 PM PDT 24
Finished Jun 09 02:57:09 PM PDT 24
Peak memory 264700 kb
Host smart-306b60c6-591a-4e3f-8811-659c7c239559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086401161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.4086401161
Directory /workspace/34.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/34.flash_ctrl_smoke.1522273331
Short name T483
Test name
Test status
Simulation time 64488000 ps
CPU time 147.21 seconds
Started Jun 09 02:55:54 PM PDT 24
Finished Jun 09 02:58:22 PM PDT 24
Peak memory 277232 kb
Host smart-8d212b31-5494-4d8a-94f6-dba2d23f5854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522273331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1522273331
Directory /workspace/34.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/35.flash_ctrl_alert_test.4139712725
Short name T793
Test name
Test status
Simulation time 46482000 ps
CPU time 13.81 seconds
Started Jun 09 02:56:08 PM PDT 24
Finished Jun 09 02:56:22 PM PDT 24
Peak memory 258552 kb
Host smart-53c7780e-b14e-47e2-8f4b-cd9cd281c811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139712725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.
4139712725
Directory /workspace/35.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.flash_ctrl_connect.1976040950
Short name T925
Test name
Test status
Simulation time 13590500 ps
CPU time 13.42 seconds
Started Jun 09 02:56:06 PM PDT 24
Finished Jun 09 02:56:20 PM PDT 24
Peak memory 284548 kb
Host smart-6726a162-c43a-4393-8abc-fb2361a7ae14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976040950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.1976040950
Directory /workspace/35.flash_ctrl_connect/latest

Test location /workspace/coverage/default/35.flash_ctrl_disable.4227680110
Short name T120
Test name
Test status
Simulation time 12787200 ps
CPU time 20.21 seconds
Started Jun 09 02:56:07 PM PDT 24
Finished Jun 09 02:56:27 PM PDT 24
Peak memory 273964 kb
Host smart-7c5a63e5-5836-42d3-a618-73d3c9b44881
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227680110 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.flash_ctrl_disable.4227680110
Directory /workspace/35.flash_ctrl_disable/latest

Test location /workspace/coverage/default/35.flash_ctrl_hw_sec_otp.3378184666
Short name T833
Test name
Test status
Simulation time 4291274200 ps
CPU time 101.57 seconds
Started Jun 09 02:56:03 PM PDT 24
Finished Jun 09 02:57:44 PM PDT 24
Peak memory 262852 kb
Host smart-d45587e9-3b9e-45e2-aea9-3273512de1d5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378184666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_
hw_sec_otp.3378184666
Directory /workspace/35.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd.512136390
Short name T708
Test name
Test status
Simulation time 662146100 ps
CPU time 160.61 seconds
Started Jun 09 02:56:09 PM PDT 24
Finished Jun 09 02:58:50 PM PDT 24
Peak memory 294472 kb
Host smart-4d8edc20-3c17-44f0-a632-e860e77b8b37
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512136390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flas
h_ctrl_intr_rd.512136390
Directory /workspace/35.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3381986595
Short name T595
Test name
Test status
Simulation time 22790555800 ps
CPU time 153 seconds
Started Jun 09 02:56:06 PM PDT 24
Finished Jun 09 02:58:40 PM PDT 24
Peak memory 293008 kb
Host smart-c1570f83-a431-4234-985d-a199c5b1be28
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381986595 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.3381986595
Directory /workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/35.flash_ctrl_otp_reset.2026271302
Short name T851
Test name
Test status
Simulation time 46324900 ps
CPU time 132.29 seconds
Started Jun 09 02:56:07 PM PDT 24
Finished Jun 09 02:58:19 PM PDT 24
Peak memory 261396 kb
Host smart-7b8c1859-14f5-4da2-a72e-4594f8a17f95
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026271302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o
tp_reset.2026271302
Directory /workspace/35.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict.3137333617
Short name T882
Test name
Test status
Simulation time 46331000 ps
CPU time 30.8 seconds
Started Jun 09 02:56:09 PM PDT 24
Finished Jun 09 02:56:40 PM PDT 24
Peak memory 277828 kb
Host smart-7e56119e-e0a6-4757-8a68-93469f56ee67
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137333617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl
ash_ctrl_rw_evict.3137333617
Directory /workspace/35.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/35.flash_ctrl_rw_evict_all_en.132519835
Short name T576
Test name
Test status
Simulation time 49184200 ps
CPU time 31.32 seconds
Started Jun 09 02:56:07 PM PDT 24
Finished Jun 09 02:56:38 PM PDT 24
Peak memory 276040 kb
Host smart-42ba46e7-e87e-4d7a-8cc1-615aca763112
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132519835 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict_all_en.132519835
Directory /workspace/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/35.flash_ctrl_sec_info_access.3139455342
Short name T424
Test name
Test status
Simulation time 1261058500 ps
CPU time 71.35 seconds
Started Jun 09 02:56:06 PM PDT 24
Finished Jun 09 02:57:18 PM PDT 24
Peak memory 265184 kb
Host smart-3918a4b1-6794-4a21-83bb-9d5515f06996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139455342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.3139455342
Directory /workspace/35.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/35.flash_ctrl_smoke.1671853313
Short name T393
Test name
Test status
Simulation time 108303400 ps
CPU time 175.53 seconds
Started Jun 09 02:56:02 PM PDT 24
Finished Jun 09 02:58:58 PM PDT 24
Peak memory 277544 kb
Host smart-7432136a-b95a-43f0-b88c-9c3367570095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671853313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.1671853313
Directory /workspace/35.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/36.flash_ctrl_alert_test.1804093612
Short name T557
Test name
Test status
Simulation time 32117700 ps
CPU time 13.7 seconds
Started Jun 09 02:56:15 PM PDT 24
Finished Jun 09 02:56:29 PM PDT 24
Peak memory 265552 kb
Host smart-8bae16a1-e613-48ee-9479-bdd3e14d288c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804093612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.
1804093612
Directory /workspace/36.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.flash_ctrl_connect.3775241681
Short name T492
Test name
Test status
Simulation time 52696000 ps
CPU time 15.89 seconds
Started Jun 09 02:56:16 PM PDT 24
Finished Jun 09 02:56:32 PM PDT 24
Peak memory 284448 kb
Host smart-eb8eb151-a6ea-47cf-9b6a-9778cf27201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775241681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3775241681
Directory /workspace/36.flash_ctrl_connect/latest

Test location /workspace/coverage/default/36.flash_ctrl_disable.1295055068
Short name T206
Test name
Test status
Simulation time 31670100 ps
CPU time 21.78 seconds
Started Jun 09 02:56:13 PM PDT 24
Finished Jun 09 02:56:35 PM PDT 24
Peak memory 273912 kb
Host smart-064443c7-863e-45b1-8347-cfefc17c370d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295055068 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.flash_ctrl_disable.1295055068
Directory /workspace/36.flash_ctrl_disable/latest

Test location /workspace/coverage/default/36.flash_ctrl_hw_sec_otp.1459511453
Short name T709
Test name
Test status
Simulation time 16720681700 ps
CPU time 145.59 seconds
Started Jun 09 02:56:08 PM PDT 24
Finished Jun 09 02:58:34 PM PDT 24
Peak memory 263444 kb
Host smart-bbd7c752-a6c0-4099-b43f-8de8e59cef1a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459511453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_
hw_sec_otp.1459511453
Directory /workspace/36.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/36.flash_ctrl_otp_reset.4291835447
Short name T711
Test name
Test status
Simulation time 71077000 ps
CPU time 132.38 seconds
Started Jun 09 02:56:07 PM PDT 24
Finished Jun 09 02:58:19 PM PDT 24
Peak memory 260420 kb
Host smart-6bc67f23-579e-4169-8d44-796ed8a73957
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291835447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o
tp_reset.4291835447
Directory /workspace/36.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/36.flash_ctrl_sec_info_access.3087532344
Short name T417
Test name
Test status
Simulation time 6853564400 ps
CPU time 63.25 seconds
Started Jun 09 02:56:13 PM PDT 24
Finished Jun 09 02:57:17 PM PDT 24
Peak memory 259852 kb
Host smart-7ce881e1-2c5d-413a-90be-2743db6368c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087532344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.3087532344
Directory /workspace/36.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/36.flash_ctrl_smoke.125162728
Short name T27
Test name
Test status
Simulation time 40331000 ps
CPU time 98.87 seconds
Started Jun 09 02:56:06 PM PDT 24
Finished Jun 09 02:57:45 PM PDT 24
Peak memory 276068 kb
Host smart-e965b122-c148-4e65-b047-0c81988394dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125162728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.125162728
Directory /workspace/36.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/37.flash_ctrl_alert_test.1216316089
Short name T912
Test name
Test status
Simulation time 108400800 ps
CPU time 14.04 seconds
Started Jun 09 02:56:22 PM PDT 24
Finished Jun 09 02:56:36 PM PDT 24
Peak memory 258592 kb
Host smart-5b53fd71-7618-4d9e-bec1-2e99d035381d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216316089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.
1216316089
Directory /workspace/37.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.flash_ctrl_connect.2421256605
Short name T915
Test name
Test status
Simulation time 73538600 ps
CPU time 16.1 seconds
Started Jun 09 02:56:22 PM PDT 24
Finished Jun 09 02:56:38 PM PDT 24
Peak memory 275024 kb
Host smart-891996ac-a598-4f6a-90b4-5af624f920c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421256605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.2421256605
Directory /workspace/37.flash_ctrl_connect/latest

Test location /workspace/coverage/default/37.flash_ctrl_disable.1580008896
Short name T760
Test name
Test status
Simulation time 17080500 ps
CPU time 21.61 seconds
Started Jun 09 02:56:20 PM PDT 24
Finished Jun 09 02:56:42 PM PDT 24
Peak memory 274068 kb
Host smart-af3eac7b-32cb-463e-992b-350c6b81fb78
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580008896 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.flash_ctrl_disable.1580008896
Directory /workspace/37.flash_ctrl_disable/latest

Test location /workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1363030647
Short name T86
Test name
Test status
Simulation time 6202675500 ps
CPU time 117.66 seconds
Started Jun 09 02:56:17 PM PDT 24
Finished Jun 09 02:58:15 PM PDT 24
Peak memory 263408 kb
Host smart-85ca7dad-c60c-43c0-bd7d-cfd9b0317811
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363030647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_
hw_sec_otp.1363030647
Directory /workspace/37.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd.1464119477
Short name T33
Test name
Test status
Simulation time 2916035900 ps
CPU time 167.12 seconds
Started Jun 09 02:56:20 PM PDT 24
Finished Jun 09 02:59:08 PM PDT 24
Peak memory 298540 kb
Host smart-1cbf7b7c-09cc-46c5-bb16-b5f2977d81f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464119477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla
sh_ctrl_intr_rd.1464119477
Directory /workspace/37.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.853709551
Short name T619
Test name
Test status
Simulation time 5845822100 ps
CPU time 134.6 seconds
Started Jun 09 02:56:17 PM PDT 24
Finished Jun 09 02:58:31 PM PDT 24
Peak memory 293408 kb
Host smart-217bc570-12b0-4cb6-a314-7e4fa20239be
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853709551 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.853709551
Directory /workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/37.flash_ctrl_otp_reset.2077895548
Short name T162
Test name
Test status
Simulation time 104817100 ps
CPU time 134.27 seconds
Started Jun 09 02:56:17 PM PDT 24
Finished Jun 09 02:58:32 PM PDT 24
Peak memory 261404 kb
Host smart-c7077b1f-752e-483c-a25b-8eacc5b77046
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077895548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o
tp_reset.2077895548
Directory /workspace/37.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/37.flash_ctrl_sec_info_access.2181540533
Short name T379
Test name
Test status
Simulation time 1386587100 ps
CPU time 64.87 seconds
Started Jun 09 02:56:20 PM PDT 24
Finished Jun 09 02:57:26 PM PDT 24
Peak memory 263896 kb
Host smart-952a0027-0076-4160-962d-5b850ed2999f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181540533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.2181540533
Directory /workspace/37.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/37.flash_ctrl_smoke.1460741833
Short name T511
Test name
Test status
Simulation time 41326200 ps
CPU time 76.07 seconds
Started Jun 09 02:56:17 PM PDT 24
Finished Jun 09 02:57:34 PM PDT 24
Peak memory 275676 kb
Host smart-35c74637-d0b4-47dd-938b-298914e10b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460741833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.1460741833
Directory /workspace/37.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/38.flash_ctrl_alert_test.1933868050
Short name T872
Test name
Test status
Simulation time 20072200 ps
CPU time 13.5 seconds
Started Jun 09 02:56:23 PM PDT 24
Finished Jun 09 02:56:37 PM PDT 24
Peak memory 265668 kb
Host smart-e31a6c06-83ab-4d28-90d3-a72d7269659c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933868050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.
1933868050
Directory /workspace/38.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.flash_ctrl_connect.3228012609
Short name T1025
Test name
Test status
Simulation time 38282600 ps
CPU time 15.56 seconds
Started Jun 09 02:56:26 PM PDT 24
Finished Jun 09 02:56:41 PM PDT 24
Peak memory 275296 kb
Host smart-ac913777-d894-4e58-a9f8-646df36902af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228012609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.3228012609
Directory /workspace/38.flash_ctrl_connect/latest

Test location /workspace/coverage/default/38.flash_ctrl_disable.2884724615
Short name T71
Test name
Test status
Simulation time 16274900 ps
CPU time 22.06 seconds
Started Jun 09 02:56:27 PM PDT 24
Finished Jun 09 02:56:49 PM PDT 24
Peak memory 274084 kb
Host smart-cbfb47a8-9344-4d18-8033-90d43243969b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884724615 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.flash_ctrl_disable.2884724615
Directory /workspace/38.flash_ctrl_disable/latest

Test location /workspace/coverage/default/38.flash_ctrl_hw_sec_otp.1162519659
Short name T444
Test name
Test status
Simulation time 4766781200 ps
CPU time 148.13 seconds
Started Jun 09 02:56:21 PM PDT 24
Finished Jun 09 02:58:50 PM PDT 24
Peak memory 263512 kb
Host smart-ff0bfbaa-bb25-4152-b89e-d91278eacf2f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162519659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_
hw_sec_otp.1162519659
Directory /workspace/38.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.150912989
Short name T532
Test name
Test status
Simulation time 33087824000 ps
CPU time 188.68 seconds
Started Jun 09 02:56:27 PM PDT 24
Finished Jun 09 02:59:36 PM PDT 24
Peak memory 294208 kb
Host smart-8fcd141c-44ad-4585-89fa-243499ebf7aa
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150912989 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.150912989
Directory /workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/38.flash_ctrl_otp_reset.1849458742
Short name T971
Test name
Test status
Simulation time 130459100 ps
CPU time 136.87 seconds
Started Jun 09 02:56:20 PM PDT 24
Finished Jun 09 02:58:38 PM PDT 24
Peak memory 265352 kb
Host smart-fddb7861-a751-4ec9-aad2-f71eeefb176a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849458742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_o
tp_reset.1849458742
Directory /workspace/38.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/38.flash_ctrl_rw_evict.1086948832
Short name T668
Test name
Test status
Simulation time 46030700 ps
CPU time 31.37 seconds
Started Jun 09 02:56:24 PM PDT 24
Finished Jun 09 02:56:56 PM PDT 24
Peak memory 275792 kb
Host smart-ffef7171-5d3f-4128-9338-85fc6b4d69a3
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086948832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fl
ash_ctrl_rw_evict.1086948832
Directory /workspace/38.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/38.flash_ctrl_sec_info_access.1818051320
Short name T414
Test name
Test status
Simulation time 342894200 ps
CPU time 55.51 seconds
Started Jun 09 02:56:26 PM PDT 24
Finished Jun 09 02:57:21 PM PDT 24
Peak memory 264224 kb
Host smart-b159c365-7dd6-4e33-918c-def7e6a297fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818051320 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.1818051320
Directory /workspace/38.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/38.flash_ctrl_smoke.3413151037
Short name T548
Test name
Test status
Simulation time 1375392700 ps
CPU time 193.48 seconds
Started Jun 09 02:56:21 PM PDT 24
Finished Jun 09 02:59:34 PM PDT 24
Peak memory 281816 kb
Host smart-d8a70e75-7ad8-4665-a3bd-cbd4bf4842f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413151037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3413151037
Directory /workspace/38.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/39.flash_ctrl_connect.3206740674
Short name T531
Test name
Test status
Simulation time 19055900 ps
CPU time 13.25 seconds
Started Jun 09 02:56:34 PM PDT 24
Finished Jun 09 02:56:47 PM PDT 24
Peak memory 284592 kb
Host smart-0b5e45a1-af61-4d38-bb98-f6ad3ebf0c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206740674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3206740674
Directory /workspace/39.flash_ctrl_connect/latest

Test location /workspace/coverage/default/39.flash_ctrl_disable.2255479953
Short name T410
Test name
Test status
Simulation time 23581000 ps
CPU time 21.84 seconds
Started Jun 09 02:56:31 PM PDT 24
Finished Jun 09 02:56:53 PM PDT 24
Peak memory 273964 kb
Host smart-1301b4c0-cfe6-4a88-a7d2-dc6a5a6e3a3f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255479953 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_disable.2255479953
Directory /workspace/39.flash_ctrl_disable/latest

Test location /workspace/coverage/default/39.flash_ctrl_hw_sec_otp.2491224001
Short name T983
Test name
Test status
Simulation time 2440060200 ps
CPU time 94.17 seconds
Started Jun 09 02:56:27 PM PDT 24
Finished Jun 09 02:58:01 PM PDT 24
Peak memory 263360 kb
Host smart-f72c1570-a601-4872-9b62-681b7a5eb848
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491224001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_
hw_sec_otp.2491224001
Directory /workspace/39.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd.1962506391
Short name T574
Test name
Test status
Simulation time 3360401800 ps
CPU time 217.7 seconds
Started Jun 09 02:56:30 PM PDT 24
Finished Jun 09 03:00:08 PM PDT 24
Peak memory 292692 kb
Host smart-d611a70e-4094-4b67-ac09-1e0dab7212e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962506391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla
sh_ctrl_intr_rd.1962506391
Directory /workspace/39.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2383867391
Short name T927
Test name
Test status
Simulation time 32098186700 ps
CPU time 143.89 seconds
Started Jun 09 02:56:31 PM PDT 24
Finished Jun 09 02:58:55 PM PDT 24
Peak memory 292732 kb
Host smart-21003103-1392-48ce-bf4a-04c8b26b1924
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383867391 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.2383867391
Directory /workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/39.flash_ctrl_otp_reset.9152074
Short name T512
Test name
Test status
Simulation time 75525500 ps
CPU time 132.05 seconds
Started Jun 09 02:56:30 PM PDT 24
Finished Jun 09 02:58:42 PM PDT 24
Peak memory 264388 kb
Host smart-139025d7-706f-4543-9935-154c8f263621
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9152074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_
otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_otp_
reset.9152074
Directory /workspace/39.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict.2160813869
Short name T496
Test name
Test status
Simulation time 29445900 ps
CPU time 28.82 seconds
Started Jun 09 02:56:31 PM PDT 24
Finished Jun 09 02:57:00 PM PDT 24
Peak memory 275720 kb
Host smart-f4a0b1e4-70d3-4ab4-8122-c6b293efa4d0
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160813869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl
ash_ctrl_rw_evict.2160813869
Directory /workspace/39.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.2732126062
Short name T552
Test name
Test status
Simulation time 42890400 ps
CPU time 31.15 seconds
Started Jun 09 02:56:32 PM PDT 24
Finished Jun 09 02:57:04 PM PDT 24
Peak memory 267852 kb
Host smart-77bc1f64-916c-4ab6-86be-77566eb0de9c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732126062 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.2732126062
Directory /workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/39.flash_ctrl_smoke.1692797305
Short name T1089
Test name
Test status
Simulation time 53454900 ps
CPU time 98.36 seconds
Started Jun 09 02:56:26 PM PDT 24
Finished Jun 09 02:58:04 PM PDT 24
Peak memory 277092 kb
Host smart-69cbf8cc-b6c6-497f-b952-31dfee420850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692797305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.1692797305
Directory /workspace/39.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_alert_test.2215978921
Short name T586
Test name
Test status
Simulation time 42341700 ps
CPU time 13.68 seconds
Started Jun 09 02:46:14 PM PDT 24
Finished Jun 09 02:46:28 PM PDT 24
Peak memory 265592 kb
Host smart-4fe166d9-fca0-420c-9135-7451bf77bfc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215978921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.2
215978921
Directory /workspace/4.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.flash_ctrl_config_regwen.3596947145
Short name T378
Test name
Test status
Simulation time 40251400 ps
CPU time 13.87 seconds
Started Jun 09 02:46:13 PM PDT 24
Finished Jun 09 02:46:27 PM PDT 24
Peak memory 261936 kb
Host smart-4d726cb6-90df-4b7b-9e05-b123b526d532
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596947145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_config_regwen.3596947145
Directory /workspace/4.flash_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.flash_ctrl_connect.3246446309
Short name T537
Test name
Test status
Simulation time 167716300 ps
CPU time 16.03 seconds
Started Jun 09 02:46:10 PM PDT 24
Finished Jun 09 02:46:27 PM PDT 24
Peak memory 275068 kb
Host smart-08ccdbbc-2b10-43a2-a9fa-8a632e9b4962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246446309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.3246446309
Directory /workspace/4.flash_ctrl_connect/latest

Test location /workspace/coverage/default/4.flash_ctrl_derr_detect.608782196
Short name T742
Test name
Test status
Simulation time 124876600 ps
CPU time 106.95 seconds
Started Jun 09 02:45:59 PM PDT 24
Finished Jun 09 02:47:46 PM PDT 24
Peak memory 273036 kb
Host smart-9406680a-6a60-428d-81a8-3bc61c0661ce
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=1 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608782196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.flash_ctrl_derr_detect.608782196
Directory /workspace/4.flash_ctrl_derr_detect/latest

Test location /workspace/coverage/default/4.flash_ctrl_disable.1970745701
Short name T700
Test name
Test status
Simulation time 16067200 ps
CPU time 21.87 seconds
Started Jun 09 02:46:05 PM PDT 24
Finished Jun 09 02:46:27 PM PDT 24
Peak memory 273932 kb
Host smart-a1049b02-f7d9-4887-a13a-606dd8c8757b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970745701 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_disable.1970745701
Directory /workspace/4.flash_ctrl_disable/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_mp.267823446
Short name T310
Test name
Test status
Simulation time 5561064600 ps
CPU time 2249.77 seconds
Started Jun 09 02:45:41 PM PDT 24
Finished Jun 09 03:23:12 PM PDT 24
Peak memory 265008 kb
Host smart-e7608e7d-a6e1-4f33-afb9-71b837ab1a7a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267823446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erro
r_mp.267823446
Directory /workspace/4.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_type.2785437203
Short name T818
Test name
Test status
Simulation time 3017842400 ps
CPU time 2007.01 seconds
Started Jun 09 02:45:39 PM PDT 24
Finished Jun 09 03:19:07 PM PDT 24
Peak memory 262236 kb
Host smart-32b8e5e4-6486-4307-b46f-334b0cf1e1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785437203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.2785437203
Directory /workspace/4.flash_ctrl_error_prog_type/latest

Test location /workspace/coverage/default/4.flash_ctrl_error_prog_win.507286274
Short name T680
Test name
Test status
Simulation time 1347867600 ps
CPU time 890.49 seconds
Started Jun 09 02:45:45 PM PDT 24
Finished Jun 09 03:00:36 PM PDT 24
Peak memory 273736 kb
Host smart-2cb5778b-a2cf-47a8-b064-164d30445064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507286274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.507286274
Directory /workspace/4.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/4.flash_ctrl_fetch_code.2879374478
Short name T505
Test name
Test status
Simulation time 469656900 ps
CPU time 27.53 seconds
Started Jun 09 02:45:38 PM PDT 24
Finished Jun 09 02:46:06 PM PDT 24
Peak memory 262648 kb
Host smart-1efe27fb-8f2b-4ddb-a421-cd4626909321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879374478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.2879374478
Directory /workspace/4.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/4.flash_ctrl_fs_sup.2784239720
Short name T301
Test name
Test status
Simulation time 345240900 ps
CPU time 44.07 seconds
Started Jun 09 02:46:07 PM PDT 24
Finished Jun 09 02:46:52 PM PDT 24
Peak memory 263304 kb
Host smart-6b8356b5-86f0-4e93-a31c-274a727290f2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784239720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas
e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_
log /dev/null -cm_name 4.flash_ctrl_fs_sup.2784239720
Directory /workspace/4.flash_ctrl_fs_sup/latest

Test location /workspace/coverage/default/4.flash_ctrl_full_mem_access.1560904067
Short name T101
Test name
Test status
Simulation time 961276414600 ps
CPU time 3176.35 seconds
Started Jun 09 02:45:39 PM PDT 24
Finished Jun 09 03:38:36 PM PDT 24
Peak memory 273832 kb
Host smart-117a95f2-71de-47ac-8495-f2aafb31708a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560904067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_full_mem_access.1560904067
Directory /workspace/4.flash_ctrl_full_mem_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.1106313321
Short name T213
Test name
Test status
Simulation time 267486863400 ps
CPU time 2737.86 seconds
Started Jun 09 02:45:33 PM PDT 24
Finished Jun 09 03:31:12 PM PDT 24
Peak memory 264456 kb
Host smart-011f54c1-c10f-47f6-9984-8bf6be4a9945
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106313321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_host_ctrl_arb.1106313321
Directory /workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1167280936
Short name T525
Test name
Test status
Simulation time 10031298700 ps
CPU time 62.89 seconds
Started Jun 09 02:46:13 PM PDT 24
Finished Jun 09 02:47:16 PM PDT 24
Peak memory 293508 kb
Host smart-0b9ab765-b877-449b-8c0f-20c782e3d511
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167280936 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1167280936
Directory /workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.4062272065
Short name T929
Test name
Test status
Simulation time 47225300 ps
CPU time 13.62 seconds
Started Jun 09 02:46:13 PM PDT 24
Finished Jun 09 02:46:27 PM PDT 24
Peak memory 259792 kb
Host smart-1e7af564-5b1e-4f06-aaa0-0307989b86e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062272065 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.4062272065
Directory /workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_rma_reset.2385780840
Short name T129
Test name
Test status
Simulation time 380256643600 ps
CPU time 1143.27 seconds
Started Jun 09 02:45:33 PM PDT 24
Finished Jun 09 03:04:37 PM PDT 24
Peak memory 265408 kb
Host smart-5f4be31c-3efe-43c6-a9d9-393aa2859488
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385780840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.flash_ctrl_hw_rma_reset.2385780840
Directory /workspace/4.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_hw_sec_otp.3282063413
Short name T447
Test name
Test status
Simulation time 3637421200 ps
CPU time 120.21 seconds
Started Jun 09 02:45:33 PM PDT 24
Finished Jun 09 02:47:33 PM PDT 24
Peak memory 263284 kb
Host smart-cd8ccfd0-b53c-4a0f-afd2-c5207a6a677a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282063413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h
w_sec_otp.3282063413
Directory /workspace/4.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd.2059433248
Short name T748
Test name
Test status
Simulation time 1656683800 ps
CPU time 261.53 seconds
Started Jun 09 02:46:01 PM PDT 24
Finished Jun 09 02:50:22 PM PDT 24
Peak memory 291808 kb
Host smart-292e837e-1f92-4d5b-a8df-b7344217b743
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059433248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_intr_rd.2059433248
Directory /workspace/4.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.4283487861
Short name T426
Test name
Test status
Simulation time 10741236400 ps
CPU time 158.9 seconds
Started Jun 09 02:46:07 PM PDT 24
Finished Jun 09 02:48:46 PM PDT 24
Peak memory 293440 kb
Host smart-660df164-7942-44ec-b8e0-15daef4b0315
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283487861 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.4283487861
Directory /workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr.768194455
Short name T782
Test name
Test status
Simulation time 5668712300 ps
CPU time 90.68 seconds
Started Jun 09 02:45:59 PM PDT 24
Finished Jun 09 02:47:30 PM PDT 24
Peak memory 265420 kb
Host smart-74784940-c317-4a29-80a5-2be4d50707bf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768194455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 4.flash_ctrl_intr_wr.768194455
Directory /workspace/4.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.2434088594
Short name T29
Test name
Test status
Simulation time 35955422400 ps
CPU time 204.06 seconds
Started Jun 09 02:46:06 PM PDT 24
Finished Jun 09 02:49:30 PM PDT 24
Peak memory 260716 kb
Host smart-6b51a22e-7e2d-4a22-98ba-8f686e06b311
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243
4088594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.2434088594
Directory /workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/4.flash_ctrl_invalid_op.3354610748
Short name T964
Test name
Test status
Simulation time 3704020600 ps
CPU time 74.09 seconds
Started Jun 09 02:45:44 PM PDT 24
Finished Jun 09 02:46:58 PM PDT 24
Peak memory 260796 kb
Host smart-0780f5de-bf23-4dca-a7a4-ec4c022959cc
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354610748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.3354610748
Directory /workspace/4.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_lcmgr_intg.1463180443
Short name T553
Test name
Test status
Simulation time 15339400 ps
CPU time 13.31 seconds
Started Jun 09 02:46:14 PM PDT 24
Finished Jun 09 02:46:27 PM PDT 24
Peak memory 260264 kb
Host smart-b4922da0-20aa-49eb-b4a9-e2881aa3f35f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463180443 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.1463180443
Directory /workspace/4.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/4.flash_ctrl_mid_op_rst.719128130
Short name T134
Test name
Test status
Simulation time 1315884400 ps
CPU time 70.82 seconds
Started Jun 09 02:45:43 PM PDT 24
Finished Jun 09 02:46:54 PM PDT 24
Peak memory 260724 kb
Host smart-4ec92c01-f351-4c18-b5cc-2787fd41c882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719128130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.719128130
Directory /workspace/4.flash_ctrl_mid_op_rst/latest

Test location /workspace/coverage/default/4.flash_ctrl_mp_regions.3570957144
Short name T78
Test name
Test status
Simulation time 12266958000 ps
CPU time 1020.63 seconds
Started Jun 09 02:45:39 PM PDT 24
Finished Jun 09 03:02:40 PM PDT 24
Peak memory 275148 kb
Host smart-77299140-d1f4-47bc-becc-50addd7a30ca
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570957144 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_mp_regions.3570957144
Directory /workspace/4.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/4.flash_ctrl_otp_reset.102365575
Short name T114
Test name
Test status
Simulation time 144765400 ps
CPU time 131.85 seconds
Started Jun 09 02:45:33 PM PDT 24
Finished Jun 09 02:47:45 PM PDT 24
Peak memory 260376 kb
Host smart-a5057932-c6d0-43f0-a341-38bcffe13d88
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102365575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp
_reset.102365575
Directory /workspace/4.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_oversize_error.774631303
Short name T488
Test name
Test status
Simulation time 1182142700 ps
CPU time 158.84 seconds
Started Jun 09 02:46:00 PM PDT 24
Finished Jun 09 02:48:39 PM PDT 24
Peak memory 297500 kb
Host smart-3d6ed165-8fc2-40d2-a288-e56b4ce2d863
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774631303 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.774631303
Directory /workspace/4.flash_ctrl_oversize_error/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.958296532
Short name T834
Test name
Test status
Simulation time 35404500 ps
CPU time 13.96 seconds
Started Jun 09 02:46:15 PM PDT 24
Finished Jun 09 02:46:29 PM PDT 24
Peak memory 265504 kb
Host smart-bd6f7cbd-ae4e-4e5d-b7c5-7ba879b6f8da
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_
check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt
b_random_seed=958296532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.958296532
Directory /workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_arb.3028433399
Short name T842
Test name
Test status
Simulation time 761575800 ps
CPU time 507.93 seconds
Started Jun 09 02:45:33 PM PDT 24
Finished Jun 09 02:54:02 PM PDT 24
Peak memory 263240 kb
Host smart-71639cb7-977e-48e1-8d9e-e8614d81a10e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3028433399 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.3028433399
Directory /workspace/4.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.2343848923
Short name T189
Test name
Test status
Simulation time 38400300 ps
CPU time 13.9 seconds
Started Jun 09 02:46:15 PM PDT 24
Finished Jun 09 02:46:29 PM PDT 24
Peak memory 263064 kb
Host smart-c5eff0ee-6665-4c97-b1eb-d4b7a3e9adbf
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343848923 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.2343848923
Directory /workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspace/coverage/default/4.flash_ctrl_prog_reset.207949013
Short name T465
Test name
Test status
Simulation time 9984946600 ps
CPU time 189.05 seconds
Started Jun 09 02:46:05 PM PDT 24
Finished Jun 09 02:49:14 PM PDT 24
Peak memory 260592 kb
Host smart-43cb4b64-356a-4a9f-9a8d-17cd5e7e2f6e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207949013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_rese
t.207949013
Directory /workspace/4.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/4.flash_ctrl_rand_ops.3573649263
Short name T593
Test name
Test status
Simulation time 63869600 ps
CPU time 304.64 seconds
Started Jun 09 02:45:28 PM PDT 24
Finished Jun 09 02:50:33 PM PDT 24
Peak memory 281916 kb
Host smart-511f24c0-13d5-43b9-95da-8f83d2e5b5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573649263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.3573649263
Directory /workspace/4.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/4.flash_ctrl_rd_buff_evict.4243557445
Short name T986
Test name
Test status
Simulation time 57036400 ps
CPU time 101.69 seconds
Started Jun 09 02:45:33 PM PDT 24
Finished Jun 09 02:47:15 PM PDT 24
Peak memory 263016 kb
Host smart-3ea8672e-c045-4f14-82d9-03e1e34f250a
User root
Command /workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4243557445 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.4243557445
Directory /workspace/4.flash_ctrl_rd_buff_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_re_evict.3663102853
Short name T765
Test name
Test status
Simulation time 422127900 ps
CPU time 36.99 seconds
Started Jun 09 02:46:07 PM PDT 24
Finished Jun 09 02:46:44 PM PDT 24
Peak memory 276084 kb
Host smart-0f4a5c01-db7d-49f1-b0e1-99e92cfd9bfa
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663102853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_re_evict.3663102853
Directory /workspace/4.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.222140571
Short name T1078
Test name
Test status
Simulation time 33142300 ps
CPU time 22.41 seconds
Started Jun 09 02:45:54 PM PDT 24
Finished Jun 09 02:46:17 PM PDT 24
Peak memory 265744 kb
Host smart-33611116-f59a-46f3-9680-b3cf5b2ec4f8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222140571 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.222140571
Directory /workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro.2155433519
Short name T675
Test name
Test status
Simulation time 1992756900 ps
CPU time 136.66 seconds
Started Jun 09 02:45:49 PM PDT 24
Finished Jun 09 02:48:06 PM PDT 24
Peak memory 282232 kb
Host smart-a94d3930-be56-4b57-b0f9-707f947a10e0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155433519 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 4.flash_ctrl_ro.2155433519
Directory /workspace/4.flash_ctrl_ro/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_derr.2761300673
Short name T839
Test name
Test status
Simulation time 703584300 ps
CPU time 164.94 seconds
Started Jun 09 02:45:54 PM PDT 24
Finished Jun 09 02:48:39 PM PDT 24
Peak memory 282416 kb
Host smart-c2c04463-d7ae-416e-aa10-9a00a410ea7c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
2761300673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.2761300673
Directory /workspace/4.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/4.flash_ctrl_ro_serr.3750174344
Short name T271
Test name
Test status
Simulation time 3191182700 ps
CPU time 170.62 seconds
Started Jun 09 02:45:51 PM PDT 24
Finished Jun 09 02:48:41 PM PDT 24
Peak memory 282244 kb
Host smart-734fa6b8-5e1e-43a9-8b7b-a7a1f722f276
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750174344 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.3750174344
Directory /workspace/4.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw.477810606
Short name T180
Test name
Test status
Simulation time 20614391700 ps
CPU time 650.92 seconds
Started Jun 09 02:45:49 PM PDT 24
Finished Jun 09 02:56:41 PM PDT 24
Peak memory 310140 kb
Host smart-fe6f5e13-3ec8-4aa7-84f5-f11feef78f13
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477810606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.flash_ctrl_rw.477810606
Directory /workspace/4.flash_ctrl_rw/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict.2477856690
Short name T567
Test name
Test status
Simulation time 26303900 ps
CPU time 30.38 seconds
Started Jun 09 02:46:03 PM PDT 24
Finished Jun 09 02:46:34 PM PDT 24
Peak memory 275728 kb
Host smart-a273a9db-8fe5-4c40-b034-ec774eedab31
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477856690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla
sh_ctrl_rw_evict.2477856690
Directory /workspace/4.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.1636910234
Short name T718
Test name
Test status
Simulation time 79366400 ps
CPU time 31.48 seconds
Started Jun 09 02:46:06 PM PDT 24
Finished Jun 09 02:46:37 PM PDT 24
Peak memory 267868 kb
Host smart-44563821-09c4-4fe1-80fb-0e8377c40af2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636910234 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.1636910234
Directory /workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/4.flash_ctrl_rw_serr.1518852536
Short name T585
Test name
Test status
Simulation time 3054506400 ps
CPU time 645.14 seconds
Started Jun 09 02:45:55 PM PDT 24
Finished Jun 09 02:56:40 PM PDT 24
Peak memory 313036 kb
Host smart-b52bf669-7995-46c8-9c56-c4b7ae962687
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518852536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_s
err.1518852536
Directory /workspace/4.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/4.flash_ctrl_sec_info_access.1886367107
Short name T836
Test name
Test status
Simulation time 1481838100 ps
CPU time 73.5 seconds
Started Jun 09 02:46:09 PM PDT 24
Finished Jun 09 02:47:22 PM PDT 24
Peak memory 264656 kb
Host smart-75534591-8659-4c0c-beb0-992f6fe9ff5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886367107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.1886367107
Directory /workspace/4.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_address.2384069303
Short name T243
Test name
Test status
Simulation time 6614050300 ps
CPU time 77.39 seconds
Started Jun 09 02:45:54 PM PDT 24
Finished Jun 09 02:47:12 PM PDT 24
Peak memory 273968 kb
Host smart-4c8c78ac-e39f-4b10-a6ee-b40af82c1da1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384069303 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_address.2384069303
Directory /workspace/4.flash_ctrl_serr_address/latest

Test location /workspace/coverage/default/4.flash_ctrl_serr_counter.877429703
Short name T958
Test name
Test status
Simulation time 1602324400 ps
CPU time 63.1 seconds
Started Jun 09 02:45:54 PM PDT 24
Finished Jun 09 02:46:57 PM PDT 24
Peak memory 274028 kb
Host smart-f6368844-ec26-4e5a-8929-84be75166cb5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877429703 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_serr_counter.877429703
Directory /workspace/4.flash_ctrl_serr_counter/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke.3197734326
Short name T651
Test name
Test status
Simulation time 50267000 ps
CPU time 211.6 seconds
Started Jun 09 02:45:24 PM PDT 24
Finished Jun 09 02:48:56 PM PDT 24
Peak memory 281532 kb
Host smart-12fba932-2960-4e12-a1a7-8023e42c5ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197734326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.3197734326
Directory /workspace/4.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/4.flash_ctrl_smoke_hw.2135319615
Short name T659
Test name
Test status
Simulation time 23102900 ps
CPU time 26.4 seconds
Started Jun 09 02:45:28 PM PDT 24
Finished Jun 09 02:45:54 PM PDT 24
Peak memory 259956 kb
Host smart-7566fae5-5fba-4b08-bc83-a49c9befa0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135319615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.2135319615
Directory /workspace/4.flash_ctrl_smoke_hw/latest

Test location /workspace/coverage/default/4.flash_ctrl_stress_all.2713134160
Short name T940
Test name
Test status
Simulation time 186452700 ps
CPU time 253.62 seconds
Started Jun 09 02:46:11 PM PDT 24
Finished Jun 09 02:50:24 PM PDT 24
Peak memory 271500 kb
Host smart-e9d5b459-1080-42d7-bb57-dd1a38540731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713134160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres
s_all.2713134160
Directory /workspace/4.flash_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.flash_ctrl_sw_op.4117902653
Short name T848
Test name
Test status
Simulation time 48976700 ps
CPU time 24 seconds
Started Jun 09 02:45:28 PM PDT 24
Finished Jun 09 02:45:53 PM PDT 24
Peak memory 262364 kb
Host smart-563ea102-f974-43b5-8a99-0f8f20bec770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117902653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.4117902653
Directory /workspace/4.flash_ctrl_sw_op/latest

Test location /workspace/coverage/default/4.flash_ctrl_wo.2351277626
Short name T588
Test name
Test status
Simulation time 2047697300 ps
CPU time 142.19 seconds
Started Jun 09 02:45:43 PM PDT 24
Finished Jun 09 02:48:06 PM PDT 24
Peak memory 259864 kb
Host smart-5cf32648-be8c-4925-a5e0-9e74c3bae1c8
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351277626 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.flash_ctrl_wo.2351277626
Directory /workspace/4.flash_ctrl_wo/latest

Test location /workspace/coverage/default/40.flash_ctrl_alert_test.765337534
Short name T761
Test name
Test status
Simulation time 58628100 ps
CPU time 14.05 seconds
Started Jun 09 02:56:34 PM PDT 24
Finished Jun 09 02:56:49 PM PDT 24
Peak memory 258576 kb
Host smart-26163a8d-8df1-4021-8725-eaf601f1ec63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765337534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.765337534
Directory /workspace/40.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.flash_ctrl_connect.921116101
Short name T460
Test name
Test status
Simulation time 24381000 ps
CPU time 15.56 seconds
Started Jun 09 02:56:41 PM PDT 24
Finished Jun 09 02:56:57 PM PDT 24
Peak memory 275128 kb
Host smart-dc540db6-1ccf-4f25-b1f8-956e0dc77e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921116101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.921116101
Directory /workspace/40.flash_ctrl_connect/latest

Test location /workspace/coverage/default/40.flash_ctrl_disable.1767412438
Short name T1002
Test name
Test status
Simulation time 13017200 ps
CPU time 21.76 seconds
Started Jun 09 02:56:35 PM PDT 24
Finished Jun 09 02:56:57 PM PDT 24
Peak memory 273960 kb
Host smart-54ae14a6-9d90-4a2d-943d-b447e89a1e0a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767412438 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.flash_ctrl_disable.1767412438
Directory /workspace/40.flash_ctrl_disable/latest

Test location /workspace/coverage/default/40.flash_ctrl_hw_sec_otp.3157781512
Short name T878
Test name
Test status
Simulation time 7604241600 ps
CPU time 196.17 seconds
Started Jun 09 02:56:34 PM PDT 24
Finished Jun 09 02:59:51 PM PDT 24
Peak memory 262980 kb
Host smart-25b1ec6e-5dad-4e32-9f84-842b5422b355
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157781512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_
hw_sec_otp.3157781512
Directory /workspace/40.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/40.flash_ctrl_otp_reset.1860943924
Short name T327
Test name
Test status
Simulation time 179333600 ps
CPU time 131.91 seconds
Started Jun 09 02:56:42 PM PDT 24
Finished Jun 09 02:58:54 PM PDT 24
Peak memory 260348 kb
Host smart-b1dd6797-f0aa-4c09-b01f-9c45aee83b0b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860943924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_o
tp_reset.1860943924
Directory /workspace/40.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/40.flash_ctrl_sec_info_access.1576739243
Short name T931
Test name
Test status
Simulation time 1576681200 ps
CPU time 70.05 seconds
Started Jun 09 02:56:41 PM PDT 24
Finished Jun 09 02:57:51 PM PDT 24
Peak memory 265480 kb
Host smart-840977ad-545f-477b-bbdc-12e0f9437178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576739243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.1576739243
Directory /workspace/40.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/40.flash_ctrl_smoke.2899514609
Short name T533
Test name
Test status
Simulation time 17846800 ps
CPU time 51.89 seconds
Started Jun 09 02:56:35 PM PDT 24
Finished Jun 09 02:57:27 PM PDT 24
Peak memory 271472 kb
Host smart-47b28e23-f750-4e92-8733-70cc38d217c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899514609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.2899514609
Directory /workspace/40.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/41.flash_ctrl_alert_test.1522583224
Short name T205
Test name
Test status
Simulation time 194985100 ps
CPU time 13.94 seconds
Started Jun 09 02:56:38 PM PDT 24
Finished Jun 09 02:56:52 PM PDT 24
Peak memory 258596 kb
Host smart-1a95e82a-e69f-49de-ba60-2f2616204a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522583224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.
1522583224
Directory /workspace/41.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.flash_ctrl_connect.3544335205
Short name T544
Test name
Test status
Simulation time 15605000 ps
CPU time 16.21 seconds
Started Jun 09 02:56:38 PM PDT 24
Finished Jun 09 02:56:54 PM PDT 24
Peak memory 284416 kb
Host smart-c31dad47-57c6-4fa4-8ec3-fbeb8468e363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544335205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.3544335205
Directory /workspace/41.flash_ctrl_connect/latest

Test location /workspace/coverage/default/41.flash_ctrl_disable.137668644
Short name T384
Test name
Test status
Simulation time 64540100 ps
CPU time 21.48 seconds
Started Jun 09 02:56:36 PM PDT 24
Finished Jun 09 02:56:58 PM PDT 24
Peak memory 265760 kb
Host smart-a53f4d56-d4df-45ab-88cb-b3fce5aa6caf
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137668644 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.flash_ctrl_disable.137668644
Directory /workspace/41.flash_ctrl_disable/latest

Test location /workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3392628009
Short name T805
Test name
Test status
Simulation time 13425268100 ps
CPU time 117.65 seconds
Started Jun 09 02:56:34 PM PDT 24
Finished Jun 09 02:58:32 PM PDT 24
Peak memory 263124 kb
Host smart-acbf1b31-05dd-4e81-bcc8-180b908466c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392628009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_
hw_sec_otp.3392628009
Directory /workspace/41.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/41.flash_ctrl_otp_reset.1835237380
Short name T68
Test name
Test status
Simulation time 157053400 ps
CPU time 133.94 seconds
Started Jun 09 02:56:45 PM PDT 24
Finished Jun 09 02:58:59 PM PDT 24
Peak memory 260368 kb
Host smart-c65d566d-39d6-4b34-892f-6b3027ab94dd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835237380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_o
tp_reset.1835237380
Directory /workspace/41.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/41.flash_ctrl_sec_info_access.2610930598
Short name T662
Test name
Test status
Simulation time 16557331600 ps
CPU time 83.47 seconds
Started Jun 09 02:56:41 PM PDT 24
Finished Jun 09 02:58:05 PM PDT 24
Peak memory 265108 kb
Host smart-eb7f9d58-e1c5-4506-9633-c709961a14fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610930598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2610930598
Directory /workspace/41.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/41.flash_ctrl_smoke.3056827197
Short name T773
Test name
Test status
Simulation time 42212900 ps
CPU time 214.9 seconds
Started Jun 09 02:56:41 PM PDT 24
Finished Jun 09 03:00:16 PM PDT 24
Peak memory 278016 kb
Host smart-6ee6c2b1-6119-46bc-836a-e3b4decd2c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056827197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.3056827197
Directory /workspace/41.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/42.flash_ctrl_alert_test.1261539186
Short name T631
Test name
Test status
Simulation time 120255300 ps
CPU time 13.83 seconds
Started Jun 09 02:56:44 PM PDT 24
Finished Jun 09 02:56:58 PM PDT 24
Peak memory 258612 kb
Host smart-a7fae3c4-5c32-44ec-af2c-6405244c9d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261539186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.
1261539186
Directory /workspace/42.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.flash_ctrl_connect.3008202560
Short name T780
Test name
Test status
Simulation time 101972400 ps
CPU time 13.44 seconds
Started Jun 09 02:56:44 PM PDT 24
Finished Jun 09 02:56:58 PM PDT 24
Peak memory 275128 kb
Host smart-f7274623-415a-42d5-93f8-0636036a0fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008202560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.3008202560
Directory /workspace/42.flash_ctrl_connect/latest

Test location /workspace/coverage/default/42.flash_ctrl_disable.3674599161
Short name T480
Test name
Test status
Simulation time 16001100 ps
CPU time 21.67 seconds
Started Jun 09 02:56:43 PM PDT 24
Finished Jun 09 02:57:05 PM PDT 24
Peak memory 274020 kb
Host smart-9864cbd1-1134-4c3e-ae63-58b241b55cc1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674599161 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.flash_ctrl_disable.3674599161
Directory /workspace/42.flash_ctrl_disable/latest

Test location /workspace/coverage/default/42.flash_ctrl_hw_sec_otp.1148438894
Short name T894
Test name
Test status
Simulation time 1747448600 ps
CPU time 54.75 seconds
Started Jun 09 02:56:44 PM PDT 24
Finished Jun 09 02:57:39 PM PDT 24
Peak memory 263216 kb
Host smart-0866a983-598a-4c58-b512-08f737a96f4f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148438894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_
hw_sec_otp.1148438894
Directory /workspace/42.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/42.flash_ctrl_otp_reset.3233282418
Short name T974
Test name
Test status
Simulation time 134303700 ps
CPU time 112.92 seconds
Started Jun 09 02:56:43 PM PDT 24
Finished Jun 09 02:58:36 PM PDT 24
Peak memory 265160 kb
Host smart-e67a24f0-882a-4254-a342-6a22db6e1d13
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233282418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o
tp_reset.3233282418
Directory /workspace/42.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/42.flash_ctrl_smoke.2256886387
Short name T973
Test name
Test status
Simulation time 42751500 ps
CPU time 119.39 seconds
Started Jun 09 02:56:45 PM PDT 24
Finished Jun 09 02:58:44 PM PDT 24
Peak memory 277872 kb
Host smart-a81f7c78-f29c-43a0-b3af-457c3b8cabd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256886387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.2256886387
Directory /workspace/42.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/43.flash_ctrl_alert_test.1342277802
Short name T510
Test name
Test status
Simulation time 81768600 ps
CPU time 13.61 seconds
Started Jun 09 02:56:49 PM PDT 24
Finished Jun 09 02:57:03 PM PDT 24
Peak memory 258608 kb
Host smart-bf8451bd-127d-48f8-be53-fb5cd3505a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342277802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.
1342277802
Directory /workspace/43.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.flash_ctrl_connect.568111848
Short name T504
Test name
Test status
Simulation time 14681700 ps
CPU time 13.52 seconds
Started Jun 09 02:56:51 PM PDT 24
Finished Jun 09 02:57:05 PM PDT 24
Peak memory 275140 kb
Host smart-dd7a22d6-15e1-4c6d-809c-d1c04e55b674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568111848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.568111848
Directory /workspace/43.flash_ctrl_connect/latest

Test location /workspace/coverage/default/43.flash_ctrl_disable.2396721952
Short name T383
Test name
Test status
Simulation time 36417800 ps
CPU time 22.57 seconds
Started Jun 09 02:56:50 PM PDT 24
Finished Jun 09 02:57:13 PM PDT 24
Peak memory 265832 kb
Host smart-e343012e-f1ee-4115-9b59-10ca41ecc760
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396721952 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.flash_ctrl_disable.2396721952
Directory /workspace/43.flash_ctrl_disable/latest

Test location /workspace/coverage/default/43.flash_ctrl_hw_sec_otp.2171216625
Short name T728
Test name
Test status
Simulation time 6147082100 ps
CPU time 131.06 seconds
Started Jun 09 02:56:47 PM PDT 24
Finished Jun 09 02:58:59 PM PDT 24
Peak memory 263288 kb
Host smart-1096636c-f3c6-4e48-b89e-5d0ebc31c4c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171216625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_
hw_sec_otp.2171216625
Directory /workspace/43.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/43.flash_ctrl_otp_reset.1759503173
Short name T534
Test name
Test status
Simulation time 76575900 ps
CPU time 109.51 seconds
Started Jun 09 02:56:48 PM PDT 24
Finished Jun 09 02:58:38 PM PDT 24
Peak memory 264448 kb
Host smart-d185bcb0-cdb3-4923-b6d8-7ae2e8d2d949
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759503173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o
tp_reset.1759503173
Directory /workspace/43.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/43.flash_ctrl_sec_info_access.2485884714
Short name T910
Test name
Test status
Simulation time 1293758500 ps
CPU time 62.58 seconds
Started Jun 09 02:56:50 PM PDT 24
Finished Jun 09 02:57:53 PM PDT 24
Peak memory 263304 kb
Host smart-8adc2048-99a9-4bf0-a402-fc5efa336e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485884714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.2485884714
Directory /workspace/43.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/43.flash_ctrl_smoke.1038683588
Short name T597
Test name
Test status
Simulation time 23120700 ps
CPU time 49.48 seconds
Started Jun 09 02:56:44 PM PDT 24
Finished Jun 09 02:57:34 PM PDT 24
Peak memory 271412 kb
Host smart-231c0df8-b62d-472c-9eef-2136f85be9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038683588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.1038683588
Directory /workspace/43.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/44.flash_ctrl_alert_test.982706515
Short name T1
Test name
Test status
Simulation time 54876200 ps
CPU time 14.5 seconds
Started Jun 09 02:56:48 PM PDT 24
Finished Jun 09 02:57:03 PM PDT 24
Peak memory 265504 kb
Host smart-7e5643c1-c524-40ec-8a12-8ecb2c7b4376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982706515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.982706515
Directory /workspace/44.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.flash_ctrl_connect.746087731
Short name T948
Test name
Test status
Simulation time 31506400 ps
CPU time 15.89 seconds
Started Jun 09 02:56:49 PM PDT 24
Finished Jun 09 02:57:05 PM PDT 24
Peak memory 284584 kb
Host smart-7e20f8ed-2ccf-4df7-8004-bf126fff82b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746087731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.746087731
Directory /workspace/44.flash_ctrl_connect/latest

Test location /workspace/coverage/default/44.flash_ctrl_disable.3203176132
Short name T382
Test name
Test status
Simulation time 30776000 ps
CPU time 20.48 seconds
Started Jun 09 02:56:48 PM PDT 24
Finished Jun 09 02:57:09 PM PDT 24
Peak memory 274076 kb
Host smart-09ea40d1-0470-4086-8e38-ddfda5743751
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203176132 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.flash_ctrl_disable.3203176132
Directory /workspace/44.flash_ctrl_disable/latest

Test location /workspace/coverage/default/44.flash_ctrl_hw_sec_otp.2178370261
Short name T989
Test name
Test status
Simulation time 4170505800 ps
CPU time 181.83 seconds
Started Jun 09 02:56:50 PM PDT 24
Finished Jun 09 02:59:52 PM PDT 24
Peak memory 263320 kb
Host smart-4457a8f7-6299-4b82-a2fd-00dad385635d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178370261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_
hw_sec_otp.2178370261
Directory /workspace/44.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/44.flash_ctrl_otp_reset.824893453
Short name T824
Test name
Test status
Simulation time 73404400 ps
CPU time 133.72 seconds
Started Jun 09 02:56:49 PM PDT 24
Finished Jun 09 02:59:03 PM PDT 24
Peak memory 264212 kb
Host smart-934f9386-f62e-4a23-92ad-7642c305fa77
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824893453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ot
p_reset.824893453
Directory /workspace/44.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/44.flash_ctrl_sec_info_access.1114949605
Short name T514
Test name
Test status
Simulation time 347009600 ps
CPU time 53.28 seconds
Started Jun 09 02:56:48 PM PDT 24
Finished Jun 09 02:57:41 PM PDT 24
Peak memory 264516 kb
Host smart-b9f21d38-4294-4a6f-b73d-e10bccf9a51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114949605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.1114949605
Directory /workspace/44.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/44.flash_ctrl_smoke.2811124877
Short name T601
Test name
Test status
Simulation time 23612300 ps
CPU time 123.33 seconds
Started Jun 09 02:56:48 PM PDT 24
Finished Jun 09 02:58:51 PM PDT 24
Peak memory 277948 kb
Host smart-3a25a1e6-0cd2-4b6d-b21b-df60e3e80d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811124877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.2811124877
Directory /workspace/44.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/45.flash_ctrl_alert_test.2341394174
Short name T1091
Test name
Test status
Simulation time 50461700 ps
CPU time 13.83 seconds
Started Jun 09 02:56:56 PM PDT 24
Finished Jun 09 02:57:10 PM PDT 24
Peak memory 258584 kb
Host smart-bdb5b107-6584-4917-8855-436ad58c2539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341394174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.
2341394174
Directory /workspace/45.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.flash_ctrl_connect.2475315766
Short name T957
Test name
Test status
Simulation time 49295600 ps
CPU time 16.01 seconds
Started Jun 09 02:56:54 PM PDT 24
Finished Jun 09 02:57:11 PM PDT 24
Peak memory 275148 kb
Host smart-827ad455-9345-4be9-9be9-e404187d653c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475315766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2475315766
Directory /workspace/45.flash_ctrl_connect/latest

Test location /workspace/coverage/default/45.flash_ctrl_disable.2495555903
Short name T1030
Test name
Test status
Simulation time 11287100 ps
CPU time 22.24 seconds
Started Jun 09 02:56:53 PM PDT 24
Finished Jun 09 02:57:16 PM PDT 24
Peak memory 274084 kb
Host smart-e0bbd598-3581-4da6-a5cc-ec88e5cd52d8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495555903 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.flash_ctrl_disable.2495555903
Directory /workspace/45.flash_ctrl_disable/latest

Test location /workspace/coverage/default/45.flash_ctrl_hw_sec_otp.510781412
Short name T800
Test name
Test status
Simulation time 3955333100 ps
CPU time 145.91 seconds
Started Jun 09 02:56:52 PM PDT 24
Finished Jun 09 02:59:18 PM PDT 24
Peak memory 263144 kb
Host smart-47eab91c-a0de-4917-9872-af729cae3980
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510781412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_h
w_sec_otp.510781412
Directory /workspace/45.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/45.flash_ctrl_smoke.1109521275
Short name T107
Test name
Test status
Simulation time 36167000 ps
CPU time 168.18 seconds
Started Jun 09 02:56:56 PM PDT 24
Finished Jun 09 02:59:44 PM PDT 24
Peak memory 277456 kb
Host smart-3a46942a-8920-4dfb-9bee-6fa7b95fc60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109521275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1109521275
Directory /workspace/45.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/46.flash_ctrl_alert_test.3591731104
Short name T672
Test name
Test status
Simulation time 129036400 ps
CPU time 13.56 seconds
Started Jun 09 02:57:14 PM PDT 24
Finished Jun 09 02:57:28 PM PDT 24
Peak memory 258588 kb
Host smart-e81c1c54-99ab-4172-98c5-97a04ebe5c4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591731104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.
3591731104
Directory /workspace/46.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.flash_ctrl_connect.1294650362
Short name T209
Test name
Test status
Simulation time 55567800 ps
CPU time 16.13 seconds
Started Jun 09 02:57:00 PM PDT 24
Finished Jun 09 02:57:16 PM PDT 24
Peak memory 275244 kb
Host smart-d7ad44ee-2fa5-4a0a-90d6-bab2b44b8167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294650362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.1294650362
Directory /workspace/46.flash_ctrl_connect/latest

Test location /workspace/coverage/default/46.flash_ctrl_disable.2595117457
Short name T139
Test name
Test status
Simulation time 23746200 ps
CPU time 21.63 seconds
Started Jun 09 02:57:01 PM PDT 24
Finished Jun 09 02:57:23 PM PDT 24
Peak memory 274132 kb
Host smart-63f753b2-4d9f-4e45-aec2-d24ecd634eba
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595117457 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.flash_ctrl_disable.2595117457
Directory /workspace/46.flash_ctrl_disable/latest

Test location /workspace/coverage/default/46.flash_ctrl_hw_sec_otp.527271822
Short name T740
Test name
Test status
Simulation time 4279875400 ps
CPU time 132.92 seconds
Started Jun 09 02:57:01 PM PDT 24
Finished Jun 09 02:59:14 PM PDT 24
Peak memory 263384 kb
Host smart-3fb2cc21-3836-49c3-8532-a24471788c20
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527271822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_h
w_sec_otp.527271822
Directory /workspace/46.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/46.flash_ctrl_otp_reset.1545213302
Short name T758
Test name
Test status
Simulation time 83085300 ps
CPU time 132.32 seconds
Started Jun 09 02:56:59 PM PDT 24
Finished Jun 09 02:59:12 PM PDT 24
Peak memory 261300 kb
Host smart-b767537d-c79c-41cd-949b-ece428902fa1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545213302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o
tp_reset.1545213302
Directory /workspace/46.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/46.flash_ctrl_sec_info_access.2007043774
Short name T665
Test name
Test status
Simulation time 1174867900 ps
CPU time 60.3 seconds
Started Jun 09 02:56:59 PM PDT 24
Finished Jun 09 02:58:00 PM PDT 24
Peak memory 263964 kb
Host smart-b08fa868-aad1-42a0-b57c-c93220382b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007043774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.2007043774
Directory /workspace/46.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/46.flash_ctrl_smoke.4293940260
Short name T217
Test name
Test status
Simulation time 130670600 ps
CPU time 100.51 seconds
Started Jun 09 02:56:59 PM PDT 24
Finished Jun 09 02:58:40 PM PDT 24
Peak memory 276048 kb
Host smart-84de8f80-2417-48c9-a8f2-697e50d12831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293940260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.4293940260
Directory /workspace/46.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/47.flash_ctrl_alert_test.3656064298
Short name T493
Test name
Test status
Simulation time 98373800 ps
CPU time 13.69 seconds
Started Jun 09 02:57:03 PM PDT 24
Finished Jun 09 02:57:17 PM PDT 24
Peak memory 258564 kb
Host smart-b9291fd9-9932-4459-8544-b86c606a77ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656064298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.
3656064298
Directory /workspace/47.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.flash_ctrl_connect.2661571852
Short name T110
Test name
Test status
Simulation time 44529700 ps
CPU time 13.33 seconds
Started Jun 09 02:57:04 PM PDT 24
Finished Jun 09 02:57:18 PM PDT 24
Peak memory 284344 kb
Host smart-69fa537b-4c9c-4d64-a0ac-a58ce519048e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661571852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.2661571852
Directory /workspace/47.flash_ctrl_connect/latest

Test location /workspace/coverage/default/47.flash_ctrl_disable.2059499744
Short name T859
Test name
Test status
Simulation time 14899900 ps
CPU time 22 seconds
Started Jun 09 02:57:05 PM PDT 24
Finished Jun 09 02:57:27 PM PDT 24
Peak memory 265260 kb
Host smart-c74b89fa-42e9-4304-ae21-4201a296eb68
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059499744 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.flash_ctrl_disable.2059499744
Directory /workspace/47.flash_ctrl_disable/latest

Test location /workspace/coverage/default/47.flash_ctrl_hw_sec_otp.1980022182
Short name T960
Test name
Test status
Simulation time 5966721700 ps
CPU time 98.53 seconds
Started Jun 09 02:57:06 PM PDT 24
Finished Jun 09 02:58:45 PM PDT 24
Peak memory 263420 kb
Host smart-8d68597e-feb8-47ef-b855-e1ffe0a7a07e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980022182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_
hw_sec_otp.1980022182
Directory /workspace/47.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/47.flash_ctrl_otp_reset.2657454390
Short name T506
Test name
Test status
Simulation time 39632200 ps
CPU time 129.64 seconds
Started Jun 09 02:57:03 PM PDT 24
Finished Jun 09 02:59:13 PM PDT 24
Peak memory 260320 kb
Host smart-78e95585-cc21-4b09-8f1d-eb0c715445fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657454390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o
tp_reset.2657454390
Directory /workspace/47.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/47.flash_ctrl_sec_info_access.3475052608
Short name T730
Test name
Test status
Simulation time 3138964100 ps
CPU time 63.21 seconds
Started Jun 09 02:57:03 PM PDT 24
Finished Jun 09 02:58:07 PM PDT 24
Peak memory 263780 kb
Host smart-e79a51fa-200b-4bba-8879-0f2250f2a11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475052608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.3475052608
Directory /workspace/47.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/47.flash_ctrl_smoke.2099193244
Short name T244
Test name
Test status
Simulation time 21052300 ps
CPU time 72.54 seconds
Started Jun 09 02:57:07 PM PDT 24
Finished Jun 09 02:58:20 PM PDT 24
Peak memory 276864 kb
Host smart-09df9090-307a-4cb1-838b-cc4466f55d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099193244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.2099193244
Directory /workspace/47.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/48.flash_ctrl_alert_test.2494614917
Short name T113
Test name
Test status
Simulation time 156167300 ps
CPU time 13.74 seconds
Started Jun 09 02:57:10 PM PDT 24
Finished Jun 09 02:57:24 PM PDT 24
Peak memory 258504 kb
Host smart-249c941d-4c45-4cc9-bf51-8d8baa2cb1be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494614917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.
2494614917
Directory /workspace/48.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.flash_ctrl_connect.1393098193
Short name T1083
Test name
Test status
Simulation time 24430200 ps
CPU time 15.69 seconds
Started Jun 09 02:57:08 PM PDT 24
Finished Jun 09 02:57:23 PM PDT 24
Peak memory 275132 kb
Host smart-6ce3ac49-69da-496e-bc0f-82da05c8dfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393098193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.1393098193
Directory /workspace/48.flash_ctrl_connect/latest

Test location /workspace/coverage/default/48.flash_ctrl_disable.575966038
Short name T449
Test name
Test status
Simulation time 45950000 ps
CPU time 22.09 seconds
Started Jun 09 02:57:09 PM PDT 24
Finished Jun 09 02:57:32 PM PDT 24
Peak memory 273988 kb
Host smart-1a7986fd-4612-4d67-b1cc-3bd9cc1e7d23
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575966038 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.flash_ctrl_disable.575966038
Directory /workspace/48.flash_ctrl_disable/latest

Test location /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.3436929086
Short name T904
Test name
Test status
Simulation time 3773973900 ps
CPU time 123.39 seconds
Started Jun 09 02:57:10 PM PDT 24
Finished Jun 09 02:59:13 PM PDT 24
Peak memory 263272 kb
Host smart-20fe7e89-e770-426b-8f55-fe3cfc81c613
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436929086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_
hw_sec_otp.3436929086
Directory /workspace/48.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/48.flash_ctrl_otp_reset.564110195
Short name T600
Test name
Test status
Simulation time 70294800 ps
CPU time 132.03 seconds
Started Jun 09 02:57:09 PM PDT 24
Finished Jun 09 02:59:22 PM PDT 24
Peak memory 260336 kb
Host smart-d410ae3f-0161-43a9-a0d4-47348152db76
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564110195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_ot
p_reset.564110195
Directory /workspace/48.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/48.flash_ctrl_sec_info_access.2085221556
Short name T995
Test name
Test status
Simulation time 1595672100 ps
CPU time 63.5 seconds
Started Jun 09 02:57:09 PM PDT 24
Finished Jun 09 02:58:13 PM PDT 24
Peak memory 263832 kb
Host smart-ddfb4e36-25cc-4c43-85ac-a86663635af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085221556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.2085221556
Directory /workspace/48.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/48.flash_ctrl_smoke.842976100
Short name T752
Test name
Test status
Simulation time 35938600 ps
CPU time 121.48 seconds
Started Jun 09 02:57:03 PM PDT 24
Finished Jun 09 02:59:05 PM PDT 24
Peak memory 277464 kb
Host smart-91f41029-0cae-4a7f-9e24-5c6048417032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842976100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.842976100
Directory /workspace/48.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/49.flash_ctrl_alert_test.374878157
Short name T451
Test name
Test status
Simulation time 39595100 ps
CPU time 14.04 seconds
Started Jun 09 02:57:13 PM PDT 24
Finished Jun 09 02:57:28 PM PDT 24
Peak memory 265692 kb
Host smart-7a6de2f7-7e15-4c6f-ba43-a08fd3a364a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374878157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.374878157
Directory /workspace/49.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.flash_ctrl_connect.428746111
Short name T484
Test name
Test status
Simulation time 16115900 ps
CPU time 13.43 seconds
Started Jun 09 02:57:12 PM PDT 24
Finished Jun 09 02:57:26 PM PDT 24
Peak memory 275180 kb
Host smart-3757ae3c-8a2d-4f5d-887f-b95b19fc9651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428746111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.428746111
Directory /workspace/49.flash_ctrl_connect/latest

Test location /workspace/coverage/default/49.flash_ctrl_disable.1852506184
Short name T119
Test name
Test status
Simulation time 21171900 ps
CPU time 22.02 seconds
Started Jun 09 02:57:14 PM PDT 24
Finished Jun 09 02:57:36 PM PDT 24
Peak memory 273956 kb
Host smart-64861f9a-4b8a-445e-8f2e-871c093f212e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852506184 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.flash_ctrl_disable.1852506184
Directory /workspace/49.flash_ctrl_disable/latest

Test location /workspace/coverage/default/49.flash_ctrl_hw_sec_otp.3002725641
Short name T540
Test name
Test status
Simulation time 3847020500 ps
CPU time 133.03 seconds
Started Jun 09 02:57:09 PM PDT 24
Finished Jun 09 02:59:23 PM PDT 24
Peak memory 263428 kb
Host smart-a4dbb2a0-53ad-4aed-9bd8-01e82e5ba48f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002725641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_
hw_sec_otp.3002725641
Directory /workspace/49.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/49.flash_ctrl_otp_reset.1528155112
Short name T1074
Test name
Test status
Simulation time 278168300 ps
CPU time 135.01 seconds
Started Jun 09 02:57:16 PM PDT 24
Finished Jun 09 02:59:32 PM PDT 24
Peak memory 260112 kb
Host smart-f20ab67b-6599-447b-8dfe-8cd050799298
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528155112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o
tp_reset.1528155112
Directory /workspace/49.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/49.flash_ctrl_sec_info_access.2360381052
Short name T421
Test name
Test status
Simulation time 6166724200 ps
CPU time 66.81 seconds
Started Jun 09 02:57:13 PM PDT 24
Finished Jun 09 02:58:20 PM PDT 24
Peak memory 264892 kb
Host smart-09f43b5a-2d48-4cec-afe6-68271515b48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360381052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.2360381052
Directory /workspace/49.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/49.flash_ctrl_smoke.1403480817
Short name T879
Test name
Test status
Simulation time 22270200 ps
CPU time 98.52 seconds
Started Jun 09 02:57:07 PM PDT 24
Finished Jun 09 02:58:46 PM PDT 24
Peak memory 276096 kb
Host smart-dfd7a1b4-da24-40d9-82fe-20f9d1d4921b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403480817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.1403480817
Directory /workspace/49.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_alert_test.506184495
Short name T939
Test name
Test status
Simulation time 159384000 ps
CPU time 14.46 seconds
Started Jun 09 02:47:05 PM PDT 24
Finished Jun 09 02:47:20 PM PDT 24
Peak memory 258616 kb
Host smart-dd334ea7-2399-4a65-8cae-b67d4861c250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506184495 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.506184495
Directory /workspace/5.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.flash_ctrl_connect.47875585
Short name T215
Test name
Test status
Simulation time 14829900 ps
CPU time 16.27 seconds
Started Jun 09 02:47:05 PM PDT 24
Finished Jun 09 02:47:22 PM PDT 24
Peak memory 275140 kb
Host smart-7ae0424a-c336-46f2-a430-417a5a470be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47875585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.47875585
Directory /workspace/5.flash_ctrl_connect/latest

Test location /workspace/coverage/default/5.flash_ctrl_disable.1362706281
Short name T165
Test name
Test status
Simulation time 34125400 ps
CPU time 20.75 seconds
Started Jun 09 02:46:54 PM PDT 24
Finished Jun 09 02:47:15 PM PDT 24
Peak memory 265388 kb
Host smart-ba0a7599-3255-4118-9236-53e894007456
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362706281 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_disable.1362706281
Directory /workspace/5.flash_ctrl_disable/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_mp.3974064595
Short name T755
Test name
Test status
Simulation time 3723854100 ps
CPU time 2367.23 seconds
Started Jun 09 02:46:28 PM PDT 24
Finished Jun 09 03:25:56 PM PDT 24
Peak memory 265036 kb
Host smart-78fa5a0f-c47f-4d12-9dfa-986d066cd9bf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974064595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_err
or_mp.3974064595
Directory /workspace/5.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/5.flash_ctrl_error_prog_win.373994597
Short name T817
Test name
Test status
Simulation time 911989700 ps
CPU time 932.76 seconds
Started Jun 09 02:46:30 PM PDT 24
Finished Jun 09 03:02:03 PM PDT 24
Peak memory 273716 kb
Host smart-bfee9ee6-c385-46a5-bf67-33bfdf8857d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373994597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.373994597
Directory /workspace/5.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/5.flash_ctrl_fetch_code.1471726703
Short name T51
Test name
Test status
Simulation time 737425100 ps
CPU time 24.08 seconds
Started Jun 09 02:46:30 PM PDT 24
Finished Jun 09 02:46:54 PM PDT 24
Peak memory 262752 kb
Host smart-ee863a76-7e1f-495d-b3e6-b180f500d3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471726703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.1471726703
Directory /workspace/5.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.38730915
Short name T561
Test name
Test status
Simulation time 10015734300 ps
CPU time 93.36 seconds
Started Jun 09 02:47:05 PM PDT 24
Finished Jun 09 02:48:39 PM PDT 24
Peak memory 297892 kb
Host smart-06f57e5a-ff97-4e49-b43b-f3bb70d27828
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38730915 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.38730915
Directory /workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.2340531566
Short name T769
Test name
Test status
Simulation time 15647800 ps
CPU time 13.4 seconds
Started Jun 09 02:47:07 PM PDT 24
Finished Jun 09 02:47:21 PM PDT 24
Peak memory 258748 kb
Host smart-d0b06b2d-ea0f-45f1-b265-a8d5c16ba479
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340531566 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.2340531566
Directory /workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_rma_reset.2357263861
Short name T994
Test name
Test status
Simulation time 160182693200 ps
CPU time 977.29 seconds
Started Jun 09 02:46:19 PM PDT 24
Finished Jun 09 03:02:37 PM PDT 24
Peak memory 264676 kb
Host smart-a42b3156-5750-4fae-91e4-64d5f1c21737
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357263861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 5.flash_ctrl_hw_rma_reset.2357263861
Directory /workspace/5.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_hw_sec_otp.475301980
Short name T822
Test name
Test status
Simulation time 10705369300 ps
CPU time 199.3 seconds
Started Jun 09 02:46:20 PM PDT 24
Finished Jun 09 02:49:40 PM PDT 24
Peak memory 263412 kb
Host smart-fd991afd-0c66-4801-84d8-d5c28333f75b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475301980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw
_sec_otp.475301980
Directory /workspace/5.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd.1876230619
Short name T222
Test name
Test status
Simulation time 1288262700 ps
CPU time 144.03 seconds
Started Jun 09 02:46:37 PM PDT 24
Finished Jun 09 02:49:01 PM PDT 24
Peak memory 293372 kb
Host smart-da6eed16-cc46-4c05-8640-50aca700bba2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876230619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_intr_rd.1876230619
Directory /workspace/5.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.1546411117
Short name T639
Test name
Test status
Simulation time 5854494200 ps
CPU time 141.9 seconds
Started Jun 09 02:46:44 PM PDT 24
Finished Jun 09 02:49:06 PM PDT 24
Peak memory 293216 kb
Host smart-97593a77-c91f-4ce4-b8dd-f88f839e663c
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546411117 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.1546411117
Directory /workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr.2473901040
Short name T975
Test name
Test status
Simulation time 35369062600 ps
CPU time 104.08 seconds
Started Jun 09 02:46:38 PM PDT 24
Finished Jun 09 02:48:23 PM PDT 24
Peak memory 260848 kb
Host smart-303f7ff0-837e-4e85-a09f-a8399c8ae38a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473901040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_wr.2473901040
Directory /workspace/5.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.2315359424
Short name T428
Test name
Test status
Simulation time 89317518500 ps
CPU time 226.72 seconds
Started Jun 09 02:46:42 PM PDT 24
Finished Jun 09 02:50:29 PM PDT 24
Peak memory 260092 kb
Host smart-1a73e2df-1d4e-489d-a6b9-e91b53a3aa1d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231
5359424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.2315359424
Directory /workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/5.flash_ctrl_invalid_op.3227264107
Short name T706
Test name
Test status
Simulation time 2125757200 ps
CPU time 67.54 seconds
Started Jun 09 02:46:28 PM PDT 24
Finished Jun 09 02:47:36 PM PDT 24
Peak memory 260792 kb
Host smart-7042b361-7d2d-458a-b741-0309c7f6fd18
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227264107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.3227264107
Directory /workspace/5.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/5.flash_ctrl_lcmgr_intg.3575082906
Short name T1077
Test name
Test status
Simulation time 15783800 ps
CPU time 13.5 seconds
Started Jun 09 02:47:05 PM PDT 24
Finished Jun 09 02:47:19 PM PDT 24
Peak memory 260168 kb
Host smart-983acedc-5a43-477e-aa28-d781f0f6ef7e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575082906 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.3575082906
Directory /workspace/5.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/5.flash_ctrl_mp_regions.3958687708
Short name T897
Test name
Test status
Simulation time 27305265000 ps
CPU time 348.25 seconds
Started Jun 09 02:46:35 PM PDT 24
Finished Jun 09 02:52:23 PM PDT 24
Peak memory 274728 kb
Host smart-94c55518-6990-4a38-9f62-a01ed6d24641
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958687708 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_mp_regions.3958687708
Directory /workspace/5.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/5.flash_ctrl_otp_reset.2990880570
Short name T790
Test name
Test status
Simulation time 248132400 ps
CPU time 133.97 seconds
Started Jun 09 02:46:19 PM PDT 24
Finished Jun 09 02:48:33 PM PDT 24
Peak memory 260544 kb
Host smart-a372aabd-d085-4fc3-8d01-d4c35a00b9de
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990880570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ot
p_reset.2990880570
Directory /workspace/5.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_phy_arb.399889242
Short name T487
Test name
Test status
Simulation time 329351200 ps
CPU time 404.87 seconds
Started Jun 09 02:46:19 PM PDT 24
Finished Jun 09 02:53:04 PM PDT 24
Peak memory 263424 kb
Host smart-1328886b-c602-406e-bd85-874e682da678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399889242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.399889242
Directory /workspace/5.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/5.flash_ctrl_prog_reset.3103012586
Short name T901
Test name
Test status
Simulation time 38076200 ps
CPU time 13.92 seconds
Started Jun 09 02:46:41 PM PDT 24
Finished Jun 09 02:46:55 PM PDT 24
Peak memory 265564 kb
Host smart-71324029-7939-4f71-a13f-0fdecb0f65a4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103012586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_res
et.3103012586
Directory /workspace/5.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/5.flash_ctrl_rand_ops.129925430
Short name T239
Test name
Test status
Simulation time 306332900 ps
CPU time 618.06 seconds
Started Jun 09 02:46:16 PM PDT 24
Finished Jun 09 02:56:34 PM PDT 24
Peak memory 286648 kb
Host smart-2d62e72f-5fbe-4ea6-a351-f5c0b92cb885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129925430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.129925430
Directory /workspace/5.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/5.flash_ctrl_re_evict.3649368764
Short name T519
Test name
Test status
Simulation time 73059700 ps
CPU time 32.5 seconds
Started Jun 09 02:46:53 PM PDT 24
Finished Jun 09 02:47:26 PM PDT 24
Peak memory 275736 kb
Host smart-d582727f-8bcc-44b6-841c-b8961ad044df
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649368764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_re_evict.3649368764
Directory /workspace/5.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro.3080779774
Short name T1051
Test name
Test status
Simulation time 2177292100 ps
CPU time 143 seconds
Started Jun 09 02:46:29 PM PDT 24
Finished Jun 09 02:48:52 PM PDT 24
Peak memory 289568 kb
Host smart-9eb7bc44-7718-47c3-b975-5209743cc5d2
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080779774 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.flash_ctrl_ro.3080779774
Directory /workspace/5.flash_ctrl_ro/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_derr.831228271
Short name T1087
Test name
Test status
Simulation time 10622146000 ps
CPU time 120.21 seconds
Started Jun 09 02:46:38 PM PDT 24
Finished Jun 09 02:48:39 PM PDT 24
Peak memory 282260 kb
Host smart-a89e20ba-ba12-4323-8651-2ee20b20fe81
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
831228271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.831228271
Directory /workspace/5.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_ro_serr.3558032258
Short name T490
Test name
Test status
Simulation time 1361144300 ps
CPU time 163.44 seconds
Started Jun 09 02:46:34 PM PDT 24
Finished Jun 09 02:49:18 PM PDT 24
Peak memory 282320 kb
Host smart-06fba596-6c34-4237-a546-a8e47b03ee1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558032258 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.3558032258
Directory /workspace/5.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_derr.673516720
Short name T184
Test name
Test status
Simulation time 9660466200 ps
CPU time 877.41 seconds
Started Jun 09 02:46:37 PM PDT 24
Finished Jun 09 03:01:15 PM PDT 24
Peak memory 343164 kb
Host smart-3eae13aa-5084-4698-a939-4648484cb7cb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673516720 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 5.flash_ctrl_rw_derr.673516720
Directory /workspace/5.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.3792251570
Short name T406
Test name
Test status
Simulation time 70502900 ps
CPU time 30.95 seconds
Started Jun 09 02:46:46 PM PDT 24
Finished Jun 09 02:47:18 PM PDT 24
Peak memory 276060 kb
Host smart-6387f4d7-90f6-48a9-921b-800cd66a493a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792251570 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.3792251570
Directory /workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/5.flash_ctrl_rw_serr.1752824696
Short name T438
Test name
Test status
Simulation time 7634908500 ps
CPU time 753.99 seconds
Started Jun 09 02:46:38 PM PDT 24
Finished Jun 09 02:59:12 PM PDT 24
Peak memory 321140 kb
Host smart-63b07656-2d3c-4a0f-b0f8-e4d660cbecc5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752824696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_s
err.1752824696
Directory /workspace/5.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/5.flash_ctrl_sec_info_access.2388502505
Short name T781
Test name
Test status
Simulation time 518625700 ps
CPU time 62.45 seconds
Started Jun 09 02:46:58 PM PDT 24
Finished Jun 09 02:48:01 PM PDT 24
Peak memory 265372 kb
Host smart-4dc7d52f-b4f2-4d5d-a72a-ad59052c7875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388502505 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.2388502505
Directory /workspace/5.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/5.flash_ctrl_smoke.100747050
Short name T394
Test name
Test status
Simulation time 81506600 ps
CPU time 49.57 seconds
Started Jun 09 02:46:15 PM PDT 24
Finished Jun 09 02:47:05 PM PDT 24
Peak memory 271548 kb
Host smart-88bd169c-4280-49e3-878d-272d24e39fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100747050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.100747050
Directory /workspace/5.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/5.flash_ctrl_wo.2590927065
Short name T679
Test name
Test status
Simulation time 8698696200 ps
CPU time 211.27 seconds
Started Jun 09 02:46:29 PM PDT 24
Finished Jun 09 02:50:00 PM PDT 24
Peak memory 261316 kb
Host smart-ef4f23d2-632e-423f-9c5f-1aee0a81d3f9
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590927065 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.flash_ctrl_wo.2590927065
Directory /workspace/5.flash_ctrl_wo/latest

Test location /workspace/coverage/default/50.flash_ctrl_connect.2582923928
Short name T578
Test name
Test status
Simulation time 14103800 ps
CPU time 13.21 seconds
Started Jun 09 02:57:14 PM PDT 24
Finished Jun 09 02:57:28 PM PDT 24
Peak memory 275160 kb
Host smart-550df46c-16eb-408f-a16e-f924bdeb3ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582923928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.2582923928
Directory /workspace/50.flash_ctrl_connect/latest

Test location /workspace/coverage/default/50.flash_ctrl_otp_reset.4094056661
Short name T1065
Test name
Test status
Simulation time 654089500 ps
CPU time 134.45 seconds
Started Jun 09 02:57:15 PM PDT 24
Finished Jun 09 02:59:30 PM PDT 24
Peak memory 261384 kb
Host smart-134048be-a2e2-43d7-8f86-005842fbb748
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094056661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o
tp_reset.4094056661
Directory /workspace/50.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/51.flash_ctrl_connect.321707489
Short name T337
Test name
Test status
Simulation time 16061800 ps
CPU time 16.63 seconds
Started Jun 09 02:57:13 PM PDT 24
Finished Jun 09 02:57:30 PM PDT 24
Peak memory 284552 kb
Host smart-8a4ef5f0-ab07-4d74-b5ce-20bee658b15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321707489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.321707489
Directory /workspace/51.flash_ctrl_connect/latest

Test location /workspace/coverage/default/51.flash_ctrl_otp_reset.1975947582
Short name T1067
Test name
Test status
Simulation time 74908100 ps
CPU time 132.23 seconds
Started Jun 09 02:57:15 PM PDT 24
Finished Jun 09 02:59:27 PM PDT 24
Peak memory 261324 kb
Host smart-4b5ce4d2-f8b1-4001-b414-7016596370b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975947582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o
tp_reset.1975947582
Directory /workspace/51.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/52.flash_ctrl_connect.3741674343
Short name T564
Test name
Test status
Simulation time 66943400 ps
CPU time 13.49 seconds
Started Jun 09 02:57:12 PM PDT 24
Finished Jun 09 02:57:26 PM PDT 24
Peak memory 284552 kb
Host smart-4d35a9e5-b5fb-4176-8096-26fdc2c6d44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741674343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.3741674343
Directory /workspace/52.flash_ctrl_connect/latest

Test location /workspace/coverage/default/52.flash_ctrl_otp_reset.3633589201
Short name T66
Test name
Test status
Simulation time 40164100 ps
CPU time 133.95 seconds
Started Jun 09 02:57:12 PM PDT 24
Finished Jun 09 02:59:27 PM PDT 24
Peak memory 265584 kb
Host smart-69e8ef91-f739-4a45-ab31-3a8ac341c46b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633589201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_o
tp_reset.3633589201
Directory /workspace/52.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/53.flash_ctrl_connect.2230306247
Short name T458
Test name
Test status
Simulation time 29545000 ps
CPU time 15.68 seconds
Started Jun 09 02:57:14 PM PDT 24
Finished Jun 09 02:57:30 PM PDT 24
Peak memory 275236 kb
Host smart-3ea643a1-14cc-4e1e-80d7-89273dc35eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230306247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.2230306247
Directory /workspace/53.flash_ctrl_connect/latest

Test location /workspace/coverage/default/53.flash_ctrl_otp_reset.387938270
Short name T529
Test name
Test status
Simulation time 68260400 ps
CPU time 132.36 seconds
Started Jun 09 02:57:12 PM PDT 24
Finished Jun 09 02:59:25 PM PDT 24
Peak memory 260356 kb
Host smart-ac86aaaf-27e2-4b15-82fb-eb259cfd4404
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387938270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_ot
p_reset.387938270
Directory /workspace/53.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/54.flash_ctrl_connect.1305097799
Short name T1009
Test name
Test status
Simulation time 15726600 ps
CPU time 13.4 seconds
Started Jun 09 02:57:18 PM PDT 24
Finished Jun 09 02:57:32 PM PDT 24
Peak memory 275076 kb
Host smart-809ebf4a-17ed-4d2a-8201-7704fa57d5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305097799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1305097799
Directory /workspace/54.flash_ctrl_connect/latest

Test location /workspace/coverage/default/54.flash_ctrl_otp_reset.1194496860
Short name T896
Test name
Test status
Simulation time 122500100 ps
CPU time 133.22 seconds
Started Jun 09 02:57:14 PM PDT 24
Finished Jun 09 02:59:28 PM PDT 24
Peak memory 260400 kb
Host smart-de03585b-fce6-4594-9e9d-7037ddaf902e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194496860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o
tp_reset.1194496860
Directory /workspace/54.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/55.flash_ctrl_connect.1219292104
Short name T843
Test name
Test status
Simulation time 16186200 ps
CPU time 13.38 seconds
Started Jun 09 02:57:19 PM PDT 24
Finished Jun 09 02:57:32 PM PDT 24
Peak memory 275104 kb
Host smart-c5aced71-ea3c-4d61-ac9b-0e191c52979c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219292104 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.1219292104
Directory /workspace/55.flash_ctrl_connect/latest

Test location /workspace/coverage/default/55.flash_ctrl_otp_reset.2670172439
Short name T775
Test name
Test status
Simulation time 39669400 ps
CPU time 132.8 seconds
Started Jun 09 02:57:19 PM PDT 24
Finished Jun 09 02:59:32 PM PDT 24
Peak memory 260356 kb
Host smart-7bdd1d03-10f6-4ead-a8df-a926b8222adc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670172439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o
tp_reset.2670172439
Directory /workspace/55.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/56.flash_ctrl_connect.2857485346
Short name T541
Test name
Test status
Simulation time 23256800 ps
CPU time 15.95 seconds
Started Jun 09 02:57:18 PM PDT 24
Finished Jun 09 02:57:35 PM PDT 24
Peak memory 275104 kb
Host smart-d110b74b-8f5e-4cdf-804a-b137bdca9a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857485346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.2857485346
Directory /workspace/56.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_connect.2536752185
Short name T1060
Test name
Test status
Simulation time 33781600 ps
CPU time 13.31 seconds
Started Jun 09 02:57:18 PM PDT 24
Finished Jun 09 02:57:31 PM PDT 24
Peak memory 275092 kb
Host smart-b7889d02-80c6-42be-8c09-4a80c7dc7fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536752185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.2536752185
Directory /workspace/57.flash_ctrl_connect/latest

Test location /workspace/coverage/default/57.flash_ctrl_otp_reset.1891375795
Short name T238
Test name
Test status
Simulation time 145598100 ps
CPU time 110.66 seconds
Started Jun 09 02:57:19 PM PDT 24
Finished Jun 09 02:59:10 PM PDT 24
Peak memory 265168 kb
Host smart-38fb1840-dafc-4176-a611-6dbd6f42a2e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891375795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o
tp_reset.1891375795
Directory /workspace/57.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/58.flash_ctrl_connect.1399251847
Short name T471
Test name
Test status
Simulation time 52001900 ps
CPU time 13.53 seconds
Started Jun 09 02:57:23 PM PDT 24
Finished Jun 09 02:57:37 PM PDT 24
Peak memory 275220 kb
Host smart-ce68e219-ea02-4215-babf-55684ae2af68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399251847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.1399251847
Directory /workspace/58.flash_ctrl_connect/latest

Test location /workspace/coverage/default/58.flash_ctrl_otp_reset.1389888946
Short name T131
Test name
Test status
Simulation time 72393800 ps
CPU time 132.86 seconds
Started Jun 09 02:57:25 PM PDT 24
Finished Jun 09 02:59:38 PM PDT 24
Peak memory 260168 kb
Host smart-022eefcd-d069-4baf-86c0-fb48a7005fe3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389888946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_o
tp_reset.1389888946
Directory /workspace/58.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/59.flash_ctrl_connect.2028748012
Short name T1092
Test name
Test status
Simulation time 22064200 ps
CPU time 13.44 seconds
Started Jun 09 02:57:23 PM PDT 24
Finished Jun 09 02:57:37 PM PDT 24
Peak memory 275108 kb
Host smart-1b623ee3-5ee9-43fe-a844-b226ed2b0333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028748012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.2028748012
Directory /workspace/59.flash_ctrl_connect/latest

Test location /workspace/coverage/default/59.flash_ctrl_otp_reset.3689594424
Short name T579
Test name
Test status
Simulation time 144680500 ps
CPU time 135.2 seconds
Started Jun 09 02:57:22 PM PDT 24
Finished Jun 09 02:59:38 PM PDT 24
Peak memory 260412 kb
Host smart-e4d5159e-67c2-436c-a6aa-449b2c836191
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689594424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o
tp_reset.3689594424
Directory /workspace/59.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_alert_test.3528760523
Short name T429
Test name
Test status
Simulation time 129371600 ps
CPU time 14.24 seconds
Started Jun 09 02:47:31 PM PDT 24
Finished Jun 09 02:47:45 PM PDT 24
Peak memory 258692 kb
Host smart-5ae406e5-1981-44ec-a243-a11c6e1800eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528760523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3
528760523
Directory /workspace/6.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.flash_ctrl_connect.3087775041
Short name T479
Test name
Test status
Simulation time 15705200 ps
CPU time 15.61 seconds
Started Jun 09 02:47:27 PM PDT 24
Finished Jun 09 02:47:43 PM PDT 24
Peak memory 275104 kb
Host smart-7dd91335-07b8-4a1f-8458-7e76ca860aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087775041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.3087775041
Directory /workspace/6.flash_ctrl_connect/latest

Test location /workspace/coverage/default/6.flash_ctrl_disable.2227274926
Short name T1086
Test name
Test status
Simulation time 37427300 ps
CPU time 21.37 seconds
Started Jun 09 02:47:23 PM PDT 24
Finished Jun 09 02:47:45 PM PDT 24
Peak memory 265384 kb
Host smart-64772517-cdb2-4374-a490-e3b60eaeab33
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227274926 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_disable.2227274926
Directory /workspace/6.flash_ctrl_disable/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_mp.2497404818
Short name T589
Test name
Test status
Simulation time 18769394400 ps
CPU time 2301.18 seconds
Started Jun 09 02:47:07 PM PDT 24
Finished Jun 09 03:25:28 PM PDT 24
Peak memory 264388 kb
Host smart-4a4737c6-13a6-485b-9f25-e47a6ef7fe75
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497404818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_err
or_mp.2497404818
Directory /workspace/6.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/6.flash_ctrl_error_prog_win.319254655
Short name T962
Test name
Test status
Simulation time 2634136800 ps
CPU time 854.48 seconds
Started Jun 09 02:47:07 PM PDT 24
Finished Jun 09 03:01:22 PM PDT 24
Peak memory 270792 kb
Host smart-bd7ad350-2c16-48eb-b2ea-68b86446ee83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319254655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.319254655
Directory /workspace/6.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/6.flash_ctrl_fetch_code.3473771518
Short name T62
Test name
Test status
Simulation time 121533000 ps
CPU time 21.05 seconds
Started Jun 09 02:47:06 PM PDT 24
Finished Jun 09 02:47:27 PM PDT 24
Peak memory 263920 kb
Host smart-21c3a751-021c-41bb-9992-c064655ac1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473771518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.3473771518
Directory /workspace/6.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3417828342
Short name T241
Test name
Test status
Simulation time 10031822600 ps
CPU time 50.83 seconds
Started Jun 09 02:47:29 PM PDT 24
Finished Jun 09 02:48:20 PM PDT 24
Peak memory 269040 kb
Host smart-7eaed052-6eaa-4b28-805a-e90f4d30e7a9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417828342 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.3417828342
Directory /workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.3140913727
Short name T830
Test name
Test status
Simulation time 43903400 ps
CPU time 13.57 seconds
Started Jun 09 02:47:30 PM PDT 24
Finished Jun 09 02:47:44 PM PDT 24
Peak memory 265360 kb
Host smart-8e3d14fe-42ee-470c-b692-c67124d09b6a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140913727 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.3140913727
Directory /workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.620623378
Short name T847
Test name
Test status
Simulation time 170200943000 ps
CPU time 932.01 seconds
Started Jun 09 02:47:06 PM PDT 24
Finished Jun 09 03:02:39 PM PDT 24
Peak memory 261172 kb
Host smart-0dc8fd3e-6db8-464a-b692-2254451c1ac7
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620623378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 6.flash_ctrl_hw_rma_reset.620623378
Directory /workspace/6.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd.1336236259
Short name T741
Test name
Test status
Simulation time 7755542700 ps
CPU time 265.31 seconds
Started Jun 09 02:47:16 PM PDT 24
Finished Jun 09 02:51:42 PM PDT 24
Peak memory 292632 kb
Host smart-e78d34a6-cc6f-4473-b162-4bcbf90ac1fb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336236259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_intr_rd.1336236259
Directory /workspace/6.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3790700322
Short name T351
Test name
Test status
Simulation time 24699478000 ps
CPU time 222.01 seconds
Started Jun 09 02:47:16 PM PDT 24
Finished Jun 09 02:50:59 PM PDT 24
Peak memory 291380 kb
Host smart-c8d79744-dbb9-4464-9ad8-f489465dc4ff
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790700322 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.3790700322
Directory /workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr.2426252521
Short name T470
Test name
Test status
Simulation time 1422585600 ps
CPU time 60.91 seconds
Started Jun 09 02:47:15 PM PDT 24
Finished Jun 09 02:48:16 PM PDT 24
Peak memory 265508 kb
Host smart-bc78f1db-cce7-4ef5-bcb1-8ccc0de2b5e6
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426252521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_wr.2426252521
Directory /workspace/6.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.1988686805
Short name T955
Test name
Test status
Simulation time 23265458400 ps
CPU time 203.26 seconds
Started Jun 09 02:47:16 PM PDT 24
Finished Jun 09 02:50:40 PM PDT 24
Peak memory 265280 kb
Host smart-edeb2d73-b8a8-4071-b0f6-bb78826fbc8d
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198
8686805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.1988686805
Directory /workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/6.flash_ctrl_invalid_op.192135690
Short name T720
Test name
Test status
Simulation time 2694542200 ps
CPU time 61.06 seconds
Started Jun 09 02:47:06 PM PDT 24
Finished Jun 09 02:48:08 PM PDT 24
Peak memory 263448 kb
Host smart-4720e445-1da5-43b6-8eb6-046d27856434
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192135690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.192135690
Directory /workspace/6.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/6.flash_ctrl_lcmgr_intg.841933680
Short name T687
Test name
Test status
Simulation time 19402300 ps
CPU time 13.46 seconds
Started Jun 09 02:47:23 PM PDT 24
Finished Jun 09 02:47:37 PM PDT 24
Peak memory 260256 kb
Host smart-7f29db9b-4e4c-470d-ac0b-7e95f2f83865
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841933680 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.841933680
Directory /workspace/6.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/6.flash_ctrl_mp_regions.1551012539
Short name T104
Test name
Test status
Simulation time 16460274100 ps
CPU time 510.83 seconds
Started Jun 09 02:47:08 PM PDT 24
Finished Jun 09 02:55:39 PM PDT 24
Peak memory 275420 kb
Host smart-442230ec-2519-4d11-a54c-58128de7d7c9
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551012539 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_mp_regions.1551012539
Directory /workspace/6.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/6.flash_ctrl_otp_reset.521843597
Short name T163
Test name
Test status
Simulation time 85990000 ps
CPU time 131.44 seconds
Started Jun 09 02:47:06 PM PDT 24
Finished Jun 09 02:49:18 PM PDT 24
Peak memory 260628 kb
Host smart-b6f2841b-b97f-473c-9e86-fa02e2b73830
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521843597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp
_reset.521843597
Directory /workspace/6.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_phy_arb.288282937
Short name T48
Test name
Test status
Simulation time 723388900 ps
CPU time 218.93 seconds
Started Jun 09 02:47:06 PM PDT 24
Finished Jun 09 02:50:45 PM PDT 24
Peak memory 263444 kb
Host smart-bb7c8680-8089-4ff2-a0c4-d29ac1fae6d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=288282937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.288282937
Directory /workspace/6.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/6.flash_ctrl_prog_reset.3347242349
Short name T865
Test name
Test status
Simulation time 71266600 ps
CPU time 13.5 seconds
Started Jun 09 02:47:14 PM PDT 24
Finished Jun 09 02:47:28 PM PDT 24
Peak memory 265492 kb
Host smart-3428e809-4e09-49e2-9e55-0d8f81db35c2
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347242349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_res
et.3347242349
Directory /workspace/6.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/6.flash_ctrl_rand_ops.1135307295
Short name T76
Test name
Test status
Simulation time 1619778400 ps
CPU time 609.02 seconds
Started Jun 09 02:47:08 PM PDT 24
Finished Jun 09 02:57:17 PM PDT 24
Peak memory 285148 kb
Host smart-f8325c60-f612-4d30-9e49-322634b3b1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135307295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.1135307295
Directory /workspace/6.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/6.flash_ctrl_re_evict.952274172
Short name T26
Test name
Test status
Simulation time 191071900 ps
CPU time 34.93 seconds
Started Jun 09 02:47:27 PM PDT 24
Finished Jun 09 02:48:03 PM PDT 24
Peak memory 270720 kb
Host smart-90f88706-643b-40c6-9411-1df2737ce936
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952274172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_re_evict.952274172
Directory /workspace/6.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro.36918823
Short name T186
Test name
Test status
Simulation time 1832689700 ps
CPU time 137.43 seconds
Started Jun 09 02:47:07 PM PDT 24
Finished Jun 09 02:49:24 PM PDT 24
Peak memory 289512 kb
Host smart-7787be59-1353-4990-a632-680c07120e68
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36918823 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.flash_ctrl_ro.36918823
Directory /workspace/6.flash_ctrl_ro/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_derr.821333909
Short name T199
Test name
Test status
Simulation time 1366468500 ps
CPU time 144.99 seconds
Started Jun 09 02:47:09 PM PDT 24
Finished Jun 09 02:49:34 PM PDT 24
Peak memory 282264 kb
Host smart-e23b28d7-e1bf-4d53-ade1-2a61bae2b8d9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
821333909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.821333909
Directory /workspace/6.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_ro_serr.1263148062
Short name T932
Test name
Test status
Simulation time 1206685900 ps
CPU time 145.46 seconds
Started Jun 09 02:47:09 PM PDT 24
Finished Jun 09 02:49:35 PM PDT 24
Peak memory 282296 kb
Host smart-5fc89c8d-ab67-4461-8544-203a5d8ce72c
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263148062 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.1263148062
Directory /workspace/6.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw.1997297976
Short name T802
Test name
Test status
Simulation time 7478394900 ps
CPU time 665.2 seconds
Started Jun 09 02:47:13 PM PDT 24
Finished Jun 09 02:58:18 PM PDT 24
Peak memory 314732 kb
Host smart-7eddcd1c-026a-4b75-8739-87cef978d770
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997297976 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.flash_ctrl_rw.1997297976
Directory /workspace/6.flash_ctrl_rw/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_derr.3543940713
Short name T640
Test name
Test status
Simulation time 14449563100 ps
CPU time 599.35 seconds
Started Jun 09 02:47:14 PM PDT 24
Finished Jun 09 02:57:14 PM PDT 24
Peak memory 334388 kb
Host smart-347c9f66-69f0-4b4e-8de2-137a148c6178
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543940713 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_rw_derr.3543940713
Directory /workspace/6.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.3754885985
Short name T766
Test name
Test status
Simulation time 32093400 ps
CPU time 31.29 seconds
Started Jun 09 02:47:21 PM PDT 24
Finished Jun 09 02:47:52 PM PDT 24
Peak memory 273928 kb
Host smart-a72b559a-4ff9-4288-83f2-77c8641f90cd
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754885985 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.3754885985
Directory /workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/6.flash_ctrl_rw_serr.1194136252
Short name T539
Test name
Test status
Simulation time 7175412200 ps
CPU time 715.02 seconds
Started Jun 09 02:47:12 PM PDT 24
Finished Jun 09 02:59:08 PM PDT 24
Peak memory 312964 kb
Host smart-afebc2b1-4317-4044-9c33-7bcd4ec7b28a
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194136252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_s
err.1194136252
Directory /workspace/6.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/6.flash_ctrl_sec_info_access.1792813111
Short name T624
Test name
Test status
Simulation time 769853600 ps
CPU time 54.1 seconds
Started Jun 09 02:47:27 PM PDT 24
Finished Jun 09 02:48:21 PM PDT 24
Peak memory 263308 kb
Host smart-ebc43edb-28df-4bc1-a362-6863d8730cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792813111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.1792813111
Directory /workspace/6.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/6.flash_ctrl_smoke.1275965393
Short name T400
Test name
Test status
Simulation time 91073800 ps
CPU time 96.1 seconds
Started Jun 09 02:47:07 PM PDT 24
Finished Jun 09 02:48:43 PM PDT 24
Peak memory 276184 kb
Host smart-5834cd6b-3f3a-4907-b658-3aac9675f691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275965393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.1275965393
Directory /workspace/6.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/6.flash_ctrl_wo.1327602992
Short name T656
Test name
Test status
Simulation time 8635275300 ps
CPU time 197.94 seconds
Started Jun 09 02:47:06 PM PDT 24
Finished Jun 09 02:50:24 PM PDT 24
Peak memory 265676 kb
Host smart-8b8ca598-4eb1-4c74-87b0-8f8e97c67ab0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327602992 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.flash_ctrl_wo.1327602992
Directory /workspace/6.flash_ctrl_wo/latest

Test location /workspace/coverage/default/60.flash_ctrl_connect.1681050416
Short name T653
Test name
Test status
Simulation time 51162300 ps
CPU time 15.6 seconds
Started Jun 09 02:57:23 PM PDT 24
Finished Jun 09 02:57:38 PM PDT 24
Peak memory 275228 kb
Host smart-0b42ed93-e168-428e-8ead-697d31e9a1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681050416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.1681050416
Directory /workspace/60.flash_ctrl_connect/latest

Test location /workspace/coverage/default/60.flash_ctrl_otp_reset.923953388
Short name T445
Test name
Test status
Simulation time 138758700 ps
CPU time 137.34 seconds
Started Jun 09 02:57:25 PM PDT 24
Finished Jun 09 02:59:42 PM PDT 24
Peak memory 260300 kb
Host smart-37fc1d50-8b94-40ac-815f-f2d1ed2a186f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923953388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_ot
p_reset.923953388
Directory /workspace/60.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/61.flash_ctrl_connect.4001810103
Short name T984
Test name
Test status
Simulation time 210673900 ps
CPU time 13.42 seconds
Started Jun 09 02:57:24 PM PDT 24
Finished Jun 09 02:57:38 PM PDT 24
Peak memory 274956 kb
Host smart-9f5f503f-48ae-4fb2-b46a-26435456ca63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001810103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.4001810103
Directory /workspace/61.flash_ctrl_connect/latest

Test location /workspace/coverage/default/61.flash_ctrl_otp_reset.1802431387
Short name T946
Test name
Test status
Simulation time 614388100 ps
CPU time 129.62 seconds
Started Jun 09 02:57:21 PM PDT 24
Finished Jun 09 02:59:31 PM PDT 24
Peak memory 265056 kb
Host smart-c43d16d8-68eb-44b4-b4b6-c31140613d7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802431387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o
tp_reset.1802431387
Directory /workspace/61.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/62.flash_ctrl_connect.3849738486
Short name T549
Test name
Test status
Simulation time 42230600 ps
CPU time 13.66 seconds
Started Jun 09 02:57:27 PM PDT 24
Finished Jun 09 02:57:41 PM PDT 24
Peak memory 275000 kb
Host smart-d90025dc-78e4-45ef-8d14-c9a7917c5333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849738486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3849738486
Directory /workspace/62.flash_ctrl_connect/latest

Test location /workspace/coverage/default/62.flash_ctrl_otp_reset.1760388539
Short name T538
Test name
Test status
Simulation time 67872400 ps
CPU time 108.63 seconds
Started Jun 09 02:57:28 PM PDT 24
Finished Jun 09 02:59:17 PM PDT 24
Peak memory 261392 kb
Host smart-c880e5b6-632c-4185-88b6-bb99e6c9872c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760388539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o
tp_reset.1760388539
Directory /workspace/62.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/63.flash_ctrl_connect.3419997494
Short name T560
Test name
Test status
Simulation time 47955600 ps
CPU time 15.7 seconds
Started Jun 09 02:57:29 PM PDT 24
Finished Jun 09 02:57:45 PM PDT 24
Peak memory 275124 kb
Host smart-64c0230e-62c1-4650-8910-dad51c5ce6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419997494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.3419997494
Directory /workspace/63.flash_ctrl_connect/latest

Test location /workspace/coverage/default/63.flash_ctrl_otp_reset.1387806406
Short name T146
Test name
Test status
Simulation time 51918400 ps
CPU time 109.51 seconds
Started Jun 09 02:57:30 PM PDT 24
Finished Jun 09 02:59:20 PM PDT 24
Peak memory 260100 kb
Host smart-ba304fbe-a91d-427e-97c0-49cf67689eb1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387806406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_o
tp_reset.1387806406
Directory /workspace/63.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/64.flash_ctrl_connect.1043504429
Short name T832
Test name
Test status
Simulation time 234971400 ps
CPU time 15.8 seconds
Started Jun 09 02:57:28 PM PDT 24
Finished Jun 09 02:57:44 PM PDT 24
Peak memory 275220 kb
Host smart-146f85fb-0b38-4a7c-8b19-9ac52b1b3086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043504429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.1043504429
Directory /workspace/64.flash_ctrl_connect/latest

Test location /workspace/coverage/default/64.flash_ctrl_otp_reset.3883706881
Short name T602
Test name
Test status
Simulation time 124347300 ps
CPU time 137.39 seconds
Started Jun 09 02:57:28 PM PDT 24
Finished Jun 09 02:59:46 PM PDT 24
Peak memory 260216 kb
Host smart-8dd6b575-ae49-48c3-8d02-16338f63e7bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883706881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o
tp_reset.3883706881
Directory /workspace/64.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/65.flash_ctrl_connect.2002037718
Short name T587
Test name
Test status
Simulation time 27567400 ps
CPU time 15.97 seconds
Started Jun 09 02:57:28 PM PDT 24
Finished Jun 09 02:57:44 PM PDT 24
Peak memory 275248 kb
Host smart-9e2b8065-c2e6-4ef5-8dce-cc759be206f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002037718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2002037718
Directory /workspace/65.flash_ctrl_connect/latest

Test location /workspace/coverage/default/65.flash_ctrl_otp_reset.3903644362
Short name T980
Test name
Test status
Simulation time 37409300 ps
CPU time 132.57 seconds
Started Jun 09 02:57:29 PM PDT 24
Finished Jun 09 02:59:42 PM PDT 24
Peak memory 260444 kb
Host smart-5ae8ada8-cdc8-47d1-88ca-cc31d4016b0f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903644362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_o
tp_reset.3903644362
Directory /workspace/65.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/66.flash_ctrl_connect.1269064296
Short name T454
Test name
Test status
Simulation time 91312900 ps
CPU time 15.71 seconds
Started Jun 09 02:57:31 PM PDT 24
Finished Jun 09 02:57:47 PM PDT 24
Peak memory 275236 kb
Host smart-63155923-0fbe-4f76-9212-a89f46a830cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269064296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.1269064296
Directory /workspace/66.flash_ctrl_connect/latest

Test location /workspace/coverage/default/66.flash_ctrl_otp_reset.3563523697
Short name T835
Test name
Test status
Simulation time 72669900 ps
CPU time 134.05 seconds
Started Jun 09 02:57:28 PM PDT 24
Finished Jun 09 02:59:43 PM PDT 24
Peak memory 260680 kb
Host smart-961ad512-a03e-420e-af3b-5549a623fe49
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563523697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o
tp_reset.3563523697
Directory /workspace/66.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/67.flash_ctrl_connect.243186674
Short name T502
Test name
Test status
Simulation time 14689900 ps
CPU time 15.96 seconds
Started Jun 09 02:57:33 PM PDT 24
Finished Jun 09 02:57:49 PM PDT 24
Peak memory 275112 kb
Host smart-ac25d702-3bbb-4e3d-88f5-4c213e877b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243186674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.243186674
Directory /workspace/67.flash_ctrl_connect/latest

Test location /workspace/coverage/default/67.flash_ctrl_otp_reset.4203996575
Short name T784
Test name
Test status
Simulation time 40599800 ps
CPU time 132.05 seconds
Started Jun 09 02:57:34 PM PDT 24
Finished Jun 09 02:59:47 PM PDT 24
Peak memory 260588 kb
Host smart-04639494-fc75-4677-b63e-1f88a8026180
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203996575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o
tp_reset.4203996575
Directory /workspace/67.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/68.flash_ctrl_connect.788975386
Short name T1088
Test name
Test status
Simulation time 42572100 ps
CPU time 15.83 seconds
Started Jun 09 02:57:32 PM PDT 24
Finished Jun 09 02:57:48 PM PDT 24
Peak memory 275152 kb
Host smart-c6fc72c3-e0ef-4a33-86b7-354f0fcde917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788975386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.788975386
Directory /workspace/68.flash_ctrl_connect/latest

Test location /workspace/coverage/default/68.flash_ctrl_otp_reset.3785365462
Short name T649
Test name
Test status
Simulation time 68765400 ps
CPU time 109.95 seconds
Started Jun 09 02:57:33 PM PDT 24
Finished Jun 09 02:59:24 PM PDT 24
Peak memory 261276 kb
Host smart-c391e5c0-98f0-4b95-a192-eb9e414533a2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785365462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o
tp_reset.3785365462
Directory /workspace/68.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/69.flash_ctrl_connect.1175639864
Short name T710
Test name
Test status
Simulation time 27294200 ps
CPU time 15.88 seconds
Started Jun 09 02:57:33 PM PDT 24
Finished Jun 09 02:57:49 PM PDT 24
Peak memory 275184 kb
Host smart-90af1cf8-d13b-48f6-a5ec-4eb282578e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175639864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.1175639864
Directory /workspace/69.flash_ctrl_connect/latest

Test location /workspace/coverage/default/69.flash_ctrl_otp_reset.3815765982
Short name T457
Test name
Test status
Simulation time 66509700 ps
CPU time 110.28 seconds
Started Jun 09 02:57:33 PM PDT 24
Finished Jun 09 02:59:24 PM PDT 24
Peak memory 260172 kb
Host smart-4472ddff-57ac-4aeb-84e5-91957645ff34
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815765982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o
tp_reset.3815765982
Directory /workspace/69.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_alert_test.3599915892
Short name T513
Test name
Test status
Simulation time 70219100 ps
CPU time 13.6 seconds
Started Jun 09 02:47:59 PM PDT 24
Finished Jun 09 02:48:13 PM PDT 24
Peak memory 258688 kb
Host smart-818e0b4a-8c67-43a2-90e4-6155e197e3d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599915892 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.3
599915892
Directory /workspace/7.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.flash_ctrl_disable.3962694164
Short name T381
Test name
Test status
Simulation time 10486900 ps
CPU time 21.57 seconds
Started Jun 09 02:47:55 PM PDT 24
Finished Jun 09 02:48:16 PM PDT 24
Peak memory 274028 kb
Host smart-71546281-5160-4dcd-8ab9-9c341d463c66
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962694164 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_disable.3962694164
Directory /workspace/7.flash_ctrl_disable/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_mp.3610523227
Short name T993
Test name
Test status
Simulation time 4031155400 ps
CPU time 2277.68 seconds
Started Jun 09 02:47:39 PM PDT 24
Finished Jun 09 03:25:37 PM PDT 24
Peak memory 265576 kb
Host smart-46eed5df-ea12-45b9-8e90-a23bacffb6eb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610523227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_err
or_mp.3610523227
Directory /workspace/7.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/7.flash_ctrl_error_prog_win.3123362336
Short name T982
Test name
Test status
Simulation time 2249030800 ps
CPU time 820.27 seconds
Started Jun 09 02:47:40 PM PDT 24
Finished Jun 09 03:01:21 PM PDT 24
Peak memory 273660 kb
Host smart-51cc0d9d-5f09-43fc-9cfb-28c351549948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123362336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.3123362336
Directory /workspace/7.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.49882555
Short name T596
Test name
Test status
Simulation time 10076740900 ps
CPU time 41.11 seconds
Started Jun 09 02:47:59 PM PDT 24
Finished Jun 09 02:48:41 PM PDT 24
Peak memory 266996 kb
Host smart-380d55db-038d-4441-a381-ff50e4031ebb
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49882555 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.49882555
Directory /workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.573017994
Short name T467
Test name
Test status
Simulation time 26072300 ps
CPU time 13.43 seconds
Started Jun 09 02:47:57 PM PDT 24
Finished Jun 09 02:48:11 PM PDT 24
Peak memory 258824 kb
Host smart-bb8b2d4e-d876-4ef1-9a16-251065c01c01
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573017994 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.573017994
Directory /workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_rma_reset.3530822852
Short name T2
Test name
Test status
Simulation time 130155114600 ps
CPU time 881.41 seconds
Started Jun 09 02:47:35 PM PDT 24
Finished Jun 09 03:02:17 PM PDT 24
Peak memory 264412 kb
Host smart-68df46ed-3ae2-44be-bfa3-3ac2573dea6e
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530822852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.flash_ctrl_hw_rma_reset.3530822852
Directory /workspace/7.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_hw_sec_otp.3775194221
Short name T472
Test name
Test status
Simulation time 3132807600 ps
CPU time 44.65 seconds
Started Jun 09 02:47:35 PM PDT 24
Finished Jun 09 02:48:20 PM PDT 24
Peak memory 260880 kb
Host smart-7904be0f-e213-46cf-8228-a739fd086c23
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775194221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h
w_sec_otp.3775194221
Directory /workspace/7.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd.2268190703
Short name T592
Test name
Test status
Simulation time 1692276600 ps
CPU time 164.98 seconds
Started Jun 09 02:47:51 PM PDT 24
Finished Jun 09 02:50:36 PM PDT 24
Peak memory 294556 kb
Host smart-f6294977-114c-49de-8896-06307cfc0702
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268190703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_intr_rd.2268190703
Directory /workspace/7.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3025518879
Short name T462
Test name
Test status
Simulation time 8048943400 ps
CPU time 157.52 seconds
Started Jun 09 02:47:52 PM PDT 24
Finished Jun 09 02:50:30 PM PDT 24
Peak memory 293436 kb
Host smart-164cc3dc-4403-4fcb-9029-81bfdc78f883
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025518879 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.3025518879
Directory /workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr.3098344962
Short name T1059
Test name
Test status
Simulation time 26735611900 ps
CPU time 86.54 seconds
Started Jun 09 02:47:51 PM PDT 24
Finished Jun 09 02:49:18 PM PDT 24
Peak memory 260888 kb
Host smart-6ce13261-0c14-4837-90f1-727e15be0496
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098344962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.flash_ctrl_intr_wr.3098344962
Directory /workspace/7.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.250667984
Short name T633
Test name
Test status
Simulation time 73828810800 ps
CPU time 197.37 seconds
Started Jun 09 02:47:51 PM PDT 24
Finished Jun 09 02:51:09 PM PDT 24
Peak memory 260056 kb
Host smart-0c871a36-9419-41d5-8d81-64a2d507d7ae
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250
667984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.250667984
Directory /workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/7.flash_ctrl_invalid_op.2740289459
Short name T543
Test name
Test status
Simulation time 1955094700 ps
CPU time 92.97 seconds
Started Jun 09 02:47:39 PM PDT 24
Finished Jun 09 02:49:13 PM PDT 24
Peak memory 260764 kb
Host smart-b2581ddd-1b1a-4f07-b12e-d91868a25cf2
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740289459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2740289459
Directory /workspace/7.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/7.flash_ctrl_lcmgr_intg.642020502
Short name T334
Test name
Test status
Simulation time 47416200 ps
CPU time 13.26 seconds
Started Jun 09 02:47:54 PM PDT 24
Finished Jun 09 02:48:08 PM PDT 24
Peak memory 260280 kb
Host smart-c5b2974e-239e-42b7-aec8-06debcbfaeb9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642020502 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.642020502
Directory /workspace/7.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/7.flash_ctrl_mp_regions.193227281
Short name T434
Test name
Test status
Simulation time 5707630100 ps
CPU time 181.98 seconds
Started Jun 09 02:47:35 PM PDT 24
Finished Jun 09 02:50:37 PM PDT 24
Peak memory 265476 kb
Host smart-1e1d63e5-a2df-4a20-9010-a452ad8b353d
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193227281 -assert nopostproc +UVM_TESTNAME=flash_ct
rl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo
g /dev/null -cm_name 7.flash_ctrl_mp_regions.193227281
Directory /workspace/7.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/7.flash_ctrl_otp_reset.2089673425
Short name T153
Test name
Test status
Simulation time 143363300 ps
CPU time 109.38 seconds
Started Jun 09 02:47:34 PM PDT 24
Finished Jun 09 02:49:24 PM PDT 24
Peak memory 260420 kb
Host smart-1b13e33a-e6e4-45de-a15d-909fd256728f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089673425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot
p_reset.2089673425
Directory /workspace/7.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_phy_arb.2201244960
Short name T871
Test name
Test status
Simulation time 3098184000 ps
CPU time 501.08 seconds
Started Jun 09 02:47:30 PM PDT 24
Finished Jun 09 02:55:51 PM PDT 24
Peak memory 263516 kb
Host smart-ac37a769-b084-4277-9104-1b508c912647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201244960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.2201244960
Directory /workspace/7.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/7.flash_ctrl_prog_reset.121263874
Short name T1049
Test name
Test status
Simulation time 11392265300 ps
CPU time 201.04 seconds
Started Jun 09 02:47:49 PM PDT 24
Finished Jun 09 02:51:11 PM PDT 24
Peak memory 260596 kb
Host smart-7336c468-e71b-41b3-b599-a44d0b479689
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121263874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_rese
t.121263874
Directory /workspace/7.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/7.flash_ctrl_rand_ops.4027861662
Short name T1012
Test name
Test status
Simulation time 95053400 ps
CPU time 323.33 seconds
Started Jun 09 02:47:32 PM PDT 24
Finished Jun 09 02:52:55 PM PDT 24
Peak memory 282640 kb
Host smart-ae835a03-49f6-4634-a9ea-27a5c0e4baf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027861662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.4027861662
Directory /workspace/7.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/7.flash_ctrl_re_evict.4194536296
Short name T1037
Test name
Test status
Simulation time 355854600 ps
CPU time 37.07 seconds
Started Jun 09 02:47:51 PM PDT 24
Finished Jun 09 02:48:29 PM PDT 24
Peak memory 276108 kb
Host smart-b4847ab3-3518-453e-b747-8ce9807ed7e9
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194536296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_re_evict.4194536296
Directory /workspace/7.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro.2815642876
Short name T198
Test name
Test status
Simulation time 495796900 ps
CPU time 143.86 seconds
Started Jun 09 02:47:41 PM PDT 24
Finished Jun 09 02:50:05 PM PDT 24
Peak memory 282072 kb
Host smart-c0da42ec-cf4c-4f6a-a3da-e87e81f541d0
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815642876 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_ro.2815642876
Directory /workspace/7.flash_ctrl_ro/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_derr.3843772335
Short name T785
Test name
Test status
Simulation time 2142616000 ps
CPU time 152.21 seconds
Started Jun 09 02:47:46 PM PDT 24
Finished Jun 09 02:50:19 PM PDT 24
Peak memory 282292 kb
Host smart-6c5335bd-dc54-4033-b100-767f623c2e40
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
3843772335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.3843772335
Directory /workspace/7.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_ro_serr.290687099
Short name T976
Test name
Test status
Simulation time 2516011800 ps
CPU time 139.08 seconds
Started Jun 09 02:47:45 PM PDT 24
Finished Jun 09 02:50:04 PM PDT 24
Peak memory 282260 kb
Host smart-c13b15b9-d18c-4b05-81fe-5a561c2d73a7
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290687099 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.290687099
Directory /workspace/7.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw.1423702627
Short name T626
Test name
Test status
Simulation time 6710456400 ps
CPU time 616.9 seconds
Started Jun 09 02:47:40 PM PDT 24
Finished Jun 09 02:57:58 PM PDT 24
Peak memory 314984 kb
Host smart-a47087d6-e447-4275-8f81-217e000891bb
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423702627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.flash_ctrl_rw.1423702627
Directory /workspace/7.flash_ctrl_rw/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_derr.2069673076
Short name T996
Test name
Test status
Simulation time 7984926400 ps
CPU time 723.99 seconds
Started Jun 09 02:47:48 PM PDT 24
Finished Jun 09 02:59:53 PM PDT 24
Peak memory 334924 kb
Host smart-b32e5fbd-f6d7-4a5b-9be9-4d0802a7c547
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069673076 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 7.flash_ctrl_rw_derr.2069673076
Directory /workspace/7.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict.2655003347
Short name T482
Test name
Test status
Simulation time 28309200 ps
CPU time 29.5 seconds
Started Jun 09 02:47:51 PM PDT 24
Finished Jun 09 02:48:21 PM PDT 24
Peak memory 275704 kb
Host smart-5e29d689-0066-4cdc-a008-7a93c03f3156
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655003347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_rw_evict.2655003347
Directory /workspace/7.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.2594937893
Short name T94
Test name
Test status
Simulation time 32743000 ps
CPU time 28.32 seconds
Started Jun 09 02:47:54 PM PDT 24
Finished Jun 09 02:48:23 PM PDT 24
Peak memory 274048 kb
Host smart-e1a51451-8a46-4a6a-ab4e-35b67ecfb9e5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594937893 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.2594937893
Directory /workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/7.flash_ctrl_sec_info_access.3367067347
Short name T508
Test name
Test status
Simulation time 2094457400 ps
CPU time 78.05 seconds
Started Jun 09 02:47:54 PM PDT 24
Finished Jun 09 02:49:12 PM PDT 24
Peak memory 259836 kb
Host smart-32e04915-2bb6-454b-8fc1-a6d2ef9e72d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367067347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.3367067347
Directory /workspace/7.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/7.flash_ctrl_wo.809286631
Short name T890
Test name
Test status
Simulation time 4423689500 ps
CPU time 206.34 seconds
Started Jun 09 02:47:40 PM PDT 24
Finished Jun 09 02:51:07 PM PDT 24
Peak memory 260272 kb
Host smart-e4337445-d245-431b-8d9f-08c8722f3ea4
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809286631 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.flash_ctrl_wo.809286631
Directory /workspace/7.flash_ctrl_wo/latest

Test location /workspace/coverage/default/70.flash_ctrl_connect.546699847
Short name T737
Test name
Test status
Simulation time 30055400 ps
CPU time 15.9 seconds
Started Jun 09 02:57:32 PM PDT 24
Finished Jun 09 02:57:48 PM PDT 24
Peak memory 275072 kb
Host smart-bba19259-5a3c-4694-8e81-bb716a6a6720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546699847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.546699847
Directory /workspace/70.flash_ctrl_connect/latest

Test location /workspace/coverage/default/70.flash_ctrl_otp_reset.2212431054
Short name T810
Test name
Test status
Simulation time 81478400 ps
CPU time 132.27 seconds
Started Jun 09 02:57:31 PM PDT 24
Finished Jun 09 02:59:44 PM PDT 24
Peak memory 264372 kb
Host smart-dfd216ce-672a-47b2-8a36-121e2b948220
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212431054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_o
tp_reset.2212431054
Directory /workspace/70.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/71.flash_ctrl_connect.3796852190
Short name T1082
Test name
Test status
Simulation time 16781200 ps
CPU time 15.87 seconds
Started Jun 09 02:57:37 PM PDT 24
Finished Jun 09 02:57:53 PM PDT 24
Peak memory 275072 kb
Host smart-50441a6a-80fb-49ee-81bb-aae11957de4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796852190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.3796852190
Directory /workspace/71.flash_ctrl_connect/latest

Test location /workspace/coverage/default/71.flash_ctrl_otp_reset.919010352
Short name T154
Test name
Test status
Simulation time 36953500 ps
CPU time 132.07 seconds
Started Jun 09 02:57:35 PM PDT 24
Finished Jun 09 02:59:47 PM PDT 24
Peak memory 260172 kb
Host smart-e4b10849-3366-4593-9d33-0e58f811d641
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919010352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_ot
p_reset.919010352
Directory /workspace/71.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/72.flash_ctrl_connect.2982068324
Short name T1004
Test name
Test status
Simulation time 14719200 ps
CPU time 15.58 seconds
Started Jun 09 02:57:38 PM PDT 24
Finished Jun 09 02:57:54 PM PDT 24
Peak memory 275256 kb
Host smart-36bea22b-becb-4318-a6f0-3b6d9e5770b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982068324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.2982068324
Directory /workspace/72.flash_ctrl_connect/latest

Test location /workspace/coverage/default/72.flash_ctrl_otp_reset.2450910835
Short name T943
Test name
Test status
Simulation time 38878600 ps
CPU time 135.1 seconds
Started Jun 09 02:57:37 PM PDT 24
Finished Jun 09 02:59:53 PM PDT 24
Peak memory 260460 kb
Host smart-d200f755-506c-4b51-8131-074ba522f55a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450910835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o
tp_reset.2450910835
Directory /workspace/72.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/73.flash_ctrl_connect.1126241775
Short name T795
Test name
Test status
Simulation time 25414500 ps
CPU time 15.96 seconds
Started Jun 09 02:57:38 PM PDT 24
Finished Jun 09 02:57:55 PM PDT 24
Peak memory 275096 kb
Host smart-34867f6d-bb10-494a-9d7d-9f042cab6f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126241775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.1126241775
Directory /workspace/73.flash_ctrl_connect/latest

Test location /workspace/coverage/default/73.flash_ctrl_otp_reset.3924021592
Short name T211
Test name
Test status
Simulation time 199265500 ps
CPU time 131.48 seconds
Started Jun 09 02:57:37 PM PDT 24
Finished Jun 09 02:59:49 PM PDT 24
Peak memory 260332 kb
Host smart-94a03bec-1fad-434c-8b22-30acb3dbb131
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924021592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o
tp_reset.3924021592
Directory /workspace/73.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/74.flash_ctrl_connect.1742199166
Short name T799
Test name
Test status
Simulation time 24272300 ps
CPU time 16.01 seconds
Started Jun 09 02:57:37 PM PDT 24
Finished Jun 09 02:57:53 PM PDT 24
Peak memory 275320 kb
Host smart-c76ea4a5-bf10-48ed-aecd-f6bbd52cc8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742199166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.1742199166
Directory /workspace/74.flash_ctrl_connect/latest

Test location /workspace/coverage/default/74.flash_ctrl_otp_reset.2608935598
Short name T565
Test name
Test status
Simulation time 35560000 ps
CPU time 109.7 seconds
Started Jun 09 02:57:37 PM PDT 24
Finished Jun 09 02:59:27 PM PDT 24
Peak memory 260280 kb
Host smart-90283434-387b-4bf8-89c2-7a33fba179a4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608935598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_o
tp_reset.2608935598
Directory /workspace/74.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/75.flash_ctrl_connect.648922481
Short name T809
Test name
Test status
Simulation time 54758800 ps
CPU time 13.27 seconds
Started Jun 09 02:57:37 PM PDT 24
Finished Jun 09 02:57:51 PM PDT 24
Peak memory 275100 kb
Host smart-6df13f63-c3e8-47c0-9b61-b7ccdc029c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648922481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.648922481
Directory /workspace/75.flash_ctrl_connect/latest

Test location /workspace/coverage/default/75.flash_ctrl_otp_reset.4203766158
Short name T788
Test name
Test status
Simulation time 39786400 ps
CPU time 108.91 seconds
Started Jun 09 02:57:34 PM PDT 24
Finished Jun 09 02:59:23 PM PDT 24
Peak memory 260376 kb
Host smart-b95fbc49-4753-409c-91ce-8e3c9403e654
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203766158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_o
tp_reset.4203766158
Directory /workspace/75.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/76.flash_ctrl_connect.1885340529
Short name T450
Test name
Test status
Simulation time 13426900 ps
CPU time 13.24 seconds
Started Jun 09 02:57:41 PM PDT 24
Finished Jun 09 02:57:55 PM PDT 24
Peak memory 284568 kb
Host smart-40cad48b-63a8-4057-a6e6-81a00c6c420b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885340529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.1885340529
Directory /workspace/76.flash_ctrl_connect/latest

Test location /workspace/coverage/default/76.flash_ctrl_otp_reset.2038963140
Short name T128
Test name
Test status
Simulation time 42427500 ps
CPU time 131.29 seconds
Started Jun 09 02:57:43 PM PDT 24
Finished Jun 09 02:59:55 PM PDT 24
Peak memory 260244 kb
Host smart-02e6f096-5afc-42fb-a93e-6f3d9f850e38
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038963140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o
tp_reset.2038963140
Directory /workspace/76.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/77.flash_ctrl_connect.2137684926
Short name T391
Test name
Test status
Simulation time 54484000 ps
CPU time 15.87 seconds
Started Jun 09 02:57:47 PM PDT 24
Finished Jun 09 02:58:03 PM PDT 24
Peak memory 275052 kb
Host smart-7b338bc3-2f10-4593-aadf-082f14464c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137684926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.2137684926
Directory /workspace/77.flash_ctrl_connect/latest

Test location /workspace/coverage/default/77.flash_ctrl_otp_reset.1868299172
Short name T881
Test name
Test status
Simulation time 136848100 ps
CPU time 134.8 seconds
Started Jun 09 02:57:40 PM PDT 24
Finished Jun 09 02:59:55 PM PDT 24
Peak memory 260324 kb
Host smart-e0c00538-68dd-4df8-8414-b1edf28b9f21
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868299172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o
tp_reset.1868299172
Directory /workspace/77.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/78.flash_ctrl_connect.1238928730
Short name T1058
Test name
Test status
Simulation time 40907800 ps
CPU time 13.55 seconds
Started Jun 09 02:57:44 PM PDT 24
Finished Jun 09 02:57:58 PM PDT 24
Peak memory 275124 kb
Host smart-ba83a331-97d1-4248-a857-b00cfa9110f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238928730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.1238928730
Directory /workspace/78.flash_ctrl_connect/latest

Test location /workspace/coverage/default/78.flash_ctrl_otp_reset.3845486424
Short name T1044
Test name
Test status
Simulation time 43684000 ps
CPU time 131.77 seconds
Started Jun 09 02:57:42 PM PDT 24
Finished Jun 09 02:59:54 PM PDT 24
Peak memory 260200 kb
Host smart-b1377fc2-c23a-40cd-a7b6-0f6f0ed78767
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845486424 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_o
tp_reset.3845486424
Directory /workspace/78.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/79.flash_ctrl_connect.533734585
Short name T1039
Test name
Test status
Simulation time 28566300 ps
CPU time 13.39 seconds
Started Jun 09 02:57:43 PM PDT 24
Finished Jun 09 02:57:56 PM PDT 24
Peak memory 275112 kb
Host smart-daa84fa0-1abb-4a0e-a30b-25ce34b26036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533734585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.533734585
Directory /workspace/79.flash_ctrl_connect/latest

Test location /workspace/coverage/default/79.flash_ctrl_otp_reset.441266133
Short name T156
Test name
Test status
Simulation time 201671300 ps
CPU time 110 seconds
Started Jun 09 02:57:47 PM PDT 24
Finished Jun 09 02:59:37 PM PDT 24
Peak memory 264356 kb
Host smart-96467862-4185-4791-aea5-e45e00b247e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441266133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_ot
p_reset.441266133
Directory /workspace/79.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_alert_test.421379317
Short name T399
Test name
Test status
Simulation time 30666400 ps
CPU time 13.63 seconds
Started Jun 09 02:48:42 PM PDT 24
Finished Jun 09 02:48:56 PM PDT 24
Peak memory 265512 kb
Host smart-137c548d-6b94-46ce-9b77-0117d599e440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421379317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.421379317
Directory /workspace/8.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.flash_ctrl_connect.12325642
Short name T845
Test name
Test status
Simulation time 31749000 ps
CPU time 15.81 seconds
Started Jun 09 02:48:36 PM PDT 24
Finished Jun 09 02:48:52 PM PDT 24
Peak memory 284448 kb
Host smart-3470df2e-6147-4364-9316-5fd3b2a1f045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12325642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.12325642
Directory /workspace/8.flash_ctrl_connect/latest

Test location /workspace/coverage/default/8.flash_ctrl_disable.1841154433
Short name T58
Test name
Test status
Simulation time 64698300 ps
CPU time 22.11 seconds
Started Jun 09 02:48:37 PM PDT 24
Finished Jun 09 02:49:00 PM PDT 24
Peak memory 265844 kb
Host smart-0a81ef02-6dd0-4b56-b374-9cf077adcbbc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841154433 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_disable.1841154433
Directory /workspace/8.flash_ctrl_disable/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_mp.2055965134
Short name T1015
Test name
Test status
Simulation time 10263755200 ps
CPU time 2448.87 seconds
Started Jun 09 02:48:13 PM PDT 24
Finished Jun 09 03:29:03 PM PDT 24
Peak memory 263108 kb
Host smart-9bf8e0df-dd03-404d-91a7-9c726d30aa1e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055965134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_err
or_mp.2055965134
Directory /workspace/8.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/8.flash_ctrl_error_prog_win.3090304024
Short name T690
Test name
Test status
Simulation time 5443319100 ps
CPU time 905.87 seconds
Started Jun 09 02:48:08 PM PDT 24
Finished Jun 09 03:03:14 PM PDT 24
Peak memory 273600 kb
Host smart-9b4187be-b70a-40c3-9b3c-1e3201f8cda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090304024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3090304024
Directory /workspace/8.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/8.flash_ctrl_fetch_code.489094317
Short name T50
Test name
Test status
Simulation time 2839165400 ps
CPU time 28.7 seconds
Started Jun 09 02:48:10 PM PDT 24
Finished Jun 09 02:48:39 PM PDT 24
Peak memory 262760 kb
Host smart-5923ce09-a58a-4069-b272-1ef849d05ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489094317 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.489094317
Directory /workspace/8.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.441918147
Short name T1093
Test name
Test status
Simulation time 10035513100 ps
CPU time 100.38 seconds
Started Jun 09 02:48:40 PM PDT 24
Finished Jun 09 02:50:20 PM PDT 24
Peak memory 266764 kb
Host smart-36fb0d29-330f-4138-a8cc-10347e687ab1
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441918147 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.441918147
Directory /workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.3240621458
Short name T132
Test name
Test status
Simulation time 19709300 ps
CPU time 13.6 seconds
Started Jun 09 02:48:41 PM PDT 24
Finished Jun 09 02:48:55 PM PDT 24
Peak memory 258608 kb
Host smart-efaa78bf-b517-4e5a-b029-ee3d358a8b72
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240621458 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.3240621458
Directory /workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_rma_reset.2547651597
Short name T930
Test name
Test status
Simulation time 40125475400 ps
CPU time 806.59 seconds
Started Jun 09 02:48:04 PM PDT 24
Finished Jun 09 03:01:31 PM PDT 24
Peak memory 264620 kb
Host smart-5a8fc314-5e23-466c-a53a-167fecf92e75
User root
Command /workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547651597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te
st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_hw_rma_reset.2547651597
Directory /workspace/8.flash_ctrl_hw_rma_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.1909582670
Short name T866
Test name
Test status
Simulation time 3167868100 ps
CPU time 108.46 seconds
Started Jun 09 02:48:03 PM PDT 24
Finished Jun 09 02:49:52 PM PDT 24
Peak memory 263380 kb
Host smart-72256282-8f34-4f75-864d-8e510c6d547a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909582670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h
w_sec_otp.1909582670
Directory /workspace/8.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd.2464926737
Short name T992
Test name
Test status
Simulation time 3065467600 ps
CPU time 147.06 seconds
Started Jun 09 02:48:21 PM PDT 24
Finished Jun 09 02:50:48 PM PDT 24
Peak memory 294468 kb
Host smart-0e323b97-d595-4fdb-972a-00489b3b24d5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464926737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_intr_rd.2464926737
Directory /workspace/8.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3542733744
Short name T991
Test name
Test status
Simulation time 8678510200 ps
CPU time 274.83 seconds
Started Jun 09 02:48:27 PM PDT 24
Finished Jun 09 02:53:02 PM PDT 24
Peak memory 285228 kb
Host smart-ee3b1e29-2004-4696-9586-6dbdf1f075fd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542733744 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.3542733744
Directory /workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr.867536041
Short name T31
Test name
Test status
Simulation time 9735144400 ps
CPU time 79.92 seconds
Started Jun 09 02:48:23 PM PDT 24
Finished Jun 09 02:49:43 PM PDT 24
Peak memory 265420 kb
Host smart-82a5ca6b-31df-4ca7-8f71-487df4beb19b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867536041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +
UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 8.flash_ctrl_intr_wr.867536041
Directory /workspace/8.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.3388847507
Short name T30
Test name
Test status
Simulation time 20041375300 ps
CPU time 175.4 seconds
Started Jun 09 02:48:26 PM PDT 24
Finished Jun 09 02:51:22 PM PDT 24
Peak memory 265704 kb
Host smart-bcd3dcfa-7f17-4126-b426-f846ff3d34dd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338
8847507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.3388847507
Directory /workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/8.flash_ctrl_invalid_op.2457064533
Short name T435
Test name
Test status
Simulation time 6575740700 ps
CPU time 74.13 seconds
Started Jun 09 02:48:13 PM PDT 24
Finished Jun 09 02:49:27 PM PDT 24
Peak memory 260744 kb
Host smart-2a794c62-54d2-4a7e-ae0b-6e800ff2cd2c
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457064533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.2457064533
Directory /workspace/8.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/8.flash_ctrl_lcmgr_intg.576451182
Short name T988
Test name
Test status
Simulation time 79299400 ps
CPU time 13.59 seconds
Started Jun 09 02:48:39 PM PDT 24
Finished Jun 09 02:48:52 PM PDT 24
Peak memory 260232 kb
Host smart-53384a5e-832e-4468-91e8-c7382da2fcf4
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576451182 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.576451182
Directory /workspace/8.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/8.flash_ctrl_mp_regions.3589234682
Short name T80
Test name
Test status
Simulation time 24425795100 ps
CPU time 1125.35 seconds
Started Jun 09 02:48:03 PM PDT 24
Finished Jun 09 03:06:49 PM PDT 24
Peak memory 275060 kb
Host smart-b58f4dbf-8a75-430b-8671-8bef05be9b50
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589234682 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_mp_regions.3589234682
Directory /workspace/8.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/8.flash_ctrl_otp_reset.696923217
Short name T1041
Test name
Test status
Simulation time 72325900 ps
CPU time 133.22 seconds
Started Jun 09 02:48:02 PM PDT 24
Finished Jun 09 02:50:16 PM PDT 24
Peak memory 260432 kb
Host smart-607d562c-2fcf-4b40-8642-22b118e04f33
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696923217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr
l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp
_reset.696923217
Directory /workspace/8.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_phy_arb.4013964132
Short name T636
Test name
Test status
Simulation time 167386500 ps
CPU time 440.89 seconds
Started Jun 09 02:48:04 PM PDT 24
Finished Jun 09 02:55:25 PM PDT 24
Peak memory 263332 kb
Host smart-6dccb14e-48c0-42fc-b7d2-71c6b20f969f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013964132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.4013964132
Directory /workspace/8.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/8.flash_ctrl_prog_reset.650228151
Short name T667
Test name
Test status
Simulation time 24749800 ps
CPU time 13.88 seconds
Started Jun 09 02:48:29 PM PDT 24
Finished Jun 09 02:48:44 PM PDT 24
Peak memory 258952 kb
Host smart-7e2d3164-325f-4d32-9249-6a4c32882841
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650228151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_
reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_rese
t.650228151
Directory /workspace/8.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/8.flash_ctrl_rand_ops.4145327958
Short name T117
Test name
Test status
Simulation time 153048200 ps
CPU time 429.57 seconds
Started Jun 09 02:47:59 PM PDT 24
Finished Jun 09 02:55:09 PM PDT 24
Peak memory 278272 kb
Host smart-e40e0702-8335-4b58-9739-60b781a3847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145327958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.4145327958
Directory /workspace/8.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro.371297967
Short name T530
Test name
Test status
Simulation time 2216118800 ps
CPU time 138.65 seconds
Started Jun 09 02:48:12 PM PDT 24
Finished Jun 09 02:50:31 PM PDT 24
Peak memory 281444 kb
Host smart-9ef3cf7c-f1fe-496f-867d-d70697cbe726
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371297967 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.flash_ctrl_ro.371297967
Directory /workspace/8.flash_ctrl_ro/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_derr.767661723
Short name T40
Test name
Test status
Simulation time 2268452100 ps
CPU time 166.54 seconds
Started Jun 09 02:48:23 PM PDT 24
Finished Jun 09 02:51:10 PM PDT 24
Peak memory 284344 kb
Host smart-9f6b786f-c8a1-42bb-9b94-3b7de331a054
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
767661723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.767661723
Directory /workspace/8.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/8.flash_ctrl_ro_serr.1465561953
Short name T658
Test name
Test status
Simulation time 690947200 ps
CPU time 162.31 seconds
Started Jun 09 02:48:16 PM PDT 24
Finished Jun 09 02:50:59 PM PDT 24
Peak memory 282444 kb
Host smart-744bc95d-412f-4179-b4e5-3052dd080fdc
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465561953 -assert nopostproc +UVM_
TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.1465561953
Directory /workspace/8.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw.145230287
Short name T536
Test name
Test status
Simulation time 50416337500 ps
CPU time 548.29 seconds
Started Jun 09 02:48:16 PM PDT 24
Finished Jun 09 02:57:25 PM PDT 24
Peak memory 309748 kb
Host smart-4b4170f3-687d-4108-ad85-e9315d13d384
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145230287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.flash_ctrl_rw.145230287
Directory /workspace/8.flash_ctrl_rw/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_evict.322471224
Short name T606
Test name
Test status
Simulation time 50179700 ps
CPU time 31.54 seconds
Started Jun 09 02:48:26 PM PDT 24
Finished Jun 09 02:48:58 PM PDT 24
Peak memory 270228 kb
Host smart-0b79e777-a1bd-4dfd-99fe-bc535fb22c53
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322471224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_rw_evict.322471224
Directory /workspace/8.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/8.flash_ctrl_rw_serr.2951531958
Short name T777
Test name
Test status
Simulation time 4922062000 ps
CPU time 785.21 seconds
Started Jun 09 02:48:18 PM PDT 24
Finished Jun 09 03:01:24 PM PDT 24
Peak memory 321084 kb
Host smart-4a47508d-2dab-4970-80ac-ebb1d102a561
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951531958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_s
err.2951531958
Directory /workspace/8.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/8.flash_ctrl_sec_info_access.4163290286
Short name T683
Test name
Test status
Simulation time 455599100 ps
CPU time 58.24 seconds
Started Jun 09 02:48:35 PM PDT 24
Finished Jun 09 02:49:34 PM PDT 24
Peak memory 263708 kb
Host smart-62bb04b5-a695-4cc8-b79a-ec9eed713d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163290286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.4163290286
Directory /workspace/8.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/8.flash_ctrl_smoke.3804606241
Short name T44
Test name
Test status
Simulation time 45986700 ps
CPU time 216.31 seconds
Started Jun 09 02:48:00 PM PDT 24
Finished Jun 09 02:51:37 PM PDT 24
Peak memory 280184 kb
Host smart-76da593e-a2f8-4ed9-9f5c-9b16d7ccf600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804606241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.3804606241
Directory /workspace/8.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/8.flash_ctrl_wo.1538677672
Short name T770
Test name
Test status
Simulation time 18327485700 ps
CPU time 155.63 seconds
Started Jun 09 02:48:14 PM PDT 24
Finished Jun 09 02:50:50 PM PDT 24
Peak memory 259716 kb
Host smart-482930cd-69fa-48be-b68f-ae4b6be626e7
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538677672 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.flash_ctrl_wo.1538677672
Directory /workspace/8.flash_ctrl_wo/latest

Test location /workspace/coverage/default/9.flash_ctrl_alert_test.3111425442
Short name T814
Test name
Test status
Simulation time 236710600 ps
CPU time 13.74 seconds
Started Jun 09 02:49:19 PM PDT 24
Finished Jun 09 02:49:33 PM PDT 24
Peak memory 265536 kb
Host smart-72b17365-d6bb-48ee-8266-3ed40061b2a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111425442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.3
111425442
Directory /workspace/9.flash_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.flash_ctrl_connect.772056394
Short name T733
Test name
Test status
Simulation time 18223600 ps
CPU time 15.91 seconds
Started Jun 09 02:49:17 PM PDT 24
Finished Jun 09 02:49:33 PM PDT 24
Peak memory 275012 kb
Host smart-10644224-40d7-4081-a026-b0273780fed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772056394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.772056394
Directory /workspace/9.flash_ctrl_connect/latest

Test location /workspace/coverage/default/9.flash_ctrl_disable.3111363159
Short name T388
Test name
Test status
Simulation time 89804900 ps
CPU time 20.99 seconds
Started Jun 09 02:49:15 PM PDT 24
Finished Jun 09 02:49:36 PM PDT 24
Peak memory 274136 kb
Host smart-cf0ed941-23db-423e-8478-077be8abe99f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111363159 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_disable.3111363159
Directory /workspace/9.flash_ctrl_disable/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_mp.1640498797
Short name T311
Test name
Test status
Simulation time 4004244000 ps
CPU time 2411.23 seconds
Started Jun 09 02:48:54 PM PDT 24
Finished Jun 09 03:29:06 PM PDT 24
Peak memory 263116 kb
Host smart-3c0bb631-8ddd-4459-be9d-2fab46e1f835
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640498797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_err
or_mp.1640498797
Directory /workspace/9.flash_ctrl_error_mp/latest

Test location /workspace/coverage/default/9.flash_ctrl_error_prog_win.258842991
Short name T312
Test name
Test status
Simulation time 857287600 ps
CPU time 916.19 seconds
Started Jun 09 02:48:55 PM PDT 24
Finished Jun 09 03:04:12 PM PDT 24
Peak memory 273752 kb
Host smart-e6f69435-bebd-4937-8e61-4ec0773c0937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258842991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.258842991
Directory /workspace/9.flash_ctrl_error_prog_win/latest

Test location /workspace/coverage/default/9.flash_ctrl_fetch_code.973862272
Short name T61
Test name
Test status
Simulation time 612519000 ps
CPU time 33.06 seconds
Started Jun 09 02:48:54 PM PDT 24
Finished Jun 09 02:49:27 PM PDT 24
Peak memory 262824 kb
Host smart-cbb3d3df-d97c-4298-a838-169d977cc8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973862272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.973862272
Directory /workspace/9.flash_ctrl_fetch_code/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.3097843774
Short name T308
Test name
Test status
Simulation time 10050171700 ps
CPU time 88.9 seconds
Started Jun 09 02:49:15 PM PDT 24
Finished Jun 09 02:50:44 PM PDT 24
Peak memory 266956 kb
Host smart-e78d9a54-2566-45f7-82cd-65358d28fab8
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097843774 -asser
t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.3097843774
Directory /workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.4291840738
Short name T614
Test name
Test status
Simulation time 48530500 ps
CPU time 13.45 seconds
Started Jun 09 02:49:14 PM PDT 24
Finished Jun 09 02:49:28 PM PDT 24
Peak memory 258904 kb
Host smart-e1629886-570c-49e3-9c05-8a50b1315872
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291840738 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.4291840738
Directory /workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1955581951
Short name T330
Test name
Test status
Simulation time 4198726500 ps
CPU time 159.02 seconds
Started Jun 09 02:48:45 PM PDT 24
Finished Jun 09 02:51:24 PM PDT 24
Peak memory 263464 kb
Host smart-4f8748c5-1313-4361-9f47-653afb7fad33
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955581951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct
rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h
w_sec_otp.1955581951
Directory /workspace/9.flash_ctrl_hw_sec_otp/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd.850779147
Short name T812
Test name
Test status
Simulation time 2714651000 ps
CPU time 201.84 seconds
Started Jun 09 02:49:00 PM PDT 24
Finished Jun 09 02:52:22 PM PDT 24
Peak memory 291588 kb
Host smart-2752069e-85ec-4b24-9c7b-1c5eb1069e4f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850779147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE
Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash
_ctrl_intr_rd.850779147
Directory /workspace/9.flash_ctrl_intr_rd/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3405885152
Short name T200
Test name
Test status
Simulation time 15366528800 ps
CPU time 161.2 seconds
Started Jun 09 02:49:02 PM PDT 24
Finished Jun 09 02:51:44 PM PDT 24
Peak memory 291344 kb
Host smart-cf34ec12-c6ef-4a0c-8e03-8ea5945ea41e
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U
VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405885152 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.3405885152
Directory /workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr.1172438804
Short name T396
Test name
Test status
Simulation time 8689732800 ps
CPU time 72.54 seconds
Started Jun 09 02:49:03 PM PDT 24
Finished Jun 09 02:50:15 PM PDT 24
Peak memory 260784 kb
Host smart-5b62d358-121f-407e-ad17-41d84e459ad5
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172438804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test
+UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_wr.1172438804
Directory /workspace/9.flash_ctrl_intr_wr/latest

Test location /workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1840310937
Short name T945
Test name
Test status
Simulation time 60432448800 ps
CPU time 250.23 seconds
Started Jun 09 02:49:05 PM PDT 24
Finished Jun 09 02:53:15 PM PDT 24
Peak memory 260644 kb
Host smart-fa8b4381-f0a2-4225-8834-5d79ecb2b9dd
User root
Command /workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184
0310937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.1840310937
Directory /workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspace/coverage/default/9.flash_ctrl_invalid_op.2356592761
Short name T523
Test name
Test status
Simulation time 2171854500 ps
CPU time 71.22 seconds
Started Jun 09 02:48:54 PM PDT 24
Finished Jun 09 02:50:05 PM PDT 24
Peak memory 261076 kb
Host smart-23a3c839-c951-416c-9439-872a60e6247b
User root
Command /workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356592761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o
p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2356592761
Directory /workspace/9.flash_ctrl_invalid_op/latest

Test location /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.4247389781
Short name T518
Test name
Test status
Simulation time 15409400 ps
CPU time 13.41 seconds
Started Jun 09 02:49:16 PM PDT 24
Finished Jun 09 02:49:30 PM PDT 24
Peak memory 265208 kb
Host smart-a6f6d17f-9846-4a77-95e5-39e58c350823
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247389781 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.4247389781
Directory /workspace/9.flash_ctrl_lcmgr_intg/latest

Test location /workspace/coverage/default/9.flash_ctrl_mp_regions.4221237953
Short name T936
Test name
Test status
Simulation time 9821323600 ps
CPU time 358.37 seconds
Started Jun 09 02:48:52 PM PDT 24
Finished Jun 09 02:54:50 PM PDT 24
Peak memory 274984 kb
Host smart-44ba0045-c03b-4701-96ee-046a91abb56b
User root
Command /workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221237953 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_mp_regions.4221237953
Directory /workspace/9.flash_ctrl_mp_regions/latest

Test location /workspace/coverage/default/9.flash_ctrl_otp_reset.91202304
Short name T828
Test name
Test status
Simulation time 75384600 ps
CPU time 109.99 seconds
Started Jun 09 02:48:47 PM PDT 24
Finished Jun 09 02:50:38 PM PDT 24
Peak memory 262656 kb
Host smart-5619a570-0131-4c58-a3b7-9b3262407df8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91202304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl
_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_
reset.91202304
Directory /workspace/9.flash_ctrl_otp_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_phy_arb.996326316
Short name T197
Test name
Test status
Simulation time 1446684100 ps
CPU time 564.29 seconds
Started Jun 09 02:48:43 PM PDT 24
Finished Jun 09 02:58:08 PM PDT 24
Peak memory 263368 kb
Host smart-e0a0715b-28bc-4f20-9245-ebbbb8bc2a72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996326316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.996326316
Directory /workspace/9.flash_ctrl_phy_arb/latest

Test location /workspace/coverage/default/9.flash_ctrl_prog_reset.3497625321
Short name T969
Test name
Test status
Simulation time 1970874600 ps
CPU time 140.38 seconds
Started Jun 09 02:49:15 PM PDT 24
Finished Jun 09 02:51:36 PM PDT 24
Peak memory 261572 kb
Host smart-d6166ec8-fdc3-4bf8-8c97-5847ef3e4917
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497625321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog
_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_res
et.3497625321
Directory /workspace/9.flash_ctrl_prog_reset/latest

Test location /workspace/coverage/default/9.flash_ctrl_rand_ops.1036214426
Short name T118
Test name
Test status
Simulation time 376573900 ps
CPU time 913.39 seconds
Started Jun 09 02:48:45 PM PDT 24
Finished Jun 09 03:03:59 PM PDT 24
Peak memory 284364 kb
Host smart-15934add-61dc-46fa-9fe8-7961c92e8d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036214426 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.1036214426
Directory /workspace/9.flash_ctrl_rand_ops/latest

Test location /workspace/coverage/default/9.flash_ctrl_re_evict.2014681795
Short name T300
Test name
Test status
Simulation time 87471100 ps
CPU time 34.38 seconds
Started Jun 09 02:49:16 PM PDT 24
Finished Jun 09 02:49:51 PM PDT 24
Peak memory 275736 kb
Host smart-14df9b1f-c33f-45b4-8538-e6af3211bc5e
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014681795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_re_evict.2014681795
Directory /workspace/9.flash_ctrl_re_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro.3858836134
Short name T629
Test name
Test status
Simulation time 4128433800 ps
CPU time 128.03 seconds
Started Jun 09 02:48:53 PM PDT 24
Finished Jun 09 02:51:01 PM PDT 24
Peak memory 289480 kb
Host smart-cd8e8535-35cf-4809-b11f-b3ddff135033
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858836134 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_ro.3858836134
Directory /workspace/9.flash_ctrl_ro/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_derr.4029339332
Short name T875
Test name
Test status
Simulation time 1257992400 ps
CPU time 167.57 seconds
Started Jun 09 02:48:58 PM PDT 24
Finished Jun 09 02:51:46 PM PDT 24
Peak memory 282356 kb
Host smart-5626fe95-1c72-40d6-b87f-dc2d9f0de647
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=
4029339332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.4029339332
Directory /workspace/9.flash_ctrl_ro_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_ro_serr.769971445
Short name T179
Test name
Test status
Simulation time 1095291200 ps
CPU time 139.6 seconds
Started Jun 09 02:49:00 PM PDT 24
Finished Jun 09 02:51:20 PM PDT 24
Peak memory 295632 kb
Host smart-9ffd48dd-dda0-4bb1-9d60-428a807cff1b
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769971445 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.769971445
Directory /workspace/9.flash_ctrl_ro_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw.1073230411
Short name T111
Test name
Test status
Simulation time 15213980900 ps
CPU time 719.16 seconds
Started Jun 09 02:48:57 PM PDT 24
Finished Jun 09 03:00:57 PM PDT 24
Peak memory 314936 kb
Host smart-f5d24ebc-f7b5-4a64-a596-881bb9d1629a
User root
Command /workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073230411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes
t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.flash_ctrl_rw.1073230411
Directory /workspace/9.flash_ctrl_rw/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_derr.3589576902
Short name T697
Test name
Test status
Simulation time 15925621000 ps
CPU time 799.78 seconds
Started Jun 09 02:48:59 PM PDT 24
Finished Jun 09 03:02:19 PM PDT 24
Peak memory 338012 kb
Host smart-3b3135ab-eb2a-4c67-a84f-fb2470697608
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589576902 -assert nopostproc +UVM_TESTNAME=fla
sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_rw_derr.3589576902
Directory /workspace/9.flash_ctrl_rw_derr/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict.2981832062
Short name T42
Test name
Test status
Simulation time 150606400 ps
CPU time 28.86 seconds
Started Jun 09 02:49:15 PM PDT 24
Finished Jun 09 02:49:44 PM PDT 24
Peak memory 276068 kb
Host smart-5d37c4f2-8c59-42e6-a9ad-fbc056e4a93d
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981832062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S
EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_rw_evict.2981832062
Directory /workspace/9.flash_ctrl_rw_evict/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.107658322
Short name T491
Test name
Test status
Simulation time 63823100 ps
CPU time 31.84 seconds
Started Jun 09 02:49:18 PM PDT 24
Finished Jun 09 02:49:50 PM PDT 24
Peak memory 274000 kb
Host smart-5a54af08-01be-4939-bb0d-6ef6e1e2c63f
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U
VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107658322 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.107658322
Directory /workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspace/coverage/default/9.flash_ctrl_rw_serr.3486862162
Short name T917
Test name
Test status
Simulation time 3406188900 ps
CPU time 611.69 seconds
Started Jun 09 02:49:00 PM PDT 24
Finished Jun 09 02:59:12 PM PDT 24
Peak memory 313240 kb
Host smart-7c7df73e-bd1a-499b-b8f2-4037f7aa4aab
User root
Command /workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -
do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486862162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_s
err.3486862162
Directory /workspace/9.flash_ctrl_rw_serr/latest

Test location /workspace/coverage/default/9.flash_ctrl_sec_info_access.2294105330
Short name T419
Test name
Test status
Simulation time 1984741100 ps
CPU time 73.85 seconds
Started Jun 09 02:49:17 PM PDT 24
Finished Jun 09 02:50:31 PM PDT 24
Peak memory 264988 kb
Host smart-4622c8b4-aee2-4a31-9a6a-9f26cf238230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294105330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.2294105330
Directory /workspace/9.flash_ctrl_sec_info_access/latest

Test location /workspace/coverage/default/9.flash_ctrl_smoke.3045558650
Short name T719
Test name
Test status
Simulation time 32198600 ps
CPU time 148.34 seconds
Started Jun 09 02:48:43 PM PDT 24
Finished Jun 09 02:51:12 PM PDT 24
Peak memory 277100 kb
Host smart-313bc779-d83a-4248-a3f0-32500a018981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045558650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.3045558650
Directory /workspace/9.flash_ctrl_smoke/latest

Test location /workspace/coverage/default/9.flash_ctrl_wo.3891023151
Short name T692
Test name
Test status
Simulation time 3442562600 ps
CPU time 261.47 seconds
Started Jun 09 02:48:54 PM PDT 24
Finished Jun 09 02:53:15 PM PDT 24
Peak memory 260836 kb
Host smart-0a8ffd1f-eee2-4d97-a264-d519f4736d3c
User root
Command /workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891023151 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.flash_ctrl_wo.3891023151
Directory /workspace/9.flash_ctrl_wo/latest
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