Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	317981	1		T1	2		T2	2		T12	1
all_values[1]	317981	1		T1	2		T2	2		T12	1
all_values[2]	317981	1		T1	2		T2	2		T12	1
all_values[3]	317981	1		T1	2		T2	2		T12	1
all_values[4]	317981	1		T1	2		T2	2		T12	1
all_values[5]	317981	1		T1	2		T2	2		T12	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	642157	1		T1	12		T2	12		T12	6
auto[1]	1265729	1		T4	25192		T37	4240		T8	4524

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	930429	1		T1	7		T2	7		T12	4
auto[1]	977457	1		T1	5		T2	5		T12	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	317814	1		T1	2		T2	2		T12	1
all_values[0]	auto[1]	auto[1]	167	1		T280	5		T281	2		T338	3
all_values[1]	auto[0]	auto[1]	317835	1		T1	2		T2	2		T12	1
all_values[1]	auto[1]	auto[1]	146	1		T280	5		T281	2		T338	1
all_values[2]	auto[0]	auto[0]	1592	1		T1	2		T2	2		T12	1
all_values[2]	auto[0]	auto[1]	39	1		T280	1		T338	1		T340	2
all_values[2]	auto[1]	auto[0]	316288	1		T4	6298		T37	1060		T8	1131
all_values[2]	auto[1]	auto[1]	62	1		T280	1		T281	3		T338	1
all_values[3]	auto[0]	auto[0]	1584	1		T1	2		T2	2		T12	1
all_values[3]	auto[0]	auto[1]	39	1		T338	1		T339	1		T340	2
all_values[3]	auto[1]	auto[0]	80967	1		T4	46		T37	530		T8	1
all_values[3]	auto[1]	auto[1]	235391	1		T4	6252		T37	530		T8	1130
all_values[4]	auto[0]	auto[0]	1118	1		T1	1		T2	1		T12	1
all_values[4]	auto[0]	auto[1]	510	1		T1	1		T2	1		T18	1
all_values[4]	auto[1]	auto[0]	211076	1		T4	4735		T37	530		T8	566
all_values[4]	auto[1]	auto[1]	105277	1		T4	1563		T37	530		T8	565
all_values[5]	auto[0]	auto[0]	1508	1		T1	2		T2	2		T12	1
all_values[5]	auto[0]	auto[1]	118	1		T42	4		T44	1		T45	4
all_values[5]	auto[1]	auto[0]	316296	1		T4	6298		T37	1060		T8	1131
all_values[5]	auto[1]	auto[1]	59	1		T280	2		T340	3		T341	3