Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	250435	1		T1	1		T2	166		T18	1
auto[FlashEraseBank]	272639	1		T2	34		T18	2		T4	794

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	263488	1		T2	83		T18	2		T4	1563
auto[FlashOpProgram]	239128	1		T1	1		T2	93		T5	101
auto[FlashOpErase]	16458	1		T2	24		T18	1		T5	101
auto[FlashOpInvalid]	4000	1		T122	200		T199	200		T131	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	263488	1		T2	83		T18	2		T4	1563
op[FlashOpProgram]	239128	1		T1	1		T2	93		T5	101
op[FlashOpErase]	16458	1		T2	24		T18	1		T5	101
read_erase_read	674	1		T2	3		T18	1		T6	1
read_prog_read	801	1		T2	19		T6	13		T47	2

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	380537	1		T1	1		T2	191		T18	3
auto[FlashPartInfo]	139257	1		T2	9		T5	406		T13	1
auto[FlashPartInfo1]	764	1		T30	11		T22	38		T87	2
auto[FlashPartInfo2]	2516	1		T29	1		T32	17		T7	6

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	190264	1		T2	80		T18	2		T4	1563
auto[FlashPartData]	auto[FlashOpProgram]	182560	1		T1	1		T2	90		T6	89
auto[FlashPartData]	auto[FlashOpErase]	3805	1		T2	21		T18	1		T6	26
auto[FlashPartData]	auto[FlashOpInvalid]	3908	1		T122	192		T199	200		T131	198
auto[FlashPartInfo]	auto[FlashOpRead]	71057	1		T2	3		T5	204		T14	1
auto[FlashPartInfo]	auto[FlashOpProgram]	55498	1		T2	3		T5	101		T6	1
auto[FlashPartInfo]	auto[FlashOpErase]	12624	1		T2	3		T5	101		T13	1
auto[FlashPartInfo]	auto[FlashOpInvalid]	78	1		T122	6		T131	2		T95	6
auto[FlashPartInfo1]	auto[FlashOpRead]	592	1		T30	11		T22	38		T87	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T85	1		T422	1		T135	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T85	1		T83	1		T423	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T85	2		T423	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1575	1		T29	1		T32	9		T7	6
auto[FlashPartInfo2]	auto[FlashOpProgram]	905	1		T30	2		T34	8		T233	9
auto[FlashPartInfo2]	auto[FlashOpErase]	26	1		T32	8		T38	1		T122	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T122	2		T95	2		T424	2