Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31587	1		T2	16		T5	188		T6	16
auto[1]	18	1		T33	1		T125	4		T355	2
auto[2]	22	1		T33	1		T129	2		T63	4
auto[3]	61	1		T31	3		T187	1		T356	4

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7917	1		T2	4		T5	47		T6	4
evic_idx[1]	7926	1		T2	4		T5	47		T6	4
evic_idx[2]	7918	1		T2	4		T5	47		T6	4
evic_idx[3]	7927	1		T2	4		T5	47		T6	4

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30863	1		T5	188		T150	716		T226	252
evic_op[2]	299	1		T31	3		T68	20		T33	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[2]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7709	1		T5	47		T150	179		T226	63
evic_idx[0]	evic_op[1]	auto[1]	1	1		T357	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	6	1		T356	2		T358	1		T359	1
evic_idx[0]	evic_op[2]	auto[0]	58	1		T68	5		T38	2		T39	1
evic_idx[0]	evic_op[2]	auto[1]	3	1		T125	1		T355	1		T360	1
evic_idx[0]	evic_op[2]	auto[2]	1	1		T129	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	6	1		T213	1		T361	1		T362	1
evic_idx[1]	evic_op[1]	auto[0]	7710	1		T5	47		T150	179		T226	63
evic_idx[1]	evic_op[1]	auto[1]	1	1		T357	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	5	1		T356	1		T358	1		T359	1
evic_idx[1]	evic_op[2]	auto[0]	60	1		T68	5		T196	1		T38	2
evic_idx[1]	evic_op[2]	auto[1]	4	1		T125	1		T355	1		T360	1
evic_idx[1]	evic_op[2]	auto[2]	1	1		T33	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	14	1		T31	1		T46	1		T363	1
evic_idx[2]	evic_op[1]	auto[0]	7709	1		T5	47		T150	179		T226	63
evic_idx[2]	evic_op[1]	auto[1]	1	1		T357	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	5	1		T356	1		T358	1		T359	1
evic_idx[2]	evic_op[2]	auto[0]	58	1		T68	5		T38	2		T39	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T125	1		T364	1		T365	1
evic_idx[2]	evic_op[2]	auto[2]	3	1		T129	1		T366	1		T367	1
evic_idx[2]	evic_op[2]	auto[3]	7	1		T31	1		T368	1		T207	1
evic_idx[3]	evic_op[1]	auto[0]	7711	1		T5	47		T150	179		T226	63
evic_idx[3]	evic_op[1]	auto[1]	1	1		T357	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	4	1		T358	1		T359	1		T357	1
evic_idx[3]	evic_op[2]	auto[0]	62	1		T68	5		T38	2		T39	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T33	1		T125	1		T365	1
evic_idx[3]	evic_op[2]	auto[2]	1	1		T367	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	14	1		T31	1		T187	1		T369	1