Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	13856	1		T346	13856		-	-		-	-
rd_lvl[2]	42977	1		T210	1350		T299	1496		T347	11292
rd_lvl[3]	19364	1		T210	644		T348	1214		T349	1026
rd_lvl[4]	35809	1		T4	5231		T210	165		T348	2929
rd_lvl[5]	15612	1		T4	964		T22	207		T210	484
rd_lvl[6]	23089	1		T22	42		T210	648		T24	350
rd_lvl[7]	12715	1		T72	381		T24	1664		T303	1552
rd_lvl[8]	21408	1		T8	900		T72	1551		T24	1374
rd_lvl[9]	5367	1		T8	214		T72	1293		T350	109
rd_lvl[10]	5807	1		T37	261		T350	108		T348	2
rd_lvl[11]	2929	1		T37	137		T8	16		T351	18
rd_lvl[12]	3211	1		T41	205		T352	1054		T299	116
rd_lvl[13]	2883	1		T37	132		T41	170		T242	521
rd_lvl[14]	6022	1		T242	1136		T353	3		T354	1165
rd_lvl[15]	1941	1		T41	168		T140	450		T354	310