Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	317981	1		T1	2		T2	2		T12	1
all_pins[1]	317981	1		T1	2		T2	2		T12	1
all_pins[2]	317981	1		T1	2		T2	2		T12	1
all_pins[3]	317981	1		T1	2		T2	2		T12	1
all_pins[4]	317981	1		T1	2		T2	2		T12	1
all_pins[5]	317981	1		T1	2		T2	2		T12	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1569623	1		T1	12		T2	12		T12	6
values[0x1]	338263	1		T4	7764		T37	1060		T8	1696
transitions[0x0=>0x1]	298348	1		T4	6241		T37	1060		T8	1131
transitions[0x1=>0x0]	298328	1		T4	6241		T37	1060		T8	1131

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	317814	1		T1	2		T2	2		T12	1
all_pins[0]	values[0x1]	167	1		T280	5		T281	2		T338	3
all_pins[0]	transitions[0x0=>0x1]	77	1		T280	1		T338	3		T340	4
all_pins[0]	transitions[0x1=>0x0]	56	1		T280	1		T338	1		T340	1
all_pins[1]	values[0x0]	317835	1		T1	2		T2	2		T12	1
all_pins[1]	values[0x1]	146	1		T280	5		T281	2		T338	1
all_pins[1]	transitions[0x0=>0x1]	114	1		T280	5		T281	1		T338	1
all_pins[1]	transitions[0x1=>0x0]	3549	1		T140	1289		T371	3		T372	1144
all_pins[2]	values[0x0]	314400	1		T1	2		T2	2		T12	1
all_pins[2]	values[0x1]	3581	1		T140	1289		T371	3		T372	1144
all_pins[2]	transitions[0x0=>0x1]	42	1		T281	2		T338	1		T340	1
all_pins[2]	transitions[0x1=>0x0]	213030	1		T4	6195		T37	530		T8	1130
all_pins[3]	values[0x0]	101412	1		T1	2		T2	2		T12	1
all_pins[3]	values[0x1]	216569	1		T4	6195		T37	530		T8	1130
all_pins[3]	transitions[0x0=>0x1]	180371	1		T4	4672		T37	530		T8	565
all_pins[3]	transitions[0x1=>0x0]	81543	1		T4	46		T37	530		T8	1
all_pins[4]	values[0x0]	200240	1		T1	2		T2	2		T12	1
all_pins[4]	values[0x1]	117741	1		T4	1569		T37	530		T8	566
all_pins[4]	transitions[0x0=>0x1]	117723	1		T4	1569		T37	530		T8	566
all_pins[4]	transitions[0x1=>0x0]	41	1		T280	2		T340	2		T341	1
all_pins[5]	values[0x0]	317922	1		T1	2		T2	2		T12	1
all_pins[5]	values[0x1]	59	1		T280	2		T340	3		T341	3
all_pins[5]	transitions[0x0=>0x1]	21	1		T280	1		T341	1		T373	1
all_pins[5]	transitions[0x1=>0x0]	109	1		T280	3		T281	1		T338	2