Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	214583	1		T1	1		T2	2		T3	1
all_values[1]	214583	1		T1	1		T2	2		T3	1
all_values[2]	214583	1		T1	1		T2	2		T3	1
all_values[3]	214583	1		T1	1		T2	2		T3	1
all_values[4]	214583	1		T1	1		T2	2		T3	1
all_values[5]	214583	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	435294	1		T1	6		T2	12		T3	6
auto[1]	852204	1		T18	3744		T6	13176		T38	14320

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	631740	1		T1	4		T2	7		T3	4
auto[1]	655758	1		T1	2		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	214429	1		T1	1		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	154	1		T263	2		T334	3		T335	4
all_values[1]	auto[0]	auto[1]	214438	1		T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	145	1		T263	3		T334	4		T335	3
all_values[2]	auto[0]	auto[0]	1556	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	63	1		T262	1		T263	3		T334	2
all_values[2]	auto[1]	auto[0]	212903	1		T18	936		T6	3294		T38	3580
all_values[2]	auto[1]	auto[1]	61	1		T262	1		T263	1		T334	2
all_values[3]	auto[0]	auto[0]	1532	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	56	1		T263	2		T334	2		T338	1
all_values[3]	auto[1]	auto[0]	82501	1		T18	420		T6	1647		T61	1810
all_values[3]	auto[1]	auto[1]	130494	1		T18	516		T6	1647		T38	3580
all_values[4]	auto[0]	auto[0]	1121	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	504	1		T2	1		T5	1		T11	1
all_values[4]	auto[1]	auto[0]	117739	1		T18	420		T6	1647		T38	1790
all_values[4]	auto[1]	auto[1]	95219	1		T18	516		T6	1647		T38	1790
all_values[5]	auto[0]	auto[0]	1471	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	124	1		T7	1		T39	1		T40	1
all_values[5]	auto[1]	auto[0]	212917	1		T18	936		T6	3294		T38	3580
all_values[5]	auto[1]	auto[1]	71	1		T262	4		T263	2		T334	3