Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	246931	1		T2	165		T3	144		T4	9
auto[FlashEraseBank]	266107	1		T2	35		T4	5		T5	2

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	253744	1		T2	88		T3	42		T4	12
auto[FlashOpProgram]	238416	1		T2	86		T3	61		T4	2
auto[FlashOpErase]	16878	1		T2	26		T3	41		T5	2
auto[FlashOpInvalid]	4000	1		T44	200		T102	200		T103	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	253744	1		T2	88		T3	42		T4	12
op[FlashOpProgram]	238416	1		T2	86		T3	61		T4	2
op[FlashOpErase]	16878	1		T2	26		T3	41		T5	2
read_erase_read	717	1		T2	8		T5	1		T16	5
read_prog_read	728	1		T2	15		T16	2		T29	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	366928	1		T2	198		T3	144		T4	7
auto[FlashPartInfo]	142327	1		T2	2		T4	7		T11	1
auto[FlashPartInfo1]	898	1		T42	10		T44	6		T43	4
auto[FlashPartInfo2]	2885	1		T21	1		T55	5		T42	5

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	179022	1		T2	86		T3	42		T4	5
auto[FlashPartData]	auto[FlashOpProgram]	180250	1		T2	86		T3	61		T4	2
auto[FlashPartData]	auto[FlashOpErase]	3728	1		T2	26		T3	41		T5	2
auto[FlashPartData]	auto[FlashOpInvalid]	3928	1		T44	198		T102	198		T103	198
auto[FlashPartInfo]	auto[FlashOpRead]	72094	1		T2	2		T4	7		T16	672
auto[FlashPartInfo]	auto[FlashOpProgram]	57056	1		T16	450		T29	1		T55	195
auto[FlashPartInfo]	auto[FlashOpErase]	13125	1		T11	1		T16	16		T21	14
auto[FlashPartInfo]	auto[FlashOpInvalid]	52	1		T102	2		T103	2		T406	2
auto[FlashPartInfo1]	auto[FlashOpRead]	720	1		T42	10		T44	2		T43	4
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T44	1		T84	1		T87	32
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T44	1		T84	1		T106	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	8	1		T44	2		T84	2		T106	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1908	1		T21	1		T42	2		T7	7
auto[FlashPartInfo2]	auto[FlashOpProgram]	944	1		T55	5		T42	3		T82	9
auto[FlashPartInfo2]	auto[FlashOpErase]	21	1		T83	1		T406	1		T407	11
auto[FlashPartInfo2]	auto[FlashOpInvalid]	12	1		T406	2		T408	2		T409	2