Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.95	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	8	24	75.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	8	24	75.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32753	1		T2	12		T3	1		T80	356
auto[1]	6	1		T52	1		T320	2		T321	1
auto[2]	29	1		T152	8		T322	2		T323	2
auto[3]	128	1		T21	14		T30	1		T50	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8229	1		T2	3		T21	3		T30	1
evic_idx[1]	8224	1		T2	3		T21	5		T80	89
evic_idx[2]	8235	1		T2	3		T21	3		T52	1
evic_idx[3]	8228	1		T2	3		T3	1		T21	3

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	32038	1		T3	1		T21	14		T80	356
evic_op[2]	280	1		T30	1		T50	1		T52	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	8	24	75.00	8

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1] - auto[2]]	--	--	8

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7989	1		T80	89		T44	100		T222	1
evic_idx[0]	evic_op[1]	auto[3]	22	1		T21	3		T94	1		T229	2
evic_idx[0]	evic_op[2]	auto[0]	53	1		T35	1		T41	1		T57	4
evic_idx[0]	evic_op[2]	auto[1]	1	1		T324	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	3	1		T322	1		T325	1		T321	1
evic_idx[0]	evic_op[2]	auto[3]	11	1		T30	1		T50	1		T165	1
evic_idx[1]	evic_op[1]	auto[0]	7988	1		T80	89		T44	100		T222	1
evic_idx[1]	evic_op[1]	auto[3]	21	1		T21	5		T94	1		T229	1
evic_idx[1]	evic_op[2]	auto[0]	55	1		T35	1		T41	1		T57	4
evic_idx[1]	evic_op[2]	auto[1]	1	1		T320	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	1	1		T326	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	8	1		T167	1		T280	1		T327	1
evic_idx[2]	evic_op[1]	auto[0]	7990	1		T80	89		T44	100		T222	1
evic_idx[2]	evic_op[1]	auto[3]	21	1		T21	3		T94	1		T229	2
evic_idx[2]	evic_op[2]	auto[0]	56	1		T35	1		T41	1		T57	4
evic_idx[2]	evic_op[2]	auto[1]	2	1		T52	1		T320	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	2	1		T323	1		T326	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	15	1		T328	1		T253	1		T329	1
evic_idx[3]	evic_op[1]	auto[0]	7990	1		T3	1		T80	89		T44	100
evic_idx[3]	evic_op[1]	auto[3]	17	1		T21	3		T229	2		T282	1
evic_idx[3]	evic_op[2]	auto[0]	54	1		T35	1		T41	1		T57	4
evic_idx[3]	evic_op[2]	auto[1]	2	1		T321	1		T330	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	3	1		T322	1		T323	1		T331	1
evic_idx[3]	evic_op[2]	auto[3]	13	1		T332	1		T165	1		T333	1