Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	6	0	6	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
instr_type_cp	3	0	3	100.00	100	1	1	0
key_cp	2	0	2	100.00	100	1	1	2

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key_instr_cross	6	0	6	100.00	100	1	1	0

Summary for Variable instr_type_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for instr_type_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	4736	1		T48	116		T64	132		T65	200
instr_types[0]	5740	1		T48	176		T64	382		T65	160
instr_types[1]	4178571	1		T4	7		T5	1		T11	29

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Summary for Variable key_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4187113	1		T4	7		T5	1		T11	29
auto[1]	1934	1		T48	141		T64	183		T65	197

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Summary for Cross key_instr_cross

Samples crossed: key_cp instr_type_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	6	0	6	100.00

Automatically Generated Cross Bins for key_instr_cross

Bins

key_cp	instr_type_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	others	4306	1		T48	79		T64	92		T65	88
auto[0]	instr_types[0]	4889	1		T48	119		T64	304		T65	132
auto[0]	instr_types[1]	4177918	1		T4	7		T5	1		T11	29
auto[1]	others	430	1		T48	37		T64	40		T65	112
auto[1]	instr_types[0]	851	1		T48	57		T64	78		T65	28
auto[1]	instr_types[1]	653	1		T48	47		T64	65		T65	57