Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	2714	1		T340	2714		-	-		-	-
rd_lvl[2]	7539	1		T341	2304		T342	1434		T340	2533
rd_lvl[3]	6439	1		T343	1300		T344	294		T341	2035
rd_lvl[4]	17322	1		T343	6327		T344	81		T345	2619
rd_lvl[5]	9030	1		T346	1482		T343	1131		T345	530
rd_lvl[6]	8916	1		T346	1086		T347	408		T341	2512
rd_lvl[7]	12433	1		T348	588		T284	527		T347	261
rd_lvl[8]	15224	1		T38	3179		T348	420		T284	206
rd_lvl[9]	6367	1		T38	401		T61	696		T349	509
rd_lvl[10]	14560	1		T6	1258		T61	1114		T349	1131
rd_lvl[11]	2528	1		T6	389		T36	628		T182	137
rd_lvl[12]	4876	1		T36	953		T350	183		T351	1483
rd_lvl[13]	4366	1		T350	67		T351	342		T352	262
rd_lvl[14]	8085	1		T36	1		T37	1227		T278	129
rd_lvl[15]	2830	1		T18	279		T37	458		T278	35