Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	214583	1		T1	1		T2	2		T3	1
all_pins[1]	214583	1		T1	1		T2	2		T3	1
all_pins[2]	214583	1		T1	1		T2	2		T3	1
all_pins[3]	214583	1		T1	1		T2	2		T3	1
all_pins[4]	214583	1		T1	1		T2	2		T3	1
all_pins[5]	214583	1		T1	1		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1058602	1		T1	6		T2	12		T3	6
values[0x1]	228896	1		T18	1410		T6	3294		T38	5370
transitions[0x0=>0x1]	209593	1		T18	936		T6	3294		T38	3580
transitions[0x1=>0x0]	209579	1		T18	936		T6	3294		T38	3580

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	214429	1		T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	154	1		T263	2		T334	3		T335	4
all_pins[0]	transitions[0x0=>0x1]	81	1		T334	1		T335	1		T336	3
all_pins[0]	transitions[0x1=>0x0]	72	1		T263	1		T334	2		T338	4
all_pins[1]	values[0x0]	214438	1		T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	145	1		T263	3		T334	4		T335	3
all_pins[1]	transitions[0x0=>0x1]	116	1		T263	2		T334	3		T335	3
all_pins[1]	transitions[0x1=>0x0]	3078	1		T18	237		T278	113		T355	1124
all_pins[2]	values[0x0]	211476	1		T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	3107	1		T18	237		T278	113		T355	1124
all_pins[2]	transitions[0x0=>0x1]	41	1		T262	1		T263	1		T334	2
all_pins[2]	transitions[0x1=>0x0]	123607	1		T18	279		T6	1647		T38	3580
all_pins[3]	values[0x0]	87910	1		T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	126673	1		T18	516		T6	1647		T38	3580
all_pins[3]	transitions[0x0=>0x1]	110594	1		T18	279		T6	1647		T38	1790
all_pins[3]	transitions[0x1=>0x0]	82667	1		T18	420		T6	1647		T61	1810
all_pins[4]	values[0x0]	115837	1		T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	98746	1		T18	657		T6	1647		T38	1790
all_pins[4]	transitions[0x0=>0x1]	98729	1		T18	657		T6	1647		T38	1790
all_pins[4]	transitions[0x1=>0x0]	54	1		T262	4		T334	3		T336	1
all_pins[5]	values[0x0]	214512	1		T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	71	1		T262	4		T263	2		T334	3
all_pins[5]	transitions[0x0=>0x1]	32	1		T262	3		T263	1		T334	2
all_pins[5]	transitions[0x1=>0x0]	101	1		T263	1		T334	2		T335	3